Wafer-scale packaging structures and their formation methods

Abstract

The present application provides a wafer-scale packaging structure and a method for forming the same, wherein the wafer-scale packaging structure comprises: a plurality of discrete first chip modules mounted on the upper surface of a substrate, the first chip modules being electrically connected to a first wiring layer; a first plastic encapsulation layer covering the first chip modules and the upper surface of the substrate, the first plastic encapsulation layer exposing the surface of the first chip modules away from the substrate; a first heat sink mounted on the upper surface of the first plastic encapsulation layer; a plurality of discrete second chip modules mounted on the lower surface of the substrate, the second chip modules being electrically connected to a second wiring layer; a second plastic encapsulation layer covering the second chip modules and the lower surface of the substrate, the second plastic encapsulation layer exposing the surface of the second chip modules away from the substrate; and a second heat sink mounted on the lower surface of the second plastic encapsulation layer. This improves the heat dissipation problem of the wafer-scale packaging structure and enhances the electrical performance of the wafer-scale packaging structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and more particularly to a wafer-scale packaging structure and a method for forming the same. Background Technology

[0002] System-in-Package (SiP) integrates chips with different functions such as optoelectronics, digital / logic, radio frequency, and memory into a single package in the form of chip stacking or package stacking, thereby realizing a system that can perform multiple functions.

[0003] The demand for data processing in emerging fields such as servers, mobile devices, artificial intelligence, automotive electronics, and data storage is growing exponentially. In order to meet the requirements of high-performance computing such as high density, high speed, high heat dissipation, low power consumption, and low latency, existing system-in-package (SiP) is expanding towards wafer scale, which integrates multiple semiconductor chips with different functions on a single silicon wafer to form a wafer-scale SiP structure.

[0004] The heat dissipation problem of existing wafer-scale packaging structures still needs to be improved, and their performance still needs to be enhanced. Summary of the Invention

[0005] The problem to be solved by this application is to provide a wafer-scale packaging structure and a method for forming the same, so as to improve the heat dissipation problem of the wafer-scale packaging structure and enhance its performance.

[0006] To address the aforementioned problems, this application provides a wafer-scale packaging structure, comprising:

[0007] A substrate, the substrate including an opposing upper surface and a lower surface, the upper surface having a first wiring layer and the lower surface having a second wiring layer;

[0008] A plurality of discrete first chip modules are mounted on the upper surface of the substrate, and the first chip modules are electrically connected to the first wiring layer.

[0009] A first molding compound covers the first chip module and the upper surface of the substrate, the first molding compound exposing the surface of the first chip module away from the substrate;

[0010] A first heat sink plate is attached to the upper surface of the first molding layer;

[0011] A plurality of discrete second chip modules are mounted on the lower surface of the substrate, and the second chip modules are electrically connected to the second wiring layer;

[0012] A second molding compound covers the second chip module and the lower surface of the substrate, the second molding compound exposing the surface of the second chip module away from the substrate;

[0013] The second heat sink is attached to the lower surface of the second molding layer.

[0014] In an optional embodiment, it further includes an interface module, which is electrically connected to an external power supply terminal and is used to supply power to the first chip module and the second chip module.

[0015] In an optional embodiment, the interface module includes an interface and a power component electrically connected to the interface. The interface is electrically connected to the external power supply terminal via a cable. The power component is used to reduce the external voltage input through the interface to a single voltage or multiple voltages of varying magnitudes, and to supply the reduced voltage to the corresponding first chip module and second chip module.

[0016] In an optional embodiment, the interface module is disposed outside the substrate, and the power components in the interface module are electrically connected to an external interface mounted on the substrate via a connecting cable. The external interface is electrically connected to the first wiring layer and the second wiring layer.

[0017] In one optional embodiment, the interface module is one or more, the power component is embedded in the substrate, the interface is exposed outside the substrate, and the power component is also electrically connected to the first wiring layer and the second wiring layer.

[0018] In an optional embodiment, there are two interface modules, including a first interface module and a second interface module. The first interface module is used to supply power to the first chip module. The first interface module includes a first interface and a first power component electrically connected to the first interface. The first interface is electrically connected to the external power supply terminal via a first cable. The first power component is also electrically connected to the first wiring layer. It is used to reduce the external voltage input through the first interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module. The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply terminal via a second cable. The second power component is also electrically connected to the second wiring layer. It is used to reduce the external voltage input through the second interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module.

[0019] In an optional embodiment, the first power component and the second power component are embedded in the substrate, with the first interface exposed outside the upper surface of the substrate and the second interface exposed outside the lower surface of the substrate.

[0020] In an optional embodiment, each of the power components includes an electrically connected first portion and a plurality of second portions, the first portion being embedded in the substrate, the interface being electrically connected to the first portion, and each second portion being located in a corresponding first chip module and second chip module.

[0021] In one optional embodiment, the first heat sink and the second heat sink are liquid-cooled heat sinks, the first heat sink having a first heat dissipation channel for refrigerant flow, and the second heat sink having a second heat dissipation channel for refrigerant flow.

[0022] In an optional embodiment, it further includes: a third heat sink plate attached to the side of the wafer-scale packaging structure portion, the third heat sink plate being an integral structure with the first heat sink plate and the second heat sink plate, the third heat sink plate having a refrigerant inflow channel and a refrigerant outflow channel, the refrigerant inflow channel being connected to the inlet end of the first heat sink channel and the second heat sink channel respectively, and the refrigerant outflow channel being connected to the outlet end of the first heat sink channel and the second heat sink channel respectively.

[0023] In one optional embodiment, the first wiring layer includes a first passivation layer and a plurality of discrete first wirings located in the first passivation layer; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings located in the second passivation layer.

[0024] In one optional embodiment, the first wiring layer and the second wiring layer may or may not be electrically connected; when the first wiring layer and the second wiring layer are electrically connected, the first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through a third wiring located in the substrate, thereby interconnecting the first chip module and the corresponding second chip module.

[0025] In one alternative embodiment, both the first chip module and the second chip module have one or more semiconductor chips.

[0026] This application also provides a method for forming a wafer-scale packaging structure, including:

[0027] A substrate is provided, the substrate including an opposing upper surface and a lower surface, the upper surface having a first wiring layer formed thereon, and the lower surface having a second wiring layer formed thereon;

[0028] A plurality of discrete first chip modules are mounted on the upper surface of the substrate, and the first chip modules are electrically connected to the first wiring layer.

[0029] A first molding compound is formed covering the first chip module and the upper surface of the substrate, the first molding compound exposing the surface of the first chip module away from the substrate;

[0030] A plurality of discrete second chip modules are mounted on the lower surface of the substrate, and the second chip modules are electrically connected to the second wiring layer.

[0031] A second molding compound is formed covering the second chip module and the lower surface of the substrate, the second molding compound exposing the surface of the second chip module away from the substrate;

[0032] A first heat sink is attached to the upper surface of the first molding layer;

[0033] A second heat sink is attached to the lower surface of the second molding layer.

[0034] In an optional embodiment, the method further includes: providing an interface module electrically connected to an external power supply terminal, which is used at least to supply power to the first chip module and the second chip module.

[0035] In an optional embodiment, the interface module includes an interface and a power component electrically connected to the interface. The interface is electrically connected to the external power supply terminal via a cable. The power component is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module and second chip module. Before mounting the first chip module on the upper surface of the substrate, the power component is embedded in the substrate, and the interface is exposed outside the substrate.

[0036] In an optional embodiment, there are two interface modules, including a first interface module and a second interface module. The first interface module is used to supply power to the first chip module. The first interface module includes a first interface and a first power component electrically connected to the first interface. The first interface is electrically connected to the external power supply terminal via a first cable. The first power component is also electrically connected to the first wiring layer. It is used to reduce the external voltage input through the first interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module. The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply terminal via a second cable. The second power component is also electrically connected to the second wiring layer. It is used to reduce the external voltage input through the second interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module.

[0037] In one optional embodiment, before mounting the first chip module on the upper surface of the substrate, the first power component and the second power component are respectively embedded in the substrate, with the first interface exposed outside the upper surface of the substrate and the second interface exposed outside the lower surface of the substrate.

[0038] In an optional embodiment, the first heat sink and the second heat sink are liquid-cooled heat sinks. The first heat sink has a first heat dissipation channel for refrigerant flow, and the second heat sink has a second heat dissipation channel for refrigerant flow. The first heat sink and the second heat sink are respectively attached to the upper surface of the first plastic sealant and the lower surface of the second plastic sealant by sealant.

[0039] In an optional embodiment, it further includes: a third heat sink plate attached to the side of the wafer-scale packaging structure portion, the third heat sink plate being an integral structure with the first heat sink plate and the second heat sink plate, the third heat sink plate having a refrigerant inflow channel and a refrigerant outflow channel, the refrigerant inflow channel being connected to the inlet end of the first heat sink channel and the second heat sink channel respectively, and the refrigerant outflow channel being connected to the outlet end of the first heat sink channel and the second heat sink channel respectively.

[0040] The advantages of the technical solution in this application are:

[0041] In this application, a plurality of first chip modules and second chip modules are respectively mounted on the upper and lower surfaces of a substrate. The plurality of first chip modules can operate independently (there is no interconnection between the first wiring layer and the second wiring layer) or cooperate (there is an interconnection between the first wiring layer and the second wiring layer) to meet different packaging requirements. While improving the electrical performance of the wafer-scale packaging structure, it can reduce the volume of the wafer-scale packaging structure. The first heat sink and the second heat sink can simultaneously dissipate heat on the front and back of the wafer-scale packaging structure, so that the heat generated by the first chip modules and the second chip modules can be quickly dissipated or released, thereby improving the heat dissipation problem of the wafer-scale packaging structure and further improving the electrical performance of the wafer-scale packaging structure.

[0042] Furthermore, in one embodiment, the wafer-scale packaging structure further includes an interface module, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module and the second chip module. The power supply problem of the wafer-scale packaging structure is solved by setting up the interface module.

[0043] Furthermore, in one embodiment, there are two interface modules, including a first interface module and a second interface module. The first interface module is used to supply power to the first chip module. The first interface module includes a first interface and a first power component electrically connected to the first interface. The first interface is electrically connected to the external power supply terminal via a first cable. The first power component is also electrically connected to the first wiring layer. It is used to reduce the external voltage input through the first interface to a single voltage or multiple voltages of varying magnitudes, and supply the reduced voltage to the corresponding first chip module. The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply terminal via a second cable. The second power component is also electrically connected to the second wiring layer. It is used to reduce the external voltage input through the second interface to a single voltage or multiple voltages of varying magnitudes, and supply the reduced voltage to the corresponding second chip module. This improves the efficiency and speed of supplying power to several first chip modules and several second chip modules.

[0044] Furthermore, in one embodiment, each power component includes an electrically connected first portion and multiple second portions. The first portion is embedded in the substrate, and the interface is electrically connected to the first portion. Each second portion is located in a corresponding first chip module and second chip module. By dividing the aforementioned overall power component into a first portion and a second portion, each of the first and second portions performs different functions of the power component, thereby reducing the size of the first portion and facilitating its embedding in the substrate. Furthermore, each second portion can independently power a corresponding first chip module or second chip module, improving the power supply rate and efficiency.

[0045] Furthermore, in one embodiment, the first wiring layer and the second wiring layer may or may not be electrically connected; when the first wiring layer and the second wiring layer are electrically connected, the first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through a third wiring located in the substrate, thereby interconnecting the first chip module and the corresponding second chip module.

[0046] Furthermore, in one embodiment, it further includes: a third heat sink plate attached to the side of the wafer-scale packaging structure portion, the third heat sink plate being an integral structure with the first heat sink plate and the second heat sink plate, the third heat sink plate having a refrigerant inflow channel and a refrigerant outflow channel, the refrigerant inflow channel being connected to the inlet ends of the first heat sink channel and the second heat sink channel respectively, and the refrigerant outflow channel being connected to the outlet ends of the first heat sink channel and the second heat sink channel respectively, thereby achieving the function of simultaneously dissipating heat on the front and back of the wafer-scale packaging structure, while allowing the first heat sink plate and the second heat sink plate to share a single refrigerant inflow channel. The system includes a refrigerant outflow channel, which simplifies the interface setup for liquid cooling, reduces the risk of leakage, and saves costs. Furthermore, since the third heat sink is an integral structure with the first and second heat sinks, forming a U-shape, with most of the wafer-scale packaging structure located within the opening of the U-shape, the first and second heat sinks press against the wafer-scale packaging structure from above and below, which helps prevent warping or deformation of the wafer-scale packaging structure (especially large-size wafer-scale packaging structures). Attached Figure Description

[0047] Figure 1 A schematic diagram of a wafer-scale packaging structure in one embodiment of this application;

[0048] Figure 2 A schematic diagram of a wafer-scale packaging structure in another embodiment of this application;

[0049] Figure 3 A schematic diagram of a wafer-scale packaging structure in yet another embodiment of this application;

[0050] Figure 4 A schematic diagram of a wafer-scale packaging structure in yet another embodiment of this application;

[0051] Figure 5 A schematic diagram of a wafer-scale packaging structure in yet another embodiment of this application;

[0052] Figure 6 A schematic diagram of a wafer-scale packaging structure in yet another embodiment of this application;

[0053] Figure 7 A schematic diagram of a wafer-scale packaging structure in another embodiment of this application. Detailed Implementation

[0054] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0055] This application firstly provides a wafer-scale packaging structure, and the wafer-scale packaging structure of this application will be described in detail below with reference to the accompanying drawings.

[0056] One embodiment of this application provides a wafer-scale packaging structure, referencing... Figure 1 The wafer-scale packaging structure includes:

[0057] The substrate 101 includes an upper surface and a lower surface opposite to each other, the upper surface having a first wiring layer (not shown in the figure) and the lower surface having a second wiring layer (not shown in the figure).

[0058] A plurality of discrete first chip modules 201 are mounted on the upper surface of the substrate 101, and the first chip modules 201 are electrically connected to the first wiring layer.

[0059] A first molding layer 102 covers the upper surface of the first chip module 201 and the substrate 101, and the first molding layer 102 exposes the surface of the first chip module 201 away from the substrate 101;

[0060] A first heat sink 401 is attached to the upper surface of the first molding layer 102;

[0061] A plurality of discrete second chip modules 202 are mounted on the lower surface of the substrate 101, and the second chip modules 202 are electrically connected to the second wiring layer.

[0062] A second molding compound 103 covers the second chip module 202 and the lower surface of the substrate 101, and the second molding compound 103 exposes the surface of the second chip module 202 away from the substrate 101;

[0063] The second heat sink 402 is attached to the lower surface of the second molding layer 103.

[0064] Specifically, the substrate 101 serves as a support and connection carrier for the wafer-scale packaging structure. In one embodiment, the substrate 101 can be one of a silicon substrate, an RDL (Re-distribution Layer) substrate, a resin substrate, a printed circuit board (PCB), a ceramic substrate, or a glass substrate. In one embodiment, the substrate can be a single-layer board or a multilayer board.

[0065] The substrate 101 includes an upper surface and a lower surface opposite to each other. The upper surface has a first wiring layer (not shown in the figure), and the lower surface has a second wiring layer (not shown in the figure). The first wiring layer is electrically connected to the first chip module 201, and the second wiring layer is electrically connected to the second chip module 202.

[0066] In one embodiment, the first wiring layer includes a first passivation layer and a plurality of discrete first wirings located within the first passivation layer, and adjacent first chip modules 201 can be interconnected through a portion of the first wirings; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings located within the second passivation layer, and adjacent second chip modules 202 can be interconnected through a portion of the first wirings. In one embodiment, the first and second wirings may include one or more of the following: a metal layer, a connector plug, a through-silicon via (TSV) connection structure, a via connection structure, and a metal conductive pillar. The first and second passivation layers may be inorganic or organic insulating materials. The inorganic insulating material may be one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride. The inorganic insulating material may be a polymer, such as polyimide. In one embodiment, the first and second wirings may be single-layer or stacked structures, and the corresponding first and second passivation layers may also be single-layer or multi-layer stacked structures.

[0067] In one embodiment, the substrate 101 may have a large size. When the substrate 101 is circular, the diameter of the substrate 101 may be 300mm±10mm or 450±15mm. When the substrate 101 is square, the diagonal of the substrate 101 may be 300mm±15mm or 450±20mm.

[0068] In one embodiment, the first chip module 201 includes a front side and a back side. The front side of the first chip module 201 has a plurality of first solder bumps 203. When the first chip module 201 is mounted on the upper surface of the substrate 101, the front side of the first chip module 201 faces the upper surface of the substrate, and the first solder bumps 203 on the front side of the first chip module 201 are soldered together with corresponding first wiring on the upper surface of the substrate 101. The second chip module 202 includes a front side and a back side. The front side of the second chip module 202 has a plurality of second solder bumps 204. When the second chip module 202 is mounted on the lower surface of the substrate 101, the front side of the second chip module 202 faces the lower surface of the substrate 101, and the second solder bumps 204 on the front side of the second chip module 202 are soldered together with corresponding second wiring on the lower surface of the substrate 101.

[0069] The first chip module 201 and the second chip module 202 can be chip modules with the same or different functions. A plurality of first chip modules 201 and second chip modules 202 are respectively mounted on the upper and lower surfaces of a substrate 101. The plurality of first chip modules 201 and the plurality of chip modules 202 can operate independently (without interconnection between the first wiring layer and the second wiring layer) or collaboratively (with interconnection between the first wiring layer and the second wiring layer) to meet different packaging requirements. This improves the electrical performance of the wafer-scale package structure while reducing its volume. In one embodiment, both the first chip module 201 and the second chip module 202 have one or more semiconductor chips. In one embodiment, when both the first chip module 201 and the second chip module 202 have multiple semiconductor chips, the functions of the multiple semiconductor chips may be the same or different. In a specific embodiment, when both the first chip module 201 and the second chip module 202 have one or more semiconductor chips, the multiple semiconductor chips may include a logic chip and a memory chip electrically connected to the logic chip. The memory chip is used to store data, and the logic chip is used to control and manage the memory chip. The logic chip includes, but is not limited to, a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a central processing unit (CPU), a microprocessor unit (MPU), a microcontroller unit (MCU), a logic integrated circuit (IC), an application processor (AP), or other known electronic circuits used as processors. The memory chip includes, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), magnetoresistive random access memory (MRAM), phase-change memory (PRAM), and resistive random access memory (RRAM).

[0070] The first molding compound 102 covers the upper surface of the first chip module 201 and the substrate 101, and exposes the surface of the first chip module 201 away from the substrate 101, so as to facilitate the mounting of the first heat sink 401 on the upper surface of the first molding compound 102. The second molding compound 103 covers the lower surface of the second chip module 202 and the substrate 101, and exposes the surface of the second chip module 202 away from the substrate 101, so as to facilitate the mounting of the second heat sink 402 on the lower surface of the second molding compound 103.

[0071] In one embodiment, the materials of the first molding layer 102 and the second molding layer 103 may be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin containing fillers; or they may be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyimide, ethylene-vinyl acetate copolymer, or polyvinyl alcohol containing fillers. In some embodiments, the filler may be inorganic filler or organic filler.

[0072] The first heat sink 401 is used to dissipate or release the heat generated by the plurality of first chip modules 201, and the second heat sink 402 is used to dissipate or release the heat generated by the plurality of second chip modules 202. That is, the first heat sink 401 and the second heat sink 402 can simultaneously dissipate heat from both the front and back sides of the wafer-scale package structure, allowing the heat generated by the first chip modules 201 and the second chip modules 202 to be quickly dissipated or released, thereby improving the heat dissipation problem of the wafer-scale package structure and further enhancing its electrical performance. In one embodiment, the first heat sink 401 and the second heat sink 402 are made of materials with high thermal conductivity, including metals such as copper, aluminum, gold, nickel, steel, or stainless steel.

[0073] In one embodiment, the first heat sink 401 and the second heat sink 402 are liquid-cooled heat sinks. The first heat sink 401 has a first heat dissipation channel for refrigerant flow, and the second heat sink 402 has a second heat dissipation channel for refrigerant flow. When the refrigerant flows in the first and second heat dissipation channels, it can quickly remove the heat from the first heat sink 401 and the second heat sink 402 to further improve the heat dissipation efficiency.

[0074] In one embodiment, the first heat sink 401 and the second heat sink 402 are respectively attached to the upper surface of the first molding layer 102 and the lower surface of the second molding layer 103 with sealant.

[0075] In one embodiment, reference continues Figure 1 The first heat sink 401 and the second heat sink 402 are independent heat sinks, respectively attached to the upper surface of the first molding layer 102 and the lower surface of the second molding layer 103.

[0076] In other embodiments, reference is made to Figure 7 It also includes: a third heat sink 403 mounted on the side of the wafer-scale packaging structure portion, wherein the third heat sink 403 is an integral structure with the first heat sink 401 and the second heat sink 402 (for edge differentiation). Figure 7 (The three are divided by dotted lines). The third heat sink 403 has a refrigerant inflow channel and a refrigerant outflow channel. The refrigerant inflow channel is connected to the inlet end of the first heat sink channel and the second heat sink channel, respectively. The refrigerant outflow channel is connected to the outlet end of the first heat sink channel and the second heat sink channel, respectively. While realizing the function of simultaneously dissipating heat on the front and back of the wafer-scale packaging structure, it allows the first heat sink 401 and the second heat sink 402 to share a refrigerant inflow channel and a refrigerant outflow channel, thereby simplifying the interface settings during liquid cooling and reducing the risk of leakage. This saves costs, and since the third heat sink 403 is an integral structure with the first heat sink 401 and the second heat sink 402, that is, the first heat sink 401, the third heat sink 403 and the second heat sink 402 are in a "U" shape, and most of the wafer-scale packaging structure is located in the opening of the "U" shape, so that the first heat sink 401 and the second heat sink 402 press the wafer-scale packaging structure from above and below, which helps to prevent the wafer-scale packaging structure (especially large-size wafer-scale packaging structures) from warping or deformation.

[0077] In one embodiment, reference continues Figure 1 The wafer-scale packaging structure further includes an interface module 301, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module 201 and the second chip module 202. The power supply problem of the wafer-scale packaging structure is solved by setting up the interface module 301.

[0078] In one embodiment, the interface module 301 includes an interface 303 and a power component 302 electrically connected to the interface 303. The interface 303 is electrically connected to the external power supply terminal via a cable 11. The power component 302 is also electrically connected to the first wiring layer and the second wiring layer, and is used to reduce the external voltage input through the interface 303 to a single voltage or multiple voltages of varying magnitudes, and supply the reduced voltage to the corresponding first chip module 201 and second chip module 202. In a specific embodiment, the interface 303 and the power component 302 are an integral structure packaged together. In other embodiments, the interface 303 and the power component 302 may also be separate structures, interconnected by wiring located in the substrate 101. Specifically, the interface 303 is attached to the upper or lower surface of the edge region of the substrate, and the power component 302 is embedded in the substrate 101. The power component 302 is electrically connected to the interface 303 through a portion of the first wiring in the first wiring layer and a portion of the second wiring in the second wiring layer.

[0079] In one embodiment, the interface module 301 can be used for data transmission in addition to power supply. The interface 303 includes various types of interfaces; besides serving as a power supply interface, the interface 303 can also serve as an input / output interface (I / O) for data transmission. The interface can be connected to the outside via wired and / or wireless means. Wired means include cables or data cables, while wireless means include light waves or electromagnetic waves.

[0080] In one embodiment, the external voltage supplied by the external power supply terminal can be greater than or equal to 48V, 24V-48V, or 5V-24V. The voltage after being reduced by the power component 302 can be 0.5V-12V, specifically 0.5V, 0.7V, 1V, 1.8V, 2V, 2.5V, 3V, 3.5V, 4V, 5V, 6V, 7V, 8V, 9V, 10V, 11V, or 12V.

[0081] In one embodiment, reference continues Figure 1 The interface module 301 is one, and the interface 303 and the power component 302 are also one. The power component 302 is embedded in the substrate 101, and the interface 302 is exposed outside the substrate 101.

[0082] In one embodiment, the substrate 101 includes a central region and an edge region surrounding the central region, wherein the first molding layer 102 and the second molding layer 103 may expose part or all of the edge region, or may cover the edge region. In one embodiment, the power component 302 may be embedded in the edge region of the substrate 101. In another embodiment, the power component 302 may be embedded in the central region of the substrate 101.

[0083] In another embodiment, reference Figure 2 The interface module 301 is one, the interface 303 is one, and the interface 303 is exposed outside the substrate 101. There are multiple power components 302, and each of the multiple power components 302 is electrically connected to one of the interfaces 303. The multiple power components 302 are embedded in the substrate 101. Specifically, the multiple power components 302 can be embedded in the edge area or the middle area of ​​the substrate 101. The multiple power components 302 are electrically connected to the first wiring layer and the second wiring layer. One of the power components 302 can supply the reduced voltage to one or more corresponding first chip modules 201, or to one or more corresponding second chip modules 202. Figure 2 The power component 302 described herein is two, and the two power components 302 are embedded in the edge region of the substrate 101. This is merely an example and should not limit the scope of protection of this application.

[0084] In another embodiment, there may be multiple interface modules 301, specifically two or more. Each interface module 301 can simultaneously supply power to multiple first chip modules 201 or multiple second chip modules 202 to improve the efficiency and speed of power supply.

[0085] In yet another embodiment, reference is made to Figure 3The interface module comprises two modules: a first interface module 301a and a second interface module 301b. The first interface module 301a supplies power to the first chip module 201. The first interface module 301a includes a first interface 303a and a first power component 302a electrically connected to the first interface 303a. The second power component 302a is embedded in the substrate 101 (specifically, it can be embedded in the edge or middle region of the substrate 101). The first interface 303a is exposed on the upper surface of the substrate 101 and is electrically connected to the external power supply terminal via a first cable 11a. The first power component 302a is also electrically connected to the first wiring layer. The first interface module 301a is used to reduce the external voltage input through the first interface 303a to a single voltage or multiple voltages of varying magnitudes, and then supplies the reduced voltage to the corresponding first chip module 201. In one specific embodiment, there is one first interface 11a, and one or more first power components 302a. When there are multiple first power components 302a, the multiple first power components 302a are electrically connected to one first interface 11a. Each first power component 302a is used to supply a reduced voltage to one or more corresponding first chip modules 201, so as to improve the efficiency and rate of power supply to the multiple first chip modules 201, and improve the stability and performance of the multiple first chip modules 201. The second interface module 301b is used to supply power to the second chip module 202. The second interface module 301b includes a second interface 303b and a second power component 302b electrically connected to the second interface 303b. The second interface 303b is electrically connected to the external power supply terminal through the second cable 11b. The second power component 302b is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface 303b to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module 202. In one specific embodiment, there is one second interface 11b, and there can be one or more second power components 302b. When there are multiple second power components 302b, the multiple second power components 302b are electrically connected to one second interface 11b. Each second power component 302b is used to supply the reduced voltage to one or more corresponding second chip modules 202, so as to improve the efficiency and rate of power supply to the multiple second chip modules 202, and improve the stability and performance of the multiple second chip modules 202.

[0086] In another embodiment, each power component includes an electrically connected first portion and multiple second portions. The first portion is embedded in the substrate 101, and the interface 303 is electrically connected to the first portion. Each second portion is located in a corresponding first chip module and second chip module. The aforementioned overall power component is divided into a first portion and a second portion, each performing different functions of the power component. This reduces the size of the first portion, facilitating its embedding in the substrate 101. Furthermore, each second portion can independently power a corresponding first chip module 201 or second chip module 202, improving power supply speed and efficiency. In a specific embodiment, the first portion is used to reduce the external voltage input to the interface 303 to an initial voltage, which is less than the external voltage. The second portion is used to reduce the initial voltage to a terminal voltage, which is less than the initial voltage. The terminal voltage is supplied to the corresponding first chip module 201 and second chip module 202. Specifically, refer to... Figure 4 The first interface module 301a includes a first power component electrically connected to a first interface 303a. The first power component includes a first portion 302a1 and a plurality of second portions 302a2 electrically connected to the first portion 302a1. The first portion 302a1 of the first power component is embedded in the substrate 101, and each second portion 302a2 of the first power component is located in a corresponding first chip module 201. The second interface module 301b includes a second power component electrically connected to a second interface 303b. The second power component includes a first portion 302b1 and a plurality of second portions 302b2 electrically connected to the first portion 302b1. The first portion 302b1 of the second power component is embedded in the substrate 101, and each second portion 302b2 of the second power component is located in a corresponding second chip module 202.

[0087] In one embodiment, the first wiring in the first wiring layer and the second wiring in the second wiring layer are not interconnected or electrically connected, that is, there is no communication and / or data transmission between the first chip module 201 on the upper surface of the substrate 101 and the second chip module 202 on the lower surface of the substrate 101, and they operate independently.

[0088] In another embodiment, reference Figure 5The first wiring in the first wiring layer is interconnected or electrically connected to the second wiring in the second wiring layer. The first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through the third wiring 104 located in the substrate 101, thereby interconnecting the first chip module 201 with the corresponding second chip module 202. This enables communication and / or data transmission between the first chip module 201 on the upper surface of the substrate 101 and the second chip module 202 on the lower surface of the substrate 101, allowing the first chip module 201 and the second chip module 202 to operate simultaneously, greatly improving the performance of the wafer-scale packaging structure (such as increasing computing power).

[0089] In yet another embodiment, reference is made to Figure 6 An external interface 304 is mounted on the upper surface of the substrate 101. The external interface 304 is electrically connected to the corresponding first chip module 201 and second chip module 202 through the first wiring layer and the second wiring layer. The interface module 301 is disposed outside the substrate 101. The interface 303 in the interface module 301 is electrically connected to an external power supply terminal through a cable 11. The power component 303 in the interface module 301 is electrically connected to the external interface 304 through a connecting cable 305. The power component 302 reduces the external voltage input through the interface 303 to one voltage or multiple voltages of different magnitudes, and transmits the reduced voltage to the external interface 304 through the connecting cable 305. The external interface 304 supplies the reduced voltage to the corresponding first chip module 201 and second chip module 202 through the first wiring layer and the second wiring layer.

[0090] It should be noted that the same or similar parts in the foregoing embodiments of this application are not repeated in each embodiment, and can be referred to or understood in each other.

[0091] This application also provides a method for forming a wafer-scale packaging structure. In one embodiment, referring to... Figure 1 The forming method includes:

[0092] A substrate 101 is provided, the substrate 101 includes an upper surface and a lower surface opposite to each other, the upper surface having a first wiring layer (not shown in the figure) formed thereon, and the lower surface having a second wiring layer (not shown in the figure).

[0093] A plurality of discrete first chip modules 201 are mounted on the upper surface of the substrate 101, and the first chip modules 201 are electrically connected to the first wiring layer.

[0094] A first molding layer 102 is formed to cover the first chip module 201 and the upper surface of the substrate 101, and the first molding layer 102 exposes the surface of the first chip module 201 away from the substrate 101;

[0095] A plurality of discrete second chip modules 202 are mounted on the lower surface of the substrate 101, and the second chip modules 202 are electrically connected to the second wiring layer.

[0096] A second molding compound 103 is formed covering the second chip module 202 and the lower surface of the substrate 101, and the second molding compound 103 exposes the surface of the second chip module away from the substrate;

[0097] A first heat sink 401 is attached to the upper surface of the first molding layer 102;

[0098] A second heat sink 402 is attached to the lower surface of the second molding layer 103.

[0099] In one embodiment, the system further includes: providing an interface module 301, which is electrically connected to an external power supply terminal and is used at least to supply power to the first chip module 201 and the second chip module 202.

[0100] In one embodiment, the interface module 301 includes an interface 303 and a power component 302 electrically connected to the interface 303. The interface 303 is electrically connected to the external power supply terminal via a cable 11. The power component 302 is also electrically connected to the first wiring layer and the second wiring layer. It is used to reduce the external voltage input through the interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module 201 and second chip module 202. Before mounting the first chip module 201 on the upper surface of the substrate 101, the power component 302 is embedded in the substrate 101, and the interface 303 is exposed outside the substrate 101.

[0101] In one embodiment, the interface module may be one or more.

[0102] In one embodiment, there are two interface modules, as shown in the reference. Figure 3The system includes a first interface module 301a and a second interface module 301b. The first interface module 301a supplies power to the first chip module 201. The first interface module 301a includes a first interface 303a and a first power component 302a electrically connected to the first interface 303a. The second power component 302a is embedded in the substrate 101 (specifically, it can be embedded in the edge area or the middle area of ​​the substrate 101). The first interface 303a is exposed outside the upper surface of the substrate 101. The first interface 303a is electrically connected to the external power supply terminal through a first cable 11a. The first power component 302a is also electrically connected to the first wiring layer. The system is used to reduce the external voltage input through the first interface 303a to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module 201. In one specific embodiment, there is one first interface 11a, and one or more first power components 302a. When there are multiple first power components 302a, the multiple first power components 302a are electrically connected to one first interface 11a. Each first power component 302a is used to supply a reduced voltage to one or more corresponding first chip modules 201, so as to improve the efficiency and rate of power supply to the multiple first chip modules 201, and improve the stability and performance of the multiple first chip modules 201. The second interface module 301b is used to supply power to the second chip module 202. The second interface module 301b includes a second interface 303b and a second power component 302b electrically connected to the second interface 303b. The second interface 303b is electrically connected to the external power supply terminal through the second cable 11b. The second power component 302b is also electrically connected to the second wiring layer, and is used to reduce the external voltage input through the second interface 303b to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module 202. In one specific embodiment, there is one second interface 11b, and there can be one or more second power components 302b. When there are multiple second power components 302b, the multiple second power components 302b are electrically connected to one second interface 11b. Each second power component 302b is used to supply the reduced voltage to one or more corresponding second chip modules 202, so as to improve the efficiency and rate of power supply to the multiple second chip modules 202, and improve the stability and performance of the multiple second chip modules 202.

[0103] In one embodiment, before mounting the first chip module 201 on the upper surface of the substrate, the first power component 302a and the second power component 302b are respectively embedded in the substrate 101, the first interface 303a is exposed outside the upper surface of the substrate 101, and the second interface 303b is exposed outside the lower surface of the substrate 101.

[0104] In one embodiment, the first heat sink 401 and the second heat sink 402 are liquid-cooled heat sinks. The first heat sink 401 has a first heat dissipation channel for refrigerant flow, and the second heat sink 402 has a second heat dissipation channel for refrigerant flow. The first heat sink 401 and the second heat sink 402 are respectively attached to the upper surface of the first molding layer 102 and the lower surface of the second molding layer 103 with sealant.

[0105] In one embodiment, reference Figure 7 It also includes a third heat sink 403 mounted on the side of the wafer-scale packaging structure portion. The third heat sink 403 is an integral structure with the first heat sink 401 and the second heat sink 402. The first heat sink 401, the second heat sink 402 and the third heat sink 403 are mounted simultaneously. The third heat sink 403 has a refrigerant inflow channel and a refrigerant outflow channel. The refrigerant inflow channel is connected to the inlet end of the first heat sink channel and the second heat sink channel respectively. The refrigerant outflow channel is connected to the outlet end of the first heat sink channel and the second heat sink channel respectively.

[0106] It should be noted that the parts that are the same as or similar to those in the previous embodiments (wafer-scale packaging structure) in this embodiment will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the previous embodiments for details.

[0107] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A wafer-scale packaging structure, characterized in that, include: A substrate, the substrate including an opposing upper surface and a lower surface, the upper surface having a first wiring layer and the lower surface having a second wiring layer; A plurality of discrete first chip modules are mounted on the upper surface of the substrate, and the first chip modules are electrically connected to the first wiring layer. A first molding compound covers the first chip module and the upper surface of the substrate, the first molding compound exposing the surface of the first chip module away from the substrate; A first heat sink plate is attached to the upper surface of the first molding layer; A plurality of discrete second chip modules are mounted on the lower surface of the substrate, and the second chip modules are electrically connected to the second wiring layer; A second molding compound covers the second chip module and the lower surface of the substrate, the second molding compound exposing the surface of the second chip module away from the substrate; A second heat sink is attached to the lower surface of the second plastic seal layer. The first heat sink and the second heat sink are liquid-cooled heat sinks. The first heat sink has a first heat dissipation channel for refrigerant flow, and the second heat sink has a second heat dissipation channel for refrigerant flow. The third heat sink is attached to the side of the wafer-scale packaging structure. The third heat sink is an integral structure with the first heat sink and the second heat sink. The third heat sink has a refrigerant inflow channel and a refrigerant outflow channel. The refrigerant inflow channel is connected to the inlet end of the first heat sink channel and the second heat sink channel, respectively. The refrigerant outflow channel is connected to the outlet end of the first heat sink channel and the second heat sink channel, respectively.

2. The wafer-scale packaging structure as described in claim 1, characterized in that, Also includes: An interface module is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module and the second chip module.

3. The wafer-scale packaging structure as described in claim 2, characterized in that, The interface module includes an interface and a power component electrically connected to the interface. The interface is electrically connected to the external power supply terminal via a cable. The power component is used to reduce the external voltage input through the interface to a single voltage or multiple voltages of varying magnitudes, and to supply the reduced voltage to the corresponding first chip module and second chip module.

4. The wafer-scale packaging structure as described in claim 3, characterized in that, The interface module is disposed outside the substrate. The power component in the interface module is electrically connected to an external interface mounted on the substrate via a connecting cable. The external interface is electrically connected to the first wiring layer and the second wiring layer.

5. The wafer-scale packaging structure as described in claim 3, characterized in that, The interface module is one or more, the power component is embedded in the substrate, the interface is exposed outside the substrate, and the power component is also electrically connected to the first wiring layer and the second wiring layer.

6. The wafer-scale packaging structure as described in claim 5, characterized in that, The interface module consists of two modules, including a first interface module and a second interface module. The first interface module is used to supply power to the first chip module. The first interface module includes a first interface and a first power component electrically connected to the first interface. The first interface is electrically connected to the external power supply terminal through a first cable. The first power component is also electrically connected to the first wiring layer. The first interface module is used to reduce the external voltage input through the first interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module. The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply terminal through a second cable. The second power component is also electrically connected to the second wiring layer. It is used to reduce the external voltage input through the second interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module.

7. The wafer-scale packaging structure as described in claim 6, characterized in that, The first power component and the second power component are embedded in the substrate, with the first interface exposed outside the upper surface of the substrate and the second interface exposed outside the lower surface of the substrate.

8. The wafer-scale packaging structure as described in claim 5 or 6, characterized in that, Each of the power components includes a first part and a plurality of second parts that are electrically connected. The first part is embedded in the substrate, and the interface is electrically connected to the first part. Each second part is located in a corresponding first chip module and second chip module.

9. The wafer-scale packaging structure as described in claim 1, characterized in that, The first wiring layer includes a first passivation layer and a plurality of discrete first wirings located in the first passivation layer; the second wiring layer includes a second passivation layer and a plurality of discrete second wirings located in the second passivation layer.

10. The wafer-scale packaging structure as described in claim 1, characterized in that, The first wiring layer and the second wiring layer may or may not be electrically connected; when the first wiring layer and the second wiring layer are electrically connected, the first wiring in the first wiring layer and the corresponding second wiring in the second wiring layer are electrically connected through a third wiring located in the substrate, thereby interconnecting the first chip module and the corresponding second chip module.

11. The wafer-scale packaging structure as described in claim 10, characterized in that, Both the first chip module and the second chip module have one or more semiconductor chips.

12. A method for forming a wafer-scale packaging structure, characterized in that, include: A substrate is provided, the substrate including an opposing upper surface and a lower surface, the upper surface having a first wiring layer formed thereon, and the lower surface having a second wiring layer formed thereon; A plurality of discrete first chip modules are mounted on the upper surface of the substrate, and the first chip modules are electrically connected to the first wiring layer. A first molding compound is formed covering the first chip module and the upper surface of the substrate, the first molding compound exposing the surface of the first chip module away from the substrate; A plurality of discrete second chip modules are mounted on the lower surface of the substrate, and the second chip modules are electrically connected to the second wiring layer. A second molding compound is formed covering the second chip module and the lower surface of the substrate, the second molding compound exposing the surface of the second chip module away from the substrate; A first heat sink is attached to the upper surface of the first molding layer; A second heat sink is attached to the lower surface of the second plastic seal layer. The first heat sink and the second heat sink are liquid-cooled heat sinks. The first heat sink has a first heat dissipation channel for refrigerant flow, and the second heat sink has a second heat dissipation channel for refrigerant flow. The first heat sink and the second heat sink are respectively attached to the upper surface of the first plastic seal layer and the lower surface of the second plastic seal layer with sealant. A third heat sink is mounted on the side of the wafer-scale packaging structure. The third heat sink is an integral structure with the first heat sink and the second heat sink. The third heat sink has a refrigerant inflow channel and a refrigerant outflow channel. The refrigerant inflow channel is connected to the inlet end of the first heat sink channel and the second heat sink channel, respectively. The refrigerant outflow channel is connected to the outlet end of the first heat sink channel and the second heat sink channel, respectively.

13. The method for forming a wafer-scale packaging structure as described in claim 12, characterized in that, Also includes: An interface module is provided, which is electrically connected to an external power supply terminal and is used to supply power to at least the first chip module and the second chip module.

14. The method for forming a wafer-scale packaging structure as described in claim 13, characterized in that, The interface module includes an interface and a power component electrically connected to the interface. The interface is electrically connected to the external power supply terminal via a cable. The power component is also electrically connected to the first wiring layer and the second wiring layer. It is used to reduce the external voltage input through the interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module and second chip module. Before mounting the first chip module on the upper surface of the substrate, the power component is embedded in the substrate, and the interface is exposed outside the substrate.

15. The method for forming a wafer-scale packaging structure as described in claim 14, characterized in that, The interface module consists of two modules, including a first interface module and a second interface module. The first interface module is used to supply power to the first chip module. The first interface module includes a first interface and a first power component electrically connected to the first interface. The first interface is electrically connected to the external power supply terminal through a first cable. The first power component is also electrically connected to the first wiring layer. The first interface module is used to reduce the external voltage input through the first interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding first chip module. The second interface module is used to supply power to the second chip module. The second interface module includes a second interface and a second power component electrically connected to the second interface. The second interface is electrically connected to the external power supply terminal through a second cable. The second power component is also electrically connected to the second wiring layer. It is used to reduce the external voltage input through the second interface to a single voltage or multiple voltages of different magnitudes, and supply the reduced voltage to the corresponding second chip module.

16. The method for forming a wafer-scale packaging structure as described in claim 15, characterized in that, Before mounting the first chip module on the upper surface of the substrate, the first power component and the second power component are respectively embedded in the substrate, with the first interface exposed outside the upper surface of the substrate and the second interface exposed outside the lower surface of the substrate.

Images