Semiconductor device with spaced supply voltage and ground reference

Abstract

A semiconductor device with spaced supply voltages and a ground reference is disclosed. The semiconductor die stack includes a first semiconductor die, one or more second semiconductor dies, and first and second contacts. A gap filler is disposed over a distal end of the one or more second semiconductor dies opposite the first semiconductor die. A first rail (e.g., a supply voltage) is disposed at a distal end of the gap filler opposite the first semiconductor die, and a first via extends from the first rail to the first contact. A dielectric material layer is disposed at least partially over the first rail. A second rail (e.g., a ground reference) is disposed at the dielectric material layer, and a second via extends from the second rail to the second contact. Third and fourth exposed contacts are coupled to the first and second rails, respectively.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor device assemblies, and more particularly to semiconductor devices having spaced supply voltages and ground references. Background Art

[0002] A microelectronic device typically has a die (e.g., a chip) that includes an integrated circuit system with a high density of very small components. Typically, the die includes an array of bonding pads that are electrically coupled to the integrated circuit system. The bonding pads are external electrical contacts through which supply voltages, signals, etc. are transmitted to and from the integrated circuit system. After the die is formed, it is "packaged" to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional processes for packaging the die include electrically coupling the bonding pads on the die to an array of leads, ball pads, or other types of electrical terminals and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical shock. Summary of the invention

[0003] One aspect of the present disclosure discloses a semiconductor device assembly, comprising: a semiconductor die stack including a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to a circuit system at the semiconductor die stack, and at least one second contact coupled to the circuit system at the semiconductor die stack; a gap filler at least partially surrounding the semiconductor die stack and disposed on a distal end of the one or more second semiconductor dies opposite to the first semiconductor die; one or more first rails disposed at a distal end of the gap filler opposite to the first semiconductor die; at least one first via extending from the one or more first rails to the at least one first contact; and a dielectric material layer. , which is at least partially disposed on the one or more first rails; one or more second rails disposed at the dielectric material layer; at least one second via extending from the one or more second rails beyond the one or more first rails to the at least one second contact; one or more third contacts coupled to the one or more first rails and exposed at a far end of the semiconductor device assembly opposite to the first semiconductor die; and one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly, wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other of the source voltage rail or the ground reference rail.

[0004] Another aspect of the present disclosure discloses a method for manufacturing a semiconductor device assembly, comprising: providing a semiconductor die stack, the semiconductor die stack comprising a first semiconductor die, one or more second semiconductor die, at least one first contact coupled to a circuit system at the semiconductor die stack, and at least one second contact coupled to the circuit system at the semiconductor die stack; disposing a gap filler at least partially surrounding the semiconductor die stack and over a distal end of the one or more second semiconductor die opposite to the first semiconductor die; disposing at least one first via from a distal end of the gap filler opposite to the first semiconductor die through the gap filler to the at least one first contact; disposing a first portion of at least one second via from the distal end of the gap filler through the gap filler to the at least one second contact; disposing one or more first rails at the end and at least one first via; disposing a dielectric material layer at least partially over the one or more first rails; disposing a second portion of the at least one second via passing through the dielectric material layer to the first portion of the at least one second via; disposing one or more second rails at the dielectric material layer and the at least one second via; disposing one or more third contacts coupled to the one or more first rails and exposed at a far end of the semiconductor device assembly relative to the first semiconductor die; and disposing one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly relative to the first semiconductor die, wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other of the source voltage rail or the ground reference rail.

[0005] Another aspect of the present disclosure discloses a semiconductor device assembly, comprising: a semiconductor die stack, comprising a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to a circuit system at the semiconductor die stack, and at least one second contact coupled to the circuit system at the semiconductor die stack; a gap filler at least partially surrounding the semiconductor die stack and disposed on a distal end of the one or more second semiconductor dies opposite to the first semiconductor die; one or more first rails having a first footprint; at least one first via extending from the one or more first rails to the at least one first contact; a dielectric material layer at least partially disposed on the one or more first rails; one or more second rails disposed between the one or more first rails; and a dielectric material layer disposed at least partially on the one or more first rails. at a dielectric material layer, the one or more second rails being electrically isolated from the one or more first rails and having a second footprint, wherein the second footprint partially overlaps the first footprint; at least one second via extending from the one or more second rails beyond the one or more first rails to the at least one second contact; one or more third contacts coupled to the one or more first rails and exposed at a far end of the semiconductor device assembly opposite to the first semiconductor die; and one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly, wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other of the source voltage rail or the ground reference rail. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Simplified schematic cross-sectional diagram illustrating a semiconductor device assembly in accordance with an embodiment of the present technology.

[0007] Figure 2 A simplified schematic partial plan view illustrating a semiconductor device assembly in accordance with an embodiment of the present technology.

[0008] Figures 3 to 7 Simplified schematic cross-sectional diagram illustrating a series of steps for fabricating a semiconductor device assembly in accordance with an embodiment of the present technology.

[0009] Figure 8 Schematic diagram illustrating a system including a semiconductor device assembly configured in accordance with embodiments of the present technology.

[0010] Fig. 9 A method of manufacturing a semiconductor device assembly according to an embodiment of the present technology is described. DETAILED DESCRIPTION

[0011] Multiple semiconductor dies can be packaged into a single semiconductor device that can operate cooperatively and provide specific functionality; however, these designs also bring various challenges. For example, due to the increase in heat generated by multiple dies within a single package, the semiconductor device may be at risk of overheating. These densely packed structures require complex wiring, which determines the positioning of the semiconductor die within the package. For example, semiconductor dies that contain dense circuit systems or require a large number of external connections (such as power, ground, input / output (I / O)) to operate are positioned within the package at locations that prioritize connectivity rather than thermal advantages. However, typically, these same semiconductor dies (such as logic dies) generate the largest amount of heat due to the density of circuit systems within them or the large power distribution required to operate these dies. Therefore, semiconductor devices can benefit from alternative thermal regulation technologies, especially those that prioritize heat dissipation from semiconductor devices (such as logic dies) that generate a lot of heat.

[0012] Take, for example, a memory device that includes a logic die (e.g., a memory controller or interface die) and one or more memory dies within a single package. In one design, the memory die may be stacked onto the logic die such that the logic die is placed at the bottom of the package. In these designs, the semiconductor die that generates the greatest amount of heat (the logic die) is positioned farthest from the upper surface of the package through which the heat can be most efficiently dissipated (e.g., due to thermal components disposed therein, such as heat sinks and heat spreaders). As a result, this design may suffer from poor thermal regulation, which can damage the device and reduce the efficiency of the device.

[0013] Compared to this design, when a high heat generating die is implemented at the top of the package (e.g., a logic die is implemented above one or more memory dies), heat can be more easily dissipated from the logic die through the upper surface of the package. However, in this arrangement, it may be difficult to implement several external connections required to provide sufficient connectivity to the logic die. For example, external connectivity can be provided by implementing through-paths through the memory die stacked on the logic die. When a large number of through-paths through the memory die are implemented, these through-paths can utilize a large portion of the circuit area on the memory die. Thereby, the space available for the circuit system implemented on the memory die can be limited, which can increase the wiring complexity or reduce the memory capacity, efficiency or reliability. In addition, there may be little flexibility in the location where these through-paths are implemented. Therefore, when the signals that need to be carried by the through-paths are away from these paths, a large amount of circuit system is required to carry the signals to their appropriate locations, thereby increasing the circuit density and device cost.

[0014] To address these issues and others, the present technology relates to a semiconductor device with a spaced supply voltage and ground reference. The semiconductor device may include a semiconductor die stack having a first semiconductor die, one or more second semiconductor die, and first and second contacts coupled to a circuit system at the semiconductor die stack. A gap filler may be disposed at least partially around the semiconductor die stack and disposed on a distal end of the one or more second semiconductor die opposite the first semiconductor die to mechanically support the semiconductor device. One or more first rails (e.g., supply voltage rails or ground reference rails) are disposed at a distal end of the gap filler opposite the first semiconductor die, and a first path extends from the first rail to the first contact. In this way, the first path can carry a signal (e.g., a supply voltage signal or a ground signal) from the first rail to the first contact. In some cases, an additional path may extend from the first rail to the semiconductor die stack to provide an additional connection to the signal carried by the first rail. A dielectric material layer is disposed at least partially on the first rail. One or more second rails (e.g., supply voltage rails or ground reference rails) are disposed at the dielectric material layer, and a second path extends from the second rail to the second contact. Thereby, the signal carried by the second rail can be communicated to the semiconductor die stack. The third and fourth contacts are coupled to the first and second rails, respectively. The third and fourth contacts can be exposed to the periphery of the semiconductor device so that the contacts can be coupled to an external component to enable signals to be communicated between the external component and the semiconductor die stack.

[0015] In some embodiments, the one or more fifth contacts may be exposed to the periphery of the semiconductor device. A third via extends from the one or more fifth contacts through the gap filler and dielectric material layer and is coupled to the semiconductor die stack. The third via may be laterally spaced from the first rail and the second rail such that the third via is electrically isolated from the first rail and the second rail. In some cases, the fifth contact and the third via may be used to communicate input signaling and output signaling to / from the semiconductor device.

[0016] The present technology provides many advantages, some of which are discussed in this article. First, the first rail and the second rail can be spaced vertically from each other. In this way, the wiring of the first rail and the second rail can be routed into an additional arrangement that was previously prohibited due to overlap when implementing these rails at the same level. Therefore, the path can extend to the semiconductor die stack at more locations, thereby improving the design flexibility of the semiconductor device and enabling the implementation of additional wiring schemes. In yet other aspects, the location where the path can be implemented is not limited to the area within the occupied area of ​​the second semiconductor die stacked on the first semiconductor die. Instead, the path can be placed at any location through the gap filler, including at a portion of the first semiconductor die exposed outside the second semiconductor die. The additional design flexibility provided by the ability to implement the path in the gap filler enables the implementation of additional wiring schemes. As another advantage, the present technology allows the implementation of high-heat-generating die (such as logic die) at the top of the package while providing sufficient connectivity to these die. Thereby, the semiconductor device can have improved thermal properties.

[0017] Figure 1 A semiconductor device assembly 100 is illustrated that includes a semiconductor die stack 102 that includes a semiconductor die 104 (e.g., a logic die) and one or more semiconductor die 106 (e.g., a memory die) coupled to each other and the semiconductor die 104 (e.g., electrically and mechanically). The semiconductor die 106 may be coupled to each other or the semiconductor die 104 by any suitable technique (e.g., hybrid bonding). In some implementations, the semiconductor device assembly 100 is a memory device. In this manner, the semiconductor die 104 may implement an interface die or a memory controller, and the semiconductor die 106 may include a memory die. In some embodiments, the semiconductor die 104 requires sufficient connectivity to receive power, ground, I / O, or other signaling from external components to which the semiconductor device assembly 100 is coupled.

[0018] Metallization layers with circuitry such as transistors, diodes, traces, lines, vias, and other circuit elements may be disposed at the front sides of the semiconductor die 106 and the semiconductor die 104. The semiconductor die 106 may be coupled with the semiconductor die 104 such that the front side of the semiconductor die 106 faces the semiconductor die 104. In other cases, the back side of the semiconductor die 106 opposite the front side may face the semiconductor die 104. The semiconductor die 104 may face the semiconductor die 106 such that the front side of the semiconductor die 104 faces the front side of the semiconductor die 106. In other embodiments, the semiconductor die 104 may face away from the semiconductor die 106 such that the back side of the semiconductor die opposite the front side faces the semiconductor die 106. The semiconductor die stack 102 may be coupled by any suitable circuitry. For example, the interconnects between the semiconductor die stack 102 may be implemented using any number of traces, lines, vias, contact pads, through silicon vias (TSVs), or any other connection circuitry.

[0019] The semiconductor die 104 may have a larger footprint than the footprint of the semiconductor die 106. Thus, a portion of the semiconductor die 104 may be exposed outside the footprint of the semiconductor die 106. A gap filler 108, such as a dielectric filler (e.g., silicon oxide, silicon nitride, silicon carbide, or silicon carbon nitride), an oxide filler (e.g., silicon oxide), or a molding resin is disposed at least partially around the semiconductor die stack 102. For example, the gap filler 108 may be disposed at the semiconductor die 104, around the semiconductor die 106, and on a distal end of the semiconductor die 106 opposite the semiconductor die 104.

[0020] One or more rails 110 may be disposed at a distal end of the gap filler opposite the semiconductor die 104. One or more rails 110 may include a conductive material capable of conveying signaling. Rails 110 may be configured to carry specific signals to the semiconductor die stack 102. For example, rails 110 may be configured to convey such signals or serve as a ground reference by connecting (e.g., by connecting circuitry, such as traces, lines, vias, or contact pads) to contacts arranged in a location where it is desired to attach to an external component capable of providing a source voltage signal and contacts configured to receive such signals. One or more vias 112 (e.g., via 112-1 and via 112-2) may extend from rails 110 through gap filler 108 to contacts 114 (e.g., contact 114-1 and contact 114-2) coupled to circuitry at the semiconductor die stack 102. Any number of vias 112 may extend from rails 110. For example, multiple passages 112 may extend from a single one of the rails 110 and may be spaced across the long axis of the rail 110 along which the rail 110 extends. As illustrated, passage 112-1 and passage 112-2 extend from the same one of the rails 110 at different lateral locations.

[0021] As illustrated, the vias 112 are coupled to contacts 114 exposed at a distal end of the semiconductor die 106 opposite the semiconductor die 104. In some cases, the contacts 114 may be connected to circuitry (e.g., contact pads, traces, lines, vias, transistors, diodes, or other circuit elements) at the semiconductor die 104 by vias extending from the contacts 114 through the semiconductor die 106 (e.g., not connected to circuitry at metallization layers on these dies). In other cases, the contacts 114 may be connected to circuitry at the semiconductor die 104 through metallization layers at the semiconductor die 106 and interconnects that couple the semiconductor die stack 102 to each other. In still other aspects, the contacts 114 are not connected to circuitry at the semiconductor die 104, but are connected to circuitry at one or more of the semiconductor dies 106. Thus, the vias 112 may be connected to any subset of semiconductor dies within the semiconductor die stack 102, either directly or by routing through metallization layers within any subset of the semiconductor dies of the semiconductor die stack 102.

[0022] Although vias 112 are illustrated as extending from within the footprint of semiconductor die 106 to the dies, vias 112 may alternatively or additionally extend from a portion of rail 110 outside the footprint of second semiconductor die 106. Vias 112 may extend outside the footprint of semiconductor die 106 through gap filler 108 to contacts at exposed portions of semiconductor die 104. Thus, vias 112 may extend between rail 110 and semiconductor die 104 and not extend through semiconductor die 106.

[0023] A dielectric material layer 116 (e.g., silicon oxide, silicon nitride, silicon carbide, silicon nitride carbon, or any other dielectric material) may be disposed at a distal end of gap filler 108 opposite semiconductor die 104. Dielectric material layer 116 may be disposed at least partially over rails 110 to insulate rails 110 from other circuitry at dielectric material layer 116. For example, one or more rails 118 may be disposed at dielectric material layer 116 and vertically spaced apart from rails 110 (e.g., along an axis normal to rails 118 or a plane along which rails 110 extend). In this manner, rails 110 and rails 118 may be vertically separated by at least a portion of dielectric material layer 116. Rails 118 may be exposed at a periphery of semiconductor device assembly 100 (e.g., at a distal end of semiconductor device assembly 100 opposite semiconductor die 104). In other cases, the rails 118 may be at least partially embedded within the dielectric material layer 116, and the contacts coupled to the rails 118 (eg, as shown in FIG. 1 ) may be at least partially embedded within the dielectric material layer 116. Figure 2 ) may be exposed at the periphery of the semiconductor device assembly 100 to enable external components to be electrically coupled to the rails 118.

[0024] Rails 118 (rails 118-1 and rails 118-2) may be implemented similarly to rails 110. For example, rails 118 may include a conductive material capable of conveying signaling. In certain aspects, rails 118 and rails 110 may be used to carry different kinds of signals. For example, rails 110 may be used to carry source voltage signals and rails 118 may carry ground signaling, or vice versa. Rails 110 and rails 118 extend in a substantially vertical direction (e.g., between 80 and 110 degrees, between 85 and 95 degrees, between 89 and 91 degrees). For example, in Figure 1 In the cross-section illustrated in FIG. 1 , rail 110 is shown extending along the major axis and rail 118 is shown having a thickness along the minor axis. Rails 118 may be spaced along the major axis of rail 110. Thus, Figure 1 The cross section illustrated in FIG. 1 includes the ends of rails 118-1 and 118-2 spaced laterally from each other. The arrangement of rails 110 and 118 in FIG. Figure 2 Further explanation in.

[0025] One or more vias 120 (e.g., via 120-1 and via 120-2) extend from rail 118 to contacts 122 (e.g., contact 122-1 and contact 122-2) at semiconductor die stack 102. Vias 120 and contacts 122 are embedded within semiconductor device assembly 100 such that they are Figure 1 100; components embedded in semiconductor device assembly 100 are hidden in this view and are therefore illustrated as dashed lines. Vias 120 may be implemented similarly to vias 112. For example, vias 120 may be spaced along the long axis of rails 118 and extend through gap filler 108. Given that rails 118 are implemented at dielectric material layer 116, vias 120 may extend through dielectric material layer 116, beyond rails 110.

[0026] As illustrated, via 120-1 is coupled to contact 122-1 exposed at a distal end of semiconductor die 106 opposite semiconductor die 104. Contact 122-1 may be connected to semiconductor die 104 or any other of semiconductor die 106 directly (e.g., using a through via that is not connected to circuitry at a metallization layer of the die through which it passes) or indirectly (e.g., by routing through circuitry at a metallization layer of a discontinuous die). As with via 112, in some embodiments, via 120 may extend from within a footprint of semiconductor die 106 or from outside of a footprint of semiconductor die 106. For example, as illustrated, via 120-2 extends through dielectric material layer 116 and gap filler 108 to contact 122-2, which is disposed at an exposed portion of semiconductor die 104 outside of a footprint of semiconductor die 106. In this manner, the via 120 - 2 may extend outside the footprint of the semiconductor die 106 through the gap filler 108 to directly couple the rail 118 - 2 and the contact 122 - 2 .

[0027] Given that rails 110 may be at least partially covered by dielectric material layer 116, rails 110 may not be exposed at the periphery of semiconductor device assembly 100 (e.g., at a distal end of semiconductor device assembly 100 opposite semiconductor die 104). To provide external connectivity to rails 110, contacts 124 coupled to rails 110 (e.g., at Figure 2 100 ) may be exposed at the periphery of the semiconductor device assembly 100. The contact 124 may be coupled to the rail 110 by any connecting circuitry. For example, one or more vias 126 may extend between and couple the contact 124 and the rail 110.

[0028] One or more contacts 128 (e.g., contact 128-1 and contact 128-2) may be disposed at dielectric material layer 116 and exposed to the periphery of semiconductor device assembly 100. One or more vias 130 (e.g., via 130-1 and via 130-2) extend from contacts 128 through dielectric material layer 116 and gap filler 108 to contacts 132 (e.g., contact 132-1 and contact 132-2) at semiconductor die stack 102. Contacts 128 may be positioned at the periphery of the semiconductor die in a position spaced from rails 118 such that contacts 128 and rails 118 are electrically isolated from one another by dielectric material layer 116. Contacts 128 may also be positioned such that vias 130 extending from contacts 128 are spaced and electrically isolated from rails 110. As shown in FIG. Figure 1 , the contact 128 and the via 130 are embedded in the semiconductor device assembly 100 to ensure that the via 130 does not contact Figure 1 1. The rail 110 is exposed in the cross section illustrated in FIG. In this way, the passage 130 can extend beyond the rail 110.

[0029] As with rails 110 and rails 118, contacts 128 and vias 130 may include conductive materials for enabling contacts 128 and vias 130 to convey signaling to semiconductor die stack 102. In certain aspects, contacts 128 and vias 130 may be used to carry any kind of signaling. For example, contacts 128 may be used to carry source voltage signals, ground signaling, I / O signaling, or any other signaling. Contacts 128 may carry different types of signaling from rails 110 or rails 118. As a specific example, contacts 128 and vias 130 convey I / O signaling. Vias 130 may extend from individual contacts 128. In this way, each of vias 130 and contacts 128 may be used to convey different signaling.

[0030] The contacts 128 and vias 130 may be implemented in an unused area between rails 110 and rails 118. Thus, the contacts 128 and vias 130 may be implemented in different locations based on a particular implementation or routing scheme that the contacts 128 and vias 130 will follow. The contacts 128 and vias 130 may be positioned within the footprint of the semiconductor die 106 or outside the footprint of the semiconductor die 106. As illustrated, via 130-1 extends from contact 128-1 and couples with contact 132-1 exposed at a distal end of the semiconductor die 106 opposite the semiconductor die 104. The contact 132-1 may be connected to the semiconductor die 104 or any other of the semiconductor die 106 directly (e.g., using a through via that is not connected to circuitry at a metallization layer of the die it passes through) or indirectly (e.g., by routing through circuitry at a metallization layer of an intermittent die). The via 130-2 extends from the contact 128-2 through the dielectric material layer 116 and the gap filler 108 to the contact 132-2, which is disposed at an exposed portion of the semiconductor die 104 outside the footprint of the semiconductor die 106. In this way, the via 130-2 can extend through the gap filler 108 outside the footprint of the semiconductor die 106 to directly couple the contact 128-2 and the contact 132-2.

[0031] In the illustrated embodiment, a portion of the gap filler 108 protrudes along the dielectric material layer 116, such that the dielectric material layer 116 covers only a portion of the exposed surface opposite the semiconductor die 104. In this manner, the contact 124 can be disposed at the protruding portion of the gap filler 108. In other embodiments, the gap filler 108 can have a planar distal end opposite the semiconductor die 104. The dielectric material layer 116 can be disposed over the distal end such that the gap filler 108 does not protrude beyond the dielectric material layer 116. Thus, the distal end of the semiconductor device assembly 100 opposite the semiconductor die 104 can include the dielectric material layer 116 and the circuitry (e.g., rails 110, rails 118, and contacts 128) disposed therein.

[0032] Although the semiconductor die stack 102 is illustrated as 4 semiconductor dies, other embodiments including more or fewer semiconductor dies are possible. For example, the semiconductor die stack 102 can be replaced with a semiconductor die stack having 2, 3, 5, 6, 8, 10, 12, 14, 16, or any other number of semiconductor dies. In some embodiments, the semiconductor die 104 can be replaced with a plurality of semiconductor dies disposed laterally adjacent to each other. In certain aspects, the semiconductor die 106 can be replaced with more or fewer semiconductor dies or multiple semiconductor die stacks coupled to different lateral positions on the semiconductor die 104. For example, multiple stacks of semiconductor dies 106 can be coupled to the semiconductor die 104 in a rectangular pattern.

[0033] Figure 2 A simplified schematic partial plan view of a semiconductor device assembly 100 according to an embodiment of the present technology is illustrated. The plan view may illustrate an exposed surface of the semiconductor device assembly 100 opposite the semiconductor die 104 (covered by the semiconductor die 106, the gap filler 108, and the dielectric material layer 116 and thus only occupying an area of Figure 2 As shown in FIG. 1 , the footprint of semiconductor die 104 corresponds to the footprint of semiconductor device assembly 100. Figure 1 As discussed, semiconductor die 106 may be coupled to semiconductor die 104, and gap filler 108 may be disposed around and over semiconductor die 106 at semiconductor die 104. Figure 2 Only the footprint of semiconductor die 106 is illustrated in FIG. 1 . At least a portion of the footprint of semiconductor die 104 may extend beyond the footprint of semiconductor die 106 .

[0034] As about Figure 1 1, vias 112 (e.g., via 112-1, via 112-2, via 112-3, and via 112-4) are disposed through gap filler 108 to semiconductor die stack 102. Rails 110 (e.g., rail 110-1 and rail 110-2) are disposed over and coupled with vias 112. For example, rail 110-1 is coupled with via 112-1 and via 112-2, and rail 110-2 is coupled with via 112-3 and via 112-4. Although illustrated as being within the footprint of semiconductor die 106, one or more of vias 112 may extend from outside the footprint of semiconductor die 106.

[0035] The dielectric material layer 116 is at least partially disposed over the rail 110. Thus, the rail 110 is not exposed to Figure 2 Instead, dashed lines are used to illustrate the surface of rail 110. Figure 2 1. The rail 110 extends along a major axis. The rail 110 has a width along a minor axis. The rail 110 may have a width sufficient to provide contact to the passage 112. Specifically, the rail 110 may have a width greater than or equal to a diameter of the passage 112. The passages 112 may be spaced apart along the rail 110. For example, the passages 112 are spaced apart along the major axis of the rail 110. The rail 110 may include a plurality of rails 110 spaced apart from one another. For example, the rails 110 may be spaced apart from one another along the minor axis of the rail 110.

[0036] Rails 118 (e.g., rails 118-1 and 118-2) may be exposed at a dielectric material layer 116 that is spaced apart and electrically isolated from rail 110. For example, rail 118 is spaced apart above rail 110 by at least a portion of dielectric material layer 116. Given that rails 110 and 118 are spaced apart from one another, the footprint of rail 110 may overlap the footprint of rail 118. As illustrated, rail 118 is exposed at the periphery of semiconductor device assembly 100; however, rail 118 may be at least partially embedded within dielectric material layer 116. Rail 118 may extend along a long axis. The long axis of rail 118 may be substantially perpendicular (e.g., between 80 and 100 degrees, between 85 and 95 degrees, between 89 and 91 degrees) to the long axis of rail 110. In this manner, rail 118 and rail 110 may extend in a substantially perpendicular direction. The width of the rail may be defined by the short axis of rail 118. Rail 118 may include a plurality of rails. In certain aspects, rails 118 may be spaced apart from one another along a minor axis of rail 118. In some embodiments, rails 118 are spaced apart from one another along a major axis of rail 110, and rails 110 are spaced apart along the major axis of rail 118.

[0037] As about Figure 1 1, vias 120 (e.g., via 120-1, via 120-2, via 120-3, and via 120-4) extend from rail 118 through gap filler 108 and dielectric material layer 116 to semiconductor die stack 102. Multiple vias 120 may extend from each of rails 118. For example, rail 118-1 is coupled with via 120-1 and via 120-3, and rail 118-2 is coupled with via 120-2 and via 120-4. Vias 120 may be spaced apart from each other along the long axis of rail 118. For example, via 120-1 is spaced apart from via 120-3 along the long axis of rail 118. Vias 120 may extend within the footprint of semiconductor die 106 or outside the footprint of semiconductor die 106. For example, as illustrated, via 120 - 1 and via 120 - 3 extend from within the footprint of semiconductor die 106 , and via 120 - 2 and via 120 - 4 extend from outside the footprint of semiconductor die 106 .

[0038] Given that rails 110 are at least partially embedded below dielectric material layer 116, contacts 124 may be disposed at the periphery of semiconductor device assembly 100 to provide external connectivity to rails 110. For example, solder or other connection structures may be disposed at contacts 124 to connect contacts 124 to external components (such as a substrate or motherboard) that provide functionality (such as power, ground, I / O, or other signaling) to semiconductor device assembly 100. Contacts 124 may extend to rails 110 through vias 126 (such as via 126-1 and via 126-2). Individual ones of vias 126 may extend from contact 124 to each of rails 110. For example, via 126-1 may extend to rail 110-1 and via 126-2 may extend to rail 110-2. Although illustrated as a single integral contact, contacts 124 may instead be implemented as multiple contacts coupled to each of rails 110.

[0039] As discussed above, rail 118 is exposed to the periphery of the semiconductor device assembly. Therefore, external connectivity can be provided directly by rail 118. For example, solder or other connection structures can be directly disposed on rail 118 and used to connect rail 118 to external components. Alternatively or in addition, contacts 202 coupled to rail 118 can be disposed at the periphery of semiconductor device assembly 100. Solder or other connection structures can be disposed at contacts 202 and used to connect rail 118 to external components. Like contacts 124, in some cases, contacts 202 can be implemented as multiple contacts corresponding to rail 118. As discussed above, in some embodiments, rail 118 is at least partially covered by dielectric material layer 116. Therefore, in order to maintain coupling to rail 118, a via (not shown) can be disposed between contact 202 and rail 118.

[0040] The contacts 128 (e.g., contact 128-1, contact 128-2, contact 128-3, and contact 128-4) may be disposed at the dielectric material layer 116 and exposed at the periphery of the semiconductor device assembly 100. One or more vias 130 (e.g., via 130-1, via 130-2, via 130-3, and via 130-4) extend from the contacts 128 through the dielectric material layer 116 and the gap filler 108 to contacts 132 (e.g., contact 132-1 and contact 132-2) at the semiconductor die stack 102. The contacts 128 and vias 130 may be spaced apart from the rails 110 and 118. For example, the contacts 128 and vias 130 may be spaced apart from the rails 110 and 118 along a plane (e.g., Figure 2 The plane having the long axis of the passage 130 extending along it (e.g., extending in and out of the passage 130) is spaced from the rails 110 and 118. Figure 2106). The contacts 128 and vias 130 may be implemented in different locations based on a particular implementation or routing scheme that the contacts 128 and vias 130 will follow. The contacts 128 and vias 130 may be positioned within the footprint of the semiconductor die 106 or outside the footprint of the semiconductor die 106. As illustrated, the contacts 128-1 and 128-3 having vias 130-1 and 130-3 extending therefrom are positioned within the footprint of the semiconductor die 106; the contacts 128-2 and 128-4 having vias 130-2 and 130-4 extending therefrom are positioned outside the footprint of the semiconductor die 106. The contacts 128 and vias 130 may provide external connectivity to the semiconductor device assembly 100. For example, solder or other connection structures may be disposed on the contacts 128 and used to connect the contacts 128 to external components.

[0041] The present disclosure now turns to a series of operations for manufacturing a semiconductor device assembly according to an embodiment of the present technology. Specifically, Figures 3 to 8 A simplified schematic cross-sectional view illustrating a series of operations for manufacturing a semiconductor device assembly according to an embodiment of the present technology. For ease of description, the operations are described with respect to a specific embodiment. However, with respect to Figures 3 to 8 The described operations may be performed to fabricate semiconductor device assemblies according to other embodiments.

[0042] Figure 3 A simplified schematic cross-sectional diagram of a semiconductor device assembly in stage 300 is illustrated, wherein semiconductor die 106 (e.g., semiconductor die 106-1 and semiconductor die 106-2) are coupled to a semiconductor die wafer including semiconductor die 104-1 and semiconductor die 104-2. For example, semiconductor die 106-1 is coupled to the semiconductor die wafer at semiconductor die 104-1 and semiconductor die 106-2 is coupled to the semiconductor die wafer at semiconductor die 104-2. For the sake of brevity, various operations will be described with respect to semiconductor die stack 102-1 (semiconductor die 104-1 and semiconductor die 106-1) and explicit description of semiconductor die stack 102-2 (semiconductor die 104-2 and semiconductor die 106-2) and various operations performed thereon are omitted. Unless otherwise noted, descriptions of semiconductor die stack 102-1, components related to semiconductor die stack 102-1 (indicated by a suffix beginning with -1), or operations performed by semiconductor die stack 102-1 may similarly apply to semiconductor die stack 102-2 and its related components (indicated by a suffix beginning with -2). Furthermore, although only two semiconductor die stacks 102 are illustrated, any number of semiconductor die stacks may be implemented at different lateral locations.

[0043] As illustrated, semiconductor die 104-1 and semiconductor die 104-2 are implemented on a semiconductor die wafer. The semiconductor die wafer may include a plurality of individual semiconductor dies that each implement the circuitry of a single semiconductor device assembly. The operations described herein are discussed as wafer-level operations only as an example. However, in general, the operations disclosed herein may be performed on a single semiconductor device assembly at the die level or on a plurality of semiconductor device assemblies at the wafer or panel level. In certain aspects, the semiconductor die wafer may have sufficient thickness to support the semiconductor device assembly during processing. The metallization layers of semiconductor die 104-1 and semiconductor die 104-2 may be formed by depositing a conductive material layer and an insulating material layer at the wafer on which semiconductor die 104-1 and semiconductor die 104-2 are implemented. For example, a conductive material may be deposited to form contacts 122-12 and contacts 132-12 of circuitry (e.g., transistors, diodes, traces, lines, vias, or other circuitry) coupled to the metallization layers of semiconductor die 104-1.

[0044] The semiconductor die stack 102-1 includes a semiconductor die 104-1 (e.g., a logic die) and one or more semiconductor dies 106-1 (e.g., a memory die). The semiconductor die 106-1 may be coupled to the semiconductor die 104-1 in various portions or as a complete stack. For example, the stack of semiconductor die 106-1 may be cube-to-wafer bonded (e.g., hybrid bonded) to the semiconductor die 104-1. Alternatively, each of the semiconductor die 106-1 may be stacked to the semiconductor die 104-1 one or more at a time. In some cases, the semiconductor die 106-1 may be tested before being added to the assembly. In this way, the yield may be improved by selecting a "known good die" or "known good cube" for the semiconductor die 106-1. Coupling the stack of semiconductor die 106-1 to the semiconductor die 104-1 may form an interconnect that couples the circuitry at the semiconductor die 106-1 and the circuitry at the semiconductor die 104-1.

[0045] Semiconductor die 106-1 is stacked to semiconductor die 104-1 such that the front side of semiconductor die 106-1 faces the front side of semiconductor die 104-1. Once the stack of semiconductor die 106-1 is attached to semiconductor die 104-1, at least one contact (e.g., contact 122-12 and contact 132-12) may extend beyond the footprint of semiconductor die 106-1 and remain unconnected to semiconductor die 106-1. The contacts may be disposed at a distal end of semiconductor die 106-1 opposite semiconductor die 104-1. As illustrated, contacts 114-1 (e.g., contact 114-11 and contact 114-12), contact 132-11, and contact 122-11 are exposed at a distal end of semiconductor die 106-1. As discussed above, semiconductor die 106-2 may be similarly coupled to semiconductor die 104-2.

[0046] Figure 4 A simplified schematic cross-sectional diagram illustrating stage 400, wherein gap filler 108 is disposed at semiconductor die 104-1 and semiconductor die 104-2 to at least partially surround semiconductor die 106-1 and semiconductor die 106-2. In certain aspects, gap filler 108 (e.g., dielectric filler, oxide filler, molding resin) may be disposed at portions of semiconductor die 104-1 and semiconductor die 104-2 that are exposed outside the footprint of semiconductor die 106-1 and semiconductor die 106-2. Gap filler 108 may mechanically support and protect the semiconductor device assembly. In other aspects, gap filler 108 may improve thermal regulation of the semiconductor device assembly. In certain aspects, gap filler 108 includes a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, or silicon nitride carbon. Gap filler 108 is disposed by any suitable technique, such as dispensing, chemical vapor deposition (CVD), or physical vapor deposition (PVD). As illustrated, gap filler 108 may be disposed over distal ends of semiconductor die 106 - 1 and semiconductor die 106 - 2 opposite semiconductor die 104 - 1 and semiconductor die 104 - 2 Once disposed, gap filler 108 may cover contacts 114 , contacts 122 , or contacts 132 .

[0047] The distal end of the gap filler 108 opposite the semiconductor die 104-1 may have a recess in which the dielectric material layer may be disposed. In this way, after the dielectric material layer is disposed in the recess, the protrusion of the gap filler may extend beyond the dielectric material layer. The recess may be formed by any suitable method. For example, the gap filler 108 may be selectively disposed to create the recess by deposition. Therefore, there is no need to remove the gap filler 108 to create the recess. In other cases, the gap filler 108 may be disposed with a planar distal end, and a portion of the gap filler 108 may be removed at the distal end to create the recess. The gap filler 108 may be removed by, for example, plasma etching, wet etching, CMP or other suitable techniques.

[0048] At least a portion of the distal end of gap filler 108 may be planarized to create a planar surface for placement of dielectric material layers and conductive materials implementing circuitry. Planarization may be performed, for example, by CMP, back grinding, or other suitable techniques. Figure 4 108 as having a concave portion, but in other embodiments, the distal end of the gap filler 108 may be a planar surface. In some aspects, this may allow for a simpler planarization process, where planarization from the protrusions need not be omitted. In these embodiments, a dielectric material layer may be disposed on the protrusions of the gap filler 108. Figure 4 Therefore, the distal end of the semiconductor device assembly opposite to the semiconductor die 104 - 1 may not expose the gap filler 108 .

[0049] Figure 5 A simplified schematic cross-sectional view of stage 500 is illustrated, wherein vias are disposed through gap filler 108. As illustrated, via 112-1 (e.g., via 112-11 and via 112-12) is disposed through gap filler 108 and coupled with contact 114-1 (e.g., contact 114-11 and contact 114-12). A first portion of via 120-1a (e.g., a first portion of via 120-11a and a first portion of via 120-12a) and a first portion of via 130-1a (e.g., a first portion of via 130-11a and a first portion of via 130-12a) are disposed through gap filler 108 and coupled with contacts 122-1 (e.g., contact 122-11 and contact 122-12) and 132-1 (e.g., contact 132-11 and contact 132-12), respectively. Some vias may extend to the far end of semiconductor die 106-1, and other vias may extend beyond semiconductor die 106-1 through gap filler 108 to semiconductor die 104-1. For example, a first portion of via 120-11a extends to contact 122-11 at the far end of semiconductor die 106-1, and a first portion of via 120-12a extends to contact 122-12 at semiconductor die 104-1. The vias may be exposed at the far end of gap filler 108.

[0050] The vias may be disposed by any suitable technique. For example, an opening may be created from a distal end of the gap filler 108 at a lateral position corresponding to a contact. The opening may extend completely through the gap filler 108 to the contact. In some aspects, the opening may be created by drilling (e.g., laser drilling). A conductive material may be deposited in the opening to implement the via. The via may thus be electrically coupled to the semiconductor die stack 102-1. Any number of vias may be disposed through the gap filler 108. In some aspects, the via may be used to communicate power, ground, I / O, or other signals to / from the semiconductor die stack 102-1. The via may be similarly disposed with respect to the semiconductor die stack 102-2.

[0051] Figure 6 A simplified schematic cross-sectional view illustrating stage 600, wherein dielectric material layer 116-1 and various circuit systems are disposed at the distal end of gap filler 108. Dielectric material layer 116 and conductive materials for implementing circuit systems may be disposed by, for example, CVD, PVD, electroplating, electroless plating, spin coating, and / or other suitable techniques. Rail 110-1 may be disposed at the distal end of gap filler 108 and coupled with via 112-1 (e.g., via 112-11 and via 112-12). Dielectric material layer 116-1 is disposed at gap filler 108, at least partially over rail 110-1. Contact 124-1 may be disposed at the periphery of the semiconductor device assembly (e.g., at the distal end opposite semiconductor die 104-1). In some cases, contact 124-1 may be disposed at a protruding portion of gap filler 108. In other examples, for example, when the distal end of the semiconductor device opposite the semiconductor die 104-1 is implemented as a dielectric material layer 116-1 lacking a protruding portion of the gap filler 108, the contact 124-1 may be implemented at the dielectric material layer. The via 126-1 may be disposed between the contact 124-1 and the rail 110-1 to electrically couple these components. The via 126-1 may extend at least partially through the dielectric material layer 116-1.

[0052] A second portion of via 120-1b (e.g., a second portion of via 120-11b and a second portion of via 120-12b) and a second portion of via 130-1b (e.g., a second portion of via 130-11b and a second portion of via 130-12b) are disposed through dielectric material layer 116-1 beyond rail 110-2. The second portion of via 120-1b may be attached to a first portion of via 120-1a (e.g., a first portion of via 120-11a and a first portion of via 120-12a) and a first portion of via 130-1a (e.g., a first portion of via 130-11a and a first portion of via 130-12a). When combined, the first and second portions of the via may implement an integral via coupled with semiconductor die stack 102-1. Although illustrated as being disposed in two separate processes, in some embodiments, the first and second portions of the via are disposed in a single process (e.g., after disposing the dielectric material layer).

[0053] Rails 118-1 (e.g., rails 118-11 and rails 118-12) may be disposed at a dielectric material layer spaced from rail 110-1. Rails 118-1 may be coupled to a second portion of via 120-1. For example, rails 118-11 may be coupled to via 120-11, and rails 118-12 may be coupled to via 120-12. Rails 118-1 may be exposed at the periphery of the semiconductor device assembly (e.g., at a far end opposite semiconductor die 104-1). In some embodiments, at least a portion of rails 118-1 is embedded in dielectric material layer 116-1. Although not illustrated, contacts may be a dielectric material layer coupled to rails 118-1 to provide external connectivity to rails 118-1.

[0054] Contacts 128-1 (e.g., contacts 128-11 and contacts 128-12) may be similarly disposed at dielectric material layer 116-1 and exposed to the periphery of the semiconductor device assembly. Contacts 128-1 may be coupled with vias 130-1 (e.g., vias 130-11 and vias 130-12). For example, contact 128-11 may be coupled with a second portion of via 130-11b, and contact 128-12 may be coupled with a second portion of via 130-12b. Contacts 128-1 may provide external connectivity to semiconductor die stack 102-1 through vias 130-1.

[0055] Any circuit system can be created by any suitable method. For example, the circuit system can be disposed by selectively disposing a conductive material when disposing the dielectric material layer 116-1. Alternatively or in addition, the circuit system can be implemented by creating an opening through at least a portion of the dielectric material layer 116-1 and dispensing the conductive material into the opening.

[0056] Contact 124-1, contacts coupled to rail 118-1, and contact 128-1 may provide external connectivity (e.g., power, ground, I / O, or other signaling) to the semiconductor device assembly. These contacts may be arranged to match the configuration of one or more external components (e.g., a motherboard) to which the semiconductor device assembly is attached. For example, these contacts may be arranged in a BGA configuration. Solder balls or other connection structures may be disposed at the contacts to provide connectivity to external components that provide various functionality (e.g., power, ground, I / O, or other signaling) to the semiconductor device assembly.

[0057] When semiconductor devices are assembled at the wafer level, various semiconductor die stacks 102 can be singulated into individual semiconductor device assemblies. For example, a wafer including semiconductor die 104-1, gap filler 108, and dielectric material layer 116-1 can be sawed between semiconductor die stacks 102 (e.g., semiconductor die stack 102-1 and semiconductor die stack 102-2). Once singulated, the individual semiconductor device assemblies can be coupled to a larger system. For example, the semiconductor device assembly can be flipped so that the dielectric material layer 116-1 is at the bottom and solder balls (or other connection structures) disposed at the contacts can be coupled to an external component (e.g., a motherboard). Given that the contacts can be arranged in a specific configuration that is compatible with the external component to which the semiconductor device assembly is attached, no additional substrate may be required to support the appropriate balls beyond the assembly. However, in some cases, the contacts may be attached to an additional substrate (e.g., a silicon interposer or a printed circuit board (PCB)) that provides a specific arrangement of external contacts. Example semiconductor device assembly in Figure 7 In the description.

[0058] Figure 7 A simplified schematic cross-sectional diagram illustrating stage 700 in which a semiconductor device assembly 702 is coupled to a substrate 704 and encapsulated. The semiconductor device assembly 702 may be Figure 6 704. The semiconductor device assembly 702 may be coupled to a substrate by a connection structure 706, such as solder. In some cases, the semiconductor device assembly 702 may be hybrid bonded to the substrate 704. Although described as flipped onto the substrate 704, in other embodiments, the semiconductor device assembly 702 may be wire bonded to the substrate 704. In these embodiments, the semiconductor device assembly 702 need not be flipped onto the substrate 704. The substrate 704 may be a singulated substrate according to one or more embodiments described herein. For example, the semiconductor device assembly 702 may be coupled to a panel-level or strip-level substrate that has been sawn to singulate the substrate 704.

[0059] The substrate 704 may similarly include contacts at the upper surface. The connection structure 706 may implement an interconnect that electrically couples the semiconductor device assembly 702 and the substrate 704. An underfill material 708, such as a capillary underfill, may be disposed between the semiconductor device assembly 702 and the substrate 704 to at least partially surround the connection structure 706. The substrate 704 may include various circuitry, such as traces, lines, vias, or other connection structures, between the contacts at the upper surface and the contacts at the underside of the substrate 704 in which the connection structure 710, such as solder, is disposed. In this manner, external connectivity, such as power, ground, I / O, or other signaling, may be provided through the connection structure 710. The semiconductor device assembly 702 and the substrate 704 may be at least partially encapsulated by an encapsulation material 712, such as a molding resin compound, to prevent electrical contact with the semiconductor device assembly or to provide mechanical strength to the semiconductor device assembly.

[0060] Although in the foregoing example embodiments, the semiconductor device assembly has been illustrated and described as including a semiconductor die of a particular configuration, in other embodiments, the assembly may have semiconductor dies of a different configuration. For example, the semiconductor device assembly illustrated in any of the foregoing examples may be implemented with, for example, a plurality of semiconductor die stacks or a single semiconductor die after appropriate modification.

[0061] According to one aspect of the present disclosure, Figures 1 to 7 The semiconductor device illustrated in the assembly of may include a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor device may include the same kind of memory die (e.g., both are NAND, both are DRAM, etc.) or different kinds of memory dies (e.g., one is DRAM and one is NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly illustrated and described above may be a logic die (e.g., a controller die, a processor die, etc.) or a mix of logic and memory die (e.g., a memory controller die and a memory die controlled by it).

[0062] References Figures 1 to 7 Any of the described semiconductor devices and semiconductor device assemblies may be incorporated into any of a variety of larger and / or more complex systems, representative examples of which are Figure 88. The system 800 may include a semiconductor device assembly 802 (eg, a discrete semiconductor device), a power supply 804, a driver 806, a processor 808, and / or other subsystems or components 810. The semiconductor device assembly 802 may include a semiconductor device assembly 802 that is substantially similar to the semiconductor device assembly 810 described above with reference to FIG. Figures 1 to 7 The resulting system 800 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 800 may include, but is not limited to, handheld devices (such as mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 800 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). The components of the system 800 may also include any of a variety of computer-readable media and remote devices.

[0063] Fig. 9 An example method 900 for manufacturing a semiconductor device assembly according to an embodiment of the present technology is described. Although described with a specific configuration, one or more operations of the method 900 may be omitted, repeated, or reorganized. Additionally, the method 900 may include Fig. 9 Other operations not described in the method, such as operations detailed in one or more other methods described in this document.

[0064] At 902, a semiconductor die stack is provided. The semiconductor die stack includes a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to circuitry at the semiconductor die stack, and at least one second contact coupled to circuitry (e.g., traces, lines, vias, transistors, diodes, or other circuitry) at the semiconductor die stack. The first and second contacts may be disposed at a remote end of the first semiconductor die or one or more second semiconductor dies opposite the first semiconductor die. In some cases, the first semiconductor die is a logic die, such as a memory controller or interface die, and the second semiconductor die is a memory die.

[0065] At 904, a gap filler is disposed at least partially around the semiconductor die stack and over distal ends of one or more second semiconductor dies opposite the first semiconductor die. In some cases, the gap filler is a dielectric filler, an oxide filler, or a molding resin. The gap filler may be disposed at an exposed portion of the first semiconductor die that is exposed outside of a footprint of the first semiconductor die.

[0066] At 906, at least one first via and a second portion of at least one second via are disposed through the gap filler. The first via may extend from a distal end of the gap filler to a first contact. The first portion of the second via may extend from a distal end of the gap filler to a second contact. The vias may be disposed by creating holes in the gap filler and dispensing conductive material in the openings.

[0067] At 908, one or more first rails are disposed at a distal end of the gap filler and at least one first via. In this manner, the one or more first rails may be coupled with the at least one first via.

[0068] A dielectric material layer is disposed at least partially over the first rail at 910. The dielectric material layer may include, for example, silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or any other dielectric material.

[0069] At 912, a second portion of at least one second via is disposed through the dielectric material layer to the first portion of the at least one second via. The second portion of the at least one second via can be formed by selectively depositing a conductive material during the same process as disposing the dielectric material layer. In other cases, an opening can be drilled through the dielectric material layer after the dielectric material layer is disposed, and the conductive material can be dispensed into the opening.

[0070] At 914, one or more second rails are disposed at the dielectric material layer and at least one second via. In this manner, the one or more second rails can be coupled to the at least one second via. The second rails can be vertically spaced from the first rails (e.g., along the long axis of the second via). The footprint of the second rails can partially overlap the footprint of the first rails.

[0071] At 916, one or more third contacts coupled to the one or more first rails and one or more fourth contacts coupled to the one or more second rails are disposed. The third contact and the fourth contact may be exposed at a far end of the semiconductor device assembly opposite to the first semiconductor die. The third contact may be coupled to the first rail by, for example, a via extending through a dielectric material layer. In some cases, the fourth contact may be implemented in combination with the second rail. For example, the fourth contact may be implemented as an exposed surface of the rail so that electrical contact may be made directly with the second rail. The third and fourth contacts may provide external connectivity to external components that provide functionality (e.g., power, ground, I / O, or other signaling) to the semiconductor device assembly. Thus, various signaling may be provided to the semiconductor device assembly through the first and second rails and vias.

[0072] Specific details of several embodiments of semiconductor devices and associated systems and methods are described above. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate. In addition, unless the context indicates otherwise, the structures disclosed herein may be formed using conventional semiconductor manufacturing techniques. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0073] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or an assembly or other structure in various processing stages before becoming a finished device. Depending on the context in which it is used, the term "substrate" may refer to a structure that supports an electronic component (e.g., a die), such as a PCB or a wafer-level substrate, a die-level substrate, or another die for die stacking or 3DI applications.

[0074] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0075] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0076] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0077] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature being located closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0078] It should be understood from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Specifically, in the foregoing description, numerous specific details are discussed to provide a thorough and feasible description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A semiconductor device assembly comprising: a semiconductor die stack comprising a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to circuitry at the semiconductor die stack, and at least one second contact coupled to the circuitry at the semiconductor die stack; a gap filler at least partially surrounding the stack of semiconductor dies and disposed over distal ends of the one or more second semiconductor dies opposite the first semiconductor die; one or more first rails disposed at a distal end of the gap filler opposite the first semiconductor die; at least one first via extending from the one or more first rails to the at least one first contact; a layer of dielectric material disposed at least partially over the one or more first rails; one or more second rails disposed at the dielectric material layer; at least one second via extending from the one or more second rails beyond the one or more first rails to the at least one second contact; one or more third contacts coupled to the one or more first rails and exposed at a distal end of the semiconductor device assembly opposite the first semiconductor die; and one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly, Wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other one of the source voltage rail or the ground reference rail.

2. The semiconductor device assembly according to claim 1, wherein: The one or more first rails extend along a first longitudinal axis; and The one or more second rails extend along a second longitudinal axis that is substantially perpendicular to the first longitudinal axis.

3. The semiconductor device assembly according to claim 2, wherein: The one or more first rails include a plurality of first rails spaced apart along the second major axis; or The one or more second rails include a plurality of second rails spaced apart along the first major axis.

4. The semiconductor device assembly according to claim 1, wherein: The at least one first passage comprises a plurality of first passages; and The plurality of first vias are spaced along a major axis of the one or more first rails.

5. The semiconductor device assembly according to claim 1, wherein: The at least one second passage comprises a plurality of second passages; and The plurality of second vias are spaced along a major axis of the one or more second rails.

6. The semiconductor device assembly of claim 1 , wherein the semiconductor die stack further comprises a fifth contact coupled to the circuitry at the semiconductor die stack, the semiconductor device assembly further comprising: a sixth contact disposed at the dielectric material layer and exposed at the distal end of the semiconductor device assembly; and A third via extends from the sixth contact to the fifth contact, the third via being spaced apart from the one or more first rails and the one or more second rails along one or more axes in a plane, wherein a major axis along which the third via extends is normal to the plane.

7. The semiconductor device assembly according to claim 1, wherein: The first semiconductor die has a first footprint; The one or more second semiconductor dies have a second footprint; The at least one first contact or the at least one second contact is disposed at the first semiconductor die and is at least partially exposed outside the second footprint; and The at least one first passage or the at least one second passage extends through the gap filler outside the second footprint.

8. The semiconductor device assembly according to claim 1, wherein: The first semiconductor die comprises a logic die; and The one or more second semiconductor dies include a memory die.

9. A method for manufacturing a semiconductor device assembly, comprising: providing a semiconductor die stack comprising a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to circuitry at the semiconductor die stack, and at least one second contact coupled to the circuitry at the semiconductor die stack; disposing a gap filler at least partially surrounding the stack of semiconductor dies and over distal ends of the one or more second semiconductor dies opposite the first semiconductor die; disposing at least one first via through the gap filler from a distal end of the gap filler opposite the first semiconductor die to the at least one first contact; disposing a first portion of at least one second via through the gap filler from the distal end of the gap filler to the at least one second contact; disposing one or more first rails at the distal end of the gap filler and the at least one first passage; disposing a layer of dielectric material at least partially over the one or more first rails; disposing a second portion of the at least one second via through the layer of dielectric material to the first portion of the at least one second via; disposing one or more second rails at the dielectric material layer and the at least one second via; disposing one or more third contacts coupled to the one or more first rails and exposed at a distal end of the semiconductor device assembly opposite the first semiconductor die; and disposing one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly opposite the first semiconductor die, Wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other one of the source voltage rail or the ground reference rail.

10. The method according to claim 9, further comprising: a semiconductor die wafer comprising the first semiconductor die and an additional first semiconductor die; coupling one or more additional second semiconductor dies to the additional first semiconductor dies; disposing the gap filler at least partially around the one or more additional second semiconductor dies; disposing at least one additional first via from the distal end of the gap filler to the additional first semiconductor die or the one or more additional second semiconductor die; disposing a first portion of at least one additional second via from the distal end of the gap filler to the additional first semiconductor die or the one or more additional second semiconductor die; disposing one or more additional first rails at the distal end of the gap filler and the at least one additional first passage; disposing the layer of dielectric material at least partially over the one or more additional first rails; disposing a second portion of the at least one additional second via through the layer of dielectric material to the first portion of the at least one additional second via; disposing one or more additional second rails at the second portion of the dielectric material layer and at least one additional second via; disposing one or more additional third contacts coupled to the one or more additional first rails and exposed at the distal end of the semiconductor device assembly; disposing one or more additional fourth contacts coupled to the one or more additional second rails and exposed at the far end of the semiconductor device assembly; and The semiconductor die wafer is sawed to singulate the first semiconductor die and the additional first semiconductor die.

11. The method according to claim 9, further comprising: creating at least one first opening and at least one second opening extending through the gap filler to the at least one first contact and the at least one second contact, respectively; disposing a conductive material within the at least one first opening to implement the at least one first via extending through the gap filler to the at least one first contact; and A conductive material is disposed within the at least one second opening to implement the first portion of the at least one second via extending through the gap filler to the at least one second contact.

12. The method according to claim 9, further comprising: removing at least a portion of the gap filler at the distal end of the gap filler to create a recess; and The one or more first rails, the one or more second rails, and the dielectric material layer are disposed at the recess.

13. The method of claim 9, wherein the semiconductor die stack further comprises a fifth contact coupled to the circuitry at the semiconductor die stack, the method further comprising: a sixth contact disposed at the dielectric material layer and exposed at the distal end of the semiconductor device assembly; and A third via is disposed extending from the sixth contact to the fifth contact, the third via being spaced from the one or more first rails and the one or more second rails along one or more axes in a plane, wherein a major axis along which the third via extends is normal to the plane.

14. The method of claim 9, wherein: The one or more first rails extend along a first longitudinal axis; and The one or more second rails extend along a second longitudinal axis that is substantially perpendicular to the first longitudinal axis.

15. The method of claim 9, wherein: The first semiconductor die has a first footprint; The one or more second semiconductor dies have a second footprint; The at least one first contact or the at least one second contact is disposed at the first semiconductor die and is at least partially exposed outside the second footprint; and The first portion of the at least one first via or the at least one second via extends through the gap filler outside of the second footprint.

16. A semiconductor device assembly comprising: a semiconductor die stack comprising a first semiconductor die, one or more second semiconductor dies, at least one first contact coupled to circuitry at the semiconductor die stack, and at least one second contact coupled to the circuitry at the semiconductor die stack; a gap filler at least partially surrounding the stack of semiconductor dies and disposed over distal ends of the one or more second semiconductor dies opposite the first semiconductor die; one or more first rails having a first footprint; at least one first via extending from the one or more first rails to the at least one first contact; a layer of dielectric material disposed at least partially over the one or more first rails; one or more second rails disposed at the dielectric material layer, the one or more second rails being electrically isolated from the one or more first rails and having a second footprint, wherein the second footprint partially overlaps the first footprint; at least one second via extending from the one or more second rails beyond the one or more first rails to the at least one second contact; one or more third contacts coupled to the one or more first rails and exposed at a distal end of the semiconductor device assembly opposite the first semiconductor die; and one or more fourth contacts coupled to the one or more second rails and exposed at the far end of the semiconductor device assembly, Wherein the one or more first rails include a first one of a source voltage rail or a ground reference rail and the one or more second rails include the other one of the source voltage rail or the ground reference rail.

17. The semiconductor device assembly of claim 16, wherein: The one or more first rails extend along a first longitudinal axis; and The one or more second rails extend along a second longitudinal axis that is substantially perpendicular to the first longitudinal axis.

18. The semiconductor device assembly of claim 17, wherein: The one or more first rails include a plurality of first rails spaced apart along the second major axis; or The one or more second rails include a plurality of second rails spaced apart along the first major axis.

19. The semiconductor device assembly of claim 16, wherein the semiconductor die stack further comprises a fifth contact coupled to the circuitry at the semiconductor die stack, the semiconductor device assembly further comprising: a sixth contact disposed at the dielectric material layer and exposed at the distal end of the semiconductor device; and A third via extends from the sixth contact to the fifth contact, the third via being spaced apart from the one or more first rails and the one or more second rails along one or more axes in a plane, wherein a major axis along which the third via extends is normal to the plane.

20. The semiconductor device assembly of claim 16, wherein: The first semiconductor die comprises a logic die; and The one or more second semiconductor dies include a memory die.

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