Display panel and display device

Abstract

The invention provides a display panel and a display device, and the display panel comprises a plurality of pixel driving circuits which are arranged in an array. The pixel driving circuit comprises a first transistor; the first transistor comprises a plurality of shielding wires extending along a first direction, and each shielding wire comprises a plurality of shielding main bodies arranged along the first direction and a first connecting part for connecting two adjacent shielding main bodies; the plurality of grid wires extend along the first direction, and each grid wire comprises a plurality of grid main bodies arranged along the first direction and a second connecting part for connecting two adjacent grid main bodies; the projections of the first connecting part and the second connecting part based on the plane where the display panel is located are only partially overlapped. According to the invention, the stray capacitance between the gate lines and the shielding lines can be reduced, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the pixel driving circuit of the display panel, the transistor that directly drives the light-emitting diode (LED) to emit light (hereinafter referred to as the driving transistor) is large in size because it needs to carry a large current. In order to reduce the self-heating effect, the driving transistor needs to use multiple transistors with small widths in parallel. However, when multiple small transistors are connected in parallel, due to the gap between the gates, a large parasitic capacitance will be formed between the gate wiring and the shield wiring in the gap, affecting the writing of the pixel driving circuit voltage, thereby affecting the display effect of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a display panel and a display device to at least solve the problem of large parasitic capacitance formed between the gate wiring and the shielding wiring.

[0005] In one aspect, an embodiment of the present invention provides a display panel, comprising a plurality of pixel driving circuits arranged in an array; the pixel driving circuit comprises a first transistor; the first transistor comprises: a plurality of shielding traces extending along a first direction, the shielding traces comprising a plurality of shielding bodies arranged along the first direction and a first connecting portion connecting two adjacent shielding bodies; a plurality of gate traces extending along the first direction, the gate traces comprising a plurality of gate bodies arranged along the first direction and a second connecting portion connecting two adjacent gate bodies; wherein the first connecting portion and the second connecting portion only partially overlap based on a projection of the plane where the display panel is located.

[0006] On the other hand, an embodiment of the present invention further provides a display device, comprising the above-mentioned display panel.

[0007] The display panel and the display device of the present invention divide the shielding wiring into a plurality of shielding bodies and a first connecting portion, and divide the gate wiring into a plurality of gate bodies and a second connecting portion. By reducing the projection of the first connecting portion and the second connecting portion based on the plane where the display panel is located from the complete overlap in the related art to only a partial overlap in the present application, the parasitic capacitance between the gate wiring and the shielding wiring can be reduced. Because the shielding wiring of the first transistor is connected to the source, the parasitic capacitance between the gate and the source of the first transistor is reduced, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the specification are used to explain the principles of the present invention. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0009] Figure 1 is a schematic diagram of a pixel driving circuit of the related art;

[0010] Figure 2 yes Figure 1 A structural schematic diagram of a driving transistor M3 of a pixel driving circuit;

[0011] Figure 3 yes Figure 2 A partial enlarged schematic diagram of the dotted line portion;

[0012] Figure 4 yes Figure 3 Schematic diagram of the AA' section;

[0013] Figure 5 is a schematic structural diagram of a driving transistor provided by an embodiment of the present invention;

[0014] Figure 6 yes Figure 5 A partial enlarged schematic diagram of the dotted line portion;

[0015] Figure 7 yes Figure 5 Schematic diagram of the BB' section;

[0016] Figure 8 yes Figure 5 Schematic diagram of CC' section;

[0017] Fig. 9 is a schematic structural diagram of another driving transistor provided by an embodiment of the present invention;

[0018] Fig.10 yes Fig. 9 A partial enlarged schematic diagram of the dotted line portion;

[0019] Fig.11 yes Fig.10 Schematic diagram of the DD' section;

[0020] Fig.12 is a parameter diagram of a driving transistor provided by an embodiment of the present invention;

[0021] Fig.13 is a schematic structural diagram of another driving transistor provided by an embodiment of the present invention;

[0022] Fig.14 yes Fig.13 A partial enlarged schematic diagram of the dotted line portion;

[0023] Fig.15 yes Fig.14 Schematic diagram of the EE' section;

[0024] Fig.16 is a partial structural diagram of another driving transistor provided by an embodiment of the present invention;

[0025] Fig.17 yes Fig.16 Schematic diagram of the FF' section;

[0026] Fig.18 is a partial structural diagram of another driving transistor provided by an embodiment of the present invention;

[0027] Fig.19 yes Fig.18 Schematic diagram of the GG' section;

[0028] Fig. 20 It is a structural schematic diagram of a display device provided by an embodiment of the present invention.

[0029] Reference numerals:

[0030] 10. Shielded wiring;

[0031] 11. Shielding the main body;

[0032] 12. a first connecting portion;

[0033] 20. Gate routing;

[0034] 21. Gate body;

[0035] 22. a second connecting portion;

[0036] 30. Active routing;

[0037] PS, channel region;

[0038] S, source;

[0039] D. Drain;

[0040] X, first direction;

[0041] Y, second direction;

[0042] 100. Display device. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their repeated description will be omitted.

[0044] The words "first", "second" and the like used in the specific description do not indicate any order, quantity or importance, but are only used to distinguish different components. In addition, in the description of the present invention, the orientation or position relationship indicated by the terms "upper" and "lower" are based on the orientation or position relationship shown in the drawings, which are only for the convenience of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0045] It should be noted that, in the absence of conflict, the embodiments of the present invention and features in different embodiments may be combined with each other.

[0046] In the related art, a display panel includes a plurality of pixel driving circuits arranged in an array, which are used to drive light emitting diodes (LEDs) to emit light, so that the display panel emits light. In the pixel driving circuit, the transistor that directly drives the light emitting diode to emit light is called a driving transistor.

[0047] For example, Figure 1 is a schematic diagram of a pixel driving circuit of the related art, such as Figure 1 As shown, in the pixel driving circuit, the M3 transistor is the driving transistor. The gate M of the driving transistor M3 is the N1 node, and the source S is the N2 node. In addition, in order to improve the output saturation performance of the driving transistor M3, the shielding line at the bottom of the driving transistor M3 is connected to the source S.

[0048] For example, Figure 2 yes Figure 1 A structural diagram of a driving transistor M3 of a pixel driving circuit is shown in FIG. Figure 2 As shown, the driving transistor M3 is larger in size because it needs to carry a larger current. In order to reduce the self-heating effect caused by the large size, the driving transistor needs to use multiple transistors with small widths in parallel. Specifically, the driving transistor M3 includes multiple shielding wires 10 and gate wires 20 arranged along the first direction X, and multiple active wires 30 arranged along the second direction Y, and the active wires 30 are arranged between the shielding wires 10 and the gate wires 20. Among them, each overlap of the gate wire 20 and the active wire 30 constitutes a transistor with a small width, and multiple transistors with small widths are connected in parallel.

[0049] Furthermore, if Figure 3 As shown in FIG. 1 , there is a gap between the gates of two adjacent transistors with small widths. Figure 4 As shown, in the gap, the gate wiring 20 and the shielding wiring 10 overlap greatly in the direction perpendicular to the plane where the display panel is located, so that a large parasitic capacitance is formed between the gate wiring 20 and the shielding wiring 10. Because the shielding wiring 10 is connected to the source S of the driving transistor M3, there is a large parasitic capacitance between the gate M and the source S of the driving transistor M3. Because the gate of the driving transistor M3 is the N1 node and the source S is the N2 node, that is, Figure 1 There is a large parasitic capacitance between the N1 node and the N2 node, which in turn affects the writing of the pixel driving circuit voltage, thereby affecting the display effect of the display panel.

[0050] The inventor of this case has provided a solution to the problems existing in the related art through careful and in-depth research. The present invention provides a display panel and a display device, wherein the display panel includes a plurality of pixel driving circuits arranged in an array; the pixel driving circuit includes a first transistor; the first transistor includes: a plurality of shielding wires extending along a first direction, the shielding wires include a plurality of shielding bodies arranged along the first direction and a first connecting portion connecting two adjacent shielding bodies; a plurality of gate wires extending along the first direction, the gate wires include a plurality of gate bodies arranged along the first direction and a second connecting portion connecting two adjacent gate bodies; wherein the first connecting portion and the second connecting portion only partially overlap based on the projection of the plane where the display panel is located. The display panel and the display device of the present invention divide the shielding wiring into a plurality of shielding bodies and a first connecting portion, and divide the gate wiring into a plurality of gate bodies and a second connecting portion. By reducing the projection of the first connecting portion and the second connecting portion based on the plane where the display panel is located from the complete overlap in the related art to only a partial overlap in the present application, the parasitic capacitance between the gate wiring and the shielding wiring can be reduced. Because the shielding wiring of the first transistor is connected to the source, the parasitic capacitance between the gate and the source of the first transistor is reduced, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0051] On one hand, Figure 5 As shown, a display panel provided by an embodiment of the present invention includes a plurality of pixel driving circuits arranged in an array, each pixel driving circuit includes a first transistor. The first transistor includes: a plurality of shielding wires 10 extending along a first direction X and a plurality of gate wires 20 extending along the first direction X. The first direction X is parallel to the plane where the display panel is located.

[0052] like Figure 5 and Figure 6As shown, specifically, a plurality of shielding wires 10 are parallel to each other. Each shielding wire 10 includes a plurality of shielding bodies 11 arranged along a first direction X and a first connecting portion 12 connecting two adjacent shielding bodies 11. That is, in the same shielding wire 10, the shielding bodies 11 and the first connecting portions 12 are alternately arranged and connected to each other.

[0053] Continue to refer Figure 5 and Figure 6 Specifically, the plurality of gate wirings 20 are parallel to each other. Each gate wiring 20 includes a plurality of gate bodies 21 arranged along the first direction X and a second connection portion 22 connecting two adjacent gate bodies 21. That is, in the same gate wiring 20, the gate bodies 21 and the second connection portions 22 are alternately arranged and connected to each other.

[0054] like Figure 6 and Figure 7 Specifically, the first connection portion 12 and the second connection portion 22 only partially overlap based on the projection of the plane where the display panel is located. It should be noted that the above-mentioned overlap of the first connection portion 12 and the second connection will form a parasitic capacitance between the two. The above-mentioned setting of dividing the shielding wiring 10 into a plurality of shielding bodies 11 and the first connection portion 12, and dividing the gate wiring 20 into a plurality of gate bodies 21 and the second connection portion 22, by reducing the first connection portion 12 and the second connection portion 22 based on the projection of the plane where the display panel is located from the complete overlap in the related art to only a partial overlap in the present application, can reduce the parasitic capacitance between the gate wiring 20 and the shielding wiring 10, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0055] In some embodiments, the first connection portion 12 and the second connection portion 22 do not overlap based on the projection of the plane where the display panel is located. By not overlapping the first connection portion 12 and the second connection, the parasitic capacitance formed between the two can be greatly reduced or even avoided, thereby significantly reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, so as to improve the display effect of the display panel.

[0056] In some embodiments, the first transistor is a driving transistor. It is understood that in the pixel driving circuit, the transistor that directly drives the light-emitting diode to emit light and determines the brightness of the light-emitting diode is called a driving transistor. Compared with the switching transistor and storage transistor in the pixel driving circuit that are mainly responsible for controlling the signal selection and retention in the pixel, the driving transistor is larger in size because it needs to carry a larger current. In order to reduce the self-heating effect caused by the large size, the driving transistor needs to use multiple small-width transistors in parallel.

[0057] like Figure 8As shown, the first transistor further includes: a plurality of active wirings 30 extending along a second direction Y. The second direction Y is perpendicular to the first direction X, and both the first direction X and the second direction Y are parallel to the plane where the display panel is located. In the direction perpendicular to the plane where the display panel is located, the active wiring 30 is located between the shielding wiring 10 and the gate wiring 20.

[0058] Specifically, in a direction perpendicular to the plane where the display panel is located, the portion where the active wiring 30 overlaps with the shielding wiring 10 is the channel region PS of the semiconductor layer of the first transistor. Along the first direction X, the portions where the active wiring 30 and the shielding wiring 10 do not overlap are the source S of the first transistor and the drain D of the first transistor, respectively. It should be noted that each overlap of the multiple gate wirings 20 extending along the first direction X and the multiple active wirings 30 extending along the second direction Y of the present application constitutes a transistor with a small width, and the multiple transistors with a small width are connected in parallel to jointly constitute part of the first transistor. For each overlap of the gate wiring 20 and the active wiring 30, that is, for each small-width transistor, the gate body 21 at the overlap of the gate wiring 20 and the active wiring 30 is the gate of the small-width transistor, the portion of the active wiring 30 overlapping with the shielding wiring 10 is the channel region PS of the semiconductor layer of the small-width transistor, and the portion of the active wiring 30 that does not overlap with the shielding wiring 10 is the source S and the drain D of the small-width transistor. The above-mentioned multiple small-width transistors together constitute the first transistor, and as a driving transistor, the self-heating effect caused by the large size of the driving transistor can be reduced.

[0059] Further, for each transistor of small width, the source S of the transistor of small width is connected to the shielding wiring 10 (not shown in the figure). Specifically, the source S of the transistor of small width can be connected to the shielding body 11 or the first connecting portion 12 of the shielding wiring 10, and the present application does not limit this. Thus, as a whole, the source S of the first transistor is connected to the shielding wiring 10, so that the potential of the source S and the shielding wiring 10 are the same, thereby increasing the drain D voltage of the first transistor to improve the output saturation performance of the first transistor and reduce the influence of the current change on the brightness of the first transistor. At this time, the overlap of the first connecting portion 12 and the second connecting portion 22 is reduced, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10, that is, reducing the parasitic capacitance between the gate and the source S of the first transistor, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0060] In some embodiments, the material of the active wiring 30 may be polysilicon (Poly), which is not limited in the present application. Polysilicon is widely used in TFT-LCD and OLED displays, especially in the driving transistor part, and can provide higher current driving capability and smaller device size.

[0061] In some embodiments, the shielding wire 10 may be a back side metal film (BSM), and its material may be metal. The shielding wire 10 may isolate the substrate of the display panel from the active wire 30 and the gate wire 20 and other structures on the shielding wire 10, thereby reducing the influence of the substrate on the active wire 30 and the gate wire 20 and other structures.

[0062] In some embodiments, the material of the gate wiring 20 may be polysilicon, which has good compatibility with silicon-based drive transistors, is easy to process, and can be used in processes at high temperatures. The material of the gate wiring 20 may also be a metal material (such as aluminum, molybdenum, titanium, tungsten, etc.), which has better conductivity than polysilicon, so it can reduce gate resistance, increase switching speed, and achieve faster response speed and lower power consumption.

[0063] like Fig. 9 , Fig.10 and Fig.11 It is shown that in some alternative embodiments, there are overlapping shielding lines 10 and gate lines 20 in a direction perpendicular to the plane where the display panel is located, and the first connection parts 12 of the shielding lines 10 are all located on the same side of the second connection parts 22 of the gate axis, and the first connection parts 12 and the second connection parts 22 do not overlap based on the projection of the plane where the display panel is located. By not overlapping the first connection part 12 and the second connection, the formation of parasitic capacitance between the two can be greatly reduced or even avoided, thereby significantly reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, so as to improve the display effect of the display panel.

[0064] In some embodiments, along the first direction X, the length of the shielding body 11 is greater than the length of the active wiring 30. It should be noted that, along the first direction X, the length of the active wiring 30 can be the same as the length of the gate body 21, and thus, the length of the shielding body 11 is greater than the length of the gate body 21. Further, when the shielding wiring 10 adopts the above-mentioned shielding body 11 and the first connecting portion 12 alternately connected, when preparing the shielding wiring 10, an etching method is used to obtain the desired shape of the shielding wiring 10. At this time, the portion with the shielding body 11 and the first connecting portion 12 will be higher than the portion without the two, thereby forming an uneven height difference. At this time, the length of the shielding body 11 is greater than the length of the active wiring 30, so that the active wiring 30 can be prepared above the shielding body 11, that is, at the height of the display panel at this time. When the active wiring 30 is made of polysilicon material, the polysilicon laser crystallizes above the shielding wiring 10, specifically above the shielding body 11, so that the polysilicon material of the active wiring 30 can be melted and flattened, reducing the electrical property differences of multiple small-width transistors of the first transistor.

[0065] like Fig.12 As shown, in some embodiments, along the first direction X, the length of the shielding body 11 is L1, the length of the gate body 21 is L2, and 1μm≤L1-L2≤2μm. It can be understood that along the first direction X, the length of the active wiring 30 can be the same as the length of the gate body 21. Therefore, along the first direction X, the length of the shielding body 11 minus the length of the gate body 21 is also greater than or equal to 1μm and less than or equal to 2μm. It should be noted that L1-L2≥1μm is the minimum value that can be obtained in order to meet the current extreme manufacturing process of the active wiring 30 and the gate body 21, but it is not limited to this. In the direction perpendicular to the plane where the display panel is located, L1-L2≤2μm can make the portion of the shielding body 11 protruding from the gate body 21 as small as possible along the first direction X, thereby reducing the parasitic capacitance generated between the portion of the shielding body 11 protruding from the gate body 21 and the second connecting portion 22 of the gate wiring 20, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10, that is, reducing the parasitic capacitance between the gate and the source S of the first transistor, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0066] Continue to refer Fig.12 In some embodiments, along the second direction Y, the width of the first connection portion 12 is W1, and the width of the second connection portion 22 is W2, W1≥1.5μm, W2≥1.5μm; wherein the second direction Y is perpendicular to the first direction X. It should be noted that the widths of the first connection portion 12 and the second connection portion 22 meet the above ranges, and the overlapping area of ​​the first connection portion 12 and the second connection portion 22 is minimized as much as possible under the premise of ensuring the preparation accuracy of the current preparation process, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10. At the same time, the widths of the first connection portion 12 and the second connection portion 22 meet the above ranges, and can also ensure that the widths of the first connection portion 12 and the second connection portion 22 are not too narrow to cause the problem of excessive resistance, so as to avoid affecting the current conductivity of the gate wiring 20 and the shielding wiring 10.

[0067] like Fig.13 , Fig.14 and Fig.15As shown, in some alternative embodiments, along the first direction X, the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 1. Among them, the second connection part 22 is located between the projections of the two first connection parts 12 based on the plane where the display panel is located. It can be understood that the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 1. Such a repeated arrangement can make the structures of multiple small-width transistors of the first transistor the same, thereby reducing the electrical differences of multiple small-width transistors of the first transistor. In addition, the second connection part 22 is located between the projections of the two first connection parts 12 based on the plane where the display panel is located, which can improve the structural stability of the shielding wiring 10. Further, two first connection parts 12 can be arranged symmetrically about one second connection part 22 to further improve the structural stability of the shielding wiring 10 and reduce the difficulty of preparation.

[0068] Continue to refer Fig.14 In some embodiments, along the second direction Y, the two first connection portions 12 are located at the two side edges of the shielding line; wherein the second direction Y is perpendicular to the first direction X. The above arrangement can further improve the structural stability of the shielding line 10 and reduce the difficulty of preparing the shielding line 10.

[0069] Continue to refer Fig.12 In some embodiments, along the second direction Y, the width of the channel region PS of the semiconductor layer of the first transistor is W3, 3μm≤W3≤5μm. It can be understood that, since along the second direction Y, the length of the gate body 21 is less than the width W3 of the channel region PS of the semiconductor layer of the first transistor, and thus the width W2 of the second connection portion 22 is less than the width W3 of the channel region PS of the semiconductor layer of the first transistor. Therefore, the above range can limit the area of ​​the second connection portion 22 between every two adjacent gate bodies 21 while ensuring the process limit of the channel region PS of the semiconductor layer of the first transistor, thereby reducing the overlapping area of ​​the first connection portion 12 and the second connection portion 22 based on the projection of the plane where the display panel is located, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10.

[0070] Continue to refer Fig.12In some embodiments, along the first direction X, the length of the second connection portion 22 is D, 2μm≤D≤5μm. The above range of the second connection portion 22 can limit the area of ​​the second connection portion 22 while ensuring the process limit of mutual influence between every two adjacent gate bodies 21 along the first direction X, thereby reducing the overlapping area of ​​the first connection portion 12 and the second connection portion 22 based on the projection of the plane where the display panel is located, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10.

[0071] like Fig.16 and Fig.17 As shown, in some alternative embodiments, along the first direction X, the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 2. Among them, the projections of the two second connection parts 22 based on the plane where the display panel is located are located between the projections of the two first connection parts 12 based on the plane where the display panel is located. It can be understood that the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 2. Such a repeated arrangement can make the structures of multiple small-width transistors of the first transistor the same, thereby reducing the electrical property differences of multiple small-width transistors of the first transistor. In addition, the projections of the two second connection parts 22 based on the plane where the display panel is located are located between the projections of the two first connection parts 12 based on the plane where the display panel is located, which can improve the structural stability of the shielding wiring 10 and the gate wiring 20. Further, the two first connection parts 12 can be symmetrically arranged, and the two second connection parts 22 can also be symmetrically arranged to further improve the structural stability of the shielding wiring 10 and reduce the difficulty of preparation.

[0072] like Fig.18 and Fig.19As shown, in some alternative embodiments, along the first direction X, the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 2. Among them, the projections of the two first connection parts 12 based on the plane where the display panel is located are located between the projections of the two second connection parts 22 based on the plane where the display panel is located. It can be understood that the number of the first connection parts 12 of every two adjacent shielding bodies 11 is 2, and the number of the second connection parts 22 of every two adjacent gate bodies 21 is 2. Such a repeated arrangement can make the structures of multiple small-width transistors of the first transistor the same, thereby reducing the electrical property differences of multiple small-width transistors of the first transistor. In addition, the projections of the two first connection parts 12 based on the plane where the display panel is located are located between the projections of the two second connection parts 22 based on the plane where the display panel is located, which can improve the structural stability of the shielding wiring 10 and the gate wiring 20. Further, the two first connection parts 12 can be symmetrically arranged, and the two second connection parts 22 can also be symmetrically arranged to further improve the structural stability of the shielding wiring 10 and reduce the difficulty of preparation.

[0073] In some alternative embodiments, the first connection portion 12 of every two adjacent shielding bodies 11 can be any number greater than or equal to 1, and the second connection portion 22 of every two adjacent gate bodies 21 can also be any number greater than or equal to 1, as long as the first connection portion 12 and the second connection portion 22 only partially overlap based on the projection of the plane where the display panel is located, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10.

[0074] In some alternative embodiments, the shape of the first connection portion 12 and / or the second connection portion 22 may be a rectangle. It is understandable that the rectangular first connection portion 12 and / or the second connection portion 22 may improve the structural stability of the shielding wiring 10 and reduce the difficulty of preparing the shielding wiring 10. In some other alternative embodiments, the shape of the first connection portion 12 and / or the second connection portion 22 may also be other shapes such as a parallelogram, a trapezoid, a mesh, and an ellipse, as long as the projection of the first connection portion 12 and the second connection portion 22 based on the plane where the display panel is located only partially overlaps, thereby reducing the parasitic capacitance between the gate wiring 20 and the shielding wiring 10.

[0075] In summary, the display panel of the present invention divides the shielding wiring 10 into multiple shielding bodies 11 and a first connecting part 12, and divides the gate wiring 20 into multiple gate bodies 21 and a second connecting part 22. By reducing the complete overlap in the related art to only partial overlap in the present application based on the projection of the first connecting part 12 and the second connecting part 22 on the plane where the display panel is located, the parasitic capacitance between the gate wiring 20 and the shielding wiring 10 can be reduced. Because the shielding wiring 10 of the first transistor is connected to the source S, the parasitic capacitance between the gate and the source S of the first transistor is reduced, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0076] On the other hand, Fig. 20 As shown, an embodiment of the present invention further provides a display device 100, including the above-mentioned display panel. The display device 100 can be: a vehicle display screen, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. The specific implementation and technical effects of the display device 100 can refer to the specific implementation of the above-mentioned display panel, and the repeated parts will not be repeated.

[0077] In summary, the display panel and the display device of the present invention divide the shielding wiring into multiple shielding bodies and a first connecting part, and divide the gate wiring into multiple gate bodies and a second connecting part. By reducing the first connecting part and the second connecting part from the complete overlap in the related art to only partial overlap in the present application based on the projection of the plane where the display panel is located, the parasitic capacitance between the gate wiring and the shielding wiring can be reduced. Because the shielding wiring of the first transistor is connected to the source, the parasitic capacitance between the gate and the source of the first transistor is reduced, thereby reducing the influence of the parasitic capacitance on the voltage writing of the pixel driving circuit, thereby improving the display effect of the display panel.

[0078] The above contents are further detailed descriptions of the present invention in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: A pixel driving circuit comprising a plurality of array arrangements; The pixel driving circuit includes a first transistor; the first transistor includes: A plurality of shielding wires extending along a first direction, wherein the shielding wires include a plurality of shielding bodies arranged along the first direction and a first connecting portion connecting two adjacent shielding bodies; A plurality of gate wirings extending along the first direction, wherein the gate wirings include a plurality of gate bodies arranged along the first direction and a second connecting portion connecting two adjacent gate bodies; The first connection portion and the second connection portion only partially overlap based on a projection of the plane where the display panel is located.

2. The display panel according to claim 1, characterized in that: The projections of the first connection portion and the second connection portion based on the plane where the display panel is located do not overlap.

3. The display panel according to claim 1, characterized in that: The first transistor is a driving transistor.

4. The display panel according to claim 1, characterized in that: The first transistor further includes: a plurality of active traces extending along a second direction; wherein the second direction is perpendicular to the first direction; In a direction perpendicular to the plane where the display panel is located, a portion where the active wiring and the shielding wiring overlap is a channel region of the semiconductor layer of the first transistor; Along the first direction, the non-overlapping portions of the active routing line and the shielding routing line are respectively the source of the first transistor and the drain of the first transistor; Wherein, the source is connected to the shielding wiring.

5. The display panel according to claim 4, characterized in that: Along the first direction, the length of the shielding body is greater than the length of the active trace.

6. The display panel according to claim 5, characterized in that: Along the first direction, the length of the shielding body is L1, the length of the gate body is L2, and 1 μm≤L1-L2≤2 μm.

7. The display panel according to claim 1, characterized in that: Along the second direction, the width of the first connection portion is W1, and the width of the second connection portion is W2, W1≥1.5 μm, W2≥1.5 μm; wherein the second direction is perpendicular to the first direction.

8. The display panel according to claim 1, characterized in that: Along the first direction, the number of the first connecting portions between every two adjacent shielding bodies is 2, and the number of the second connecting portions between every two adjacent gate bodies is 1; The projection of the second connection portion based on the plane where the display panel is located is located between two projections of the first connection portions based on the plane where the display panel is located.

9. The display panel according to claim 8, characterized in that: Along a second direction, the two first connection portions are located at two side edges of the shielding trace; wherein the second direction is perpendicular to the first direction.

10. The display panel according to claim 1, characterized in that: The first connection portion and / or the second connection portion is / are in a rectangular shape.

11. The display panel according to claim 4, characterized in that: Along the second direction, a width of a channel region of the semiconductor layer of the first transistor is W3, and 3 μm≤W3≤5 μm.

12. The display panel according to claim 1, characterized in that: Along the first direction, the length of the second connection portion is D, 2 μm≤D≤5 μm.

13. A display device, characterized in that: The invention comprises a display panel according to any one of claims 1 to 12.

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