Semiconductor structure and its formation method

Abstract

A semiconductor structure and its formation method are disclosed. The structure includes: a substrate comprising a capacitor region and a transistor region disposed adjacently; a third electrode layer located on the substrate of the transistor region; a first dielectric layer located on the third electrode layer; a channel layer located on the first dielectric layer on the third electrode layer; alternating first and second electrode layers stacked from bottom to top on the substrate of the capacitor region, wherein any second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer; a second dielectric layer located between adjacent first and second electrode layers; a fourth electrode layer located in the transistor region, the fourth electrode layer contacting the channel layer and being isolated from the second electrode layer; a first electrical connection structure located in the transistor region and electrically connected to the fourth electrode layer; and a second electrical connection structure located in the capacitor region and electrically connected to the first electrode layer. This invention enables a switched capacitor circuit to function as a power supply voltage regulator circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Today, many electronic devices require DC power, which typically comes from an adapter. The adapter draws AC voltage from a wall socket (electrical grid), converts this AC voltage to an uncontrolled DC voltage via a rectifier bridge, and then converts this uncontrolled DC voltage into the required DC power supply voltage via a switching power supply.

[0003] Switching power supplies typically use transformers or inductors as energy storage elements. For example, a flyback converter uses a transformer as its energy storage element. A switch is electrically coupled to the primary side of the transformer, and a control circuit controls the switching on and off of this switch, allowing energy to be alternately stored in the transformer or transferred to the secondary side. The secondary side of the transformer, after passing through a filter, generates an output voltage across the output capacitor; this output voltage is the DC output voltage of the flyback converter. The increase and decrease of the DC output voltage are inversely related to the power transferred to the load; an increase in load leads to a decrease in DC output voltage, and a decrease in load leads to an increase in DC output voltage. Normally, the DC output voltage is fed back to the control circuit so that the switching power supply can compensate for load changes.

[0004] A switched-capacitor circuit is a circuit composed of a switch and a capacitor. The switch is controlled by a clock signal, and the switched-capacitor circuit can perform various signal processing operations by storing and transferring charge. Because switched-capacitor circuits use metal-oxide-semiconductor (MOS) technology, they are small in size, have low power consumption, are relatively simple to manufacture, and are easy to integrate on a large scale, thus leading to their rapid development and widespread application. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to realize the function of a switched capacitor circuit as a power supply voltage regulator circuit.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including an adjacent capacitor region and a transistor region; a third electrode layer located on the substrate of the transistor region; a first dielectric layer located on the third electrode layer; a channel layer located on the first dielectric layer on the third electrode layer; alternating stacked first electrode layers and second electrode layers from bottom to top located on the substrate of the capacitor region, wherein any second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer; a second dielectric layer located between adjacent first electrode layers and second electrode layers; a fourth electrode layer located in the transistor region, the fourth electrode layer contacting the channel layer and being isolated from the second electrode layer; a first electrical connection structure located in the transistor region and electrically connected to the fourth electrode layer; and a second electrical connection structure located in the capacitor region and electrically connected to the first electrode layer.

[0007] Optionally, the adjacent second dielectric layer located below the second electrode layer in contact with the channel layer is integrated with the first dielectric layer.

[0008] Optionally, the second electrode layer closest to the substrate extends into the transistor region and contacts the channel layer, while being isolated from the third electrode layer.

[0009] Optionally, the first electrode layer and the third electrode layer are of the same structure; the second electrode layer and the fourth electrode layer that are in contact with the channel layer are of the same structure.

[0010] Optionally, along the arrangement direction perpendicular to the capacitor region and the transistor region, a portion of the third electrode layer is exposed by the channel layer; the semiconductor structure also includes: a third electrical connection structure located in the transistor region and electrically connected to the third electrode layer exposed by the channel layer.

[0011] Optionally, the channel layer covers the top and sidewalls of the third electrode layer along the arrangement direction of the capacitor region and the transistor region; the second electrode layer in contact with the channel layer covers the channel layer located on the first sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the first sidewall facing the capacitor region; the fourth electrode layer covers the channel layer located on the second sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the second sidewall facing away from the capacitor region.

[0012] Optionally, the first electrical connection structure penetrates the fourth electrode layer and is electrically connected to the fourth electrode layer; the second electrical connection structure penetrates the first electrode layer and is electrically connected to the first electrode layer.

[0013] Optionally, the second dielectric layer covering the top surface of the second electrode layer in contact with the channel layer also covers the top of the fourth electrode layer; the semiconductor structure further includes: a dummy electrode layer located on the first dielectric layer on top of the fourth electrode layer; and the first electrical connection structure also penetrates the dummy electrode layer on the fourth electrode layer.

[0014] Optionally, the material of the first dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; the material of the second dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; the material of the first electrode layer... The materials of the first electrode layer include one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; the materials of the second electrode layer include one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; the materials of the third electrode layer include one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; the materials of the fourth electrode layer include one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; and the materials of the channel layer include polycrystalline silicon or indium gallium zinc oxide.

[0015] Optionally, the thickness of the third electrode layer is to

[0016] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate including an adjacently disposed capacitor region and a transistor region; forming a third electrode layer on the substrate of the transistor region; forming a first dielectric layer on the third electrode layer; forming a channel layer on the first dielectric layer on the third electrode layer; forming, on the substrate of the capacitor region, alternatingly stacked first electrode layers and second electrode layers from bottom to top, and a second dielectric layer located between adjacent first electrode layers and second electrode layers, wherein any second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer; forming a fourth electrode layer on the substrate of the transistor region, the fourth electrode layer contacting the channel layer and being isolated from the second electrode layer; forming a first electrical connection structure electrically connected to the fourth electrode layer in the transistor region; and forming a second electrical connection structure electrically connected to the first electrode layer in the capacitor region.

[0017] Optionally, before forming the second electrode layer in contact with the channel layer, the first dielectric layer and the second dielectric layer are formed in the same step to make the first dielectric layer and the second dielectric layer integrally connected; in the step of forming the second electrode layer for contact with the channel layer, the second electrode layer is formed on the second dielectric layer which is integrally connected with the first dielectric layer.

[0018] Optionally, in the step of forming the second electrode layer closest to the substrate, the second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer.

[0019] Optionally, the steps of forming the first electrode layer and the third electrode layer include: forming a first electrode material layer covering the substrate; patterning the first electrode material layer, retaining the first electrode material layer located in the capacitor region as the first electrode layer, and retaining the first electrode material layer located in the transistor region as the third electrode layer; the steps of forming the fourth electrode layer and the second electrode layer in contact with the channel layer include: forming a second electrode material layer covering the first electrode layer, the third electrode layer, and the substrate exposed by the first electrode layer and the third electrode layer; patterning the second electrode material layer, removing a portion of the second electrode material layer at the top of the third electrode layer, such that the remaining second electrode material layers located on both sides of the third electrode layer are isolated, and retaining the second electrode material layer located on the side of the third electrode layer closer to the capacitor region as the second electrode layer, and retaining the second electrode material layer located on the side of the third electrode layer away from the capacitor region as the fourth electrode layer.

[0020] Optionally, in the step of forming the channel layer, a portion of the third electrode layer is exposed by the channel layer along the arrangement direction perpendicular to the capacitor region and the transistor region; the forming method further includes: forming a third electrical connection structure in the transistor region that is electrically connected to the third electrode layer exposed by the channel layer.

[0021] Optionally, in the step of forming the channel layer, the channel layer covers the top and sidewalls of the third electrode layer along the arrangement direction of the capacitor region and the transistor region; in the step of forming the second electrode layer in contact with the channel layer, the second electrode layer covers the channel layer of the first sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the first sidewall facing the capacitor region; in the step of forming the fourth electrode layer, the fourth electrode layer covers the channel layer of the second sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the second sidewall facing away from the capacitor region.

[0022] Optionally, in the step of forming the first electrical connection structure, the first electrical connection structure penetrates the fourth electrode layer and is electrically connected to the fourth electrode layer; in the step of forming the second electrical connection structure, the second electrical connection structure penetrates the first electrode layer and is electrically connected to the first electrode layer.

[0023] Optionally, in the step of forming a second dielectric layer on a second electrode layer in contact with the channel layer, the second dielectric layer further covers the top of the fourth electrode layer; before forming the second electrical connection structure, the step further includes: forming a dummy electrode layer on a first dielectric layer on top of the fourth electrode layer; in the step of forming the first electrical connection structure, the first electrical connection structure further penetrates the dummy electrode layer on the fourth electrode layer.

[0024] Optionally, the steps of forming a first electrode layer above the second electrode layer in contact with the channel layer and forming a dummy electrode layer include: forming a third electrode material layer covering the second dielectric layer; patterning the third electrode material layer, retaining the third electrode material layer located in the capacitor region as the first electrode layer, and retaining a portion of the third electrode material layer located on the fourth electrode layer as the dummy electrode layer.

[0025] Optionally, the first electrical connection structure and the second electrical connection structure are formed in the same step.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0027] In the semiconductor structure provided by this invention, the third electrode layer is located on the substrate of the transistor region, the first dielectric layer is located on the third electrode layer, the channel layer is located on the first dielectric layer on the third electrode layer, and the first electrode layer and the second electrode layer, which are alternately stacked from bottom to top, are located on the substrate of the capacitor region. Any second electrode layer extends into the transistor region and contacts the channel layer, while being isolated from the third electrode layer. The second dielectric layer is located between adjacent first electrode layers and second electrode layers. The fourth electrode layer is located in the transistor region, contacts the channel layer, and is isolated from the second electrode layer. In this invention, a transistor structure is constructed by forming a third electrode layer and a channel layer on the third electrode layer. This allows the transistor structure to be used as a switch in the capacitor region. By applying an electrical signal to the third electrode layer, the second electrode layer and the fourth electrode layer are made conductive through the channel layer. By applying an electrical signal to the second electrode layer through the fourth electrode layer, the capacitance value of the capacitor formed by the first electrode layer and the second electrode layer is adjusted, thereby realizing the function of the switched capacitor circuit as a power supply voltage regulator circuit.

[0028] In the semiconductor structure formation method provided by the embodiments of the present invention, a third electrode layer is formed on the substrate of the transistor region, a first dielectric layer is formed on the third electrode layer, a channel layer is formed on the first dielectric layer on the third electrode layer, and a first electrode layer and a second electrode layer, which are alternately stacked from bottom to top, and a dielectric layer located between adjacent first electrode layers and second electrode layers are formed on the substrate of the capacitor region. Any second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer. A fourth electrode layer is formed on the substrate of the transistor region, and the fourth electrode layer contacts the channel layer and is isolated from the second electrode layer. In the embodiments of the present invention, a transistor structure is constructed by forming a third electrode layer and a channel layer on the third electrode layer, so that the transistor structure can be used as a switch of the capacitor region. By applying an electrical signal to the third electrode layer, the second electrode layer and the fourth electrode layer are made to conduct through the channel layer. Thus, by applying an electrical signal to the second electrode layer through the fourth electrode layer, the capacitance value of the capacitor formed by the first electrode layer and the second electrode layer is adjusted, thereby realizing the function of the switched capacitor circuit as a power supply voltage regulator circuit. Attached Figure Description

[0029] Figures 1 to 3 A schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0031] As can be seen from the background technology, it is currently difficult to obtain a power supply voltage regulator circuit using a more flexible switched capacitor circuit.

[0032] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate including an adjacent capacitor region and a transistor region; a third electrode layer located on the substrate of the transistor region; a first dielectric layer located on the third electrode layer; a channel layer located on the first dielectric layer on the third electrode layer; alternating stacked first electrode layers and second electrode layers from bottom to top located on the substrate of the capacitor region, wherein any second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer; a second dielectric layer located between adjacent first electrode layers and second electrode layers; a fourth electrode layer located in the transistor region, the fourth electrode layer contacting the channel layer and being isolated from the second electrode layer; a first electrical connection structure located in the transistor region and electrically connected to the fourth electrode layer; and a second electrical connection structure located in the capacitor region and electrically connected to the first electrode layer.

[0033] In this embodiment of the invention, a transistor structure is formed by forming a third electrode layer and a channel layer on the third electrode layer. This allows the transistor structure to be used as a switch for the capacitor region. By applying an electrical signal to the third electrode layer, the second electrode layer and the fourth electrode layer are made to conduct through the channel layer. The fourth electrode layer applies an electrical signal to the second electrode layer to adjust the capacitance value of the capacitor formed by the first electrode layer and the second electrode layer, thereby realizing the function of the switched capacitor circuit as a power supply voltage regulator circuit.

[0034] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 1 to 3 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0035] Reference Figures 1 to 3 , Figure 2 for Figure 1 Top view, Figure 3 for Figure 1The circuit diagram shows a semiconductor structure including: a substrate 100, comprising an adjacent capacitor region 100C and a transistor region 100M; a third electrode layer 130 located on the substrate of the transistor region 100M; a first dielectric layer 210 located on the third electrode layer 130; a channel layer 200 located on the first dielectric layer 210 on the third electrode layer 120; and alternating first electrode layers 110 and second electrode layers 120 stacked from bottom to top on the substrate of the capacitor region 100C, wherein any second electrode layer 120 extends into the transistor region 100M and connects to the channel layer 110. The first electrode layer 200 is in contact with the second electrode layer 110 and isolated from the third electrode layer 130; the second dielectric layer 220 is located between the adjacent first electrode layer 110 and second electrode layer 120; the fourth electrode layer 140 is located in the transistor region 100M, and the fourth electrode layer 140 is in contact with the channel layer 200 and isolated from the second electrode layer 120; the first electrical connection structure 310 is located in the transistor region 100M and is electrically connected to the fourth electrode layer 140; the second electrical connection structure 320 is located in the capacitor region 100C and is electrically connected to the first electrode layer 110.

[0036] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0037] In this embodiment, the substrate 100 includes a capacitor region 100C and a transistor region 100M disposed adjacently.

[0038] The capacitor region 100C is used to form the MIM capacitor structure, and the transistor region 100M is used to form the switching structure for controlling the capacitor.

[0039] In this embodiment, a positioning structure (not shown) is also formed in the substrate 100 to serve as a positioning element for forming the electrical connection structure.

[0040] The third electrode layer 130, the first dielectric layer 210, and the channel layer 210 are used to form a transistor structure.

[0041] Specifically, in this embodiment, the channel layer 210 is used to provide a channel, the third electrode layer 130 is used as a gate structure to control the opening and closing of the channel, and the first dielectric layer 210 is used as a gate dielectric layer between the gate structure and the channel.

[0042] In this embodiment, the second electrode layer 120 and the fourth electrode layer 140 located on both sides of the channel layer 210 are regarded as the source and drain layers of the transistor structure. By applying a voltage to the third electrode layer 130, when the voltage applied to the third electrode layer 130 reaches or exceeds the threshold voltage, the channel layer 210 can be turned on, realizing the conduction between the source and drain, that is, realizing the conduction between the second electrode layer 120 and the fourth electrode layer 140.

[0043] In this embodiment, the channel layer 200 is arranged along the direction of the capacitor region 100C and the transistor region 100M (e.g., Figure 1 (As shown in the X direction) Covers the top and sidewalls of the third electrode layer 130.

[0044] The channel layer 200 covers the top and sidewalls of the third electrode layer 130 along the arrangement direction of the capacitor region 100C and the transistor region 100M. This is beneficial to maximize the channel area and increase the contact area between the channel layer 200 and the second electrode layer 120, as well as between the channel layer 200 and the fourth electrode layer 140. This is beneficial to make the channel layer 200 conduct and to make the electrical connection between the second electrode layer 120 and the third electrode layer 130 better.

[0045] In this embodiment, along the arrangement direction perpendicular to the capacitor region 100C and the transistor region 100M (e.g. Figure 2 (As shown in the Y direction), part of the third electrode layer 130 is exposed by the channel layer 200.

[0046] Part of the third electrode layer 130 is exposed by the channel layer 200. The exposed third electrode layer 130 is used for electrical connection with the outside. In this embodiment, the third electrode layer 130 has a second electrode layer 120 and a fourth electrode layer 140 on both sides along the arrangement direction of the capacitor region 100C and the transistor region 100M, respectively. Therefore, the third electrode layer 130 is easy to expose along the arrangement direction perpendicular to the capacitor region 100C and the transistor region 100M. It is also beneficial to leave enough space to form a third electrical connection structure that is electrically connected to the third electrode layer 130, which is beneficial to the electrical connection between the third electrode layer 130 and the outside.

[0047] Accordingly, in this embodiment, the third electrode layer 130 is made of metal and the channel layer 210 is made of semiconductor material, so that the third electrode layer 130, the first dielectric layer 210 and the channel layer 210 can form a transistor structure.

[0048] Specifically, in this embodiment, the material of the third electrode layer 130 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; the material of the first dielectric layer 210 includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; and the material of the channel layer 200 includes polycrystalline silicon or indium gallium zinc oxide.

[0049] As an example, in this embodiment, the material of the channel layer 200 is indium gallium zinc oxide (IGZO). IGZO material is easy to form a thin film layer, which is beneficial for forming a thin channel layer 200 covering the top and sidewalls of the third electrode layer 130.

[0050] It should be noted that in this embodiment, the thickness of the third electrode layer 130 should not be too large or too small. If the thickness of the third electrode layer 130 is too large, it will easily lead to excessive space occupation and unnecessary waste; if the thickness of the third electrode layer 130 is too small, it will easily lead to excessive resistance of the third electrode layer 130, affecting the performance of the transistor structure and thus the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the third electrode layer 130 is [not specified in the original text]. to

[0051] It should also be noted that the thickness of the first dielectric layer 210 should be selected according to actual process requirements. The thickness of the first dielectric layer 210 should not be too large or too small. If the thickness of the first dielectric layer 210 is too large, it may lead to an excessively high threshold voltage in the transistor structure, affecting the turn-on of the channel layer 200. If the thickness of the first dielectric layer 210 is too small, it may increase the leakage current of the transistor structure, affecting the operating performance of the transistor structure. Therefore, it is necessary to select an appropriate thickness of the first dielectric layer 210 according to actual process requirements.

[0052] The first electrode layer 110 and the second electrode layer 120, which are stacked alternately from bottom to top, serve as the electrode plates of the MIM capacitor structure. The second dielectric layer 220, the first electrode layer 110, the second electrode layer 120, and the second dielectric layer 220 are used to form the MIM capacitor structure.

[0053] In this embodiment, any second electrode layer 120 extends into the transistor region 100M and contacts the channel layer 200, while being isolated from the third electrode layer 130. When the channel layer 200 is not conducting, the second electrode layer 120 and the fourth electrode layer 140 are not connected, and no electrical signal is applied to the second electrode layer 120 through the fourth electrode layer 140. This also prevents the electrical signal applied to the third electrode layer 130 from being mistakenly connected to the second electrode layer 120. At the same time, when the channel layer 200 is conducting, the second electrode layer 120 and the fourth electrode layer 140 are connected, and an electrical signal is applied to the second electrode layer 120 through the fourth electrode layer 140.

[0054] Specifically, such as Figure 3As shown in the circuit structure, the transistor structure in transistor region 100M acts as a switch and is connected to the capacitor structure in capacitor region 100C. As a circuit structure in the power supply voltage regulator circuit, the charging and discharging of the capacitor structure is controlled by the opening and closing of the switch, thereby adjusting the capacitance value of the capacitor structure.

[0055] In this embodiment, the second electrode layer 120 closest to the substrate 100 extends into the transistor region 100M and contacts the channel layer 200, and is isolated from the third electrode layer 130.

[0056] By extending the second electrode layer 120 closest to the substrate 100 into the transistor region 100M and contacting the channel layer 200, the process steps for forming the second electrode layer 120 in contact with the channel layer 200 are relatively simple and easy to form. This makes it easier to simplify the connection structure between the switch structure and the capacitor structure, reduce the formation difficulty, and thus facilitate the formation of a more stable semiconductor structure.

[0057] In this embodiment, the first electrode layer 110 and the third electrode layer 120 are of the same layer structure.

[0058] In the semiconductor structure formation step, the first electrode layer 110 and the third electrode layer 120 are obtained by patterning the same electrode material layer. Therefore, the first electrode layer 110 and the third electrode layer 120 are homogeneous structures, which helps to simplify the process flow and improve process efficiency.

[0059] In this embodiment, the second electrode layer 120, which is in contact with the channel layer 200, covers the channel layer 200 located on the first sidewall of the third electrode layer 130, as well as a portion of the channel layer 200 on top of the third electrode layer 130, with the first sidewall facing the capacitor region 100C.

[0060] The second electrode layer 120, which is in contact with the channel layer 200, covers the channel layer 200 located on the first sidewall of the third electrode layer 130 and the portion of the channel layer 200 at the top of the third electrode layer 130. The first sidewall faces the capacitor region 100C, which is beneficial to ensure that the second electrode layer 120 and the channel layer 200 are in full contact. Therefore, when the channel layer 200 is turned on, it is beneficial to ensure that the electrical connection performance of the electrical signal loaded through the channel layer 200 to the second electrode layer 120 is better.

[0061] In this embodiment, the material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0062] In this embodiment, the material of the second electrode layer 120 is a conductive material. As an example, the material of the second electrode layer 120 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0063] The second dielectric layer 220 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the first electrode layer 110 and the second electrode layer 120.

[0064] In this embodiment, the material of the second dielectric layer 220 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0065] Specifically, the second dielectric layer 220 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 220 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 220 can meet the process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes one or more of the following: La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0066] In this embodiment, the second dielectric layer 220 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0067] In this embodiment, the adjacent second dielectric layer 220 located below the second electrode layer 120 which is in contact with the channel layer 200 is integrated with the first dielectric layer 210.

[0068] In the semiconductor structure formation step, in the step of forming a second dielectric layer 220 covering the first electrode layer 110 in the capacitor region 100C, the second dielectric layer 220 extends into the transistor region 100M and covers the third electrode layer 130. Using the second dielectric layer 220 covering the third electrode layer 130 as the first dielectric layer 210, the adjacent second dielectric layer 220 below the second electrode layer 120 in contact with the channel layer 200 is connected to the first dielectric layer 210 into a single structure, which helps to simplify the process flow and improve process efficiency.

[0069] The fourth electrode layer 140 is used to load electrical signals onto the second electrode layer 120.

[0070] Specifically, in this embodiment, the fourth electrode layer 140 is in contact with the channel layer 200 and isolated from the second electrode layer 120. When the channel layer 200 is not conducting, the fourth electrode layer 140 is isolated from the second electrode layer 120. When the channel layer 200 is conducting, an electrical signal is applied to the second electrode layer 120 through the channel layer 200.

[0071] In this embodiment, a transistor structure is formed by forming a third electrode layer 130 and a channel layer 200 on the third electrode layer 130. The transistor structure can be used as a switch for the capacitor region 100C. By applying an electrical signal to the third electrode layer 130, the second electrode layer 120 and the fourth electrode layer 140 are turned on through the channel layer 200. The fourth electrode layer 140 applies an electrical signal to the second electrode layer 120 to adjust the capacitance value of the capacitor formed by the first electrode layer 110 and the second electrode layer 120, thereby realizing the function of the switched capacitor circuit as a power supply voltage regulator circuit.

[0072] In this embodiment, the second electrode layer 120 and the fourth electrode layer 140, which are in contact with the channel layer 200, are of the same layer structure.

[0073] In the semiconductor structure formation step, the second electrode layer 120 and the fourth electrode layer 140 that are in contact with the channel layer 200 are obtained by patterning the same electrode material layer. Therefore, the second electrode layer 120 and the fourth electrode layer 140 that are in contact with the channel layer 200 are of the same layer structure, which helps to simplify the process flow and improve the process efficiency.

[0074] In this embodiment, the fourth electrode layer 140 covers the channel layer 200 located on the second sidewall of the third electrode layer 130 and a portion of the channel layer 200 on top of the third electrode layer 130, with the second sidewall facing away from the capacitor region 100C.

[0075] The fourth electrode layer 140 covers the channel layer 200 located on the second sidewall of the third electrode layer 130 and a portion of the channel layer 200 on top of the third electrode layer 130. The second sidewall faces away from the capacitor region 100C, which helps to ensure that the fourth electrode layer 140 and the channel layer 200 are in full contact. Therefore, when the channel layer 200 is turned on, it helps to ensure that the fourth electrode layer 140 has good electrical connection performance to the second electrode layer 120 through the channel layer 200 to load electrical signals.

[0076] In this embodiment, during the step of forming the second dielectric layer 220 covering the top surface of the second electrode layer 120 in contact with the channel layer 200, the top of the fourth electrode layer 140 is also exposed. Therefore, the second dielectric layer 220 extends into the transistor region 100M and covers the top of the fourth electrode layer 140. Thus, in this embodiment, the second dielectric layer 220 covering the top surface of the second electrode layer 120 in contact with the channel layer 200 also covers the top of the fourth electrode layer 140. Correspondingly, the second dielectric layer 220 is also used to isolate the fourth electrode layer 140 from the dummy electrode layer located on the fourth electrode layer 140.

[0077] In this embodiment, the material of the fourth electrode layer 140 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0078] The first electrical connection structure 310 is used for electrical connection with the fourth electrode layer 140.

[0079] In this embodiment, the first electrical connection structure 310 penetrates the fourth electrode layer 140 and is electrically connected to the fourth electrode layer 140.

[0080] Specifically, in this embodiment, the positioning structure corresponding to the first electrical connection structure 310 is used as the formation position to form the first electrical connection structure 310 that penetrates the fourth electrode layer 140. The first electrical connection structure 310 penetrates the fourth electrode layer 140 and makes full contact with the fourth electrode layer 140, thereby achieving better electrical connection performance.

[0081] In this embodiment, the material of the first electrical connection structure 310 is a conductive material. As an example, the material of the first electrical connection structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0082] The second electrical connection structure 320 is used for electrical connection with the first electrode layer 110.

[0083] In this embodiment, the second electrical connection structure 320 penetrates the first electrode layer 110 and is electrically connected to the first electrode layer 110.

[0084] Specifically, in this embodiment, the positioning structure corresponding to the second electrical connection structure 320 is used as the formation position to form the second electrical connection structure 320 that penetrates the first electrode layer 110. The second electrical connection structure 320 penetrates the first electrode layer 110 and makes full contact with the first electrode layer 110, thereby achieving better electrical connection performance.

[0085] It should be noted that when there are multiple layers of the first electrode layer 110, the second electrical connection structure 320 penetrates through the multiple layers of the first electrode layer 110 and is electrically connected to the multiple layers of the first electrode layer 110.

[0086] In this embodiment, the material of the second electrical connection structure 320 is a conductive material. As an example, the material of the second electrical connection structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0087] In this embodiment, the semiconductor structure further includes a dummy electrode layer 150, located on the second dielectric layer 220 on top of the fourth electrode layer 140.

[0088] When the number of first electrode layers 110 is multiple, the second electrical connection structure 320 penetrates multiple first electrode layers 110. The dummy electrode layer 150 is used to increase the thickness of the metal film at the location where the first electrical connection structure 310 is formed, so that the thickness of the metal film etched when forming the first electrical connection structure 310 is similar to the thickness of the metal film etched when forming the second electrical connection structure 320. This allows the etching process for forming the first electrical connection structure 310 and the etching process for forming the second electrical connection structure 320 to use the same etching process parameters. In other words, the first electrical connection structure 310 and the second electrical connection structure 320 can be formed in the same step, improving process efficiency.

[0089] Accordingly, in this embodiment, the first electrical connection structure 310 also penetrates the dummy electrode layer 150 on the fourth electrode layer 140.

[0090] In this embodiment, the dummy electrode layer 150 and the first electrode layer 110 above the second electrode layer 120 which is in contact with the channel layer 200 are of the same layer structure.

[0091] In the step of forming the semiconductor structure, the dummy electrode layer 150 and the first electrode layer 110 above the second electrode layer 120 that contacts the channel layer 200 are obtained by patterning the same electrode material layer. Thus, the dummy electrode layer 150 and the first electrode layer 110 above the second electrode layer 120 that contacts the channel layer 200 are of the same layer structure, which helps to simplify the process flow and improve process efficiency. Moreover, it also makes the thickness of the dummy electrode layer 150 and the first electrode layer 110 that penetrates the second electrical connection structure 320 equal. Furthermore, it makes the thickness of the metal film layer etched when forming the first electrical connection structure 310 and the thickness of the metal film layer etched when forming the second electrical connection structure 320 tend to be consistent, which further facilitates the formation of the first electrical connection structure 310 and the second electrical connection structure 320 in the same step.

[0092] Accordingly, in this embodiment, the material of the dummy electrode layer 150 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0093] In this embodiment, the semiconductor structure further includes a third electrical connection structure 330, located in the transistor region 100M, and electrically connected to the third electrode layer 130 exposed by the channel layer 200.

[0094] The third electrical connection structure 330 is used to electrically connect with the third electrode layer 130, thereby loading an electrical signal onto the third electrode layer 130.

[0095] In this embodiment, the material of the third electrical connection structure 330 is a conductive material. As an example, the material of the third electrical connection structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0096] It should be noted that, in other embodiments, a fourth electrical connection structure may also be formed in the capacitor region, which is electrically connected to the second electrode layer of the capacitor region, and is used to load an electrical signal onto the second electrode layer when the channel layer is not conducting.

[0097] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0098] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0099] refer to Figure 4 A substrate 100 is provided, including a capacitor region 100C and a transistor region 100M disposed adjacently.

[0100] Substrate 100 is used to provide a process platform for the formation of semiconductor structures.

[0101] In this embodiment, the substrate 100 includes a capacitor region 100C and a transistor region 100M disposed adjacently.

[0102] The capacitor region 100C is used to form the MIM capacitor structure, and the transistor region 100M is used to form the switching structure for controlling the capacitor.

[0103] In this embodiment, a positioning structure (not shown) is also formed in the substrate 100 to serve as a positioning element for forming the electrical connection structure.

[0104] Reference Figures 5 to 9A third electrode layer 130 is formed on a substrate 100 of transistor region 100M; a first dielectric layer 210 is formed on the third electrode layer 130; a channel layer 200 is formed on the first dielectric layer 210 on the third electrode layer 130; a first electrode layer 110 and a second electrode layer 120, stacked alternately from bottom to top, and a second dielectric layer 220 located between adjacent first electrode layers 110 and second electrode layers 120 are formed on a substrate 100 of capacitor region 100C, wherein any second electrode layer 120 extends into transistor region 100M and contacts the channel layer 200, and is isolated from the third electrode layer 130; a fourth electrode layer 140 is formed on the substrate 100 of transistor region 100M, wherein the fourth electrode layer 140 contacts the channel layer 200 and is isolated from the second electrode layer 120.

[0105] The third electrode layer 130, the first dielectric layer 210, and the channel layer 210 are used to form a transistor structure.

[0106] Specifically, in this embodiment, the channel layer 210 is used to provide a channel, the third electrode layer 130 is used as a gate structure to control the opening and closing of the channel, and the first dielectric layer 210 is used as a gate dielectric layer between the gate structure and the channel.

[0107] In this embodiment, the second electrode layer 120 and the fourth electrode layer 140 located on both sides of the channel layer 210 are regarded as the source and drain layers of the transistor structure. By applying a voltage to the third electrode layer 130, when the voltage applied to the third electrode layer 130 reaches or exceeds the threshold voltage, the channel layer 210 can be turned on, realizing the conduction between the source and drain, that is, realizing the conduction between the second electrode layer 120 and the fourth electrode layer 140.

[0108] In this embodiment, in the step of forming the channel layer 200, the channel layer 200 is arranged along the direction of the capacitor region 100C and the transistor region 100M (e.g., Figure 9 (As shown in the X direction) Covers the top and sidewalls of the third electrode layer 130.

[0109] The channel layer 200 covers the top and sidewalls of the third electrode layer 130 along the arrangement direction of the capacitor region 100C and the transistor region 100M. This is beneficial to maximize the channel area and increase the contact area between the channel layer 200 and the second electrode layer 120, as well as between the channel layer 200 and the fourth electrode layer 140. This is beneficial to make the channel layer 200 conduct and to make the electrical connection between the second electrode layer 120 and the third electrode layer 130 better.

[0110] In this embodiment, during the step of forming the channel layer 200, along the arrangement direction perpendicular to the capacitor region 100C and the transistor region 100M (e.g., Figure 11 (As shown in the Y direction), part of the third electrode layer 130 is exposed by the channel layer 200.

[0111] Part of the third electrode layer 130 is exposed by the channel layer 200. The exposed third electrode layer 130 is used for electrical connection with the outside. In this embodiment, the third electrode layer 130 has a second electrode layer 120 and a fourth electrode layer 140 on both sides along the arrangement direction of the capacitor region 100C and the transistor region 100M, respectively. Therefore, the third electrode layer 130 is easy to expose along the arrangement direction perpendicular to the capacitor region 100C and the transistor region 100M. It is also beneficial to leave enough space to form a third electrical connection structure that is electrically connected to the third electrode layer 130, which is beneficial to the electrical connection between the third electrode layer 130 and the outside.

[0112] Accordingly, in this embodiment, the third electrode layer 130 is made of metal and the channel layer 210 is made of semiconductor material, so that the third electrode layer 130, the first dielectric layer 210 and the channel layer 210 can form a transistor structure.

[0113] Specifically, in this embodiment, in the step of forming the third electrode layer 130, the material of the third electrode layer 130 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; in the step of forming the first dielectric layer 210, the material of the first dielectric layer 210 includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; in the step of forming the channel layer 200, the material of the channel layer 200 includes polycrystalline silicon or indium gallium zinc oxide.

[0114] As an example, in this embodiment, the material of the channel layer 200 is indium gallium zinc oxide (IGZO). IGZO material is easy to form a thin film layer, which is beneficial for forming a thin channel layer 200 covering the top and sidewalls of the third electrode layer 130.

[0115] It should be noted that, in this embodiment, the thickness of the third electrode layer 130 should not be too large or too small during the step of forming the third electrode layer 130. If the thickness of the third electrode layer 130 is too large, it will easily lead to excessive space occupation and unnecessary waste; if the thickness of the third electrode layer 130 is too small, it will easily lead to excessive resistance of the third electrode layer 130, affecting the performance of the transistor structure and thus the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the third electrode layer 130 in the step of forming the third electrode layer 130 is... to

[0116] It should also be noted that, in this embodiment, the thickness of the first dielectric layer 210 is selected according to actual process requirements during the formation of the first dielectric layer 210. The thickness of the first dielectric layer 210 should not be too large or too small. If the thickness of the first dielectric layer 210 is too large, it may lead to an excessively high threshold voltage in the transistor structure, affecting the turn-on of the channel layer 200. If the thickness of the first dielectric layer 210 is too small, it may increase the leakage current of the transistor structure, affecting the working performance of the transistor structure. Therefore, in this embodiment, the thickness of the first dielectric layer 210 needs to be selected according to actual process requirements during the formation of the first dielectric layer 210.

[0117] The first electrode layer 110 and the second electrode layer 120, which are stacked alternately from bottom to top, serve as the electrode plates of the MIM capacitor structure. The second dielectric layer 220, the first electrode layer 110, the second electrode layer 120, and the second dielectric layer 220 are used to form the MIM capacitor structure.

[0118] In this embodiment, any second electrode layer 120 extends into the transistor region 100M and contacts the channel layer 200, while being isolated from the third electrode layer 130. When the channel layer 200 is not conducting, the second electrode layer 120 and the fourth electrode layer 140 are not connected, and no electrical signal is applied to the second electrode layer 120 through the fourth electrode layer 140. This also prevents the electrical signal applied to the third electrode layer 130 from being mistakenly connected to the second electrode layer 120. At the same time, when the channel layer 200 is conducting, the second electrode layer 120 and the fourth electrode layer 140 are connected, and an electrical signal is applied to the second electrode layer 120 through the fourth electrode layer 140.

[0119] In this embodiment, in the step of forming the second electrode layer 120 closest to the substrate 100, the second electrode layer 120 extends into the transistor region 100M and contacts the channel layer 200, and is isolated from the third electrode layer 130.

[0120] By extending the second electrode layer 120 closest to the substrate 100 into the transistor region 100M and contacting the channel layer 200, the process steps for forming the second electrode layer 120 in contact with the channel layer 200 are relatively simple and easy to form. This makes it easier to simplify the connection structure between the switch structure and the capacitor structure, reduce the formation difficulty, and thus facilitate the formation of a more stable semiconductor structure.

[0121] Specifically, in this embodiment, the steps of forming the first electrode layer 110 and the third electrode layer 130 include: referencing Figure 5 A first electrode material layer 410 is formed covering the substrate; Reference Figure 6The first electrode material layer 410 is graphically represented, and the first electrode material layer 410 located in the capacitor region 100C is retained as the first electrode layer 110, and the first electrode material layer 410 located in the transistor region 100M is retained as the third electrode layer 130.

[0122] The first electrode layer 110 and the third electrode layer 120 are obtained by patterning the same electrode material layer. Therefore, the first electrode layer 110 and the third electrode layer 120 are of the same layer structure, which is beneficial to simplify the process flow and improve the process efficiency.

[0123] In this embodiment, in the step of forming the second electrode layer 120 in contact with the channel layer 200, the second electrode layer 120 covers the channel layer 200 located on the first sidewall of the third electrode layer 130 and a portion of the channel layer 200 on top of the third electrode layer 130, with the first sidewall facing the capacitor region 100C.

[0124] The second electrode layer 120, which is in contact with the channel layer 200, covers the channel layer 200 located on the first sidewall of the third electrode layer 130 and the portion of the channel layer 200 at the top of the third electrode layer 130. The first sidewall faces the capacitor region 100C, which is beneficial to ensure that the second electrode layer 120 and the channel layer 200 are in full contact. Therefore, when the channel layer 200 is turned on, it is beneficial to ensure that the electrical connection performance of the electrical signal loaded through the channel layer 200 to the second electrode layer 120 is better.

[0125] In this embodiment, during the step of forming the first electrode layer 110, the material of the first electrode layer 110 is a conductive material. As an example, the material of the first electrode layer 110 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0126] In this embodiment, during the step of forming the second electrode layer 120, the material of the second electrode layer 120 is a conductive material. As an example, the material of the second electrode layer 120 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0127] The second dielectric layer 220 serves as an insulating layer in the formation of the MIM capacitor, and is used to isolate the first electrode layer 110 and the second electrode layer 120.

[0128] In this embodiment, in the step of forming the second dielectric layer 220, the material of the second dielectric layer 220 is a high-k dielectric material; wherein, a high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. By selecting a high-k dielectric material, it is beneficial to increase the capacitance value of the MIM capacitor, and correspondingly increase the capacitance density.

[0129] Specifically, the second dielectric layer 220 is a high-k dielectric layer formed by stacking, that is, the second dielectric layer 220 is a high-k composite dielectric layer. Once the thickness of the high-k dielectric layer reaches a certain value, its formation quality tends to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the second dielectric layer 220 can meet the process requirements while maintaining good formation quality. For this purpose, the high-k dielectric material includes one or more of the following: La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN.

[0130] In this embodiment, the second dielectric layer 220 is a ZAZ layer. The ZAZ layer comprises a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, depending on process requirements, the material of the first dielectric layer may also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0131] Continue to refer to Figure 6 Before forming the second electrode layer 120 that contacts the channel layer 200, the first dielectric layer 210 and the second dielectric layer 220 are formed in the same step so that the first dielectric layer 210 and the second dielectric layer 220 are connected as a single structure.

[0132] It should be noted that in this embodiment, when the second dielectric layer 220 is formed, both the first electrode layer 110 and the third electrode layer 130 are exposed. Therefore, when the second dielectric layer 220 covering the first electrode layer 110 is formed, the second dielectric layer 220 also extends into the transistor region 100M and covers the third electrode layer 130. Using the second dielectric layer 220 covering the third electrode layer 130 as the first dielectric layer 210, the adjacent second dielectric layer 220 below the second electrode layer 120 in contact with the channel layer 200 is connected to the first dielectric layer 210 into a single structure, which is beneficial to simplify the process flow and improve process efficiency.

[0133] The fourth electrode layer 140 is used to load electrical signals onto the second electrode layer 120.

[0134] Specifically, in this embodiment, the fourth electrode layer 140 is in contact with the channel layer 200 and isolated from the second electrode layer 120. When the channel layer 200 is not conducting, the fourth electrode layer 140 is isolated from the second electrode layer 120. When the channel layer 200 is conducting, an electrical signal is applied to the second electrode layer 120 through the channel layer 200.

[0135] In this embodiment, a transistor structure is formed by forming a third electrode layer 130 and a channel layer 200 on the third electrode layer 130. The transistor structure can be used as a switch for the capacitor region 100C. By applying an electrical signal to the third electrode layer 130, the second electrode layer 120 and the fourth electrode layer 140 are turned on through the channel layer 200. The fourth electrode layer 140 applies an electrical signal to the second electrode layer 120 to adjust the capacitance value of the capacitor formed by the first electrode layer 110 and the second electrode layer 120, thereby realizing the function of the switched capacitor circuit as a power supply voltage regulator circuit.

[0136] Specifically, in this embodiment, the steps of forming the fourth electrode layer 140 and the second electrode layer 120 in contact with the channel layer 200 include: referring to Figure 7 A second electrode material layer 420 is formed covering the first electrode layer 110, the third electrode layer 130, and the exposed substrate 100 of the first electrode layer 110 and the third electrode layer 130; Reference Figure 8 The second electrode material layer 420 is graphically represented, and a portion of the second electrode material layer 420 at the top of the third electrode layer 130 is removed, so that the remaining second electrode material layers 420 on both sides of the third electrode layer 130 are isolated from each other. The second electrode material layer 420 on the side of the third electrode layer 130 closer to the capacitor region 100C is retained as the second electrode layer 120, and the second electrode material layer 420 on the side of the third electrode layer 130 away from the capacitor region 100C is retained as the fourth electrode layer 140.

[0137] The second electrode layer 120 and the fourth electrode layer 140, which are in contact with the channel layer 200, are obtained by patterning the same electrode material layer. Therefore, the second electrode layer 120 and the fourth electrode layer 140, which are in contact with the channel layer 200, have the same structure, which helps to simplify the process flow and improve the process efficiency.

[0138] Accordingly, in this embodiment, in the step of forming a second electrode layer 120 for contacting the channel layer 200, the second electrode layer 120 is formed on a second dielectric layer 220 that is integrally connected with the first dielectric layer 210.

[0139] In this embodiment, in the step of forming the fourth electrode layer 140, the fourth electrode layer 140 covers the channel layer 200 located on the second sidewall of the third electrode layer 130 and a portion of the channel layer 200 on the top of the third electrode layer 130, with the second sidewall facing away from the capacitor region 100C.

[0140] The fourth electrode layer 140 covers the channel layer 200 located on the second sidewall of the third electrode layer 130 and a portion of the channel layer 200 on top of the third electrode layer 130. The second sidewall faces away from the capacitor region 100C, which helps to ensure that the fourth electrode layer 140 and the channel layer 200 are in full contact. Therefore, when the channel layer 200 is turned on, it helps to ensure that the fourth electrode layer 140 has good electrical connection performance to the second electrode layer 120 through the channel layer 200 to load electrical signals.

[0141] In this embodiment, the material of the fourth electrode layer 140 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0142] Continue to refer to Figure 8 In the step of forming a second dielectric layer 220 on the second electrode layer 120 in contact with the channel layer 200, the second dielectric layer 220 also covers the top of the fourth electrode layer 140.

[0143] In this embodiment, during the step of forming the second dielectric layer 220 covering the top surface of the second electrode layer 120 in contact with the channel layer 200, the top of the fourth electrode layer 140 is also exposed. Therefore, the second dielectric layer 220 extends into the transistor region 100M and covers the top of the fourth electrode layer 140. Thus, in this embodiment, the second dielectric layer 220 covering the top surface of the second electrode layer 120 in contact with the channel layer 200 also covers the top of the fourth electrode layer 140. Correspondingly, the second dielectric layer 220 is also used to isolate the fourth electrode layer 140 from the dummy electrode layer subsequently formed on the fourth electrode layer 140.

[0144] refer to Figure 9 Before the formation of the second electrical connection structure, the method further includes: forming a dummy electrode layer 150 on the first dielectric layer 210 on top of the fourth electrode layer 140.

[0145] When the number of first electrode layers 110 is multiple, the second electrical connection structure formed subsequently penetrates multiple first electrode layers 110. The dummy electrode layer 150 is used to increase the thickness of the metal film at the location of the first electrical connection structure formed subsequently, so that the thickness of the metal film etched when forming the first electrical connection structure is consistent with the thickness of the metal film etched when forming the second electrical connection structure. This allows the etching process when forming the first electrical connection structure and the etching process when forming the second electrical connection structure to use the same etching process parameters. In other words, the first electrical connection structure and the second electrical connection structure can be formed in the same step, which improves process efficiency.

[0146] In this embodiment, the steps of forming a first electrode layer 110 and a dummy electrode layer 150 above the second electrode layer 120 in contact with the channel layer 200 include: forming a third electrode material layer (not shown) covering the second dielectric layer 220; patterning the third electrode material layer, retaining the third electrode material layer located in the capacitor region 100C as the first electrode layer 110, and retaining a portion of the third electrode material layer located on the fourth electrode layer 140 as the dummy electrode layer 150.

[0147] The dummy electrode layer 150 and the first electrode layer 110 above the second electrode layer 120 in contact with the channel layer 200 are obtained by patterning the same electrode material layer. Thus, the dummy electrode layer 150 and the first electrode layer 110 above the second electrode layer 120 in contact with the channel layer 200 are of the same layer structure, which is beneficial to simplify the process flow and improve the process efficiency. Moreover, it also makes the thickness of the dummy electrode layer 150 and the first electrode layer 110 through which the second electrical connection structure penetrates equal, and further makes the thickness of the metal film layer etched when forming the first electrical connection structure and the thickness of the metal film layer etched when forming the second electrical connection structure tend to be consistent, which is further beneficial to forming the first electrical connection structure and the second electrical connection structure in the same step.

[0148] Accordingly, in this embodiment, the material of the dummy electrode layer 150 includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0149] Reference Figures 10 to 12 , Figure 11 for Figure 10 Top view, Figure 12 for Figure 10 The circuit diagram shows that a first electrical connection structure 310, which is electrically connected to the fourth electrode layer 140, is formed in the transistor region 100M; and a second electrical connection structure 320, which is electrically connected to the first electrode layer 110, is formed in the capacitor region 100C.

[0150] The first electrical connection structure 310 is used for electrical connection with the fourth electrode layer 140.

[0151] In this embodiment, during the step of forming the first electrical connection structure 310, the first electrical connection structure 310 penetrates the fourth electrode layer 140 and is electrically connected to the fourth electrode layer 140.

[0152] Specifically, in this embodiment, in the step of forming the first electrical connection structure 310, the positioning structure corresponding to the first electrical connection structure 310 is used as the forming position to form the first electrical connection structure 310 penetrating the fourth electrode layer 140. The first electrical connection structure 310 penetrates the fourth electrode layer 140 and makes full contact with the fourth electrode layer 140, thereby achieving better electrical connection performance.

[0153] In this embodiment, in the step of forming the first electrical connection structure 310, the material of the first electrical connection structure 310 is a conductive material. As an example, the material of the first electrical connection structure 310 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0154] Accordingly, in this embodiment, the first electrical connection structure 310 also penetrates the dummy electrode layer 150 on the fourth electrode layer 140.

[0155] When the number of first electrode layers 110 is multiple, the second electrical connection structure penetrates multiple first electrode layers 110. The dummy electrode layer 150 increases the thickness of the metal film at the location of the first electrical connection structure 310, so that the thickness of the metal film etched when forming the first electrical connection structure 310 is close to the thickness of the metal film etched when forming the second electrical connection structure 320. This allows the etching process when forming the first electrical connection structure 310 and the etching process when forming the second electrical connection structure 320 to use the same etching process parameters, which is beneficial to forming the first electrical connection structure 310 and the second electrical connection structure 320 in the same step, thus improving process efficiency.

[0156] The second electrical connection structure 320 is used for electrical connection with the first electrode layer 110.

[0157] In this embodiment, in the step of forming the second electrical connection structure 320, the second electrical connection structure 320 penetrates the first electrode layer 110 and is electrically connected to the first electrode layer 110.

[0158] Specifically, in this embodiment, in the step of forming the second electrical connection structure 320, the positioning structure corresponding to the second electrical connection structure 320 is used as the forming position to form the second electrical connection structure 320 that penetrates the first electrode layer 110. The second electrical connection structure 320 penetrates the first electrode layer 110 and makes full contact with the first electrode layer 110, thereby achieving better electrical connection performance.

[0159] It should be noted that in the step of forming the second electrical connection structure 320, when the number of first electrode layers 110 is multiple, the second electrical connection structure 320 penetrates through multiple first electrode layers 110 and is electrically connected to the multiple first electrode layers 110.

[0160] In this embodiment, during the step of forming the second electrical connection structure 320, the material of the second electrical connection structure 320 is a conductive material. As an example, the material of the second electrical connection structure 320 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0161] Accordingly, in this embodiment, during the step of forming the first electrical connection structure 310, the first electrical connection structure 310 also penetrates the dummy electrode layer 150 on the fourth electrode layer 140.

[0162] In this embodiment, the first electrical connection structure 310 and the second electrical connection structure 320 are formed in the same step, which helps to simplify the process steps and improve the process efficiency.

[0163] In this embodiment, the steps of forming the first electrical connection structure 310 and the second electrical connection structure 320 include: forming a first through hole penetrating the fourth electrode layer 140 and the dummy electrode layer 150, and forming a second through hole penetrating the first electrode layer 110; filling the first through hole and the second through hole, forming the first electrical connection structure 310 in the first through hole, and forming the second electrical connection structure 320 in the second through hole.

[0164] Specifically, in this embodiment, the first through hole and the second through hole are formed in the same step, and the first through hole and the second through hole are filled in the same step.

[0165] In this embodiment, the forming method further includes: forming a third electrical connection structure 330 in the transistor region 100M that is electrically connected to the third electrode layer 130 exposed by the channel layer 200.

[0166] The third electrical connection structure 330 is used to electrically connect with the third electrode layer 130, thereby loading an electrical signal onto the third electrode layer 130.

[0167] In this embodiment, the material of the third electrical connection structure 330 is a conductive material. As an example, the material of the third electrical connection structure 330 includes one or more of W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al.

[0168] Specifically, in this embodiment, as Figure 12 As shown in the circuit structure, the transistor structure in transistor region 100M acts as a switch and is connected to the capacitor structure in capacitor region 100C. As a circuit structure in the power supply voltage regulator circuit, the charging and discharging of the capacitor structure is controlled by the opening and closing of the switch, thereby adjusting the capacitance value of the capacitor structure.

[0169] It should be noted that, in other embodiments, a fourth electrical connection structure may also be formed in the capacitor region, which is electrically connected to the second electrode layer of the capacitor region, and is used to load an electrical signal onto the second electrode layer when the channel layer is not conducting.

[0170] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes adjacent capacitor regions and transistor regions; The third electrode layer is located on the substrate of the transistor region; A first dielectric layer is located on the third electrode layer; The channel layer is located on the first dielectric layer above the third electrode layer; The first electrode layer and the second electrode layer are stacked alternately from bottom to top on the substrate of the capacitor region. Each second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer. The second dielectric layer is located between the adjacent first electrode layer and the second electrode layer; A fourth electrode layer is located in the transistor region, the fourth electrode layer is in contact with the channel layer and is isolated from the second electrode layer; A first electrical connection structure is located in the transistor region and is electrically connected to the fourth electrode layer; The second electrical connection structure is located in the capacitor region and is electrically connected to the first electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, The adjacent second dielectric layer located below the second electrode layer that is in contact with the channel layer is integrally connected with the first dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, The second electrode layer, which is closest to the substrate, extends into the transistor region and contacts the channel layer, while being isolated from the third electrode layer.

4. The semiconductor structure as described in claim 1 or 3, characterized in that, The first electrode layer and the third electrode layer are of the same layer structure; The second electrode layer and the fourth electrode layer, which are in contact with the channel layer, are of the same structure.

5. The semiconductor structure as described in claim 1, characterized in that, Along the arrangement direction perpendicular to the capacitor region and the transistor region, a portion of the third electrode layer is exposed by the channel layer; The semiconductor structure further includes a third electrical connection structure located in the transistor region and electrically connected to the third electrode layer exposed by the channel layer.

6. The semiconductor structure as described in claim 1 or 3, characterized in that, The channel layer covers the top and sidewalls of the third electrode layer along the arrangement direction of the capacitor region and the transistor region; The second electrode layer, which is in contact with the channel layer, covers the channel layer located on the first sidewall of the third electrode layer and a portion of the channel layer on top of the third electrode layer, with the first sidewall facing the capacitor region; The fourth electrode layer covers the channel layer located on the second sidewall of the third electrode layer and a portion of the channel layer on top of the third electrode layer, with the second sidewall facing away from the capacitor region.

7. The semiconductor structure as described in claim 1, characterized in that, The first electrical connection structure penetrates the fourth electrode layer and is electrically connected to the fourth electrode layer; the second electrical connection structure penetrates the first electrode layer and is electrically connected to the first electrode layer.

8. The semiconductor structure as described in claim 7, characterized in that, The second dielectric layer, which covers the top surface of the second electrode layer in contact with the channel layer, also covers the top of the fourth electrode layer; The semiconductor structure further includes: a dummy electrode layer located on the first dielectric layer on top of the fourth electrode layer; The first electrical connection structure also penetrates the dummy electrode layer on the fourth electrode layer.

9. The semiconductor structure as described in claim 1, characterized in that, The material of the first dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; The material of the second dielectric layer includes any one or more of La2O3, HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO, and SiN; The material of the first electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the second electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the third electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The material of the fourth electrode layer includes one or more of Pt, Ni, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN, and Al; The channel layer is made of polycrystalline silicon or indium gallium zinc oxide.

10. The semiconductor structure as claimed in claim 1, characterized in that, The thickness of the third electrode layer is to 11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, comprising adjacently arranged capacitor regions and transistor regions; A third electrode layer is formed on the substrate of the transistor region; A first dielectric layer is formed on the third electrode layer; A channel layer is formed on the first dielectric layer on the third electrode layer; A first electrode layer and a second electrode layer, stacked alternately from bottom to top, and a second dielectric layer located between adjacent first electrode layers and second electrode layers are formed on the substrate of the capacitor region. Each second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer. A fourth electrode layer is formed on the substrate of the transistor region, the fourth electrode layer being in contact with the channel layer and isolated from the second electrode layer; A first electrical connection structure electrically connected to the fourth electrode layer is formed in the transistor region; A second electrical connection structure that is electrically connected to the first electrode layer is formed in the capacitor region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the second electrode layer that contacts the channel layer, the first dielectric layer and the second dielectric layer are formed in the same step so that the first dielectric layer and the second dielectric layer are connected as a single structure. In the step of forming a second electrode layer for contacting the channel layer, the second electrode layer is formed on a second dielectric layer that is integrally connected with the first dielectric layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the second electrode layer closest to the substrate, the second electrode layer extends into the transistor region and contacts the channel layer, and is isolated from the third electrode layer.

14. The method for forming a semiconductor structure as described in claim 11 or 13, characterized in that, The steps of forming the first electrode layer and the third electrode layer include: forming a first electrode material layer covering the substrate; The first electrode material layer is graphically represented, and the first electrode material layer located in the capacitor region is retained as the first electrode layer, while the first electrode material layer located in the transistor region is retained as the third electrode layer. The step of forming a fourth electrode layer and a second electrode layer in contact with the channel layer includes: forming a second electrode material layer covering the first electrode layer, the third electrode layer, and the substrate exposed by the first electrode layer and the third electrode layer; The second electrode material layer is graphically represented, and a portion of the second electrode material layer at the top of the third electrode layer is removed, so that the remaining second electrode material layers on both sides of the third electrode layer are isolated. The second electrode material layer on the side of the third electrode layer closer to the capacitor region is retained as the second electrode layer, and the second electrode material layer on the side of the third electrode layer away from the capacitor region is retained as the fourth electrode layer.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the channel layer, along the arrangement direction perpendicular to the capacitor region and the transistor region, a portion of the third electrode layer is exposed by the channel layer; The forming method further includes: forming a third electrical connection structure in the transistor region that is electrically connected to the third electrode layer exposed by the channel layer.

16. The method for forming a semiconductor structure as described in claim 11 or 13, characterized in that, In the step of forming the channel layer, the channel layer covers the top and sidewalls of the third electrode layer along the arrangement direction of the capacitor region and the transistor region; In the step of forming a second electrode layer in contact with the channel layer, the second electrode layer covers the channel layer of the first sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the first sidewall facing the capacitor region; In the step of forming the fourth electrode layer, the fourth electrode layer covers the channel layer of the second sidewall of the third electrode layer and a portion of the channel layer at the top of the third electrode layer, with the second sidewall facing away from the capacitor region.

17. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the first electrical connection structure, the first electrical connection structure penetrates the fourth electrode layer and is electrically connected to the fourth electrode layer; In the step of forming the second electrical connection structure, the second electrical connection structure penetrates the first electrode layer and is electrically connected to the first electrode layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, In the step of forming the second dielectric layer on the second electrode layer in contact with the channel layer, the second dielectric layer also covers the top of the fourth electrode layer; Before forming the second electrical connection structure, the method further includes: forming a dummy electrode layer on the first dielectric layer on top of the fourth electrode layer; In the step of forming the first electrical connection structure, the first electrical connection structure also penetrates the dummy electrode layer on the fourth electrode layer.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The steps of forming the first electrode layer over the second electrode layer in contact with the channel layer and forming the dummy electrode layer include: forming a third electrode material layer covering the second dielectric layer; The third electrode material layer is graphically represented, and the third electrode material layer located in the capacitor region is retained as the first electrode layer, while a portion of the third electrode material layer located on the fourth electrode layer is retained as the dummy electrode layer.

20. The method for forming a semiconductor structure as described in claim 11 or 18, characterized in that, The first electrical connection structure and the second electrical connection structure are formed in the same step.

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