Manufacturing method of lightly doped drain electrode and semiconductor device

Abstract

The invention relates to a manufacturing method of a lightly doped drain electrode and a semiconductor device, and the method comprises the steps: obtaining a semiconductor structure which comprises a substrate, a grid electrode on the substrate, and a dielectric anti-reflection coating on the grid electrode, and the dielectric anti-reflection coating is an anti-reflection coating during the photoetching of the grid electrode; and ion implantation is carried out in the substrate, so that a lightly doped drain electrode region is formed in the substrate, and the grid electrode and the dielectric anti-reflection coating are used as an implantation barrier layer together. According to the method, the dielectric anti-reflection coating during grid photoetching is reserved after LDD ion implantation, the characteristic that patterns of the dielectric anti-reflection coating and the grid are consistent is utilized, injection blocking is carried out on ions injected by the LDD through the grid and the dielectric anti-reflection coating together, and therefore compared with injection blocking carried out through the grid, the method has higher injection blocking capacity, and the performance of the LDD is improved. Therefore, ions injected by the LDD can be prevented from being injected into the conductive channel.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a lightly doped drain, and also to a semiconductor device. Background Art

[0002] As the semiconductor line width gradually decreases, in order to improve the process window, the thickness of polysilicon (such as polysilicon gate) is gradually reduced. In an exemplary CMOS (complementary metal oxide semiconductor) process, the ion implantation of lightly doped drain (LDD) adopts a polysilicon self-aligned implantation process.

[0003] However, as the thickness of polysilicon becomes thinner, the injection blocking effect of polysilicon during LDD injection becomes worse, and some of the injected ions will pass through the polysilicon and be injected into the conductive channel of the device, which will lead to the uniformity of some electrical parameters of the device, such as the uniformity of Vt (threshold voltage) and Idsat (saturation current) and the stability becoming worse. However, if the energy of LDD injection is reduced to enable the polysilicon layer to block the injected ions, the reliability requirements of the hot carrier injection (HCI) effect of the device cannot be met. Summary of the invention

[0004] Based on this, it is necessary to provide a method for manufacturing a lightly doped drain of an ion-implanted conductive channel that can avoid LDD implantation.

[0005] A method for manufacturing a lightly doped drain comprises: obtaining a semiconductor structure, the semiconductor structure comprising a substrate, a gate on the substrate, and a dielectric anti-reflection coating on the gate, wherein the dielectric anti-reflection coating is an anti-reflection coating during photolithography of the gate; performing ion implantation into the substrate to form a lightly doped drain region in the substrate, wherein the gate and the dielectric anti-reflection coating together serve as an implantation barrier layer.

[0006] The above-mentioned method for manufacturing a lightly doped drain retains the dielectric anti-reflective coating during gate lithography until after LDD ion implantation, and utilizes the characteristic that the dielectric anti-reflective coating and the gate have consistent patterns, so that the gate and the dielectric anti-reflective coating are used together to block the LDD injected ions. Therefore, compared with injection blocking through the gate, it has a stronger injection blocking ability, thereby preventing the LDD injected ions from being injected into the conductive channel.

[0007] In one embodiment, after the step of obtaining the semiconductor structure and before the step of performing ion implantation into the substrate, a step of photolithographically forming a lightly doped drain implantation photoresist layer on the semiconductor structure is also included.

[0008] In one embodiment, the dielectric anti-reflective coating comprises a silicon oxynitride layer.

[0009] In one embodiment, the gate comprises a polysilicon gate.

[0010] In one embodiment, the semiconductor structure further includes a gate dielectric layer on the substrate, and the gate is located on the gate dielectric layer.

[0011] In one embodiment, the size and shape of the cross-section of the dielectric anti-reflection coating are consistent with the upper surface of the gate.

[0012] In one of the embodiments, the method further includes removing the dielectric anti-reflection coating.

[0013] In one of the embodiments, before the step of removing the dielectric anti-reflection coating, the step of thermally oxidizing the semiconductor structure is also included; the step of removing the dielectric anti-reflection coating includes: removing the dielectric anti-reflection coating by dry etching.

[0014] In one embodiment, the thermal oxidation process comprises rapid thermal oxidation.

[0015] In one embodiment, the thermal oxidation treatment is performed before the step of implanting ions into the substrate.

[0016] In one embodiment, the thickness of the gate is not greater than

[0017] In one embodiment, the method for manufacturing the lightly doped drain is applied to the manufacture of a CMOS device with an operating voltage of 5 volts.

[0018] In one embodiment, the method for manufacturing the lightly doped drain is applied to the manufacture of devices with a line width of 0.11 microns or less.

[0019] It is also necessary to provide a semiconductor device, which is manufactured by the manufacturing method described in any of the aforementioned embodiments.

[0020] In one embodiment, the thickness of the gate is not greater than

[0021] In one embodiment, the semiconductor device is a CMOS device with an operating voltage of 5 volts.

[0022] In one embodiment, the line width of the semiconductor device is 0.11 microns or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0024] Figure 1 is a flow chart of a method for manufacturing a lightly doped drain in one embodiment of the present application;

[0025] Figure 2 is a schematic cross-sectional view of a portion of a semiconductor structure obtained in step S110 in one embodiment of the present application;

[0026] Figure 3 is a schematic diagram of performing LDD implantation on a semiconductor structure in one embodiment of the present application;

[0027] Figure 4 is a schematic cross-sectional view of a portion of a semiconductor structure having a lightly doped drain formed therein in an embodiment of the present application;

[0028] Figure 5 It is a flow chart of a method for manufacturing a lightly doped drain in another embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0031] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0032] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0033] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0035] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0036] Regarding the technical problem that the LDD-implanted ions mentioned in the background technology will pass through the polysilicon gate and be injected into the conductive channel, it will be more obvious in the process of small line width devices. For example, for a CMOS device with a line width of less than 0.11 microns and an operating voltage of 5V, a higher LDD injection energy (e.g., 80 keV) is used so that the LDD region can wrap around the source region / drain region, then some of the LDD-implanted ions will pass through the polysilicon gate and enter the conductive channel, resulting in the uniformity of some electrical parameters of the device (e.g., the uniformity of Vt and the uniformity of Idsat) and stability being deteriorated. If the LDD injection energy is reduced, for example, to 70 keV or even 60 keV, the uniformity of Vt and Idsat of the device, as well as the HCI reliability will be deteriorated.

[0037] The present application proposes a method for manufacturing a lightly doped drain electrode of an ion-implanted conductive channel capable of avoiding LDD implantation. Figure 1 1 is a flow chart of a method for manufacturing a lightly doped drain in an embodiment of the present application, comprising the following steps:

[0038] S110, obtaining a semiconductor structure.

[0039] Figure 2 is a schematic cross-sectional view of a portion of the semiconductor structure in one embodiment of the present application, Figures 2 to 4 The structure shown is bilaterally symmetrical, so Figures 2 to 4Only one side of the structure is labeled. The semiconductor structure includes a substrate 10, a gate 24 on the substrate 10, and a dielectric anti-reflective coating (DARC) 32 on the gate 24. The gate 24 is formed by photolithography and etching of the gate material, and the dielectric anti-reflective coating 32 is used to suppress the reflected light generated by the structure below the photoresist when the gate 24 is photolithographically exposed (exposing the photoresist on the gate 24), so as to avoid the reflected light and the incident light from interfering with each other to form standing waves. The standing wave distribution of light intensity will cause the edge profile of the photoresist to have certain fluctuations after development, thereby reducing the pattern accuracy of the photoresist. Therefore, by setting the dielectric anti-reflective coating 32, the standing wave effect can be suppressed, thereby improving the photolithography accuracy. Specifically, after forming a layer of gate material on the substrate 10, a layer of dielectric anti-reflection coating 32 is formed on the gate material, and then a photoresist is coated on the dielectric anti-reflection coating 32, and the photoresist is exposed (exposed using a gate photomask), developed, and other photolithography processes are performed to form a gate pattern (i.e., the photoresist is removed at the position where the gate 24 is not formed). Then, the gate 24 is etched, and the remaining photoresist is used as a barrier layer during etching. After the etching is completed, the remaining photoresist is removed.

[0040] Since the gate 24 and the dielectric anti-reflection coating 32 are formed by photolithography and etching, their patterns are consistent, that is, the size and shape of the cross section of the dielectric anti-reflection coating 32 are the same or approximately the same as the upper surface of the gate 24 .

[0041] In one embodiment of the present application, the substrate 10 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 1 In the illustrated embodiment, the material used to form the substrate 10 is single crystal silicon.

[0042] In one embodiment of the present application, the gate 24 is made of polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the material of the gate 24 .

[0043] exist Figure 1In the illustrated embodiment, the semiconductor structure further includes a gate dielectric layer 22 on the substrate 10, and a gate 24 is located on the gate dielectric layer 22. In one embodiment of the present application, the gate dielectric layer 22 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer 22 may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0044] S120, performing LDD implantation into the substrate, with the gate and the dielectric anti-reflection coating together serving as an implantation barrier layer.

[0045] See also Figure 3 and Figure 4 , ion implantation is performed into the substrate 10 , thereby forming a lightly doped drain region 12 in the substrate 10 .

[0046] In one embodiment of the present application, the material of the dielectric anti-reflection coating 32 is silicon oxynitride.

[0047] In the above-mentioned method for manufacturing the lightly doped drain, the dielectric anti-reflective coating 32 during the photolithography of the gate 24 is retained until after the LDD ion implantation. The dielectric anti-reflective coating 32 is consistent with the pattern of the gate 24 after the photolithography and etching of the gate, and the LDD injected ions are blocked by the gate 24 and the dielectric anti-reflective coating 32 together. Therefore, compared with the injection blocking through the gate 24, it has a stronger injection blocking ability, thereby preventing the LDD injected ions from being injected into the conductive channel.

[0048] Figure 5 FIG. 1 is a flow chart of a method for manufacturing a lightly doped drain in another embodiment, comprising the following steps:

[0049] S110, obtaining a semiconductor structure.

[0050] The semiconductor structure includes a substrate 10, a gate 24 on the substrate 10, and a dielectric anti-reflection coating 32 on the gate 24. The dielectric anti-reflection coating is an anti-reflection coating during photolithography of the gate 24, and is used to suppress the reflected light generated by the structure below the photoresist during photolithography exposure of the gate 24. That is, after a layer of gate material is formed on the substrate 10, a layer of dielectric anti-reflection coating 32 is formed on the gate material, and then a photoresist is coated on the dielectric anti-reflection coating 32, and the photoresist is subjected to photolithography processes such as exposure and development to form a gate pattern on the photoresist, and then the gate 24 is etched, and the remaining photoresist is used as a barrier layer during etching. After the etching is completed, the remaining photoresist is removed.

[0051] Since the gate 24 and the dielectric anti-reflection coating 32 are formed by photolithography and etching, their patterns are consistent, that is, the size and shape of the cross section of the dielectric anti-reflection coating 32 are the same or approximately the same as the upper surface of the gate 24 .

[0052] In one embodiment of the present application, the substrate 10 is a semiconductor substrate, and its material can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc., and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. Figure 1 In the illustrated embodiment, the material used to form the substrate 10 is single crystal silicon.

[0053] In one embodiment of the present application, the gate 24 is made of polysilicon. In other embodiments, metal, metal nitride, metal silicide or similar compounds may be used as the material of the gate 24 .

[0054] exist Figure 1 In the illustrated embodiment, the semiconductor structure further includes a gate dielectric layer 22 on the substrate 10, and a gate 24 is located on the gate dielectric layer 22. In one embodiment of the present application, the gate dielectric layer 22 may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in a vacuum), or the gate dielectric layer 22 may include a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).

[0055] S112, forming a lightly doped drain implantation photoresist layer on the semiconductor structure by photolithography.

[0056] See also Figure 3 The purpose of the photoresist layer 92 for forming the lightly doped drain by photolithography is to distinguish the NLDD and PLDD (i.e., the N-type lightly doped drain and the P-type lightly doped drain) and the area where the LDD is not formed. However, the LDD injection will be blocked by the gate 24, and the injection area (i.e., the area where the LDD is formed) will not shift with the alignment shift of the photoresist layer 92.

[0057] S120, performing LDD implantation into the substrate, with the gate and the dielectric anti-reflection coating together serving as an implantation barrier layer.

[0058] See also Figure 3 and Figure 4 , ion implantation is performed into the substrate 10 , thereby forming a lightly doped drain region 12 in the substrate 10 .

[0059] After LDD implantation, the photoresist layer 92 is removed.

[0060] S130, removing the dielectric anti-reflection coating.

[0061] In one embodiment of the present application, the material of the dielectric anti-reflection coating 32 is silicon oxynitride.

[0062] In one embodiment of the present application, after step S110 and before step S130, a step of thermally oxidizing the semiconductor structure is further included. The thermal oxidation process is used to repair the damage caused by etching of the gate 24. The photoresist layer 92 must be removed before the thermal oxidation process. In one embodiment of the present application, the thermal oxidation process uses rapid thermal oxidation (RTO).

[0063] For the technical solution of using only the gate 24 for self-aligned LDD injection, the dielectric anti-reflective coating 32 is removed after the etching of the gate 24 is completed and before the aforementioned thermal oxidation treatment. Therefore, phosphoric acid wet etching can be used to remove the dielectric anti-reflective coating 32, and then thermal oxidation treatment is performed. However, the dielectric anti-reflective coating 32 of the present application is removed after LDD injection, so it will undergo the thermal oxidation process and be affected by the thermal oxidation treatment. Taking the dielectric anti-reflective coating 32 as a silicon oxynitride layer as an example, the properties of silicon oxynitride change after thermal oxidation treatment, making its properties close to SIO2, so it can no longer be removed by phosphoric acid. In one embodiment of the present application, step S130 is to remove the dielectric anti-reflective coating 32 by dry etching. Therefore, the method for making a lightly doped drain of the present application can ensure the blocking ability of the polysilicon self-aligned injection process to LDD injected ions without increasing the process steps by adjusting the order of removing the dielectric anti-reflective coating 32 in the process steps and matching a suitable dry etching menu, thereby improving the uniformity of the corresponding electrical parameters of the device and the HCI reliability.

[0064] In one embodiment of the present application, the step of thermal oxidation treatment is performed after step S110 and before step S120.

[0065] In actual production, the uniformity and stability problems of some electrical parameters of the device described in the background technology are only found in some devices. In one embodiment of the present application, the above-mentioned method for making a lightly doped drain is applicable to a CMOS device with an operating voltage of 5 volts. Since the ions injected by LDD enter the conductive channel because the polysilicon gate is thin, the above-mentioned method for making a lightly doped drain is particularly applicable to polysilicon gates with a thickness of 5 volts. The device has a corresponding device line width of 0.11 microns or less.

[0066] The present application provides a semiconductor device, wherein the lightly doped drain region is formed by the manufacturing method described in any of the above embodiments. The cross-sectional structure of the semiconductor device after the lightly doped drain region 12 is formed can be referred to as Figure 4 , including a substrate 10 , a lightly doped drain region 12 in the substrate 10 , a gate dielectric layer 22 on the substrate 10 , and a gate 24 on the gate dielectric layer 22 .

[0067] In one embodiment of the present application, the semiconductor device is a CMOS device with an operating voltage of 5 volts.

[0068] In one embodiment of the present application, the thickness of the polysilicon gate of the semiconductor device is not greater than

[0069] In one embodiment of the present application, the line width of the semiconductor device is 0.11 microns or less.

[0070] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0071] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0072] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a lightly doped drain, comprising: Acquire a semiconductor structure, the semiconductor structure comprising a substrate, a gate on the substrate, and a dielectric anti-reflection coating on the gate, wherein the dielectric anti-reflection coating is an anti-reflection coating during photolithography of the gate; Ions are implanted into the substrate to form a lightly doped drain region in the substrate, and the gate and the dielectric anti-reflection coating together serve as an implantation barrier layer.

2. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: After the step of obtaining the semiconductor structure and before the step of performing ion implantation into the substrate, the method further includes the step of photolithographically forming a lightly doped drain implantation photoresist layer on the semiconductor structure.

3. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: The dielectric antireflection coating includes a silicon oxynitride layer.

4. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: The gate includes a polysilicon gate.

5. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: The semiconductor structure further includes a gate dielectric layer on the substrate, and the gate is located on the gate dielectric layer.

6. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: The size and shape of the cross section of the dielectric anti-reflection coating are consistent with the upper surface of the gate.

7. The method for manufacturing a lightly doped drain according to claim 1, characterized in that: The method also includes the step of removing the dielectric anti-reflective coating.

8. The method for manufacturing a lightly doped drain according to claim 7, characterized in that: Before the step of removing the dielectric anti-reflection coating, the step of thermally oxidizing the semiconductor structure is also included; The step of removing the dielectric anti-reflection coating comprises: removing the dielectric anti-reflection coating by dry etching.

9. The method for manufacturing a lightly doped drain according to claim 8, characterized in that: The thermal oxidation treatment comprises rapid thermal oxidation; and / or The thermal oxidation treatment is performed before the step of implanting ions into the substrate.

10. A semiconductor device, characterized in that: The lightly doped drain region of the semiconductor device is formed by the manufacturing method according to any one of claims 1 to 9.

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