Fet-type igbt device and method of manufacturing the same

Abstract

The application discloses an FS-IGBT device, which comprises a drift region, a well region formed on the surface of the drift region, a gate structure, and an emitter region formed on the surface of the well region and self-aligned with the gate structure. A second semiconductor material layer is formed on the back surface of a semiconductor substrate, and the band gap of the second semiconductor material layer is lower than that of the semiconductor substrate. A hydrogen implantation layer is formed by hydrogen implantation from the back surface, and the top surface of the hydrogen implantation layer is in contact with the bottom surface of the drift region. A P-type heavily doped collector region is in contact with the bottom surface of the hydrogen implantation layer and forms a back surface PN junction. The top surface of the collector region is in the same level as or below the top surface of the second semiconductor material layer. The application also discloses a manufacturing method of the FS-IGBT device. The application improves the material of the collector region, reduces the opening voltage of the back surface PN junction, the on-state voltage drop and the on-state loss of the whole device, and further improves the switching characteristic.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor power devices, and in particular to a field stop (FS) insulated gate bipolar transistor (IGBT) device; the present invention also relates to a FS-IGBT device and a manufacturing method thereof. Background Art

[0002] An IGBT is a voltage-driven device composed of a metal oxide semiconductor field-effect transistor (MOSFET) and a bipolar junction transistor (BJT). MOSFETs offer high input impedance and fast switching speeds, but also low carrier density and high on-resistance. BJTs offer high current density and low on-voltage drop, but also high drive current. IGBTs combine the advantages of both, offering low drive losses, fast switching speeds, and low on-voltage drop. Consequently, they are widely used in medium- and high-voltage applications such as home appliances, photovoltaics, industrial control, new energy vehicles, and rail transit.

[0003] The FS-IGBT device has a field resistance layer, i.e., a field stop layer, and a transparent anode structure. The field resistance layer can appropriately reduce the thickness of the drift region, speed up the switching speed of the device, and reduce the conduction loss. The transparent anode structure regulates the injection efficiency of the collector region, achieving a good compromise between the conduction loss and switching speed of the IGBT device.

[0004] The collector side of the FS-IGBT device has a PN junction diode structure. When the device is turned on, the channel on the front side of the device opens, and electrons are injected from the emitter region into the drift region. Simultaneously, the PN junction on the collector side opens, and a large number of holes are injected from the collector region into the drift region. As a result, a large number of carriers accumulate in the drift region, forming a conductivity modulation effect. This significantly reduces the IGBT's on-resistance and, in turn, its conduction losses.

[0005] In existing Si-based devices, IGBTs are fabricated on a silicon substrate. Since Si has a bandgap of approximately 1.12 eV, the turn-on voltage of the silicon-based PN junction diode is 0.7 V, nearly half the on-state voltage drop of existing IGBTs. This means that 50% of the IGBT's conduction losses are caused by the collector-side PN junction diode. Therefore, further improvements to the collector region structure to lower the turn-on voltage of the collector-side PN junction diode would significantly reduce device conduction losses.

[0006] like Figure 1 The figure shows the structure of an existing FS-IGBT device. Existing FS-IGBT devices generally use N-type devices. Taking N-type devices as an example, existing FS-IGBT devices include:

[0007] The drift region 103 is composed of an N-type lightly doped region formed on the surface of the silicon substrate.

[0008] A P-type doped well region 105 is formed on the surface of the drift region 103 .

[0009] The gate structure includes a gate oxide layer 104 and a polysilicon gate 106 stacked in sequence. Figure 1 In the embodiment, the gate structure is a trench gate, the gate oxide layer 104 is formed on the inner surface of the gate trench, the polysilicon gate 106 fills the gate trench, the gate trench vertically passes through the well region 105, and the surface of the well region 105 covered by the side of the gate structure serves as the channel region. The gate structure can also adopt a planar gate.

[0010] An N-type heavily doped emitter region 107 is formed on the surface of the well region 105 and is self-aligned with the gate structure.

[0011] An N-type doped field stop layer 102 is formed on the back side of the drift region 103 . The field stop layer 102 is usually formed by backside implantation. The doping concentration of the field stop layer 102 is greater than that of the drift region 103 .

[0012] A heavily P-type doped collector region 101 is formed on the back surface of the field stop layer 102 .

[0013] The top surface of the collector region 101 and the bottom surface of the field stop layer 102 are in contact with each other and form a back PN junction.

[0014] The turn-on voltage of the back PN junction is mainly determined by the band gap width of the silicon material. The band gap width of silicon is about 1.12 eV, and the turn-on voltage of the back PN junction is about 0.7V.

[0015] The front metal layer 109 is patterned to form a gate and an emitter. Figure 1 Only the emitter is shown in FIG. 1 , and the gate composed of the front metal layer 109 is not shown in FIG. Figure 1 The gate is connected to the polysilicon gate 106 at the bottom, and the emitter is connected to the emitter region 107 at the bottom. A well contact region 108 is also formed on the surface of the well region 105. The well contact region 108 is heavily doped with the second conductivity type, and the emitter is also connected to the well contact region 108.

[0016] A collector electrode composed of a back metal layer 110 is formed on the back side of the collector region 101 . Summary of the Invention

[0017] The technical problem to be solved by the present invention is to provide an FS-IGBT device that improves the material of the collector region, thereby reducing the turn-on voltage of the back PN junction and, in turn, the on-state voltage drop and conduction loss of the entire device. To this end, the present invention also provides a method for manufacturing the FS-IGBT device.

[0018] To solve the above technical problems, the present invention provides a FS-IGBT device comprising:

[0019] The drift region consists of an N-type lightly doped region formed on the surface of the semiconductor substrate.

[0020] A P-type doped well region is formed on the surface of the drift region.

[0021] The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0022] An N-type heavily doped emitter region is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure.

[0023] A second semiconductor material layer is formed on the back side of the semiconductor substrate, wherein the band gap of the second semiconductor material layer is lower than the band gap of the semiconductor substrate.

[0024] A hydrogen injection layer is formed by backside hydrogen injection, wherein a top surface of the hydrogen injection layer contacts a bottom surface of the drift region, and an equivalent N-type doping concentration of the hydrogen injection layer is greater than a doping concentration of the drift region.

[0025] A P-type heavily doped collector region, wherein a top surface of the collector region contacts a bottom surface of the hydrogen injection layer to form a back PN junction.

[0026] The top surface of the collector region is flush with or below the top surface of the second semiconductor material layer, so that the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower band gap width of the second semiconductor material layer is utilized to reduce the turn-on voltage of the back PN junction.

[0027] A further improvement is that the material of the semiconductor substrate includes Si.

[0028] A further improvement is that the material of the second semiconductor material layer includes Ge and GeSi.

[0029] A further improvement is that the second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate.

[0030] Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

[0031] A further improvement is that the second semiconductor material layer has undergone annealing treatment, and the hydrogen injection layer and the collector region have undergone backside laser annealing treatment.

[0032] The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

[0033] A further improvement is that the doping impurities in the collector region are P-type heavily doped back-implanted impurities or in-situ doping impurities in the second semiconductor material layer.

[0034] A bottom surface of the collector region is flush with a bottom surface of the second semiconductor material layer.

[0035] The junction depth of the collector region is less than 0.5 μm.

[0036] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

[0037] A further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench passes through the well region longitudinally, and the surface of the well region covered by the side of the gate structure serves as the channel region.

[0038] Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

[0039] To solve the above technical problems, the present invention provides a method for manufacturing a FS-IGBT device, comprising the following steps:

[0040] Step 1: Complete the front side process to form the front side process structure of the FS-IGBT device.

[0041] The front process structure of the FS-IGBT device includes:

[0042] The drift region consists of an N-type lightly doped region formed on the surface of the semiconductor substrate.

[0043] A P-type doped well region is formed on the surface of the drift region.

[0044] The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0045] An N-type heavily doped emitter region is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure.

[0046] Step 2: thinning the back side of the semiconductor substrate.

[0047] Step three: forming a second semiconductor material layer on the back side of the thinned semiconductor substrate; the band gap width of the second semiconductor material layer is lower than the band gap width of the semiconductor substrate.

[0048] Step 4: Perform backside hydrogen ion implantation to form a hydrogen implantation layer, wherein the top surface of the hydrogen implantation layer contacts the bottom surface of the drift region, and the equivalent N-type doping concentration of the hydrogen implantation layer is greater than the doping concentration of the drift region.

[0049] Step 5: forming a heavily P-type doped collector region, wherein the top surface of the collector region contacts the bottom surface of the hydrogen injection layer to form a back PN junction.

[0050] The top surface of the collector region is flush with or below the top surface of the second semiconductor material layer, so that the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower band gap width of the second semiconductor material layer is utilized to reduce the turn-on voltage of the back PN junction.

[0051] A further improvement is that the material of the semiconductor substrate includes Si.

[0052] A further improvement is that the material of the second semiconductor material layer includes Ge and GeSi.

[0053] A further improvement is that in step three, a deposition process is used to form the second semiconductor material layer on the back side of the thinned semiconductor substrate.

[0054] Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing back-side Ge injection, the Ge injected from the back-side Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

[0055] A further improvement is that the second semiconductor material layer has undergone annealing treatment, and the hydrogen injection layer and the collector region have undergone backside laser annealing treatment.

[0056] The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

[0057] A further improvement is that, when the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is performed after step three and before steps four and five.

[0058] The backside laser annealing is performed after steps four and five are completed.

[0059] The order of steps 4 and 5 can be interchanged.

[0060] A further improvement is that in step five, the collector region is formed by heavily P-type doped back ion implantation.

[0061] Alternatively, when the second semiconductor material layer is formed by a deposition process in step three, step five is omitted. In step three, the second semiconductor material layer is doped in situ, and the in-situ doped impurities of the second semiconductor material layer serve as doping impurities for the collector region.

[0062] A bottom surface of the collector region is flush with a bottom surface of the second semiconductor material layer.

[0063] The junction depth of the collector region is less than 0.5 μm.

[0064] The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

[0065] A further improvement is that the gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench passes through the well region longitudinally, and the surface of the well region covered by the side of the gate structure serves as the channel region.

[0066] Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

[0067] A further improvement is that in step 4, the implantation depth of the back side hydrogen ion implantation is within 20 microns.

[0068] Unlike the prior art, in which the collector region of the FS-IGBT device is directly formed by implantation on the back side of the thinned semiconductor substrate, the present invention adds a second semiconductor material layer with a lower bandgap width to the back side of the semiconductor substrate after the back side of the semiconductor substrate is thinned. The collector region is formed on the basis of the second semiconductor material layer, and the top surface of the collector region is lowered to be set below the top surface of the second semiconductor material layer. This can ensure that the interface of the back PN junction formed between the collector region and the hydrogen implanted layer on the top of the collector region is located within the second semiconductor material layer, and part or all of the built-in space charge region is located within the second semiconductor material layer. Therefore, the turn-on voltage of the back PN junction of the present invention is determined by the second semiconductor material layer, while the turn-on voltage of the back PN junction in the existing FS-IGBT device is determined by the material of the semiconductor substrate. Since the lower the bandgap width of the material constituting the PN junction, the lower the turn-on voltage of the PN junction, the present invention can reduce the bandgap width of the constituent materials of the back PN junction, thereby reducing the turn-on voltage of the back PN junction. In other words, the present invention utilizes the lower bandgap width of the second semiconductor material layer to reduce the turn-on voltage of the back PN junction. In summary, the present invention can improve the material of the collector region so that the collector region is located inside the second semiconductor material layer with a band gap width lower than that of the semiconductor substrate, thereby reducing the turn-on voltage of the back PN junction and further reducing the conduction voltage drop and conduction loss of the entire device.

[0069] In addition, the present invention uses a hydrogen injection layer formed by backside hydrogen injection to perform equivalent N-type doping, which can further improve the switching characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0071] Figure 1 It is a schematic diagram of the structure of the existing FS-IGBT device;

[0072] Figure 2 1 is a schematic structural diagram of an FS-IGBT device according to a first embodiment of the present invention;

[0073] Figure 3 1 is a schematic structural diagram of a FS-IGBT device according to a third embodiment of the present invention;

[0074] Figure 4 is a flow chart of a method for manufacturing an FS-IGBT device according to a first embodiment of the present invention;

[0075] Figure 5 FIG. 4 is a flow chart of a method for manufacturing an FS-IGBT device according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0076] The FS-IGBT device of the first embodiment of the present invention:

[0077] like Figure 2 FIG. 1 is a schematic structural diagram of an FS-IGBT device according to a first embodiment of the present invention. The FS-IGBT device according to the first embodiment of the present invention includes:

[0078] The drift region 203 is composed of an N-type lightly doped region formed on the surface of the semiconductor substrate.

[0079] A P-type doped well region 205 is formed on the surface of the drift region 203 .

[0080] The gate structure includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0081] An N-type heavily doped emitter region 207 is formed on the surface of the well region 205 and is self-aligned with the gate structure. The surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0082] In the first embodiment of the present invention, the gate structure is a trench gate. The gate dielectric layer 204 is formed on the inner surface of the gate trench, and the gate conductive material layer 206 fills the gate trench. The gate trench vertically passes through the well region 205, and the surface of the well region 205 covered by the side of the gate structure serves as the channel region. In some embodiments, the gate dielectric layer 204 is a gate oxide layer, and the gate conductive material 206 is a polysilicon gate.

[0083] A second semiconductor material layer 301 is formed on the back side of the semiconductor substrate, and the band gap width of the second semiconductor material layer 301 is lower than the band gap width of the semiconductor substrate. Figure 2 In the figure, the back side of the semiconductor substrate is separately marked with a mark 303, and the surface 303 is also the top surface of the second semiconductor material layer 301.

[0084] A hydrogen injection layer 202 is formed by backside hydrogen implantation. The top surface of the hydrogen injection layer 202 contacts the bottom surface of the drift region 203. The equivalent N-type doping concentration of the hydrogen injection layer 202 is greater than the doping concentration of the drift region 203. The hydrogen injection layer 202 is located within the region indicated by the curly brackets corresponding to the marker 202.

[0085] The collector region 201 is heavily doped with a P-type, and the top surface of the collector region 201 contacts the bottom surface of the hydrogen injection layer 202 to form a back-side PN junction. The collector region 201 is located in the area indicated by the brackets corresponding to the mark 201.

[0086] The top surface of the collector region 201 is flush with the top surface of the second semiconductor material layer 301 or is located below the top surface of the second semiconductor material layer 301, so that the interface of the back PN junction is located inside the second semiconductor material layer 301 or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer 301, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer 301 and the lower band gap width of the second semiconductor material layer 301 is used to reduce the turn-on voltage of the back PN junction. Figure 2 In the figure, the interface of the back PN junction is marked with a mark 302 , and it can be seen that the interface 302 is located below the surface 303 .

[0087] In the first embodiment of the present invention, the material of the semiconductor substrate includes Si.

[0088] In some embodiments, an epitaxial layer is further formed on the surface of the semiconductor substrate, and the drift region 203 is formed in the epitaxial layer; the semiconductor substrate is completely removed after back thinning, and the hydrogen injection layer 202 is formed in the back region of the epitaxial layer.

[0089] The material of the second semiconductor material layer 301 includes Ge. Since the band gap of Si is approximately 1.12 eV and the band gap of Ge is approximately 0.67 eV, the turn-on voltage of the back PN junction is reduced to approximately 0.3 V after the space charge region of the back PN junction is located within Ge, which is lower than the turn-on voltage of the PN junction in Si material of approximately 0.7 V. In other embodiments, the material of the second semiconductor material layer 301 can also be GeSi or other semiconductor materials with a band gap lower than the band gap of Si.

[0090] The second semiconductor material layer 301 is a deposited layer formed on the back side of the semiconductor substrate. In some embodiments, the deposition process of the second semiconductor material layer 301 includes molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma-enhanced chemical vapor deposition, low-temperature germanium buffer layer deposition, etc.

[0091] In the first embodiment of the present invention, the second semiconductor material layer 301 undergoes annealing, and the hydrogen-implanted layer 202 and the collector region 201 undergo backside laser annealing. The second semiconductor material layer 301 can repair Ge crystallization after annealing, and the hydrogen-implanted layer 202 and the collector region 201 can activate impurities after backside laser annealing.

[0092] In some embodiments, the annealing of the second semiconductor material layer 301 is performed using furnace annealing or backside laser annealing. The process conditions for the furnace annealing include an annealing temperature of 400°C to 500°C and an annealing time of 40 minutes. In other embodiments, the annealing of the second semiconductor material layer 301 can also be performed using only backside laser annealing, without furnace annealing. In this way, the crystallization repair of the second semiconductor material layer 301 and the impurity activation of the hydrogen injection layer 202 and the collector region 201 are both achieved through the same backside laser annealing.

[0093] In some embodiments, the doping impurities in the collector region 201 are P-type heavily doped back-implanted impurities. In other embodiments, the doping impurities in the collector region 201 may be in-situ doping impurities in the second semiconductor material layer 301 .

[0094] The bottom surface of the collector region 201 is flush with the bottom surface of the second semiconductor material layer 301 .

[0095] The first embodiment of the present invention further includes: a front metal layer 209 , wherein the front metal layer 209 is patterned to form a gate and an emitter. Figure 2 Only the emitter is shown in FIG. 2 , and the gate composed of the front metal layer 209 is not shown in FIG. Figure 2 The gate is connected to the gate conductive material layer 206 at the bottom, and the emitter is connected to the emitter region 207 at the bottom. A well contact region 208 is also formed on the surface of the well region 205. The well contact region 208 is heavily P-type doped, and the emitter is also connected to the well contact region 208. In some embodiments, the front metal layer 209 includes multiple layers, and each layer of the front metal layer 209 is isolated by an interlayer film and connected by vias passing through the interlayer film.

[0096] A collector electrode composed of a back metal layer 210 is formed on the back side of the collector region 201 .

[0097] In some embodiments, the thickness of the hydrogen injection layer 202 is within 20 microns. The junction depth of the collector region 201 is less than 0.5 μm. The thickness of the second semiconductor material layer 301 is greater than the junction depth of the collector region 201 and is 0.3 μm to 1 μm.

[0098] The collector region 201 is doped with boron at a concentration of 1E16 cm -3 ~1E18cm -3 between.

[0099] Unlike the prior art, in which the collector region 201 of the FS-IGBT device is directly formed by implantation on the back side of the thinned semiconductor substrate, in the first embodiment of the present invention, after the back side of the semiconductor substrate is thinned, a second semiconductor material layer 301 with a lower bandgap width is added to the back side of the semiconductor substrate, the collector region 201 is formed on the basis of the second semiconductor material layer 301, and the top surface of the collector region 201 is lowered to be set below the top surface of the second semiconductor material layer 301, so that the interface of the back PN junction formed between the collector region 201 and the hydrogen implantation layer 202 on the top of the collector region 201 is located inside the second semiconductor material layer 301 and the built-in space Since the inter-charge region is partially or entirely located within the second semiconductor material layer 301, the turn-on voltage of the back PN junction in the first embodiment of the present invention is determined by the second semiconductor material layer 301, whereas the turn-on voltage of the back PN junction in existing FS-IGBT devices is determined by the material of the semiconductor substrate. Since the lower the bandgap of the material constituting the PN junction, the lower the turn-on voltage of the PN junction, the first embodiment of the present invention can reduce the bandgap of the constituent materials of the back PN junction, thereby reducing the turn-on voltage of the back PN junction. In other words, the first embodiment of the present invention utilizes the lower bandgap of the second semiconductor material layer 301 to reduce the turn-on voltage of the back PN junction. In short, the first embodiment of the present invention improves the material of the collector region 201, positioning the collector region 201 within the second semiconductor material layer 301, which has a lower bandgap than the semiconductor substrate. This reduces the turn-on voltage of the back PN junction and, in turn, reduces the conduction voltage drop and conduction loss of the entire device.

[0100] In addition, the first embodiment of the present invention uses the hydrogen implantation layer 202 formed by backside hydrogen implantation to perform equivalent N-type doping, which can further improve the switching characteristics of the device.

[0101] The FS-IGBT device according to the second embodiment of the present invention:

[0102] The differences between the FS-IGBT device according to the second embodiment of the present invention and the FS-IGBT device according to the first embodiment of the present invention are as follows:

[0103] In the second embodiment of the FS-IGBT device of the present application, the material of the semiconductor substrate is Si, the material of the second semiconductor material layer 301 is GeSi, and the second semiconductor material layer 301 is a GeSi layer formed by backside Ge implantation into Si. The GeSi layer formed by backside Ge implantation can be well crystallized by combining with annealing treatment.

[0104] The third embodiment of the FS-IGBT device of the present application is as follows:

[0105] The difference between the third embodiment of the FS-IGBT device of the present application and the first embodiment of the FS-IGBT device of the present application is as follows:

[0106] In the third embodiment of the FS-IGBT device of the present application, as shown in Figure 3 , the gate structure is a planar gate, the gate dielectric layer 204a covers the top surface of the well region 205 and extends to the top surface of the drift region 203 adjacent to the well region 205, and the gate conductive material layer 206a is superimposed on the top surface of the gate dielectric layer 204, and the surface of the well region 205 covered by the gate structure from the top side of the well region 205 serves as the channel region. Figure 3 In the third embodiment of the FS-IGBT device of the present application, the gate dielectric layer is separately denoted by the mark 204a, and the gate conductive material layer is separately denoted by the mark 206a, and the surface of the other structure is unchanged.

[0107] The manufacturing method of the first embodiment of the FS-IGBT device of the present application is as follows:

[0108] As shown in Figure 4 , it is the manufacturing method of the first embodiment of the FS-IGBT device of the present application, and the manufacturing method of the first embodiment of the FS-IGBT device of the present application can manufacture Figure 2 the first embodiment of the FS-IGBT device of the present application and Figure 3 the third embodiment of the FS-IGBT device of the present application shown in Figure 2 , and also the second embodiment of the FS-IGBT device of the present application can be obtained, and the manufacturing method of the first embodiment of the FS-IGBT device of the present application will be described below by taking the structure shown in as an example, which includes the following steps:

[0109] Figure 4 Step one, complete the front process to form the front process structure of the FS-IGBT device. Step one corresponds to step S101 in , and the front process is completed.

[0110] The front process structure of the FS-IGBT device includes:

[0111] The drift region 203 is composed of an N-type lightly doped region formed on the surface of the semiconductor substrate.

[0112] A P-type doped well region 205 is formed on the surface of the drift region 203 .

[0113] The gate structure includes a gate dielectric layer 204 and a gate conductive material layer 206 stacked in sequence.

[0114] An N-type heavily doped emitter region 207 is formed on the surface of the well region 205 and is self-aligned with the gate structure. The surface of the well region 205 between the emitter region 207 and the drift region 203 serves as a channel region and is covered by the gate structure.

[0115] In the method according to the first embodiment of the present invention, the material of the semiconductor substrate includes Si.

[0116] In some embodiments, an epitaxial layer is formed on the surface of the semiconductor substrate, and the drift region 203 is formed in the epitaxial layer. The semiconductor substrate is completely removed in a subsequent backside thinning process, and a subsequent hydrogen implantation layer 202 is formed in the backside region of the epitaxial layer.

[0117] The gate structure is a trench gate, the gate dielectric layer 204 is formed on the inner surface of the gate trench, the gate conductive material layer 206 is filled in the gate trench, the gate trench vertically passes through the well region 205, and the surface of the well region 205 covered by the side of the gate structure serves as the channel region.

[0118] When used to manufacture Figure 3 In the FS-IGBT device of the third embodiment of the present invention shown, the gate structure is a planar gate, the gate dielectric layer 204 covers the top surface of the well region 205 and extends to the top surface of the drift region 203 adjacent to the well region 205, the gate conductive material layer 206 is superimposed on the top surface of the gate dielectric layer 204, and the surface of the well region 205 covered by the gate structure from the top side of the well region 205 serves as the channel region.

[0119] In the method of the first embodiment of the present invention, the front process structure of the FS-IGBT device further includes: a front metal layer 209 , and the front metal layer 209 is patterned to form a gate and an emitter. Figure 2 Only the emitter is shown in FIG. 2 , and the gate composed of the front metal layer 209 is not shown in FIG. Figure 2The gate is connected to the gate conductive material layer 206 at the bottom, and the emitter is connected to the emitter region 207 at the bottom. A well contact region 208 is also formed on the surface of the well region 205. The well contact region 208 is heavily P-type doped, and the emitter is also connected to the well contact region 208. In some embodiments, the front metal layer 209 includes multiple layers, and each layer of the front metal layer 209 is isolated by an interlayer film and connected by vias passing through the interlayer film.

[0120] Step 2: Thinning the back side of the semiconductor substrate. Step 2 corresponds to Figure 4 Step S102, back side thinning.

[0121] Step 3: forming a second semiconductor material layer 301 on the back side of the thinned semiconductor substrate; the band gap width of the second semiconductor material layer 301 is lower than the band gap width of the semiconductor substrate.

[0122] In the method of the first embodiment of the present invention, the material of the second semiconductor material layer 301 is Ge, and the Ge layer is formed by a deposition process. Step 3 corresponds to Figure 4 Step S103, Ge layer deposition.

[0123] In other embodiments, the second semiconductor material layer 301 may also be made of GeSi or other semiconductor materials with a bandgap lower than that of Si.

[0124] In some embodiment methods, the deposition process of the second semiconductor material layer 301 includes: molecular beam epitaxy, organic chemical vapor deposition, pulsed laser deposition, magnetron sputtering, plasma enhanced chemical vapor deposition, low temperature germanium buffer layer deposition, etc.

[0125] In other embodiments, the semiconductor substrate may be made of Si and the second semiconductor material layer 301 may be made of GeSi. The process for forming the second semiconductor material layer 301 includes performing backside Ge implantation, where the Ge implanted from the backside Ge and the Si in the semiconductor substrate form a GeSi layer, thereby forming the second semiconductor material layer 301. The device formed in this case corresponds to the FS-IGBT device of the second embodiment of the present invention.

[0126] In the method of the first embodiment of the present invention, after step three is completed, the method further includes:

[0127] The second semiconductor material layer 301 is subjected to furnace annealing to repair the crystallization of the Ge layer. This step corresponds to Figure 4The process conditions of the furnace tube annealing include: annealing temperature of 400° C. to 500° C., and annealing time of 40 minutes.

[0128] Step 4: Perform backside hydrogen ion implantation to form a hydrogen implantation layer 202 , wherein the top surface of the hydrogen implantation layer 202 contacts the bottom surface of the drift region 203 , and the equivalent N-type doping concentration of the hydrogen implantation layer 202 is greater than the doping concentration of the drift region 203 .

[0129] In some embodiment methods, the back side hydrogen ion implantation has an implantation depth of less than 20 microns.

[0130] Step 4 corresponds to Figure 4 Step S105, hydrogen injection.

[0131] Step 5: forming a heavily P-type doped collector region 201 , wherein the top surface of the collector region 201 contacts the bottom surface of the hydrogen injection layer 202 to form a back PN junction.

[0132] In the method of the first embodiment of the present invention, the collector region 201 is formed by back ion implantation with heavy P-type doping. The P-type is P-type, and the P-type heavy doping is P-type heavy doping; Step 5 corresponds to Figure 4 In step S106, back-side Pplus injection, Pplus represents P-type heavy doping injection, i.e., P-type heavy doping injection.

[0133] In other embodiments, the method can also be as follows: when the second semiconductor material layer 301 is formed by a deposition process in step 3, step 5 is omitted. In step 3, the second semiconductor material layer 301 is doped in situ, and the impurities doped in situ in the second semiconductor material layer 301 serve as the doping impurities of the collector region 201. Figure 4 There is a description in the brackets of step S106, which is: if the Ge layer is in-situ doped, skip this process.

[0134] In the method of the first embodiment of the present invention, the bottom surface of the collector region 201 is flush with the bottom surface of the second semiconductor material layer 301;

[0135] In some embodiment methods, the junction depth of the collector region 201 is less than 0.5 μm;

[0136] The thickness of the second semiconductor material layer 301 is greater than the junction depth of the collector region 201 and the thickness of the second semiconductor material layer 301 is 0.3 μm to 1 μm.

[0137] After step 5, it also includes:

[0138] Perform back laser annealing to activate the impurities in the hydrogen injection layer 202 and the collector region 201. Figure 4 Step S107, laser annealing.

[0139] The top surface of the collector region 201 is flush with the top surface of the second semiconductor material layer 301 or is located below the top surface of the second semiconductor material layer 301, so that the interface of the back PN junction is located inside the second semiconductor material layer 301 or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer 301, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer 301 and the lower band gap width of the second semiconductor material layer 301 is used to reduce the turn-on voltage of the back PN junction.

[0140] The follow-up also includes:

[0141] A collector electrode composed of a back metal layer 210 is formed on the back of the collector region 201. The back metal layer 210 is usually formed by a metal sputtering process. Figure 4 Step S108, metal sputtering.

[0142] In the method of the first embodiment of the present invention, the order of the above-mentioned step 4 and step 5 can be interchanged.

[0143] A method for manufacturing a FS-IGBT device according to a second embodiment of the present invention:

[0144] like Figure 5 FIG. 1 shows a method for manufacturing a FS-IGBT device according to a second embodiment of the present invention. The differences between the method for manufacturing a FS-IGBT device according to the second embodiment of the present invention and the method for manufacturing a FS-IGBT device according to the first embodiment of the present invention are as follows:

[0145] In the manufacturing method of the FS-IGBT device according to the second embodiment of the present invention, the annealing of the second semiconductor material layer 301 does not include the furnace annealing. Figure 5 Omitted Figure 4 In this way, the annealing for crystallization repair of the second semiconductor material layer 301 directly adopts the backside laser annealing for activating the hydrogen injection layer 202 and the collector region 201 .

[0146] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A FS-IGBT device, characterized in that: include: The drift region consists of an N-type lightly doped region formed on the surface of the semiconductor substrate; A P-type doped well region is formed on the surface of the drift region; A gate structure comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An N-type heavily doped emitter region is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure; a second semiconductor material layer formed on the back side of the semiconductor substrate, wherein the band gap of the second semiconductor material layer is lower than the band gap of the semiconductor substrate; a hydrogen injection layer formed by backside hydrogen injection, wherein a top surface of the hydrogen injection layer contacts a bottom surface of the drift region, and an equivalent N-type doping concentration of the hydrogen injection layer is greater than a doping concentration of the drift region; A P-type heavily doped collector region, wherein a top surface of the collector region contacts a bottom surface of the hydrogen injection layer and forms a back PN junction; The top surface of the collector region is located below the top surface of the second semiconductor material layer, so that the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower band gap width of the second semiconductor material layer is utilized to reduce the turn-on voltage of the back PN junction; The doping impurities in the collector region are P-type heavily doped back-implanted impurities or in-situ doping impurities in the second semiconductor material layer; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is less than 0.5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

2. The FS-IGBT device according to claim 1, wherein: The material of the semiconductor substrate includes Si.

3. The FS-IGBT device according to claim 2, wherein: The material of the second semiconductor material layer includes Ge and GeSi.

4. The FS-IGBT device according to claim 3, wherein: The second semiconductor material layer is a deposition layer formed on the back side of the semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the second semiconductor material layer is a GeSi layer formed by backside Ge implantation into Si.

5. The FS-IGBT device according to claim 4, wherein: The second semiconductor material layer has been subjected to annealing treatment, and the hydrogen injection layer and the collector region have been subjected to backside laser annealing treatment; The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

6. The FS-IGBT device according to claim 1, wherein: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

7. A method for manufacturing a FS-IGBT device, characterized in that: The steps include: Step 1: Complete the front side process to form the front side process structure of the FS-IGBT device; The front process structure of the FS-IGBT device includes: The drift region consists of an N-type lightly doped region formed on the surface of the semiconductor substrate; A P-type doped well region is formed on the surface of the drift region; A gate structure comprising a gate dielectric layer and a gate conductive material layer stacked in sequence; An N-type heavily doped emitter region is formed on the surface of the well region and is self-aligned with the gate structure; the surface of the well region located between the emitter region and the drift region serves as a channel region and is covered by the gate structure; Step 2: thinning the back side of the semiconductor substrate; Step 3: forming a second semiconductor material layer on the back side of the thinned semiconductor substrate; the band gap width of the second semiconductor material layer is lower than the band gap width of the semiconductor substrate; Step 4: Performing backside hydrogen ion implantation to form a hydrogen implantation layer, wherein the top surface of the hydrogen implantation layer contacts the bottom surface of the drift region, and the equivalent N-type doping concentration of the hydrogen implantation layer is greater than the doping concentration of the drift region; Step 5: forming a heavily P-type doped collector region, wherein the top surface of the collector region contacts the bottom surface of the hydrogen injection layer to form a back PN junction; The top surface of the collector region is located below the top surface of the second semiconductor material layer, so that the interface of the back PN junction is located inside the second semiconductor material layer or part or all of the built-in space charge region of the back PN junction is located inside the second semiconductor material layer, so that the turn-on voltage of the back PN junction is determined by the second semiconductor material layer and the lower band gap width of the second semiconductor material layer is utilized to reduce the turn-on voltage of the back PN junction; In step 5, the collector region is formed by heavily P-type doped back ion implantation; Alternatively, when the second semiconductor material layer is formed by a deposition process in step 3, step 5 is omitted, and in step 3, the second semiconductor material layer is in-situ doped with impurities, and the in-situ doped impurities of the second semiconductor material layer serve as doping impurities for the collector region; The bottom surface of the collector region is flush with the bottom surface of the second semiconductor material layer; The junction depth of the collector region is less than 0.5 μm; The thickness of the second semiconductor material layer is greater than the junction depth of the collector region and the thickness of the second semiconductor material layer is 0.3 μm to 1 μm.

8. The method for manufacturing a FS-IGBT device according to claim 7, wherein: The material of the semiconductor substrate includes Si.

9. The method for manufacturing a FS-IGBT device according to claim 8, wherein: The material of the second semiconductor material layer includes Ge and GeSi.

10. The method for manufacturing a FS-IGBT device according to claim 9, wherein: In step three, a deposition process is used to form the second semiconductor material layer on the back side of the thinned semiconductor substrate; Alternatively, when the material of the semiconductor substrate is Si and the material of the second semiconductor material layer is GeSi, the process of forming the second semiconductor material layer in step three includes: performing back-side Ge injection, the Ge injected from the back-side Ge and the Si in the semiconductor substrate form a GeSi layer to form the second semiconductor material layer.

11. The method for manufacturing a FS-IGBT device according to claim 10, wherein: The second semiconductor material layer has been subjected to annealing treatment, and the hydrogen injection layer and the collector region have been subjected to backside laser annealing treatment; The second semiconductor material layer is annealed by furnace annealing or backside laser annealing.

12. The method for manufacturing a FS-IGBT device according to claim 11, wherein: When the annealing of the second semiconductor material layer includes the furnace tube annealing, the furnace tube annealing of the second semiconductor material layer is performed after step 3 and before step 4 and step 5; The backside laser annealing is performed after step 4 and step 5 are completed; The order of steps 4 and 5 can be interchanged.

13. The method for manufacturing a FS-IGBT device according to claim 7, wherein: The gate structure is a trench gate, the gate dielectric layer is formed on the inner surface of the gate trench, the gate conductive material layer is filled in the gate trench, the gate trench vertically passes through the well region, and the surface of the well region covered by the side of the gate structure serves as the channel region; Alternatively, the gate structure is a planar gate, the gate dielectric layer covers the top surface of the well region and extends to the top surface of the drift region adjacent to the well region, the gate conductive material layer is superimposed on the top surface of the gate dielectric layer, and the surface of the well region covered by the gate structure from the top side of the well region serves as the channel region.

14. The method for manufacturing a FS-IGBT device according to claim 7, wherein: In step 4, the back side hydrogen ion implantation has an implantation depth of less than 20 microns.

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