Power supply control circuit and control method based on BMS
By introducing a signal latch module into the BMS power supply control circuit, the normal operation problem of traditional BMS power supply system in the wake-up source is solved, ensuring that the power supply module still cannot work normally when it cannot work normally It can maintain a wake-up state to ensure continuous power supply of the BMS.
Patent Information
- Application Number
- CN202411378877.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2024-12-31
AI Technical Summary
The working state of the DCDC power supply of the traditional BMS battery management system is easily affected by the wake-up source, and cannot work normally or the wake-up circuit is short-circuited, which will affect the normal operation of the power supply system.
A BMS-based power control circuit is designed, including a power module, a signal transmission module and a signal latch module. The high-level signals sent by the wake-up source are latched through the signal latch module to ensure that the power module cannot be normal in the wake-up source. It can still be awakened while working.
It effectively solves the impact of the normal operation of the power system under abnormal wake-up source, ensures that the power module remains awake under the continuous signal of the signal latch module, and ensures that the BMS is continuously powered.
Smart Images
Figure CN119231886A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of BMS control circuits, and in particular to a power supply control circuit and a control method based on a BMS. Background Art
[0002] In the BMS (BATTERY MANAGEMENT SYSTEM) battery management system, the working state of the traditional DCDC power supply is easily affected by the wake-up source. The power system needs to keep awake by continuously sending high-level signals from the wake-up source. However, when the wake-up source fails to work properly or the wake-up circuit is short-circuited, etc., it will directly affect the normal operation of the power system. Summary of the invention
[0003] In order to overcome the above shortcomings, the purpose of the present application is to provide a power supply control circuit and control method based on BMS, so as to effectively solve the above problems.
[0004] In order to achieve the above objectives, this application adopts the following technical solutions:
[0005] In a first aspect, the present application provides a power control circuit based on a BMS, comprising:
[0006] Power module, used to power the BMS.
[0007] a first signal sending module, the first signal sending module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS, and the power module receives the low level signal and enters a sleep state to stop supplying power to the BMS,
[0008] a signal latch module, the signal latch module is electrically connected to the first signal sending module, and the signal latch module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the signal latch module, the signal latch module latches the received signal and sends the latched signal to the power module,
[0009] The second signal sending module is electrically connected to the signal latch module, and the second signal sending module sends a control signal to the signal latch module to enable the signal latch module to switch the latched signal.
[0010] Furthermore, the power module includes a first chip, the first chip includes a first input pin, a first control pin and a first output pin, the first input pin is electrically connected to the constant voltage source, the first output pin is electrically connected to the output port to supply power to the BMS, and the first control pin is electrically connected to the first signal sending module to receive high level signals and low level signals.
[0011] Furthermore, the first signal sending module includes a first signal sending source, which is electrically connected to the first control pin of the first chip and a first resistor is arranged in the circuit connecting the two. The first signal sending source can send a high level signal or a low level signal to the first control pin of the first chip.
[0012] Furthermore, the signal latch module includes a second chip, the second chip includes a second input pin, a second output pin and a second control pin, the second input pin is electrically connected to the first signal sending source and a second resistor is arranged in the circuit connecting the two, the second output pin of the second chip is electrically connected to the first control pin of the first chip and a third resistor is arranged in the circuit connecting the two, and the second control pin of the second chip is electrically connected to the second signal sending module.
[0013] Furthermore, the second signal sending module includes a second signal sending source, the second signal sending source is electrically connected to the second control pin of the second chip, and a fourth resistor is provided in the circuit connecting the two.
[0014] Furthermore, a diode is provided on the circuit connecting the first signal transmission source and the first control pin of the first chip, and the diode is used to block the current from flowing back to the first signal transmission source.
[0015] Furthermore, it also includes a first voltage pull-down circuit and a second voltage pull-down circuit, the first voltage pull-down circuit is electrically connected to the second input pin of the second chip, and the second voltage pull-down circuit is electrically connected to the second control pin of the second chip.
[0016] Furthermore, a fifth resistor is provided on the first voltage pull-down circuit, one end of the first voltage pull-down circuit is electrically connected to the second input pin of the second chip, and the other end is grounded.
[0017] Furthermore, a sixth resistor is provided on the second voltage pull-down circuit, one end of the second voltage pull-down circuit is electrically connected to the second control pin of the second chip, and the other end is grounded.
[0018] The present application provides a power control method based on a BMS, the control method comprising a wake-up and hold phase and a sleep phase, wherein:
[0019] The wake-up and hold phase comprises the following steps:
[0020] Based on the first signal sending module sending a high level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS.
[0021] Based on the first signal sending module, a high-level signal is sent to the signal latch module, and based on the second signal sending module, a control signal is sent to make the signal latch module latch the high-level signal. The signal latch module continuously sends a high-level signal to the power module, so that the power module is in a wake-up hold state by receiving the high-level signal sent by the signal latch module when the first signal sending module does not send a high-level signal;
[0022] The dormant stage includes the following steps:
[0023] Based on the first signal sending module, a low level signal is sent to the power supply module, and at the same time, based on the first signal sending module, a low level signal is sent to the signal latch module.
[0024] Based on the control signal sent by the second signal sending module, the signal latch module converts the latched high level signal into a low level signal, so that the power supply module simultaneously receives the low level signals sent by the first signal sending module and the signal latch module to enter the sleep state.
[0025] Beneficial Effects
[0026] The present application provides a power control circuit and control method based on BMS, in which a signal latch module is set to latch the high-level signal sent by the wake-up source, so that the signal latch module can continuously send signals to the power module. When the wake-up source fails to work normally, the signal latch module sends the latched signal to the power module to keep it in the awake state and continue to work. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the content of the present application.
[0028] Figure 1 This is a block diagram of the power control circuit system of the BMS of this application.
[0029] Figure 2 Schematic diagram of the power control circuit structure of a BMS in one embodiment of the present application. DETAILED DESCRIPTION
[0030] The above scheme is further described below in conjunction with specific examples. It should be understood that these examples are used to illustrate the present application and are not limited to the scope of the present application. The implementation conditions adopted in the examples can be further adjusted as the conditions of the specific manufacturer, and the unspecified implementation conditions are usually the conditions in conventional experiments.
[0031] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. In this article, "electrical connection" includes the situation where the constituent elements are connected together through an element with some electrical function. "Elements with some electrical function" are not particularly limited as long as they can transfer electrical signals between the connected constituent elements. "Elements with some electrical function" can be, for example, electrodes or wiring, or switching elements such as transistors, or other functional elements such as resistors, inductors or capacitors. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.
[0032] In this application, the directions or positional relationships indicated by the terms "upper", "lower", "inner", "middle", etc. are based on the directions or positional relationships shown in the drawings. These terms are mainly used to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction.
[0033] As described in the background technology, in the battery management system, the working state of the traditional DCDC power supply is easily affected by the wake-up source. The power system needs to maintain the wake-up state by the wake-up source continuously sending a high-level signal. However, when the wake-up source cannot work normally, the wake-up circuit is short-circuited, and other abnormal situations occur, it will directly affect the normal operation of the power system.
[0034] In view of the above content, the inventor provides a power control circuit based on BMS, such as Figure 1As shown, the power control circuit of the BMS includes a power module for supplying power to the BMS, a first signal sending module, the first signal sending module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS, and the power module receives the low level signal and enters a sleep state to stop supplying power to the BMS, a signal latch module, the signal latch module is electrically connected to the first signal sending module, and the signal latch module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the signal latch module, the signal latch module latches the received signal and sends the latched signal to the power module, and a second signal sending module, the second signal sending module is electrically connected to the signal latch module, and the second signal sending module sends a control signal to the signal latch module so that the signal latch module switches the latched signal.
[0035] At the same time, the inventor also provides a power control method based on BMS, which includes a wake-up and hold phase and a sleep phase, wherein:
[0036] The wake-up hold phase includes the following steps:
[0037] Based on the first signal sending module sending a high level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS.
[0038] Based on the first signal sending module, a high-level signal is sent to the signal latch module, and based on the second signal sending module, a control signal is sent to make the signal latch module latch the high-level signal. The signal latch module continuously sends a high-level signal to the power module, so that the power module is in a wake-up hold state by receiving the high-level signal sent by the signal latch module when the first signal sending module does not send a high-level signal;
[0039] The dormant phase includes the following steps:
[0040] Based on the first signal sending module, a low level signal is sent to the power supply module, and at the same time, based on the first signal sending module, a low level signal is sent to the signal latch module.
[0041] Based on the control signal sent by the second signal sending module, the signal latch module converts the latched high level signal into a low level signal, so that the power supply module simultaneously receives the low level signals sent by the first signal sending module and the signal latch module to enter the sleep state.
[0042] The present application sets a signal latch module to latch the high-level signal sent by the wake-up source, so that the signal latch module can continuously send signals to the power module. When the wake-up source fails to work normally, the signal latch module sends the latched signal to the power module to keep it in the awake state and continue to work.
[0043] Next, combine Figure 2 The present application is described exemplarily.
[0044] An embodiment of the present application provides a power control circuit based on a BMS, the circuit comprising:
[0045] A power supply module, the power supply module includes a first chip U1, the first chip includes a DCDC power supply chip, the first chip U1 includes a first input pin IN, the first input pin IN is electrically connected to the constant voltage source LV-12V, and also includes a first output pin OUT, the first output pin OUT outputs the constant voltage source LV-12V for power supply, and also includes a first control pin EN, the first control pin EN is electrically connected to the wake-up source EXT-KL15, and the first signal sending source EXT-KL15 sends a high level signal or a low level signal to the first control pin EN.
[0046] A first resistor R1 is provided on the circuit connecting the first signal sending source EXT-KL15 (wake-up source) and the first control pin EN of the first chip U1. The first resistor R1 is a wake-up source current limiting resistor.
[0047] A signal latch module includes a second chip U2, which is a D-type trigger chip. The second chip U2 includes a second input pin D, which is electrically connected to the wake-up source EXT-KL15, and a second resistor R2 is provided on the connected circuit, and the second resistor R2 is a wake-up source current limiting resistor. The second output pin Q is electrically connected to the pin EN of the first chip U1, and a third resistor R3 is provided on the connected circuit, and the third resistor R3 is a current limiting resistor. The second control pin CP is electrically connected to the second signal sending source MCU-IO, and in The connected circuit is provided with a fourth resistor R4, which is a current limiting resistor of the MCU-IO interface. The working principle of the D-type trigger chip is as follows: when the pin CP is converted from a low level to a high level, the Q pin state follows the D pin, that is, when the D pin receives a high level signal, the Q pin sends a high level signal, and when the D pin receives a low level signal, the Q pin sends a low level signal. If the Q pin state needs to be updated, the D pin needs to be operated, and the CP pin is converted from low to high again to lock the state of the Q pin. Otherwise, even if D is converted from high to low, the Q pin does not follow the D pin state at this time, and the CP pin needs to be re-operated to update and lock the Q pin.
[0048] Table 1 below is the control truth table of the D-type trigger chip, in which: "↑" indicates a transition from a low level to a high level.
[0049] Pin CP Pin D Pin Q indivual High level High level indivual Low level Low level
[0050] Table 1
[0051] In some embodiments, a diode D1 is provided on the circuit connecting the first signal transmission source EXT-KL15 and the pin EN of the first chip U1 , and the diode D1 can block the current from flowing back to the first signal transmission source EXT-KL15 .
[0052] In some embodiments, the circuit also includes a first voltage pull-down circuit and a second voltage pull-down circuit, a fifth resistor R5 is arranged on the first voltage pull-down circuit, one end of the first voltage pull-down circuit is electrically connected to the second input pin D of the second chip, and the other end is grounded GND, a sixth resistor R6 is arranged on the second voltage pull-down circuit, one end of the second voltage pull-down circuit is electrically connected to the second control pin CP of the second chip, and the other end is grounded GND, when EXT-KL15 is disconnected and the MCU-IO port is in a high-impedance state, the D pin defaults to a low level.
[0053] Another embodiment of the present application provides a power control method based on a BMS, the control method comprising a wake-up and hold phase and a sleep phase, wherein:
[0054] The wake-up hold phase includes the following steps:
[0055] The wake-up source EXT-KL15 sends a high-level signal to the pin EN of the first chip U1, and the first chip U1 controls the pin OUT to output the constant voltage source LV-12V for power supply. The first chip U1 is in the wake-up stage.
[0056] The wake-up source EXT-KL15 sends a high-level signal to the pin D of the second chip U2, and the second signal sending source MCU-IO sends a signal that changes from a low-level signal to a high-level signal. At this time, the second chip U2 latches the high-level signal, that is, the pin Q follows the pin D, and the pin Q of the second chip U2 outputs a high-level signal to the pin EN of the first chip U1. At this time, even if the wake-up source EXT-KL15 does not send a high-level signal, the pin Q of the second chip U2 can continue to send a high-level signal to the pin EN of the first chip U1, so that the first chip U1 is in a wake-up hold state;
[0057] In the sleep stage, the wake-up source EXT-KL15 sends a low-level signal to the pin EN of the first chip U1, and at the same time, the wake-up source EXT-KL15 sends a low-level signal to the pin D of the second chip U2. The second signal sending source MCU-IO sends a signal that changes from a low-level signal to a high-level signal. At this time, the second chip U2 switches the latch signal, and pin Q follows pin D. Pin Q outputs a low-level signal to the pin EN of the first chip U1, and the first chip U1 is in sleep state.
[0058] The above embodiments are only for illustrating the technical concept and features of the present application, and their purpose is to enable people familiar with the technology to understand the content of the present application and implement it accordingly, and they cannot be used to limit the protection scope of the present application. Any equivalent transformation or modification made according to the spirit of the present application shall be included in the protection scope of the present application.
Claims
1. A power control circuit based on BMS, characterized in that: include: Power module, used to power the BMS. a first signal sending module, the first signal sending module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS, and the power module receives the low level signal and enters a sleep state to stop supplying power to the BMS, a signal latch module, the signal latch module is electrically connected to the first signal sending module, and the signal latch module is electrically connected to the power module, the first signal sending module sends a high level signal or a low level signal to the signal latch module, the signal latch module latches the received signal and sends the latched signal to the power module, The second signal sending module is electrically connected to the signal latch module, and the second signal sending module sends a control signal to the signal latch module to enable the signal latch module to switch the latched signal.
2. The BMS-based power control circuit according to claim 1, characterized in that: The power module includes a first chip, which includes a first input pin, a first control pin and a first output pin, the first input pin is electrically connected to a constant voltage source, the first output pin is electrically connected to an output port to supply power to the BMS, and the first control pin is electrically connected to the first signal sending module to receive a high level signal and a low level signal.
3. The BMS-based power control circuit according to claim 2, characterized in that: The first signal sending module includes a first signal sending source, which is electrically connected to the first control pin of the first chip and a first resistor is arranged on the circuit connecting the two. The first signal sending source can send a high level signal or a low level signal to the first control pin of the first chip.
4. The BMS-based power control circuit according to claim 3, characterized in that: The signal latch module includes a second chip, the second chip includes a second input pin, a second output pin and a second control pin, the second input pin is electrically connected to the first signal sending source and a second resistor is arranged on the circuit connecting the two, the second output pin of the second chip is electrically connected to the first control pin of the first chip and a third resistor is arranged on the circuit connecting the two, and the second control pin of the second chip is electrically connected to the second signal sending module.
5. The BMS-based power control circuit according to claim 4, characterized in that: The second signal sending module includes a second signal sending source, the second signal sending source is electrically connected to the second control pin of the second chip, and a fourth resistor is arranged on the circuit connecting the two.
6. The BMS-based power control circuit according to claim 4, characterized in that: A diode is provided on the circuit connecting the first signal transmission source and the first control pin of the first chip, and the diode is used to block the current from flowing back to the first signal transmission source.
7. The BMS-based power control circuit according to claim 4, characterized in that: It also includes a first voltage pull-down circuit and a second voltage pull-down circuit, the first voltage pull-down circuit is electrically connected to the second input pin of the second chip, and the second voltage pull-down circuit is electrically connected to the second control pin of the second chip.
8. The BMS-based power control circuit according to claim 7, characterized in that: The first voltage pull-down circuit is provided with a fifth resistor. One end of the first voltage pull-down circuit is electrically connected to the second input pin of the second chip, and the other end of the first voltage pull-down circuit is grounded.
9. The BMS-based power control circuit according to claim 7, characterized in that: The second voltage pull-down circuit is provided with a sixth resistor. One end of the second voltage pull-down circuit is electrically connected to the second control pin of the second chip, and the other end of the second voltage pull-down circuit is grounded.
10. A power control method based on BMS, characterized in that: The control method includes a wake-up hold phase and a sleep phase, wherein: The wake-up and hold phase comprises the following steps: Based on the first signal sending module sending a high level signal to the power module, the power module receives the high level signal and enters a wake-up state to supply power to the BMS. Based on the first signal sending module, a high-level signal is sent to the signal latch module, and based on the second signal sending module, a control signal is sent to make the signal latch module latch the high-level signal. The signal latch module continuously sends a high-level signal to the power module, so that the power module is in a wake-up hold state by receiving the high-level signal sent by the signal latch module when the first signal sending module does not send a high-level signal; The dormant stage includes the following steps: Based on the first signal sending module, a low level signal is sent to the power supply module, and at the same time, based on the first signal sending module, a low level signal is sent to the signal latch module. Based on the control signal sent by the second signal sending module, the signal latch module converts the latched high level signal into a low level signal, so that the power supply module simultaneously receives the low level signals sent by the first signal sending module and the signal latch module to enter the sleep state.