Analyzing and testing system and method for analog and mixed signal integrated circuit

Abstract

The invention provides an analysis test system and method for an analog and mixed signal integrated circuit, and particularly relates to the technical field of integrated circuit testing, and the system integrates data acquisition, jitter and noise separation, spectrum leakage elimination, clipping distortion suppression and FPGA test substrate modules. The data acquisition module is responsible for collecting original test data of a circuit to be tested, mainly focuses on output signals of an A / D converter and a D / A converter, and processes the output signals through a jitter and noise separation technology, a spectrum leakage elimination technology and a clipping distortion suppression technology so as to improve data quality. The FPGA test substrate module is based on a general configurable test platform, carries out the deep analysis of the processed data, finally obtains the performance test result of the simulation and mixed signal integrated circuit to be tested, and guarantees the high efficiency and accuracy of the test. The system breaks through the jitter and noise separation technology, the spectrum leakage elimination technology and the clipping distortion suppression technology, and further improves the precision and efficiency of the analysis test of the analog and mixed signal integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to an analysis and testing system and method for analog and mixed signal integrated circuits. Background Art

[0002] With the rapid development of modern electronic information systems and equipment, especially the continuous progress in 5G mobile communications, cognitive radar, multi-carrier wireless communications and other fields, unprecedented challenges have been posed to the performance and power consumption of high-precision analog and mixed-signal integrated circuits. As the core components of these systems, low-power, high-speed, and high-precision data converters are becoming increasingly important. However, the main problem facing the industry today is how to meet the growing performance requirements, especially in terms of data conversion speed, accuracy, and power consumption. For example, 5G mobile communication systems, electronic countermeasure systems, Ethernet systems, and cognitive radars all require high-precision, ultra-high-speed data converters, but the existing technical level and production capacity are difficult to meet these high-end requirements, resulting in limited industrial development.

[0003] Traditional data converter testing methods mainly rely on instrument-based testing solutions. This method performs well when testing low-speed, low-precision data converters and is simple and easy to use. However, when faced with high-speed, high-precision data converters, traditional methods are unable to cope with it. In order to test A / D converters, traditional methods require a high-precision D / A converter with higher accuracy than the A / D converter to be tested as the core component of the data acquisition card. This approach not only increases the test cost, but also reduces the reliability of the test due to the performance limitations of the D / A converter itself. In addition, when the accuracy of the A / D converter to be tested exceeds the D / A converter embedded in the test platform, the entire test system will not be able to perform the test task, and it is necessary to replace the test instrument with a higher accuracy or build a new test platform. This discrete and inflexible test method also limits the test efficiency and accuracy.

[0004] In summary, how to break through the jitter and noise separation technology, spectrum leakage elimination technology and clipping distortion suppression technology, and then improve the accuracy and efficiency of analysis and testing of analog and mixed-signal integrated circuits is an urgent problem to be solved. Summary of the invention

[0005] The main purpose of the present invention is to provide an analysis and testing system and method for analog and mixed-signal integrated circuits, so as to at least solve the technical problem of low accuracy and efficiency of analysis and testing of analog and mixed-signal integrated circuits due to the inability to break through jitter and noise separation technology, spectrum leakage elimination technology and clipping distortion suppression technology.

[0006] In order to achieve the above-mentioned object, the present invention provides an analysis and testing system and method for analog and mixed signal integrated circuits.

[0007] In a first aspect, the present invention provides an analysis and testing system for analog and mixed signal integrated circuits, the system comprising: A data acquisition module, which is deployed in the analysis and testing system and is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, wherein the original test data is used to indicate output signals of the A / D converter and the D / A converter; A jitter and noise separation module, connected to the data acquisition module, and configured to process the original test data by using a jitter and noise separation technology to obtain the original test data after jitter and noise are separated; A spectrum leakage elimination module is connected to the data acquisition module, and is used for processing the original test data by using a spectrum leakage elimination technology to obtain the original test data after spectrum leakage is eliminated; A clipping distortion suppression module is connected to the data acquisition module, and is used for processing the original test data by a clipping distortion suppression technology to obtain the original test data after the clipping distortion is suppressed; The FPGA test substrate module is connected with the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module. The FPGA test substrate module is used to build a universal configurable test platform based on the FPGA test substrate technology, and process and analyze the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module, and finally obtain the performance test results of the analog and mixed signal integrated circuits to be tested.

[0008] Optionally, the jitter and noise separation module includes the A / D converter, and the jitter and noise separation technology includes a jitter and noise separation algorithm based on the root mean square of jitter and noise, and the jitter and noise separation algorithm based on the root mean square of jitter and noise is used to separate the jitter and noise of the output signal of the A / D converter.

[0009] Optionally, the spectrum leakage elimination technology includes a spectrum leakage elimination algorithm based on transformation error, and the spectrum leakage elimination algorithm based on transformation error is used to obtain the original test data after spectrum leakage is eliminated.

[0010] Optionally, the clipping distortion suppression technology includes a novel clipping distortion suppression spectrum test algorithm, and the novel clipping distortion suppression spectrum test algorithm is used to obtain the original test data after clipping distortion is suppressed.

[0011] Optionally, the universal configurable test platform includes a software interface that matches the FPGA test substrate, and a hardware interface of a device that matches the FPGA test substrate.

[0012] In a second aspect, the present invention provides an analysis and testing method for analog and mixed signal integrated circuits, characterized in that the analysis and testing method is applied to the analysis and testing system described in the first aspect, and the method comprises: The acquisition module is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, wherein the original test data is used to indicate the output signals of the A / D converter and the D / A converter; Processing the original test data by using a jitter and noise separation technology to obtain the original test data after jitter and noise are separated; Processing the original test data using a spectrum leakage elimination technique to obtain the original test data after spectrum leakage is eliminated; Processing the original test data by clipping distortion suppression technology to obtain the original test data after clipping distortion is suppressed; By building a universal configurable test platform based on FPGA test substrate technology, and processing and analyzing the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module, and the clipping distortion suppression module, the performance test results of the analog and mixed-signal integrated circuits to be tested are finally obtained.

[0013] The present application provides an analysis and testing system and method for analog and mixed signal integrated circuits, which integrates multiple modules including data acquisition, jitter and noise separation, spectrum leakage elimination, clipping distortion suppression and FPGA test substrate. The system first collects the original test data of the circuit to be tested through the data acquisition module, which can reflect the output signal state of the A / D converter and the D / A converter. Then, the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module are used to pre-process the original test data respectively, effectively separate jitter and noise, eliminate spectrum leakage and suppress clipping distortion, thereby improving the accuracy and reliability of the data. Finally, the FPGA test substrate module is based on a configurable test platform to conduct an in-depth analysis of the pre-processed data and accurately obtain the performance test results of the analog and mixed signal integrated circuit to be tested. The system provides a comprehensive and efficient solution for the testing of analog and mixed signal integrated circuits. The system breaks through the jitter and noise separation technology, the spectrum leakage elimination technology and the clipping distortion suppression technology, thereby improving the accuracy and efficiency of the analysis and testing of analog and mixed signal integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 A schematic diagram of the flow chart of the analysis and testing system for analog and mixed-signal integrated circuits provided in this application; Figure 2 The least square method provided for this application fits the phase difference into a straight line model; Figure 3 A structural diagram of the entire test substrate provided for this application; Figure 4 A structural diagram of a high-speed and high-precision data converter test platform provided for this application; Figure 5 A schematic flow chart of the analysis and testing method for analog and mixed-signal integrated circuits provided in this application.

[0015] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0017] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein.

[0018] In the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0019] The analysis and testing system and method of analog and mixed-signal integrated circuits provided in this application aims to achieve comprehensive optimization and processing of original test data by integrating data acquisition, jitter and noise separation, spectrum leakage elimination, clipping distortion suppression and FPGA test substrate modules. The system uses advanced signal processing technology to improve data quality, and then conducts in-depth analysis of the optimized data through a test platform built with FPGA test substrate technology, so as to accurately obtain the performance test results of the circuit to be tested, providing an efficient and accurate solution for the testing of analog and mixed-signal integrated circuits.

[0020] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0021] Figure 1 The flowchart of the analysis and testing system of the analog and mixed signal integrated circuit provided in this application is intended to provide a detailed description of the analysis and testing system of the analog and mixed signal integrated circuit, such as Figure 1 As shown, the analysis and testing system for analog and mixed signal integrated circuits provided in this embodiment includes: A data acquisition module, which is deployed in the analysis and testing system and is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, wherein the original test data is used to indicate output signals of the A / D converter and the D / A converter; The following is a detailed description of the direct connection between various devices, equipment and data during the implementation of this step to ensure the adequacy of disclosure.

[0022] 1. System composition and connection IC under test: The core test object in this embodiment, including the A / D converter and D / A converter functional parts, is used to generate analog and mixed signals in the actual test environment.

[0023] Data acquisition module: Label: M1 Function: Responsible for capturing raw test data from the IC under test, which specifically indicates the output signal status of the A / D converter and D / A converter.

[0024] Connection method: The data acquisition module M1 is directly connected to the IC to be tested through a high-speed interface (such as SPI, I2C or a dedicated test interface) to ensure real-time and accurate transmission of data.

[0025] Signal Generator: Label: G1 Function: Provide input excitation signal for the IC under test to simulate the signal input in the actual working scenario.

[0026] Connection method: The output of the signal generator G1 is connected to the input of the IC to be tested through a coaxial cable or a dedicated test cable to ensure that the signal quality is not damaged.

[0027] Data acquisition card: Label: C1 Function: Receive and store the original test data transmitted by the data acquisition module M1.

[0028] Connection method: The data acquisition card C1 is connected to the data acquisition module M1 through PCIe, USB or other high-speed data transmission interfaces to ensure high-speed and stable data transmission.

[0029] Control and display unit: Label: U1 Function: Control the test process and display the test results, including key parameters such as output signal waveform, frequency, amplitude, etc. of A / D converter and D / A converter.

[0030] Connection mode: The control and display unit U1 is connected to the data acquisition module M1 and the data acquisition card C1 through Ethernet, serial port or other communication protocols to realize the automatic control of the test process and the real-time display of the results.

[0031] 2. Output signal generation principle and data acquisition process Signal generation: The signal generator G1 generates an analog input signal according to the preset test scheme, and the signal is sent to the input terminal of the IC to be tested.

[0032] A / D conversion and D / A conversion: The A / D converter inside the IC under test converts the analog input signal into a digital signal, while the D / A converter may convert the internal or external digital signal into an analog output signal according to the test requirements.

[0033] Data capture: The data acquisition module M1 monitors the output of the A / D converter and the D / A converter in real time, and captures the original test data of these output signals through a high-speed interface. These data include but are not limited to key parameters such as the waveform, frequency, amplitude, and phase of the signal.

[0034] Data storage and display: The captured raw test data is transmitted to the data acquisition card C1 for storage, and is displayed and analyzed in real time through the control and display unit U1. The control and display unit U1 can also further process the test data according to the test requirements, such as filtering, amplification, spectrum analysis, etc., to extract more useful information.

[0035] Through the data acquisition module M1 in this embodiment, the output signals of the A / D converter and the D / A converter in the analog and mixed signal integrated circuit can be accurately captured and analyzed. This not only helps to evaluate the performance indicators of the IC to be tested, but also provides reliable data support for subsequent fault diagnosis, optimization design and other work. At the same time, the connection method, test process and data processing method in this embodiment are in line with industry standards and best practices, ensuring the accuracy and reliability of the test.

[0036] A jitter and noise separation module, the jitter and noise separation module is used to process the original test data by using a jitter and noise separation technology to obtain the original test data after the jitter and noise are separated; Further, the jitter and noise separation module includes the A / D converter, and the jitter and noise separation technology includes a jitter and noise separation algorithm based on the root mean square of jitter and noise, and the jitter and noise separation algorithm based on the root mean square of jitter and noise is used to separate the jitter and noise of the output signal of the A / D converter. The jitter and noise separation algorithm based on the root mean square of jitter and noise specifically includes the following principles: A / D converter spectrum testing usually applies a pure sine wave to the DUT and uses FFT to analyze the output code. Parameters such as THD, SFDR, and SNR can be obtained from the FFT spectrum. A spectrum test model for an A / D converter with clock jitter. This model applies a pure input sine wave to the A / D converter, and the additional noise of the A / D converter is simulated by random noise added to the input signal. At the same time, jitter is simulated by random clock changes added to the ideal instantaneous clock.

[0037] Assume that the input signal of the A / D converter under test is a pure sine wave:

[0038] in A , and φ Represent the amplitude, frequency and phase of the input signal respectively. Collect a set of M The A / D converter output of the sampling point is expressed in analog form as:

[0039] in, hd represents high-order distortion, represents the sum of additive and quantization noise, represents the clock jitter at each sampling moment, T s represents the sampling period. Both jitter and noise are random variables following Gaussian distribution: and The output set of the A / D converter is coherently sampled, that is, it contains an integer number of cycles and the phase of each sampling point is different.

[0040] The jitter effect in A / D converter testing shows that the input signal should be sampled at the rising edge of the sampling clock, but the uncertainty of the clock instant Resulting in output The uncertainty of the output signal is proportional to the input signal slope. In the A / D converter spectrum test, if the clock jitter is random and white noise, the error caused by jitter will change with the input phase, larger near the zero crossing point and smaller at the top and bottom of the sine wave.

[0041] The time domain A / D converter output data is used to separate jitter and noise. Two segments of A / D converter output samples are collected under coherent conditions, and then the two sets of data are subtracted to obtain the residual containing jitter and noise information. According to the characteristics of jitter and noise, the residual is mathematically processed to separate the jitter and noise power. Because the root mean square of jitter is usually small, Taylor expansion is used. It can be expressed as: It can be seen that the A / D converter output error caused by the jitter effect is It is proportional to the slope and frequency of the input signal. For the same clock jitter, the higher the input frequency, the greater the error caused by jitter. Therefore, jitter is usually measured when the input frequency is slightly lower than half of the sampling frequency. In addition, because the impact of jitter on harmonics is very small, only the impact of jitter on the fundamental wave is considered and the impact on harmonics is ignored.

[0042] If another set of output signals of the A / D converter under test is continuously collected, the data length is , we can get a new data sequence

[0043] because Follow closely After that, and it is coherent sampling. So their initial phases are the same, and the fundamental and higher harmonics of the two sets of data are the same. Subtracting the above two equations, the residual is:

[0044] in The influence of jitter on higher harmonics can be ignored. The result is almost 0. as well as , since two sets of data are collected continuously in the same environment, and With and The same distribution. According to basic statistical knowledge, we can get and The distribution of .

[0045] Under the conditions of coherent sampling and long data length, multiple mathematical processing of the residual data can separate jitter and A / D converter noise. The sum of squares residual is:

[0046] Each residual value is multiplied by ,get

[0047] M The sum of the points is:

[0048] Combining the above two equations, the variances of jitter and noise are:

[0049] Then the power of the RMS jitter and intrinsic noise is:

[0050] Now jitter and noise have been separated, and It can be used to calculate the SNR of the A / D converter.

[0051] A spectrum leakage elimination module, the spectrum leakage elimination module is used to process the original test data using a spectrum leakage elimination technology to obtain the original test data after spectrum leakage is eliminated; Furthermore, the spectrum leakage elimination technology includes a spectrum leakage elimination algorithm based on transformation error, and the spectrum leakage elimination algorithm based on transformation error is used to obtain the original test data after eliminating spectrum leakage. Among them, the spectrum leakage elimination algorithm based on transformation error specifically includes the following principles: Spectral leakage due to the measurement time interval The mismatch between the integer cycles of the measured signal introduces errors in amplitude, phase and read frequency. When calculating the spectrum of a time-continuous signal and a time-discrete signal, spectrum leakage occurs. The present invention utilizes the typical characteristics of the transformation error to obtain an easy-to-implement spectral leakage elimination algorithm based on the transformation error to obtain the correct frequency of the measured signal. , Amplitude A m and Phase Typically, the measured time signal The frequencies are unrelated to each other MEach component in this time signal (which has not been coherently sampled) will be affected by spectral leakage phenomena, but will also have a very typical pattern around the exact frequency of the component within its spectrum. Using this pattern, the correct frequency, amplitude, and phase can be accurately estimated.

[0052] One with only one frequency component The simple time signal can be expressed as:

[0053] Measurement time interval Include N samples, of which l The range is from 0 to N -1. Applying DFT, we get:

[0054] Spectrum Include N The order is k , j represents the imaginary unit. Get the correct order

[0055] when When is not an integer, spectral leakage will occur. The input signal can be rewritten as:

[0056] Will Remember to do can be written as:

[0057] if Defined as:

[0058] can be rewritten as:

[0059] Because for all complex numbers , and for all integers P 2 and P 1, P 2> P 1, get:

[0060] Rewritten as:

[0061] Using Euler and trigonometric functions, we get:

[0062] when N When it is very big, .when Much smaller than N hour, .so:

[0063] When the signal is coherently sampled ( is an integer), equal . When spectrum leakage occurs ( is not an integer), the component Introducing the correct order around Since all k The values ​​are all integers. , the above formula can be simplified to:

[0064] Clearly, the sign change occurs at the correct order When considering the input signal M When the frequency is M The spectrum leakage pattern consists of:

[0065] If the frequency is ( ; n The range is 1 to m ) comes from the spectrum pairs of different sinusoidal components The overlap of the spectrum groups of is small enough, and the negative spectrum group right The influence of can be ignored, so it can be assumed that nearby, .Depend on The impact of the resulting spectral set depends not only on the correct order ,amplitude A n and Phase , but also depends on .

[0066] The experiment showed that when =40.21, =45.68, A m = A n =2 and The simulation results show that the two correct orders , , their real parts , and the combined spectrum .because and and Proportional, The relative error on Due to and , relative error Also reduced.

[0067] In fact, assuming and have the same order of magnitude. In order to minimize the impact between harmonic groups, usually is sufficient. In addition, in order to minimize right The impact of , .on the other hand, k m and k m +1 is obtained by looking for a sign change, and the weighted average is obtained from k m and k m +1 to get the correct order exactly .

[0068]

[0069] Use the correct order , can be obtained from Get the amplitude and phase. is an approximate value of magnitude, is an approximate value of the phase of a time signal, is the phase sign. Greater than hour, Can replace , Can replace , you can get better results.

[0070] In summary, the first step of the spectral leakage elimination algorithm based on transform error is to calculate the DFT of the measured signal. The second step is to search for sign changes in the spectrum (find k m and k m +1). Use k m and k m +1, calculated the correct order The fourth step calculates the amplitude and phase. When the frequency components are coherently sampled, the algorithm will not find a sign change for that particular frequency component in the spectrum. To ensure that the frequency of each component is found without omission, the algorithm is performed twice on the same signal. During the first run, all N samples, but during the second run only N -1 sample.

[0071] A clipping distortion suppression module, the clipping distortion suppression module is used to process the original test data by a clipping distortion suppression technology to obtain the original test data after the clipping distortion is suppressed; Furthermore, the clipping distortion suppression technology includes a novel clipping distortion suppression spectrum test algorithm, and the novel clipping distortion suppression spectrum test algorithm is used to obtain the original test data after clipping distortion is suppressed. The novel clipping distortion suppression spectrum test algorithm includes the following principles: Clipping causes spurs in the spectrum, while incoherence causes power leakage in the fundamental, both of which mask higher-order distortion. It can be assumed that the spurs in the clipped spectrum are mainly caused by clipping of the fundamental component. Assume is the input signal of the A / D converter, where A , , and V os are the amplitude, frequency, initial phase and offset of the input signal respectively, A Slightly less than or equal to half of the FS of the A / D converter. The analog representation of the digital output code converted by the A / D converter is

[0072] in, is the sampling frequency, w ( n ) is the additional noise, A h The output of the A / D converter h Subharmonics, H is the total number of harmonics, M is the total number of sampling points. There are three assumptions in the actual A / D converter test: 1) the A / D converter test setup must be stable and have sufficient repeatability; 2) the A / D converter is continuous, which means , For all h are all continuous; 3) Spectral performance mainly depends on A , and ,this means, Significantly, but .

[0073] In the case of coherent sampling, the captured window must be an integer number of periods. J is the total number of sampling periods, then M , , and J The relationship is

[0074] if M is a power of 2, then any odd number J Both M The mutual element. It can be expressed as

[0075] In incoherent sampling, Substitute J In order to obtain the accurate fundamental wave, it is necessary to calculate the parameters accurately from the output of the A / D converter. A , V os , , J int and The amplitude and offset of the fundamental are estimated based on the number of clipping points. K t is the number of clipping points at the top, K b The number of bottom clipping points. and These are the positive and negative reference voltages for the A / D converter. A and V os It can be expressed as:

[0076] From the time domain data A and V os Then, we get J int and Applying the DFT to the A / D converter output sequence , and estimates based on the index of the frequency window J int .

[0077] in,

[0078] is the initial phase of the fundamental component of the sampling sequence. The first estimate of can be expressed as

[0079] Among them, image is the imaginary part, real is the real part, is the modulo sign, and the least squares method is used to accurately estimate the zero crossing point of the A / D converter time domain output and The approximate fundamental phase approximation at each point can be described as:

[0080] However, since the phase is calculated directly from the incoherent data, it does not represent the actual phase of the input sine wave or the phase of the first sample point. to obtain the actual frequency. After removing the offset, the actual frequency and phase of the input sine wave are collected from the zero crossing of the sampling point. To select the fitting points, define

[0081] Ignoring higher-order distortion and noise, the actual phase at these points can be described as:

[0082] is satisfied All k The actual phase and fundamental phase difference is:

[0083] in is the difference between the actual initial phase and its first estimate, is a fraction of the number of periods. Using the least squares method, Fitting a straight line gives an estimated and Value. Figure 2 As shown, the sine wave consists of all the output points, and the points on the straight line represent the phase difference of the zero crossing point. and J It can be expressed as:

[0084] The incoherent fundamental wave is:

[0085] In practice, the incoherent fundamental component cannot be completely removed as long as the test is incoherent. In this case, if only , then the fundamental wave effect still exists in the residual. Assume that the error of the fundamental wave component is:

[0086] in, is the amplitude. The non-ideal fundamental component consists of two parts: the incoherent fundamental component and the fundamental error. Limited by the FS of the A / D converter, the non-ideal fundamental can be expressed as:

[0087] When the non-ideal fundamental component is subtracted from the sampled points, only harmonics and noise distortions without incoherence and clipping remain in the residual. Adding the ideal fundamental to the residual yields a new sequence. The ideal fundamental component is expressed as:

[0088] After replacing the incoherent and clipped fundamental component with the ideal reference component, we obtain

[0089] The new sequence can be used to analyze the spectral performance of A / D converters.

[0090] The FPGA test substrate module is connected with the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module. The FPGA test substrate module is used to build a universal configurable test platform based on the FPGA test substrate technology, and process and analyze the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module, and finally obtain the performance test results of the analog and mixed signal integrated circuits to be tested.

[0091] Furthermore, the universal configurable test platform includes a software interface that matches the FPGA test substrate, and a hardware interface of a device that matches the FPGA test substrate.

[0092] Connection of FPGA test baseboard module: The FPGA test base module is connected to the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module through dedicated data connection lines. These connection lines ensure that the pre-processed data can be accurately transmitted to the FPGA test base module.

[0093] Universal configurable test platform: The universal configurable test platform is an important part of the FPGA test baseboard module. The platform includes software interfaces and hardware interfaces that match the FPGA test baseboard.

[0094] Software interface: The software interface is used to communicate with the host computer or other control software, receive control instructions and return test results. The interface uses a standard communication protocol to ensure compatibility with different control software.

[0095] Hardware interface: The hardware interface is used to connect devices that match the FPGA test substrate, such as signal generators, oscilloscopes, etc. These interfaces adopt a standardized design and can be easily connected to various test equipment, realizing the flexibility and scalability of the test platform.

[0096] During the test, the FPGA test base module receives control instructions through the software interface, and connects to the test equipment through the hardware interface to process and analyze the pre-processed raw test data. Finally, the FPGA test base module returns the analysis results to the host computer or other control software through the software interface, thereby obtaining the performance test results of the analog and mixed-signal integrated circuits to be tested.

[0097] The configurable universal data converter test platform implements the testing of A / D converters and D / A converters on the same platform, realizing the reuse of test resources and thus reducing the testing cost. In addition, based on the configuration of the high-performance FPGA in the test platform, it is easy to implement the testing of high-speed and high-precision data converters with different conversion accuracy and conversion speed without rebuilding a new test platform, which can greatly improve the testing efficiency and reduce the testing cost.

[0098] The core part of the configurable universal data converter test platform is a test substrate based on a high-speed FPGA. By configuring the FPGA, the functions of high-speed data acquisition and digital graphics generation can be realized. In addition, the substrate can provide connection functions with the evaluation board of the device under test, communication functions with the software in the PC, and interface functions with test instruments and equipment.

[0099] The structure diagram of the entire test substrate is as follows: Figure 3 As shown, the core is a high-performance FPGA (such as Altera's StratixⅢ), which can be connected to the computer through a communication interface (USB or RJ45, etc.) and a USB chip to complete the configuration of the FPGA and the communication with the computer; and provide connection interfaces for the A / D converter evaluation board and the D / A converter evaluation board (compatible with LVDS and LVCMOS high-speed interfaces, supporting up to 1.6Gbps) (corresponding to Figure 3The ADC connection interface and DAC connector in the board are used to connect the FPGA to the ADC. When testing the D / A converter, the board receives the control and encoding data of the computer and sends the data to the D / A converter through the connector. When testing the A / D converter, the board is responsible for receiving computer instructions, controlling and collecting converted data. The board contains a power module to provide power to each component. In addition to the local oscillator clock source, an external clock signal can also be input. The onboard SDRAM can be implemented in different ways (Flash and DRAM, etc.), which can expand the data storage capacity of the FPGA during testing, store test data, and increase the test speed. The signal of the external clock is usually generated by an external oscillator (such as a crystal oscillator, also known as a clock crystal oscillator) or an external signal source, and is connected to the system or device through a specific pin or interface. In systems such as single-chip microcomputers, microcontrollers, and FPGAs, external clock signals are usually used to provide reference frequencies for the system's timing counters, clock trees, etc. The power module is mainly responsible for power consumption testing and evaluation. For example, in terms of low-power design verification, the power consumption of the chip or device on the board under specific working conditions is tested to verify whether it meets the low-power design requirements. By adjusting the test parameters, different working scenarios are simulated to evaluate the power consumption performance of the chip. In terms of power management strategy verification, the power management modules on the substrate are tested, such as the effectiveness of dynamic voltage and frequency scaling (DVFS), clock gating, power gating and other technologies. The adaptability of the power management strategy under different load and power conditions is verified.

[0100] Figure 4 The structure diagram of the entire configurable general high-speed and high-precision data converter test platform is given. The device to be tested can be selected through the configuration of FPGA to realize the test of A / D converter and D / A converter. When selected as a D / A converter test platform, computer software can be used to generate various test vectors required for D / A converter testing and quantize them into binary numbers, such as single-tone signal, dual-tone signal, digital sine wave and linear frequency modulation signal. When configured as an A / D converter test platform, the A / D converter can be controlled by computer to collect data and import it into the computer. The converted data can be analyzed in the frequency domain using special software to give the final test results and waveforms. The test platform uses the computer as the core control unit and communicates with the FPGA evaluation substrate through the USB interface. As the core processing unit of the test platform, the FPGA evaluation substrate is responsible for receiving control instructions from the computer and coordinating the work of each module.

[0101] During the test, the test signal source first generates analog signals, which are then sent to the ADC test board and the DAC test board. The analog-to-digital converter (ADC) on the ADC test board converts the analog signals into digital signals, while the digital-to-analog converter (DAC) on the DAC test board converts the digital signals into analog signals.

[0102] For the ADC test board, the converted digital signal is sent to the data packet decoding module for decoding through the ADC board data acquisition and export control module. After the decoded data is further processed by the ADC board data acquisition and export control module and the ADC board SPI control module, the processed data is sent to the ADC test board on the one hand, and sent to the DAC board clock control module and DAC board data distribution module through the data packet decoding module on the other hand, and then sent to the DAC test board, and finally sent to the oscilloscope and logic analyzer.

[0103] In addition, the test platform also includes a collection and export module for real-time collection and export of test data during the test process for subsequent data processing and analysis.

[0104] In summary, the entire configurable general-purpose high-precision analog and mixed-signal integrated circuit test platform realizes comprehensive testing and analysis of high-speed and high-precision data converters through the collaborative work of computers, FPGA evaluation substrates, various control modules, and data transmission modules.

[0105] This embodiment provides an analysis and test system for analog and mixed signal integrated circuits, which integrates multiple functional modules such as data acquisition, jitter and noise separation, spectrum leakage elimination, clipping distortion suppression and FPGA test substrate, and realizes comprehensive analysis and testing of analog and mixed signal integrated circuits. The system first collects the original test data of the circuit to be tested through the data acquisition module, and then uses the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module to pre-process the original data, effectively improving the accuracy and reliability of the data. On this basis, the FPGA test substrate module builds a general configurable test platform based on advanced FPGA technology, conducts in-depth analysis of the pre-processed data, and finally accurately obtains the performance test results of the circuit to be tested. The system not only improves the test efficiency, but also reduces the test cost, providing strong support for the research and development and production of analog and mixed signal integrated circuits. At the same time, its modular design makes the system easy to expand and maintain, and has good application prospects. The system breaks through the jitter and noise separation technology, the spectrum leakage elimination technology and the clipping distortion suppression technology, thereby improving the accuracy and efficiency of the analysis and test of analog and mixed signal integrated circuits.

[0106] Figure 5 The flowchart of the analysis and testing method of analog and mixed signal integrated circuits provided in this application is intended to explain the analysis and testing method of analog and mixed signal integrated circuits in detail, such as Figure 5 As shown, the analysis and testing system for analog and mixed signal integrated circuits provided in this embodiment includes: S101: The acquisition module is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, and the original test data is used to indicate the output signals of the A / D converter and the D / A converter.

[0107] Among them, in the test process of analog and mixed-signal integrated circuits (hereinafter referred to as "IC"), the acquisition module plays a vital role. It is responsible for collecting the original test data of the IC to be tested, which directly reflects the output signal characteristics of the A / D converter (analog to digital converter) and the D / A converter (digital to analog converter). The specific implementation steps and functions of the acquisition module will be described in detail below.

[0108] Implementation steps: Test environment preparation: First, ensure that the IC to be tested has been properly installed in the test system, which includes the necessary power supply, signal generator, and data acquisition equipment.

[0109] Connect the A / D converter and D / A converter to the corresponding interfaces of the test system to ensure that the signal path is unobstructed.

[0110] Configure the test system and set appropriate sampling rate, resolution and other related parameters to meet the test requirements of the IC under test.

[0111] Acquisition module configuration: Activate the acquisition module and set its working mode to data acquisition mode through the software interface or hardware switch.

[0112] Configure the input channels of the acquisition module to match the output ports of the A / D converter and D / A converter.

[0113] According to the specification of the IC to be tested, set the trigger conditions of the acquisition module, such as external trigger, internal timing trigger, etc., to ensure that the output signals of the A / D and D / A converters can be accurately captured.

[0114] Original test data acquisition: Start the test program and input preset test signals to the IC under test. These signals may include sine waves, square waves, pulse sequences, etc., which are used to simulate signal changes in actual working scenarios.

[0115] The acquisition module starts working, collects the output signals of the A / D converter and the D / A converter in real time, and converts them into digital format and stores them in the specified data storage medium, such as memory, hard disk or network storage device.

[0116] During the acquisition process, the acquisition module records the voltage or current value of each sampling point, as well as the sampling timestamp to ensure the integrity and accuracy of the data.

[0117] Data verification and storage: After completing data collection, conduct preliminary verification on the original test data to check whether the data is complete and has no abnormal values ​​or missing data.

[0118] If the data quality meets the requirements, it will be saved as a file in a specific format, such as CSV, TXT or binary file, for subsequent processing and analysis.

[0119] At the same time, a data collection report is generated to record information such as test conditions, sampling parameters, and data quality assessment to provide a reference for subsequent steps. Implementation Effect

[0120] Through the above implementation steps, the acquisition module can efficiently collect the original test data of the IC under test, which accurately reflects the output signal characteristics of the A / D converter and the D / A converter, providing a solid foundation for subsequent processing and analysis through jitter and noise separation technology, spectrum leakage elimination technology, clipping distortion suppression technology, and FPGA-based test substrate technology.

[0121] S102: Processing the original test data by using a jitter and noise separation technology to obtain the original test data after jitter and noise are separated.

[0122] The jitter and noise separation technology includes a jitter and noise separation algorithm based on the root mean square of jitter and noise, and the jitter and noise separation algorithm based on the root mean square of jitter and noise is used to separate the jitter and noise of the output signal of the A / D converter.

[0123] The implementation process of this step is described in detail below.

[0124] 1. Technical foundation The jitter and noise separation technology used in this embodiment is based on a jitter and noise separation algorithm based on the root mean square (RMS) of jitter and noise (the specific principle of the algorithm is referred to in Figure 1 The embodiment will not be described in detail here). The algorithm performs statistical analysis on the original test data and calculates the RMS value of jitter and noise, thereby achieving effective separation of the two. Jitter usually appears as a slight offset of the signal edge position, while noise appears as random fluctuations in the signal amplitude.

[0125] 2. Implementation steps Data preprocessing: Extract the output signal data of the A / D converter from the original test data received by the acquisition module.

[0126] Perform a preliminary screening of the data to remove outliers or invalid data points to ensure data quality.

[0127] Calculate the RMS value: For each sample point of the A / D converter output signal, calculate its deviation from the ideal value (that is, the sum of jitter and noise).

[0128] The deviation values ​​for all samples are squared, summed, and divided by the total number of samples to obtain the total RMS value of jitter and noise.

[0129] Separation of jitter and noise: Using an RMS-based separation algorithm, jitter and noise are separated from the total RMS value based on the statistical characteristics of the signal.

[0130] Jitter usually appears as a regular or periodic deviation in the position of signal edges and can be estimated by analyzing the transition time of the signal edges.

[0131] Noise appears as random fluctuations and can be evaluated by calculating the signal's spectral density or autocorrelation function.

[0132] Result output: The separated jitter and noise data are stored separately for subsequent analysis.

[0133] Generate a separation result report, record the RMS value of jitter and noise, key parameters of the separation process and result evaluation.

[0134] 3. Technical features and advantages High precision: The RMS-based separation algorithm can accurately calculate the RMS values ​​of jitter and noise, thereby effectively separating the two.

[0135] Flexibility: The algorithm is applicable to different types of A / D converter output signals and can cope with various test scenarios.

[0136] Configurability: By adjusting the algorithm parameters, the separation effect can be optimized to meet different test requirements.

[0137] IV. Implementation Effect After processing in step S102, the jitter and noise in the original test data are effectively separated, providing more accurate data support for subsequent performance evaluation. At the same time, the implementation of this step also lays a solid foundation for subsequent technical processing such as spectrum leakage elimination and clipping distortion suppression.

[0138] S103: Process the original test data using spectrum leakage elimination technology to obtain the original test data after spectrum leakage is eliminated.

[0139] The spectrum leakage elimination technology includes a spectrum leakage elimination algorithm based on transformation error, and the spectrum leakage elimination algorithm based on transformation error is used to obtain the original test data after eliminating spectrum leakage. In the test process of analog and mixed signal integrated circuits (ICs), the goal of step S103 is to use spectrum leakage elimination technology to further optimize the original test data after preliminary processing to eliminate spectrum leakage, thereby improving the accuracy and reliability of the test data. The implementation process of this step is described in detail below.

[0140] 1. Technical foundation The core of the spectrum leakage elimination technology used in this embodiment is the spectrum leakage elimination algorithm based on transformation error (the specific principle of the algorithm is referred to in Figure 1 The embodiments are not described in detail here.) The algorithm performs frequency domain transformation on the original test data, analyzes the error sources in the transformation process, and designs corresponding compensation measures accordingly to eliminate the spectrum leakage phenomenon.

[0141] 2. Implementation steps Data preparation: Receive the original test data after jitter and noise separation from the acquisition module.

[0142] Ensure the integrity, accuracy and consistency of data to provide a reliable basis for subsequent processing.

[0143] Frequency domain transformation: Perform fast Fourier transform (FFT) or other appropriate frequency domain transformation methods on the original test data to convert the time domain data into frequency domain data.

[0144] During the transformation process, the transformation errors, including truncation error, sampling error, etc., are recorded and analyzed.

[0145] Spectral leakage analysis: Identify leakage phenomena in the spectrum based on the frequency domain transformation results.

[0146] Analyze the source of the leakage phenomenon, such as non-periodicity of the signal, insufficient sampling rate, etc.

[0147] Elimination algorithm application: The spectral leakage elimination algorithm based on transformation error is used to process the frequency domain data.

[0148] The algorithm corrects the leakage components in the spectrum by calculating the compensation amount of the transformation error to eliminate the spectrum leakage phenomenon.

[0149] The calculation of the compensation amount can be based on the results of error analysis or obtained through iterative optimization methods.

[0150] Result verification: Verify the processed frequency domain data to ensure that spectrum leakage is effectively eliminated.

[0151] If necessary, adjust the algorithm parameters to optimize the elimination effect.

[0152] Data output: Convert the frequency domain data after spectrum leakage removal back to time domain data (if necessary), or keep the frequency domain data form.

[0153] Output the processed data for use in subsequent steps.

[0154] 3. Technical features and advantages High precision: The spectrum leakage elimination algorithm based on transformation error can accurately calculate the compensation amount and effectively eliminate the spectrum leakage phenomenon.

[0155] Wide applicability: The algorithm is applicable to different types of analog and mixed-signal integrated circuit test data and has wide applicability.

[0156] Configurability: Algorithm parameters can be flexibly adjusted according to test requirements to meet the accuracy requirements in different test scenarios.

[0157] IV. Implementation Effect After processing in step S103, the spectrum leakage phenomenon in the original test data is effectively eliminated, providing more accurate data support for subsequent performance evaluation. At the same time, the implementation of this step also lays a solid foundation for subsequent clipping distortion suppression and processing based on FPGA test substrate technology.

[0158] S104: Processing the original test data by means of a clipping distortion suppression technique to obtain the original test data after clipping distortion is suppressed.

[0159] The clipping distortion suppression technology includes a novel clipping distortion suppression spectrum test algorithm, and the novel clipping distortion suppression spectrum test algorithm is used to obtain the original test data after clipping distortion is suppressed.

[0160] In the test process of analog and mixed-signal integrated circuits (ICs), the key to step S104 is to use clipping distortion suppression technology to further optimize the original test data that has been processed in the early stage, so as to effectively suppress the clipping distortion phenomenon and ensure the accuracy and integrity of the test data. The implementation process of this step is described in detail below.

[0161] 1. Technical foundation The core of the clipping distortion suppression technology used in this embodiment is a new clipping distortion suppression spectrum test algorithm (the specific principle of the algorithm is referenced in Figure 1 The embodiments are not described in detail here.) The algorithm aims at the problem of clipping distortion, and designs a corresponding compensation strategy by accurately analyzing the signal spectrum characteristics, so as to effectively suppress the clipping distortion and improve the accuracy of the test data.

[0162] 2. Implementation steps Data preparation: Receive the original test data from the acquisition module after jitter and noise separation and spectrum leakage elimination.

[0163] Ensure the integrity, accuracy and consistency of data to provide a reliable basis for subsequent processing.

[0164] Clipping distortion detection: Perform clipping distortion detection on the original test data to identify signal segments with clipping distortion.

[0165] Clipping distortion usually appears as a sudden cutoff of the signal amplitude or nonlinear distortion, and can be identified by observing the signal waveform or spectral characteristics.

[0166] Spectrum feature analysis: Perform spectrum feature analysis on signal segments with clipping distortion and extract key spectrum parameters.

[0167] Spectrum feature analysis helps to understand the degree of clipping distortion and spectrum distribution, and provides a basis for the design of subsequent compensation strategies.

[0168] Application of new clipping distortion suppression algorithm: A new clipping distortion suppression spectrum test algorithm is used to process signal segments with clipping distortion.

[0169] The algorithm corrects the clipping distortion by calculating the compensation amount to restore the true spectrum characteristics of the signal.

[0170] The calculation of the compensation amount can be based on the results of spectrum characteristic analysis or obtained through an iterative optimization method.

[0171] Result verification: Verify the processed data to ensure that clipping distortion is effectively suppressed.

[0172] The verification process can be carried out by comparing the waveform, spectrum characteristics or performance indicators of the signal before and after processing.

[0173] Data output: The data with clipping distortion suppressed is output for use in subsequent steps.

[0174] The data output format can be flexibly configured according to test requirements to meet the requirements of different application scenarios.

[0175] 3. Technical features and advantages High precision: The new spectrum test algorithm for suppressing clipping distortion can accurately calculate the compensation amount, effectively suppress clipping distortion, and improve the accuracy of test data.

[0176] Wide applicability: The algorithm is applicable to different types of analog and mixed-signal integrated circuit test data and has wide applicability.

[0177] Configurability: Algorithm parameters can be flexibly adjusted according to test requirements to meet the accuracy requirements in different test scenarios.

[0178] IV. Implementation Effect After processing in step S104, the clipping distortion in the original test data is effectively suppressed, providing more accurate data support for subsequent performance evaluation. At the same time, the implementation of this step also lays a solid foundation for subsequent processing and analysis based on FPGA test substrate technology.

[0179] S105: A universal configurable test platform is built based on FPGA test substrate technology, and the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module, and the clipping distortion suppression module are processed and analyzed, and finally the performance test results of the analog and mixed signal integrated circuits to be tested are obtained.

[0180] The universal configurable test platform includes a software interface matching the FPGA test substrate and a hardware interface of a device matching the FPGA test substrate.

[0181] In the test process of analog and mixed-signal integrated circuits (ICs), step S105 is the core part of the test process. It aims to build a universal and configurable test platform based on FPGA (field programmable gate array) test substrate technology, deeply process and analyze the original test data after being processed by multiple modules in the early stage, and finally obtain the performance test results of the IC to be tested. The implementation process of this step is described in detail below.

[0182] 1. Technical foundation and platform construction FPGA test substrate selection: According to the characteristics of the IC to be tested and the test requirements, select an FPGA test substrate with sufficient logic units, IO interfaces and high-speed communication capabilities.

[0183] Ensure that the FPGA test baseboard can support the required test frequency, accuracy, and data processing capabilities.

[0184] General configurable test platform design: Design the hardware architecture of the test platform, including FPGA test substrate, test fixture, signal conditioning circuit, etc.

[0185] Develop a software interface that matches the FPGA test substrate to realize the reading, storage and processing of test data.

[0186] Design the hardware interface of the equipment that matches the FPGA test substrate, such as ADC (analog-to-digital converter), DAC (digital-to-analog converter), clock source, etc., to ensure that the test platform can accurately and stably receive and process the output signal of the IC under test.

[0187] Test platform configuration and calibration: Configure the test platform parameters such as sampling rate, test frequency, test vectors, etc. according to the specifications and test requirements of the IC to be tested.

[0188] Calibrate the test platform to ensure the accuracy and reliability of the test results.

[0189] 2. Data Processing and Analysis Data reception and preprocessing: The original test data processed by the jitter and noise separation module, the spectrum leakage elimination module, and the clipping distortion suppression module is received through the software interface.

[0190] Pre-process the received data, such as data format conversion, data synchronization, etc., to ensure that the data can be correctly and efficiently passed to the subsequent processing modules.

[0191] Data processing and analysis: Utilize the parallel processing capability of the FPGA test substrate to perform in-depth processing and analysis on the pre-processed data.

[0192] Analyze the output signal characteristics of the IC under test, such as frequency response, phase response, harmonic distortion, etc.

[0193] Based on the test results, evaluate the performance indicators of the IC under test, such as conversion rate, signal-to-noise ratio, dynamic range, etc.

[0194] Result output and report generation: The processing and analysis results are output to the software interface of the test platform for testers to view and analyze.

[0195] Generate a detailed test report based on the test results, including test parameters, test results, performance indicator evaluation, etc.

[0196] 3. Technical features and advantages Versatility: The test platform adopts a modular design and can be flexibly configured according to the characteristics of the IC to be tested and the test requirements. It is suitable for different types of analog and mixed-signal integrated circuit tests.

[0197] High precision: Utilize the high-speed parallel processing capability of the FPGA test substrate, combined with high-precision test fixtures and signal conditioning circuits to ensure the accuracy and reliability of the test results.

[0198] Scalability: The test platform supports multiple test vectors and test modes, and can be expanded and upgraded according to test requirements.

[0199] Efficiency: The test platform adopts an automated testing process, which can greatly improve test efficiency and accuracy.

[0200] IV. Implementation Effect After processing and analysis in step S105, the test platform can accurately and efficiently obtain the performance test results of the analog and mixed-signal integrated circuits to be tested. The test results can provide strong data support for subsequent IC design optimization, production process improvement, etc.

[0201] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0202] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An analysis and testing system for analog and mixed signal integrated circuits, characterized in that: The system comprises: A data acquisition module, which is deployed in the analysis and testing system and is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, wherein the original test data is used to indicate output signals of the A / D converter and the D / A converter; A jitter and noise separation module, connected to the data acquisition module, and configured to process the original test data by using a jitter and noise separation technology to obtain the original test data after jitter and noise are separated; A spectrum leakage elimination module, connected to the data acquisition module, and configured to process the original test data using a spectrum leakage elimination technique to obtain the original test data after spectrum leakage is eliminated; A clipping distortion suppression module connected to the data acquisition module, the clipping distortion suppression module is used to process the original test data by clipping distortion suppression technology to obtain the original test data after clipping distortion is suppressed; The FPGA test substrate module is connected with the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module. The FPGA test substrate module is used to build a universal configurable test platform based on the FPGA test substrate technology, and process and analyze the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module and the clipping distortion suppression module, and finally obtain the performance test results of the analog and mixed signal integrated circuits to be tested.

2. The system according to claim 1, characterized in that The jitter and noise separation module includes the A / D converter, and the jitter and noise separation technology includes a jitter and noise separation algorithm based on the root mean square of jitter and noise, and the jitter and noise separation algorithm based on the root mean square of jitter and noise is used to separate the jitter and noise of the output signal of the A / D converter.

3. The system according to claim 1, characterized in that The spectrum leakage elimination technology includes a spectrum leakage elimination algorithm based on transformation error, and the spectrum leakage elimination algorithm based on transformation error is used to obtain the original test data after eliminating spectrum leakage.

4. The system according to claim 1, characterized in that The clipping distortion suppression technology includes a novel clipping distortion suppression spectrum test algorithm, and the novel clipping distortion suppression spectrum test algorithm is used to obtain the original test data after clipping distortion is suppressed.

5. The system according to claim 1, characterized in that The universal configurable test platform includes a software interface matching the FPGA test substrate and a hardware interface of a device matching the FPGA test substrate.

6. A method for analyzing and testing analog and mixed signal integrated circuits, characterized in that: The analysis and testing method is applied to the analysis and testing system according to any one of claims 1 to 5, and the method comprises: The acquisition module is used to acquire original test data of the analog and mixed signal integrated circuit to be tested, wherein the original test data is used to indicate the output signals of the A / D converter and the D / A converter; Processing the original test data by using a jitter and noise separation technology to obtain the original test data after jitter and noise are separated; Processing the original test data using a spectrum leakage elimination technique to obtain the original test data after spectrum leakage is eliminated; Processing the original test data by clipping distortion suppression technology to obtain the original test data after clipping distortion is suppressed; By building a universal configurable test platform based on FPGA test substrate technology, and processing and analyzing the original test data processed by the jitter and noise separation module, the spectrum leakage elimination module, and the clipping distortion suppression module, the performance test results of the analog and mixed-signal integrated circuits to be tested are finally obtained.

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