Time-interleaved analog-to-digital converter and signal conversion method

Abstract

The invention relates to a time-interleaved analog-to-digital converter and a signal conversion method. The time-interleaved analog-to-digital converter comprises a plurality of sampling circuits, a plurality of analog-to-digital converter circuits, an output circuit and a correction circuit. The plurality of sampling circuits are configured to sequentially sample an input signal to generate a plurality of first signals, wherein a circuit parameter of each of the sampling circuits is set according to a corresponding control signal of a plurality of control signals. The plurality of analog-to-digital converter circuits are configured to generate a plurality of first digital codes according to the first signal. The output circuit is used for outputting a second digital code according to the first digital code. The correction circuit is used for generating the control signal and adjusting the control signal according to the second digital code.

Description

Technical Field

[0001] The present disclosure relates to an analog-to-digital converter, and more particularly to a time-interleaved analog-to-digital converter capable of correcting bandwidth mismatch and a signal conversion method. Background Art

[0002] In existing time-interleaved analog to digital converters, non-ideal factors such as time skew and gain error between multiple channels are usually corrected to improve overall performance. However, there are still problems such as bandwidth mismatch between multiple channels. To correct bandwidth mismatch, current technology requires a complex correction mechanism to provide different correction parameters according to the frequency of the input signal, resulting in a significant increase in the overall circuit area and power consumption. Summary of the invention

[0003] In some implementations, one of the purposes of the present disclosure is (but not limited to) to provide a time-interleaved analog-to-digital converter and a signal conversion method capable of correcting bandwidth mismatch, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, a time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of analog-to-digital converter circuits, an output circuit, and a calibration circuit. The plurality of sampling circuits are used to sequentially sample an input signal to generate a plurality of first signals, wherein a circuit parameter of each of the sampling circuits is set according to a corresponding control signal among a plurality of control signals. The plurality of analog-to-digital converter circuits are used to generate a plurality of first digital codes according to the first signals. The output circuit is used to output a second digital code according to the first digital codes. The calibration circuit is used to generate the control signals and adjust the control signals according to the second digital code.

[0005] In some embodiments, the signal conversion method includes the following operations: sequentially sampling an input signal through a plurality of sampling circuits to generate a plurality of first signals, wherein a circuit parameter of each of the sampling circuits is set according to a corresponding control signal among a plurality of control signals; generating a plurality of first digital codes according to the first signals; outputting a second digital code according to the first digital codes; and adjusting the control signals according to the second digital code.

[0006] The features, implementation and technical effects of the present disclosure are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A schematic diagram of a time-interleaved analog-to-digital converter according to some embodiments of the present disclosure;

[0008] Figure 2 According to some embodiments of the present disclosure Figure 1 A flowchart of multiple operations performed by a correction circuit;

[0009] Figure 3A According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit in;

[0010] Figure 3B According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit in;

[0011] Figure 4A According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit in;

[0012] Figure 4B According to some embodiments of the present disclosure Figure 4A Schematic diagram of the bootstrap circuit in ;

[0013] Figure 5A According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit in;

[0014] Figure 5B According to some embodiments of the present disclosure Figure 1 A schematic diagram of a variable capacitance circuit in; and

[0015] Figure 6 The present invention is a flowchart of a signal conversion method according to some embodiments of the present disclosure.

[0016] Explanation of symbols

[0017] 100: Time-interleaved analog-to-digital converter

[0018] 110[1],110[2]:Sampling circuit

[0019] 120[1],120[2]: Analog-to-digital converter circuit

[0020] 130: Output circuit

[0021] 140: Correction circuit

[0022] 310: Transistor

[0023] 320: Digital to Analog Converter Circuit

[0024] 330,410: Bootstrap circuit

[0025] 510: Buffer circuit

[0026] 520: Variable Capacitor Circuit

[0027] 521: Switch

[0028] 600: Signal conversion method

[0029] C1, C2, C3, C4: capacitors

[0030] CF: Capacitor array

[0031] CLK1, CLK2: clock signal

[0032] D1[1], D1[2], D2: digital code

[0033] M1~M4:Transistor

[0034] R: Resistance

[0035] S1[1],S1[2],S2:signal

[0036] S210,S220,S230,S240,S250,S260,S270: Operation

[0037] S610, S620, S630, S640: Operation

[0038] SC[1], SC[2]: control signal

[0039] SIN: Input signal

[0040] SS1, SS2: switching signal

[0041] SW: Switch

[0042] VB: Bias voltage

[0043] VDC: Predetermined voltage

[0044] VDD: supply voltage

[0045] VL: Voltage DETAILED DESCRIPTION

[0046] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein in the content of this disclosure are only illustrative and should not limit the scope and meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0047] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may be a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0048] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this article, the words first, second, third, etc. are used to describe and distinguish each element. Therefore, the first element in this article can also be called the second element without departing from the original intention of the present disclosure. For ease of understanding, similar elements in the various drawings will be designated with the same reference numerals.

[0049] Figure 1 FIG. 1 is a schematic diagram of a time-interleaved analog-to-digital converter 100 according to some embodiments of the present disclosure. The time-interleaved analog-to-digital converter 100 includes a plurality of sampling circuits 110 [ 1 ] and 110 [ 2 ], a plurality of analog-to-digital converter circuits 120 [ 1 ] and 120 [ 2 ], an output circuit 130 and a calibration circuit 140 .

[0050] A plurality of sampling circuits 110[1] and 110[2] are used to sequentially sample an input signal SIN to generate a plurality of signals S1[1] and S1[2]. For example, the sampling circuit 110[1] can be selectively turned on according to a clock signal CLK1 to sample the input signal SIN, thereby generating a signal S1[1]. Similarly, the sampling circuit 110[2] can be selectively turned on according to a clock signal CLK2 to sample the input signal SIN, thereby generating a signal S1[2]. In some embodiments, there is a predetermined phase difference between the clock signal CLK1 and the clock signal CLK2, so that the sampling circuit 110[1] and the sampling circuit 110[2] are turned on at different periods to sequentially sample the input signal SIN. In some embodiments, a circuit parameter of each of the plurality of sampling circuits 110[1] and 110[2] is set according to a corresponding control signal of the plurality of control signals SC[1] and SC[2]. For example, the circuit parameters of the sampling circuit 110[1] can be set via the control signal SC[1], and the circuit parameters of the sampling circuit 110[2] can be set via the control signal SC[2]. In some embodiments, the aforementioned circuit parameters can be at least one of the on-resistance and / or capacitance of a corresponding sampling circuit in the plurality of sampling circuits 110[1] and 110[2]. In some embodiments, the aforementioned circuit parameters can be used to adjust the bandwidth of the corresponding sampling circuit, thereby reducing the bandwidth mismatch between the plurality of sampling circuits 110[1] and 110[2]. The configuration of the plurality of sampling circuits 110[1] and 110[2] will be described later with reference to other drawings.

[0051] Multiple analog-to-digital converter circuits 120[1] and 120[2] are used to generate multiple digital codes D1[1] and D1[2] according to multiple signals S1[1] and S1[2]. In detail, the analog-to-digital converter circuit 120[1] can convert the signal S1[1] into the digital code D1[1], and the analog-to-digital converter circuit 120[2] can convert the signal S1[2] into the digital code D1[2]. Each of the multiple analog-to-digital converter circuits 120[1] and 120[2] can be, but not limited to, a flash analog-to-digital converter circuit, a successive approximation register analog-to-digital converter circuit, a pipeline analog-to-digital converter circuit, etc., but the present disclosure is not limited thereto. Various types of analog-to-digital converter circuits are all within the scope of the present disclosure.

[0052] The output circuit 130 is coupled to the plurality of analog-to-digital converter circuits 120[1] and 120[2] to receive the plurality of digital codes D1[1] and D1[2]. The output circuit 130 may output the plurality of digital codes D1[1] and D1[2] as a digital code D2. In some embodiments, the output circuit 130 may be a parallel-to-serial converter circuit that may convert parallel data (e.g., the plurality of digital codes D1[1] and D1[2]) into serial data (e.g., the digital code D2). In some embodiments, the output circuit 130 may be a multiplexer circuit.

[0053] The calibration circuit 140 is used to output a plurality of control signals SC[1] and SC[2], and adjust the plurality of control signals SC[1] and SC[2] according to the digital code D2. For example, during an initial period, the calibration circuit 140 may first output a plurality of control signals SC[1] and SC[2] having a first set of values ​​to set circuit parameters in the plurality of sampling circuits 110[1] and 110[2]. Under this condition, the calibration circuit 140 may obtain a digital code D2 corresponding to the first set of values, and analyze a performance indicator of the digital code D2 accordingly. Then, the calibration circuit 140 may adjust the plurality of control signals SC[1] and SC[2] from having the first set of values ​​to having a second set of values, so as to adjust the circuit parameters in the plurality of sampling circuits 110[1] and 110[2]. Under this condition, the calibration circuit 140 may obtain a digital code D2 corresponding to the second set of values, and analyze a performance indicator of the digital code D2 accordingly. In this way, the calibration circuit 140 can determine whether to use the plurality of control signals SC[1] and SC[2] having the first set of values ​​or the plurality of control signals SC[1] and SC[2] having the second set of values ​​according to the aforementioned plurality of performance indicators. Figure 2 illustrate.

[0054] In some embodiments, the calibration circuit 140 may be a signal processing circuit with computing capability, which may be used to perform Figure 2 In some embodiments, the calibration circuit 140 may include one or more storage circuits (such as, but not limited to, registers) that can be used to temporarily store the aforementioned performance indicator, the first set of values, and the second set of values.

[0055] It should be understood that Figure 1 The number of circuits shown is for example only and the present disclosure is not limited thereto. In different embodiments, the time-interleaved analog-to-digital converter 100 may include more sampling circuits and more analog-to-digital converters. Figure 1 The present invention is limited to the embodiments of the present invention.

[0056] Figure 2 According to some embodiments of the present disclosure Figure 1Flowchart of multiple operations performed by the calibration circuit 140. In operation S210, multiple control signals SC[1] and SC[2] having a first set of values ​​are output. In operation S220, a first performance indicator is determined according to a digital code D2 corresponding to the first set of values.

[0057] For example, during the initial period, the calibration circuit 140 may first output a plurality of control signals SC[1] and SC[2] having a first set of values ​​(which may be a set of preset values) to set the circuit parameters in the plurality of sampling circuits 110[1] and 110[2] to a preset state. During the initial period, the calibration circuit 140 may also switch the input signal SIN to a test signal. Under this condition, during the initial period, the calibration circuit 140 may obtain a digital code D2 corresponding to the first set of values, and perform performance analysis based on the digital code D2 to obtain a first performance indicator corresponding to the first set of values. In some embodiments, the aforementioned performance indicator includes at least one of effective number of bits (ENOB), spurious free dynamic range (SFDR), or signal to noise ratio (SNR). The higher the value of the aforementioned performance indicator, the higher the resolution of the digital code D2. The aforementioned multiple performance indicators are well known to those skilled in the art, and therefore will not be further described in detail herein. The various performance indicators provided above are only for example, and the present disclosure is not limited thereto. Various performance indicators that can indicate the resolution of the digital code D2 or the performance of the time-interleaved analog-to-digital converter 100 are all within the scope of the present disclosure.

[0058] In operation S230, a plurality of control signals SC[1] and SC[2] are adjusted from having a first set of values ​​to having a second set of values. In operation S240, a second performance indicator is determined according to a digital code D2 corresponding to the second set of values. In operation S250, operations S230 and S240 are repeatedly performed to obtain a plurality of performance indicators corresponding to different sets of values. In operation S260, an optimal performance indicator is determined according to the plurality of performance indicators previously obtained. In operation S270, a plurality of control signals SC[1] and SC[2] having a set of values ​​corresponding to the optimal performance indicator are selected.

[0059] For example, after obtaining the first performance indicator, the calibration circuit 140 may adjust the plurality of control signals SC[1] and SC[2] from having a first set of values ​​to having a second set of values ​​(which is different from the first set of values). In this way, the circuit parameters of the plurality of sampling circuits 110[1] and 110[2] will be changed, so that the calibration circuit 140 can obtain a different digital code D2. The calibration circuit 140 can analyze the digital code D2 to obtain a corresponding second performance indicator. The calibration circuit 140 can further adjust the plurality of control signals SC[1] and SC[2] from having a second set of values ​​to having a third set of values ​​(which is different from the first set of values ​​and the second set of values), so that the calibration circuit 140 can obtain a corresponding third performance indicator according to the digital code D2. Similarly, the calibration circuit 140 can obtain a plurality of performance indicators corresponding to different sets of values ​​by sequentially outputting all value combinations of the plurality of control signals SC[1] and SC[2]. The calibration circuit 140 can store all previously obtained performance indicators, and can determine a best performance indicator among the performance indicators based on the performance indicators, and select a set of values ​​corresponding to the best performance indicator from the sets of values. In this way, the calibration circuit 140 can output a plurality of control signals SC[1] and SC[2] having the set of values ​​corresponding to the best performance indicator. For example, if the calibration circuit 140 determines that the performance indicator having the highest value or corresponding to the best performance among the plurality of performance indicators is the aforementioned second performance indicator, the calibration circuit 140 can select to output a plurality of control signals SC[1] and SC[2] having the second set of values ​​(which corresponds to the second performance indicator), thereby adjusting the circuit parameters of the plurality of sampling circuits 110[1] and 110[2] to improve the circuit performance.

[0060] Through the above configuration, the calibration circuit 140 can use the above multiple operations to calibrate the circuit parameters of the multiple sampling circuits 110[1] and 110[2], thereby reducing the bandwidth mismatch between the multiple sampling circuits 110[1] and 110[2] caused by non-ideal factors (such as, but not limited to, process variations).

[0061] In some related arts, the time-interleaved analog-to-digital converter does not correct the bandwidth mismatch between multiple channels. Thus, in these arts, the compensation parameters used for the gain correction and / or time skew correction of the time-interleaved analog-to-digital converter may be related to the frequency of the input signal. In order to make the aforementioned compensation parameters more accurate, a more complex mechanism (such as an oversampling system) is required in these arts to monitor the frequency of the input signal so as to use the corresponding compensation parameters according to the current frequency of the input signal. In this way, the overall circuit cost will be greatly increased. Compared with the above-mentioned related arts, in some embodiments of the present disclosure, through the correction circuit 140, the bandwidth mismatch between multiple channels can be reduced, so that the dependence between the aforementioned compensation parameters and the frequency of the input signal SIN can be reduced, so that the time-interleaved analog-to-digital converter can be subjected to gain correction and / or time skew correction without using the aforementioned more complex mechanism.

[0062] In some embodiments, the plurality of sampling circuits 110 [ 1 ] and 110 [ 2 ] have the same circuit configuration. For ease of description, the sampling circuit 110 [ 1 ] is used as an example to illustrate several implementations, but the present disclosure is not limited thereto.

[0063] Figure 3A According to some embodiments of the present disclosure Figure 1 Schematic diagram of sampling circuit 110[1] in FIG. Sampling circuit 110[1] includes transistor 310, capacitor C1, and digital-to-analog converter circuit 320. A first end (e.g., drain) of transistor 310 receives input signal SIN, a second end (e.g., source) of transistor 310 is coupled to a first end of capacitor C1, a control end (e.g., gate) of transistor 310 receives clock signal CLK1, and a third end (e.g., base) of transistor 310 receives bias voltage VB from digital-to-analog converter circuit 320. A second end of capacitor C1 is coupled to ground. Transistor 310 can be selectively turned on according to clock signal CLK1 to transmit input signal SIN to capacitor C1, thereby sampling input signal SIN. Capacitor C1 can output the sampled input signal SIN as signal S1[1].

[0064] The digital-to-analog converter circuit 320 may generate a bias voltage VB according to a corresponding control signal SC[1]. In some embodiments, the digital-to-analog converter circuit 320 may be, but is not limited to, a resistive digital-to-analog converter, which may be used to divide the supply voltage VDD according to the control signal SC[1] to generate the bias voltage VB. For example, the digital-to-analog converter circuit 320 may include a plurality of resistors R and a plurality of switches SW, wherein the plurality of resistors R are coupled in series, and the plurality of switches SW are coupled between the resistors R and the transistor 310 and selectively turned on according to the control signal SC[1] to generate the bias voltage VB. In other words, the plurality of switches SW may be used to set the connection relationship between the plurality of resistors R, thereby adjusting the voltage division ratio of the supply voltage VDD to generate different bias voltages VB. The above-mentioned configuration method of the digital-to-analog converter circuit 320 is merely an example, and the present disclosure is not limited thereto. Various digital-to-analog converter circuits 320 that may be used to generate the bias voltage VB are all within the scope of the present disclosure.

[0065] In this example, the aforementioned circuit parameter may be the equivalent on-resistance of the sampling circuit 110[1]. For example, if the bias voltage VB is higher, the critical voltage of the transistor 310 will be lower, so that the on-resistance of the transistor 310 will be lower. In this way, the equivalent on-resistance of the sampling circuit 110[1] can be lowered. Alternatively, if the bias voltage VB is lower, the critical voltage of the transistor 310 will be higher, so that the on-resistance of the transistor 310 will be higher. In this way, the equivalent on-resistance of the sampling circuit 110[1] can be higher. In this example, the transistor 310 is an N-type transistor, but the present disclosure is not limited to this. In other embodiments, the transistor 310 may also be a P-type transistor. When the transistor 310 is a P-type transistor, if the bias voltage VB is lower, the critical voltage of the transistor 310 will be lower, so that the on-resistance of the transistor 310 will be lower; conversely, if the bias voltage VB is higher, the critical voltage of the transistor 310 will be higher, so that the on-resistance of the transistor 310 will be higher.

[0066] Through the above configuration, by adjusting the control signal SC[1], the sampling circuit 110[1] can present different conduction resistance values, thereby adjusting the bandwidth of the sampling circuit 110[1]. Figure 2 Through the multiple operations, the calibration circuit 140 can find out the multiple control signals SC[1] and SC[2] that can make the time-interleaved analog-to-digital converter 100 have the best performance.

[0067] Figure 3B According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit 110[1]. Figure 3AIn this example, the sampling circuit 110[1] further includes a bootstrap circuit 330. The bootstrap circuit 330 can generate a switching signal SS1 to turn on the transistor 310 according to the input signal SIN and the clock signal CLK1. For example, the bootstrap circuit 330 can track the input signal SIN to generate the switching signal SS1, wherein the switching signal SS1 and the input signal SIN are fixedly different by a preset voltage difference, so that the transistor 310 can have a more stable on-resistance during the on-time, thereby improving the performance of the sampling circuit 110[1]. In some embodiments, the bootstrap circuit 330 can be implemented via a plurality of transistors and at least one capacitor (not shown), wherein the at least one capacitor is used to generate the aforementioned preset voltage difference.

[0068] Figure 4A According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit 110[1] in FIG. In this example, the sampling circuit 110[1] includes a transistor 310, a capacitor C1, a digital-to-analog converter circuit 320, and a bootstrap circuit 410. Figure 3B ,exist Figure 4A In the embodiment of the present invention, the digital-to-analog converter circuit 320 provides a bias voltage VB to the bootstrap circuit 410, and the bootstrap circuit 410 can be used to generate a switching signal SS2 according to the clock signal CLK1, the bias voltage VB and the predetermined voltage VDC to turn on the transistor 310. The bootstrap circuit 410 can track the predetermined voltage VDC to generate the switching signal SS2. When the transistor 310 is turned on, the switching signal SS2 can be the sum of the bias voltage VB and the predetermined voltage VDC. In this way, if the bias voltage VB is higher, the enable level of the switching signal SS2 is higher, so that the on-resistance value of the transistor 310 is higher. Alternatively, if the bias voltage VB is lower, the enable level of the switching signal SS2 is lower, so that the on-resistance value of the transistor 310 is lower.

[0069] Figure 4B According to some embodiments of the present disclosure Figure 4ASchematic diagram of a bootstrap circuit 410 in . The bootstrap circuit 410 includes a plurality of transistors M1 to M4 and a capacitor C2. The first end (e.g., source) of the transistor M1 receives a voltage VL, the second end (e.g., drain) of the transistor M1 is coupled to the first end of the capacitor C2, and the control end (e.g., gate) of the transistor M1 receives a clock signal CLK1. The first end of the transistor M2 receives a bias voltage VB, the second end of the transistor M2 is coupled to the second end of the capacitor C2, and the control end of the transistor M2 receives the clock signal CLK1. The first end of the transistor M3 is coupled to the first end of the capacitor C2, the second end of the transistor M3 receives a predetermined voltage VDC, and the control end of the transistor M3 receives the clock signal CLK1. The first end of the transistor M4 is coupled to the second end of the capacitor C2, the second end of the transistor M4 outputs a switching signal SS2, and the control end of the transistor M4 receives the clock signal CLK1.

[0070] A plurality of transistors M1 and M2 are P-type transistors, and a plurality of transistors M3 and M4 are N-type transistors. A plurality of transistors M1 to M4 can be selectively turned on according to a clock signal CLK1. In some embodiments, the voltage VL can be, but is not limited to, a ground voltage. When the clock signal CLK1 has a low level, a plurality of transistors M1 and M2 are turned on, and a plurality of transistors M3 and M4 are not turned on. In this way, the transistor M1 can transmit the voltage VL to the first end of the capacitor C2, and the transistor M2 can transmit the bias voltage VB to the second end of the capacitor C2. Under this condition, the capacitor C2 is charged by the bias voltage VB, so that the voltage across the two ends of the capacitor C2 is approximately the bias voltage VB. Then, when the clock signal CLK1 has a high level, a plurality of transistors M1 and M2 are not turned on, and a plurality of transistors M3 and M4 are turned on. In this way, the transistor M3 can transmit a predetermined voltage VDC to the first end of the capacitor C2, and the transistor M4 can output the voltage on the second end of the capacitor C2 as a switching signal SS2. Under this condition, the capacitor C2 is charged by the predetermined voltage VDC instead, so that the voltage across the capacitor C2 becomes the sum of the predetermined voltage VDC and the bias voltage VB, and accordingly outputs a switching signal SS2 having a level equal to the voltage across the capacitor C2 to turn on the transistor 310 .

[0071] Figure 5A According to some embodiments of the present disclosure Figure 1 Schematic diagram of the sampling circuit 110[1] in FIG. 1 . In this example, the aforementioned circuit parameter may be the equivalent capacitance value of the sampling circuit 110[1]. The sampling circuit 110[1] includes a transistor 310, a capacitor C1, a buffer circuit 510, and a variable capacitance circuit 520. Figure 3AIn this example, transistor 310 is turned on according to clock signal CLK1 to sample input signal SIN, and capacitor C1 can output the sampled input signal SIN as signal S2. Buffer circuit 510 is coupled to capacitor C1 to receive signal S2, and generates signal S1[1] according to signal S2. In some embodiments, buffer circuit 510 can be, but is not limited to, a source follower, which can be used to improve the driving capability of sampling circuit 110[1] to drive Figure 1 The analog-to-digital converter circuit 120[1] in the embodiment of the present invention. The variable capacitor circuit 520 is coupled to the output terminal of the buffer circuit 510 for outputting the signal S1[1], and the capacitance of the variable capacitor circuit 520 is adjusted according to the control signal SC[1], thereby adjusting the equivalent capacitance of the sampling circuit 110[1]. In some embodiments, the sampling circuit 110[1] may not be provided with the buffer circuit 510, and the variable capacitor circuit 520 may be directly coupled to the output terminal of the transistor 310 (for example, an end of the transistor 310 coupled to the capacitor C1). Under this condition, the transistor 310 may be turned on according to the clock signal CLK1 to sample the input signal SIN, and generate the signal S1[1] accordingly.

[0072] Figure 5B According to some embodiments of the present disclosure Figure 1 Schematic diagram of a variable capacitance circuit 520 in FIG. The variable capacitance circuit 520 includes a capacitor C3 and a capacitor array CF. The capacitor C3 is coupled to Figure 5A The output terminal of the buffer circuit 510 is connected to the ground. The capacitor array CF is coupled in parallel to the capacitor C3, and the capacitance of the capacitor array CF is set according to the control signal SC[1]. For example, the capacitor array CF may include a capacitor C4 and a switch 521. In other embodiments, the capacitor array CF may include multiple capacitors and multiple switches. Figure 5B In the circuit, capacitor C4 is coupled to Figure 5A The output terminal of the buffer circuit 510 is connected to the switch 521, and the other end of the switch 521 is coupled to the ground. The switch 521 can be selectively turned on according to the control signal SC[1]. When the switch 521 is turned on, the capacitor C4 can be connected in parallel to the capacitor C3, thereby increasing the capacitance of the capacitor array CF (or the variable capacitor circuit 520). Alternatively, when the switch 521 is not turned on, the capacitor C4 may not be connected to the capacitor C3, thereby reducing the capacitance of the capacitor array CF (or the variable capacitor circuit 520).

[0073] The above-mentioned multiple configuration methods for the sampling circuit 110[1] are used for example only, and the present disclosure is not limited thereto. In other embodiments, the above-mentioned multiple configuration methods may also be implemented together. For example, Figure 5A The sampling circuit 110[1] in FIG. Figure 3A , Figure 3B and / or Figure 4AA digital-to-analog converter circuit 320, a bootstrap circuit 330 and / or a bootstrap circuit 410 are added, etc. In addition, the number of components presented in the above drawings is only an example, and the present disclosure is not limited thereto.

[0074] Figure 6 A flow chart of a signal conversion method 600 is drawn according to some embodiments of the present disclosure. In some embodiments, the signal conversion method 600 may be, but is not limited to, Figure 1 The time-interleaved analog-to-digital converter 100 is executed.

[0075] In operation S610, an input signal is sequentially sampled through a plurality of sampling circuits to generate a plurality of first signals, wherein a circuit parameter of each of the sampling circuits is set according to a corresponding control signal among a plurality of control signals. In operation S620, a plurality of first digital codes are generated according to the first signals. In operation S630, a second digital code is output according to the first digital codes. In operation S640, the control signals are adjusted according to the second digital code.

[0076] The operations in the signal conversion method 600 may refer to the descriptions of the aforementioned embodiments, and thus will not be repeated here. Figure 2 and Figure 6 The multiple operations in the example are only examples and are not limited to being executed in the order in the example. Without violating the operation mode and scope of each embodiment of the present disclosure, Figure 2 and Figure 6 The various operations in can be appropriately added, replaced, omitted or performed in a different order. Figure 2 and Figure 6 The various operations in may be performed concurrently or with partial concurrence.

[0077] In summary, the time-interleaved analog-to-digital converter and signal conversion method provided in some embodiments of the present disclosure can utilize a simple correction mechanism to modify the circuit parameters of the sampling circuit, thereby correcting the bandwidth mismatch between multiple channels in the time-interleaved analog-to-digital converter.

[0078] Although the embodiments of the present disclosure are described above, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make changes to the technical features of the present disclosure based on the explicit or implicit contents of the present disclosure. All these changes may fall within the scope of patent protection sought by the present disclosure. In other words, the scope of patent protection of the present disclosure shall be based on what is defined in the claims of this specification.

Claims

1. A time-interleaved analog-to-digital converter, comprising: A plurality of sampling circuits, for sequentially sampling an input signal to generate a plurality of first signals, wherein a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal among a plurality of control signals; A plurality of analog-to-digital converter circuits, configured to generate a plurality of first digital codes according to the plurality of first signals; an output circuit, configured to output a second digital code according to the plurality of first digital codes; as well as A calibration circuit is used to generate the plurality of control signals and adjust the plurality of control signals according to the second digital code.

2. The time-interleaved analog-to-digital converter of claim 1 , wherein the correction circuit is configured to output the plurality of control signals having a first set of values, determine a first performance indicator according to the second digital code corresponding to the first set of values, adjust the plurality of control signals from having the first set of values ​​to having a second set of values, determine a second performance indicator according to the second digital code corresponding to the second set of values, and determine the plurality of control signals according to the first performance indicator and the second performance indicator. 3 . The time-interleaved analog-to-digital converter of claim 2 , wherein each of the first performance indicator and the second performance indicator comprises at least one of an effective number of bits, a spurious-free dynamic range, or a signal-to-noise ratio. 4 . The time-interleaved analog-to-digital converter of claim 2 , wherein the circuit parameter comprises at least one of an on-resistance or a capacitance associated with a corresponding one of the plurality of sampling circuits.

5. The time-interleaved analog-to-digital converter of claim 1 , wherein each of the plurality of sampling circuits comprises: a transistor for selectively conducting to sample the input signal; and A digital-to-analog converter circuit is used to generate a bias voltage to a base of the transistor according to the corresponding control signal.

6. The time-interleaved analog-to-digital converter of claim 5, wherein each of the plurality of sampling circuits further comprises: A bootstrap circuit is used to turn on the transistor according to the input signal and a clock signal.

7. The time-interleaved analog-to-digital converter of claim 1 , wherein each of the plurality of sampling circuits comprises: a first capacitor; a transistor, configured to selectively conduct according to a clock signal to transmit the input signal to the first capacitor to generate a corresponding first signal among the plurality of first signals; and A variable capacitance circuit is coupled to an output terminal of the transistor and is used to adjust the capacitance of the variable capacitance circuit according to the corresponding control signal.

8. The time-interleaved analog-to-digital converter of claim 7, wherein the variable capacitance circuit comprises: a second capacitor coupled between the output terminal and ground; and A capacitor array is coupled in parallel to the second capacitor, wherein the capacitance of the capacitor array is set according to the corresponding control signal.

9. The time-interleaved analog-to-digital converter of claim 1 , wherein each of the plurality of sampling circuits comprises: a first transistor, configured to selectively conduct to sample the input signal; a digital-to-analog converter circuit for generating a bias voltage according to the corresponding control signal; and A bootstrap circuit is used to turn on the first transistor according to a clock signal, the bias voltage and a predetermined voltage.

10. A signal conversion method, comprising: sequentially sampling an input signal via a plurality of sampling circuits to generate a plurality of first signals, wherein a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal among a plurality of control signals; generating a plurality of first digital codes according to the plurality of first signals; Output a second digital code according to the plurality of first digital codes; as well as The plurality of control signals are adjusted according to the second digital code.

Images