A multi-port radio frequency transceiver switch synthesis module

Abstract

The present invention discloses a multi-port radio frequency transceiver switch synthesis module, belonging to the field of communication technology. It includes a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, transfer switches TRS1 to TRS12, a power interface POW, a transmit signal port, a transceiver selection control interface, and a channel selection control interface. It solves the technical problems of transceiver switching and synthesis of multi-channel signals, integrates the transceiver conversion function, synthesis network, switch components, and signals of the dual-port receivable branch, which can be single-channel signals or two-channel synthesized signals. It can reduce the use of instruments such as signal sources and spectrum analyzers, save test costs, improve test efficiency, has good expansion ability, can be expanded to more ports, can significantly shorten the test time, and realizes the collaborative control of multiple devices through hardware interfaces such as TTL signals and RS422.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and particularly relates to a multi-port radio frequency transceiver switch synthesis module. Background Art

[0002] In modern wireless communication systems, the transmission and reception of radio frequency channels usually rely on separate signal sources and spectrum analyzers. Especially when performing transceiver tests on multiple channels, a large number of instrument devices (such as signal sources and spectrum analyzers) are required. This demand increases costs and reduces test efficiency.

[0003] To improve the flexibility and economy of testing, a switch matrix is introduced into the test system. Traditional switch matrices are usually unidirectional and can only control the transmission of signals from the input port to multiple output ports, and cannot meet the complex test requirements of transceiver time-sharing switching and multi-channel signal synthesis. There is a lack of a signal synthesis, transceiver switching, and efficient signal transmission processing mechanism for multi-port radio frequency signals in the prior art. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-port radio frequency transceiver switch synthesis module, which solves the technical problems of transceiver switching and synthesis of multi-channel signals.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A multi-port radio frequency transceiver switch synthesis module includes a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a transfer switch TRS1, a transfer switch TRS2, a transfer switch TRS3, a transfer switch TRS4, a transfer switch TRS5, a transfer switch TRS6, a transfer switch TRS7, a transfer switch TRS8, a transfer switch TRS9, a transfer switch TRS10, a transfer switch TRS11, a transfer switch TRS12, a power interface POW, a transmit signal port, a transceiver selection control interface, and a channel selection control interface. The transfer switches TRS1 to TRS6 are respectively connected to 6 signal receiving ports of the switch matrix SW2, namely, the A1 end to the A6 end, and the transfer switches TRS7 to TRS12 are respectively connected to 6 signal receiving ports of the switch matrix SW3, namely, the A7 end to the A12 end;

[0007] One split signal output end of the switch matrix SW2 is connected to the combiner CMB1, and another split signal output end is connected to one signal input end of the switch matrix SW1;

[0008] One split signal output end of the switch matrix SW3 is connected to the combiner CMB2, and another split signal output end is connected to another signal input end of the switch matrix SW1;

[0009] The two signal output terminals of the switch matrix SW1 are respectively connected to the combiner CMB1 and the combiner CMB2;

[0010] The changeover switches TRS1 to TRS12 are all connected to the transmit signal port, i.e., the JL_in terminal, and the changeover switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal;

[0011] The output terminal of the combiner CMB1 is connected to the first signal output terminal, i.e., the CH_A terminal, and the output terminal of the combiner CMB2 is connected to the second signal output port, i.e., the CH_B terminal;

[0012] The power interface POW is connected to an external power supply and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the changeover switches TRS1 to TRS12.

[0013] Preferably, the TX terminals of the changeover switch TRS1 to the TX terminals of the changeover switch TRS12 are all connected to the JL_in terminal;

[0014] The RX terminals of the changeover switch TRS1 to the RX terminals of the changeover switch TRS6 are respectively connected to the A1 terminal to the A6 terminal of the switch matrix SW2;

[0015] The RX terminals of the changeover switch TRS7 to the RX terminals of the changeover switch TRS12 are respectively connected to the A7 terminal to the A12 terminal of the switch matrix SW3;

[0016] The ANT terminals of the changeover switch TRS1 to the ANT terminals of the changeover switch TRS12 are respectively connected to the CH1 terminal to the CH12 terminal.

[0017] Preferably, the two signal input terminals of the switch matrix SW1 are respectively the 2 terminal and the 3 terminal of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are respectively the 1 terminal and the 4 terminal of the switch matrix SW1;

[0018] The two split signal output terminals of the switch matrix SW2 are respectively the FL_A terminal and the FL_B terminal of the switch matrix SW2. The FL_A terminal is connected to the IN1 terminal of the combiner CMB1, and the FL_B terminal is connected to the 2 terminal of the switch matrix SW1;

[0019] The two split signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2. The FL_C terminal is connected to the 3 terminal of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2;

[0020] One end of the switch matrix SW1 is connected to the IN2 end of the combiner CMB1, and the 4th end is connected to the IN1 end of the combiner CMB2.

[0021] Preferably, the switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3, and SW1_4. The COM pin of switch SW1_1 is connected to the 2nd end, the P1 pin is connected to the P1 pin of switch SW1_4, and the P2 pin is connected to the P1 pin of switch SW1_3;

[0022] The COM pin of switch SW1_2 is connected to the 3rd end, the P1 pin is connected to the P2 pin of switch SW1_4, and the P2 pin is connected to the P2 pin of switch SW1_3;

[0023] The COM pin of switch SW1_3 is connected to the 4th end;

[0024] The COM pin of switch SW1_4 is connected to the 1st end.

[0025] Preferably, the switches SW1_1, SW1_2, SW1_3, and SW1_4 are all single-pole double-throw switches.

[0026] Preferably, the switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9, and S10. The COM pin of switch S9 is connected to the FL_A end, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8;

[0027] The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B end;

[0028] The P2 pin, P3 pin, and P4 pin of switch S7 are respectively connected to the P3 pin of switch S1, the P3 pin of switch S2, and the P3 pin of switch S3;

[0029] The P1 pin, P2 pin, and P3 pin of switch S8 are respectively connected to the P2 pin of switch S4, the P2 pin of switch S5, and the P2 pin of switch S6;

[0030] The COM pin of switch S1 is connected to the A1 end, the COM pin of switch S2 is connected to the A2 end, the COM pin of switch S3 is connected to the A3 end, the COM pin of switch S4 is connected to the A4 end, the COM pin of switch S5 is connected to the A5 end, and the COM pin of switch S6 is connected to the A6 end;

[0031] The P1 pin of switch S7, the P4 pin of switch S8, the P2 and P1 pins of switch S1, the P2 and P1 pins of switch S2, the P2 and P1 pins of switch S3, the P4 and P3 pins of switch S4, the P4 and P3 pins of switch S5, and the P4 and P3 pins of switch S6 are all connected to an external load;

[0032] The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20. The COM pin of switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of switch S11, the P2 pin is connected to the P4 pin of switch S12, the P3 pin is connected to the P4 pin of switch S13, and the P4 pin is connected to the COM pin of switch S18;

[0033] The P1 pin of switch S20 is connected to the COM pin of switch S17, the P2 pin is connected to the P1 pin of switch S14, the P3 pin is connected to the P1 pin of switch S15, the P4 pin is connected to the P1 pin of switch S16, and the COM pin is connected to the FL_D terminal;

[0034] The P2, P3, and P4 pins of switch S17 are respectively connected to the P3 pin of switch S11, the P3 pin of switch S12, and the P3 pin of switch S13;

[0035] The P1, P2, and P3 pins of switch S18 are respectively connected to the P2 pin of switch S14, the P2 pin of switch S15, and the P2 pin of switch S16;

[0036] The COM pin of switch S11 is connected to terminal A7, the COM pin of switch S12 is connected to terminal A8, the COM pin of switch S13 is connected to terminal A9, the COM pin of switch S14 is connected to terminal A10, the COM pin of switch S15 is connected to terminal A11, and the COM pin of switch S16 is connected to terminal A12;

[0037] The P1 pin of switch S17, the P4 pin of switch S18, the P2 and P1 pins of switch S11, the P2 and P1 pins of switch S2, the P2 and P1 pins of switch S13, the P4 and P3 pins of switch S14, the P4 and P3 pins of switch S15, and the P4 and P3 pins of switch S16 are all connected to an external load.

[0038] Preferably, switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20 are all single - pole four - throw switches.

[0039] A multi-port RF transceiver switch synthesis module according to the present invention solves the technical problems of transceiver switching and synthesis of multi-channel signals. It integrates a transceiver conversion function, a synthesis network, and a switch component on the basis of a traditional unidirectional matrix switch. The dual-port can receive signals of a branch, which can be a single-channel signal or a two-channel synthesized signal, so as to meet the test requirements of different scenarios, reduce the use of instruments such as signal sources and spectrum analyzers, save test costs, improve test efficiency, and have good expansion capabilities. By adding switch modules and channels, it can be expanded to more ports to meet more complex test requirements, has the potential for further optimization and simplification, can significantly shorten the test time, and realizes the collaborative control of multiple devices through hardware interfaces such as TTL signals and RS422. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is the schematic block diagram of the principle of the present invention;

[0041] Figure 2 is the schematic block diagram of the switch matrix SW1 of the present invention;

[0042] Figure 3 is the schematic block diagram of the switch matrix SW2 of the present invention;

[0043] Figure 4 is the schematic block diagram of the switch matrix SW3 of the present invention;

[0044] Figure 5 is the single-channel output state combination diagram of the switch matrix SW2 of the present invention;

[0045] Figure 6 is the two-channel output state combination diagram of the switch matrix SW2 of the present invention;

[0046] Figure 7 is the schematic diagram in which the main path A has 30 combinations and the main path B has 30 combinations of the present invention;

[0047] Figure 8 is the schematic diagram in which the main path A has 36 combinations and the state of the main path B is adjusted according to the selection of the main path A of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0048] Such as Figures 1-8A multi-port radio frequency transceiver switch synthesis module as shown, including a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a transfer switch TRS1, a transfer switch TRS2, a transfer switch TRS3, a transfer switch TRS4, a transfer switch TRS5, a transfer switch TRS6, a transfer switch TRS7, a transfer switch TRS8, a transfer switch TRS9, a transfer switch TRS10, a transfer switch TRS11, a transfer switch TRS12, a power interface POW, a transmit signal port, a transceiver selection control interface, and a channel selection control interface.

[0049] The transceiver selection control interface is used to control the transceiver state of the module. This interface should be connected in parallel with the internal control circuit of the module and is responsible for switching between the transmit and receive modes. It switches to the transmit state at a high level and to the receive state at a low level.

[0050] The channel selection control interface is responsible for selecting the specific signal transmission path and determining which branch signals are combined into the main path A (output from the CH_A terminal) or the main path B (output from the CH_B terminal) in the receive state. It should be connected in parallel with each SP2T / SP4T switch, and controls the switching state of each switch through the change of high and low levels.

[0051] The transfer switch TRS1 to the transfer switch TRS6 are respectively connected to 6 signal receiving ports of the switch matrix SW2, namely the A1 terminal to the A6 terminal, and the transfer switch TRS7 to the transfer switch TRS12 are respectively connected to 6 signal receiving ports of the switch matrix SW3, namely the A7 terminal to the A12 terminal;

[0052] The TX terminals of the transfer switch TRS1 to the TX terminals of the transfer switch TRS12 are all connected to the JL_in terminal;

[0053] The RX terminals of the transfer switch TRS1 to the RX terminals of the transfer switch TRS6 are respectively connected to the A1 terminal to the A6 terminal of the switch matrix SW2;

[0054] The RX terminals of the transfer switch TRS7 to the RX terminals of the transfer switch TRS12 are respectively connected to the A7 terminal to the A12 terminal of the switch matrix SW3;

[0055] The ANT terminals of the transfer switch TRS1 to the ANT terminals of the transfer switch TRS12 are respectively connected to the CH1 terminal to the CH12 terminal.

[0056] One shunt signal output terminal of the switch matrix SW2 is connected to the combiner CMB1, and the other shunt signal output terminal is connected to one signal input terminal of the switch matrix SW1;

[0057] One shunt signal output terminal of the switch matrix SW3 is connected to the combiner CMB2, and the other shunt signal output terminal is connected to another signal input terminal of the switch matrix SW1;

[0058] The two signal output terminals of the switch matrix SW1 are respectively connected to the combiner CMB1 and the combiner CMB2;

[0059] The two signal input terminals of the switch matrix SW1 are respectively the 2 terminal and the 3 terminal of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are respectively the 1 terminal and the 4 terminal of the switch matrix SW1;

[0060] The two shunt signal output terminals of the switch matrix SW2 are respectively the FL_A terminal and the FL_B terminal of the switch matrix SW2. The FL_A terminal is connected to the IN1 terminal of the combiner CMB1, and the FL_B terminal is connected to the 2 terminal of the switch matrix SW1;

[0061] The switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9, and S10. The COM pin of switch S9 is connected to the FL_A terminal, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8;

[0062] The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B terminal;

[0063] The P2 pin, P3 pin, and P4 pin of switch S7 are respectively connected to the P3 pin of switch S1, the P3 pin of switch S2, and the P3 pin of switch S3;

[0064] The P1 pin, P2 pin, and P3 pin of switch S8 are respectively connected to the P2 pin of switch S4, the P2 pin of switch S5, and the P2 pin of switch S6;

[0065] The COM pin of switch S1 is connected to the A1 terminal, the COM pin of switch S2 is connected to the A2 terminal, the COM pin of switch S3 is connected to the A3 terminal, the COM pin of switch S4 is connected to the A4 terminal, the COM pin of switch S5 is connected to the A5 terminal, and the COM pin of switch S6 is connected to the A6 terminal;

[0066] The P1 pin of switch S7, the P4 pin of switch S8, the P2 pin and P1 pin of switch S1, the P2 pin and P1 pin of switch S2, the P2 pin and P1 pin of switch S3, the P4 pin and P3 pin of switch S4, the P4 pin and P3 pin of switch S5, and the P4 pin and P3 pin of switch S6 are all connected to external loads.

[0067] The two shunt signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2. The FL_C terminal is connected to terminal 3 of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2;

[0068] The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19, and S20. The COM pin of switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of switch S11, the P2 pin is connected to the P4 pin of switch S12, the P3 is connected to the P4 pin of switch S13, and the P4 pin is connected to the COM pin of switch S18;

[0069] The P1 pin of switch S20 is connected to the COM pin of switch S17, the P2 pin is connected to the P1 pin of switch S14, the P3 pin is connected to the P1 pin of switch S15, the P4 pin is connected to the P1 pin of switch S16, and the COM pin is connected to the FL_D terminal;

[0070] The P2 pin, P3 pin, and P4 pin of switch S17 are respectively connected to the P3 pin of switch S11, the P3 pin of switch S12, and the P3 pin of switch S13;

[0071] The P1 pin, P2 pin, and P3 pin of switch S18 are respectively connected to the P2 pin of switch S14, the P2 pin of switch S15, and the P2 pin of switch S16;

[0072] The COM pin of switch S11 is connected to terminal A7, the COM pin of switch S12 is connected to terminal A8, the COM pin of switch S13 is connected to terminal A9, the COM pin of switch S14 is connected to terminal A10, the COM pin of switch S15 is connected to terminal A11, and the COM pin of switch S16 is connected to terminal A12;

[0073] The P1 pin of switch S17, the P4 pin of switch S18, the P2 pin and P1 pin of switch S11, the P2 pin and P1 pin of switch S2, the P2 pin and P1 pin of switch S13, the P4 pin and P3 pin of switch S14, the P4 pin and P3 pin of switch S15, and the P4 pin and P3 pin of switch S16 are all connected to external loads.

[0074] Terminal 1 of the switch matrix SW1 is connected to the IN2 terminal of the combiner CMB1, and terminal 4 is connected to the IN1 terminal of the combiner CMB2.

[0075] The switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3, and SW1_4. The COM pin of switch SW1_1 is connected to the said terminal 2, the P1 pin is connected to the P1 pin of switch SW1_4, and the P2 pin is connected to the P1 pin of switch SW1_3;

[0076] The COM pin of switch SW1_2 is connected to the 3rd terminal, the P1 pin is connected to the P2 pin of switch SW1_4, and the P2 pin is connected to the P2 pin of switch SW1_3;

[0077] The COM pin of switch SW1_3 is connected to the 4th terminal;

[0078] The COM pin of switch SW1_4 is connected to the 1st terminal.

[0079] The switch SW1_1, the switch SW1_2, the switch SW1_3 and the switch SW1_4 are all single-pole double-throw switches.

[0080] The changeover switches TRS1 to TRS12 are all connected to the transmission signal port, i.e., the JL_in terminal, and the changeover switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal;

[0081] The output terminal of the combiner CMB1 is connected to the first signal output terminal, i.e., the CH_A terminal, and the output terminal of the combiner CMB2 is connected to the second signal output port, i.e., the CH_B terminal;

[0082] The power interface POW is connected to an external power supply and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the changeover switches TRS1 to TRS12.

[0083] The switch S1, the switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8, the switch S9, the switch S10, the switch S11, the switch S12, the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18, the switch S19 and the switch S20 are all single-pole four-throw switches.

[0084] The present invention is based on switch matrix technology and realizes the transceiver switching and signal synthesis of radio frequency signals by combining the use of multiple transceiver changeover switches and switch matrices. Specifically, the module includes 12 branches (the CH1 terminal to the CH12 terminal), 2 2-6 switch modules (the switch matrix SW2 and the switch matrix SW3), 1 SP2T switch combination (the switch matrix SW1), 2 combining units (the combiner CMB1 and the combiner CMB2) and multiple transceiver changeover switches (the changeover switches TRS1 to TRS12 are powered).

[0085] The working process principle is as follows:

[0086] Transmission state: When the transceiver selection control interface is at a high level, the excitation signal is input from the transmission signal port and then evenly distributed to 12 branch ports through a power distribution network for transmission. The switch matrix switches the signal path to ensure that each branch can correctly send signals to the device under test (DUT).

[0087] Receiving state: When the transceiver selection control interface is at a low level, the receiving end is enabled. By selecting different signal paths through the channel selection control interface, the received signals from 12 branch ports can be synthesized and output to main path A and main path B. Main path A is synthesized and output by signals A1 and A2, and main path B is synthesized and output by signals B1 and B2. Each combining unit is responsible for combining multiple signals into a single signal for output.

[0088] In this embodiment, combiner CMB1, combiner CMB2, switch matrix SW1, switch matrix SW2, switch matrix SW3, transfer switch TRS1, transfer switch TRS2, transfer switch TRS3, transfer switch TRS4, transfer switch TRS5, transfer switch TRS6, transfer switch TRS7, transfer switch TRS8, transfer switch TRS9, transfer switch TRS10, transfer switch TRS11, transfer switch TRS12, power supply interface POW, transmission signal port, transceiver selection control interface, and channel selection control interface are all arranged on the same PCB board or in the same module.

[0089] In this embodiment, the switch matrix of the multi-port RF transceiver switch synthesis module is controlled by a drive board, and the serial port is connected to the upper computer. The control instructions sent by the upper computer are converted into TTL signals by the drive board to drive each switch. The internal SP4T switch (single-pole four-throw switch) and SP2T switch (single-pole double-throw switch) are responsible for selecting the signal transmission path to achieve the function of dual-channel signal output or single-channel signal output. When dual-channel output is required, the present invention supports selecting two signals from multiple branches and synthesizing them into main path A and main path B, further improving the test efficiency and flexibility.

[0090] In this embodiment, when outputting a single-channel signal, only one of the split A (output from FL_A) or split B (output from FL_B) of switch matrix SW2 has a signal output. The split A or split B signal is one of the branches from branch 1 (input and output from terminal A1) to branch 6 (input and output from terminal A6), a total of 12 cases, such as branch 1 / branch 2, branch 1 / branch 3, branch 1 / branch 4, branch 6 / branch 1, branch 6 / branch 2, branch 6 / branch 3, etc. arranged in combinations. If it is required that split A or split B does not output a signal, the corresponding SP4T can be connected to the load port.

[0091] Similarly, for split C (output from FL_C) or split D (output from FL_D).

[0092] When outputting dual-channel signals, the signals of branch A / branch B are selected from any two of branch 1 to branch 6, with a total of 30 cases.

[0093] Similarly, the circuit principle and function of switch matrix SW3 are the same as those of switch matrix SW2.

[0094] Switch matrix SW1 is composed of 4 SP2T switches (switch SW1_1 to switch SW1_4). Its function is to switch and output the signals of branch B and branch C to terminal 1 and terminal 4 of switch matrix SW1 through the control channel.

[0095] Combiner CMB1 combines the signal of branch A and the signal of terminal 1 of switch matrix SW1 and outputs them to the main path A port. Combiner CMB2 combines the signal of terminal 4 of switch matrix SW1 and the signal of branch D and outputs them to the main path B port.

[0096] In this embodiment, POW is connected to an external 5V power supply. The transceiver selection control interface outputs a 5V TTL signal. The high level enables transmission, and the low level enables reception.

[0097] The channel selection control interface outputs a 5V TTL signal, and its control logic is as follows:

[0098] When the level is high: Any 2 paths are selected from branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6 and combined to the main path A; Any 2 paths are selected from branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12 and combined to the main path B;

[0099] When the level is low: Any 1 path is selected from branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6 and any 1 path is selected from branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12 and combined to the main path A; One path output to the main path A is removed from branch 1, branch 2, branch 3, branch 4, branch 5, and branch 6, and any 1 path is selected from the other 5 paths, and one path output to the main path A is removed from branch 7, branch 8, branch 9, branch 10, branch 11, and branch 12, and any 1 path is selected from the other 5 paths; These two paths are combined to the main path B.

[0100] The working state of the feedback output is normal at high level and faulty at low level.

[0101] During specific use, its working process is as follows:

[0102] When the transceiver conversion control signal is high, the module is in the transmit state. The transmit excitation signal is evenly distributed to 12 branch interfaces and amplified.

[0103] When the transceiver conversion control signal is low, the module is in the receiving state. According to the channel selection control signal, the signals input from 12 branch interfaces are synthesized into 2 outputs and amplified:

[0104] Control the internal SP4T switches (S1 to S10) to select any one of the branches 1 to 6 to output from splitter A or splitter A does not output a signal (the switch is connected to the load).

[0105] Control the internal SP4T switches (S1 to S10) to select any one of the branches 1 to 6 to output from splitter B or splitter B does not output a signal (the switch is connected to the load).

[0106] Control the internal SP4T switches (S11 to S20) to select any one of the branches 7 to 12 to output from splitter C or splitter C does not output a signal (the switch is connected to the load). Branches 7 to 12 are input and output through terminals CH7 to CH12 respectively.

[0107] Control the internal SP4T switches (S11 to S20) to select any one of the branches 7 to 12 to output from splitter D or splitter D does not output a signal (the switch is connected to the load).

[0108] The signals of splitter B and splitter C need to pass through two - stage SP2T (switches SW1_1 to SW1_4) to reach the combiner. Channel selection is performed by controlling the SP2T switches (switches SW1_1 to SW1_4).

[0109] When the channel selection control signal is high, the signal of splitter B passes through SP2T switch SW1_1 and SP2T switch SW1_3 and then outputs to terminal 1; the signal of splitter C passes through SP2T switch SW1_2 and SP2T switch SW1_4 and then outputs to terminal 4. When the channel selection control signal is low, the signal of splitter C passes through SP2T switch SW1_2 and SP2T switch SW1_3 and then outputs to terminal 1; the signal of splitter B passes through SP2T switch SW1_1 and SP2T switch SW1_4 and then outputs to terminal 4.

[0110] When the receive channel selection control signal is high, arbitrarily select 2 signals from the signals input at the interfaces of branches 1 to 6. The outputs are the signal output at FL_A terminal and the signal output at terminal 1 respectively. Combine these two signals into main path A. Arbitrarily select 2 signals from the signals input at the interfaces of branches 7 to 12. The outputs are the signal output at terminal 4 and the signal output at FL_D terminal respectively. Combine these two signals into main path B.

[0111] When the receive channel selection control signal is low, any one of the signals input at the interfaces of branch 1 to branch 6 is selected, and the output signal is the signal output by FL_A. Any one of the signals input at the interfaces of branch 7 to branch 12 is selected, and the output signal is the signal output at terminal 1. These two signals are combined into main path A.

[0112] The signal output by FL_A is removed from the signals input at the interfaces of branch 1 to branch 6, and any one of the other 5 paths is selected. The output signal is the signal output at terminal 4. The signal output at terminal 1 is removed from the signals input at the interfaces of branch 7 to branch 12, and any one of the other 5 paths is selected. The output signal is the signal output at FL_D terminal. These two signals are combined into main path B.

[0113] In this embodiment, the working state of the module can also be fed back through the low-frequency connector interface, and by setting a front panel, the working state of the module is displayed through the LED lights on the panel.

[0114] In this embodiment, the power dividers CMB1 and CMB2 of the combiner select the DC to 18 GHz power divider of mini company, with the model number EP2RKU+, which is a packaged chip. In the DC to 4 GHz frequency band, the insertion loss is 3.2 dB, the isolation is at least 8 dB, the maximum phase imbalance difference is 4°, and the maximum amplitude imbalance difference is 0.3 dB. In the 4 GHz to 18 GHz frequency band, the insertion loss is 3.3 dB, the isolation is at least 14 dB, the phase imbalance difference is 14°, and the amplitude imbalance difference is 0.4 dB.

[0115] The SP4T selects the DC to 20 GHz switch of Hittite company, with the model number HMC641LP4E, which is a packaged chip. In the DC to 20 GHz frequency band, the insertion loss is 3 dB, and the isolation is at least 30 dB.

[0116] The SP2T selects the DC to 20 GHz switch of Hittite company, with the model number HMC547LP3E, which is a packaged chip. In the DC to 20 GHz frequency band, the insertion loss is 2 dB, and the isolation is at least 33 dB.

[0117] The power divider used in the power distribution network for transceiver conversion is EP2RKU+, and the transceiver conversion switch used is HMC547LP3E.

[0118] A multi-port RF transceiver switch synthesis module according to the present invention solves the technical problems of transceiver switching and synthesis of multi-channel signals. Based on a traditional unidirectional matrix switch, it integrates a transceiver conversion function, a synthesis network, and a switch component. The dual-port can receive signals on the branch, which can be single-channel signals or two-channel synthesized signals, thus meeting the test requirements of different scenarios, reducing the use of instruments such as signal sources and spectrum analyzers, saving test costs, improving test efficiency, and having good expansion capabilities. By adding switch modules and channels, it can be expanded to more ports to meet more complex test requirements, has the potential for further optimization and simplification, can significantly shorten the test time, and realizes the collaborative control of multiple devices through hardware interfaces such as TTL signals and RS422.

Claims

1. A multi-port radio frequency transceiver switch synthesis module, characterized in that: It includes a combiner CMB1, a combiner CMB2, a switch matrix SW1, a switch matrix SW2, a switch matrix SW3, a conversion switch TRS1, a conversion switch TRS2, a conversion switch TRS3, a conversion switch TRS4, ​​a conversion switch TRS5, a conversion switch TRS6, a conversion switch TRS7, a conversion switch TRS8, a conversion switch TRS9, a conversion switch TRS10, a conversion switch TRS11, a conversion switch TRS12, a power interface POW, a transmission signal port, a transceiver selection control interface and a channel selection control interface, wherein the conversion switches TRS1 to TRS6 are respectively connected to 6 signal receiving ports of the switch matrix SW2, i.e., end A1 to end A6, and the conversion switches TRS7 to TRS12 are respectively connected to 6 signal receiving ports of the switch matrix SW3, i.e., end A7 to end A12; One branch signal output end of the switch matrix SW2 is connected to the combiner CMB1, and another branch signal output end is connected to a signal input end of the switch matrix SW1; The switch matrix SW2 is used to select the synthesis path of the received signal to the CH_A terminal; One branch signal output end of the switch matrix SW3 is connected to the combiner CMB2, and another branch signal output end is connected to another signal input end of the switch matrix SW1; The switch matrix SW3 is used to select the synthesis path of the received signal to the CH_B terminal; The two signal output terminals of the switch matrix SW1 are connected to the combiner CMB1 and the combiner CMB2 respectively; The transfer switches TRS1 to TRS12 are all connected to the transmission signal port, i.e., the JL_in terminal, and the transfer switches TRS1 to TRS12 are respectively connected to 12 branch signal ports, i.e., the CH1 terminal to the CH12 terminal; The output end of the combiner CMB1 is connected to the first signal output end, namely, the CH_A end, and the output end of the combiner CMB2 is connected to the second signal output port, namely, the CH_B end; The power interface POW is connected to an external power supply and supplies power to the combiner CMB1, the combiner CMB2, the switch matrix SW1, the switch matrix SW2, the switch matrix SW3, and the transfer switches TRS1 to TRS12; The two signal input terminals of the switch matrix SW1 are terminal 2 and terminal 3 of the switch matrix SW1, and the two signal output terminals of the switch matrix SW1 are terminal 1 and terminal 4 of the switch matrix SW1; The two branch signal output ends of the switch matrix SW2 are the FL_A end and the FL_B end of the switch matrix SW2, the FL_A end is connected to the IN1 end of the combiner CMB1, and the FL_B end is connected to the 2 end of the switch matrix SW1; The two branch signal output terminals of the switch matrix SW3 are respectively the FL_C terminal and the FL_D terminal of the switch matrix SW2, the FL_C terminal is connected to the 3 terminal of the switch matrix SW1, and the FL_D terminal is connected to the IN2 terminal of the combiner CMB2; The 1 terminal of the switch matrix SW1 is connected to the IN2 terminal of the combiner CMB1, and the 4 terminal is connected to the IN1 terminal of the combiner CMB2; The switch matrix SW1 includes switches SW1_1, SW1_2, SW1_3 and SW1_4, the COM pin of the switch SW1_1 is connected to the two terminals, the P1 pin is connected to the P1 pin of the switch SW1_4, and the P2 pin is connected to the P1 pin of the switch SW1_3; The COM pin of the switch SW1_2 is connected to the three terminals, the P1 pin is connected to the P2 pin of the switch SW1_4, and the P2 pin is connected to the P2 pin of the switch SW1_3; The COM pin of the switch SW1_3 is connected to the 4 terminals; The COM pin of the switch SW1_4 is connected to the 1 terminal.

2. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 1, characterized in that: The TX end of the switching switch TRS1 to the TX end of the switching switch TRS12 are both connected to the JL_in end; The RX end of the transfer switch TRS1 to the RX end of the transfer switch TRS6 are respectively connected to the A1 end to the A6 end of the switch matrix SW2; The RX end of the transfer switch TRS7 to the RX end of the transfer switch TRS12 are respectively connected to the A7 end to the A12 end of the switch matrix SW3; The ANT end of the conversion switch TRS1 to the ANT end of the conversion switch TRS12 are connected to the CH1 end to the CH12 end respectively.

3. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 2, characterized in that: The switch SW1_1 , the switch SW1_2 , the switch SW1_3 , and the switch SW1_4 are all single-pole double-throw switches.

4. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 2, characterized in that: The switch matrix SW2 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10, wherein the COM pin of switch S9 is connected to the FL_A terminal, the P1 pin is connected to the P4 pin of switch S1, the P2 pin is connected to the P4 pin of switch S2, the P3 pin is connected to the P4 pin of switch S3, and the P4 pin is connected to the COM pin of switch S8; The P1 pin of switch S10 is connected to the COM pin of switch S7, the P2 pin is connected to the P1 pin of switch S4, the P3 pin is connected to the P1 pin of switch S5, the P4 pin is connected to the P1 pin of switch S6, and the COM pin is connected to the FL_B terminal; The P2 pin, P3 pin and P4 pin of the switch S7 are connected to the P3 pin of the switch S1, the P3 pin of the switch S2 and the P3 pin of the switch S3 respectively; The P1 pin, P2 pin and P3 pin of the switch S8 are connected to the P2 pin of the switch S4, the P2 pin of the switch S5 and the P2 pin of the switch S6 respectively; The COM pin of switch S1 is connected to the A1 terminal, the COM pin of switch S2 is connected to the A2 terminal, the COM pin of switch S3 is connected to the A3 terminal, the COM pin of switch S4 is connected to the A4 terminal, the COM pin of switch S5 is connected to the A5 terminal, and the COM pin of switch S6 is connected to the A6 terminal; The P1 pin of switch S7, the P4 pin of switch S8, the P2 pin and the P1 pin of switch S1, the P2 pin and the P1 pin of switch S2, the P2 pin and the P1 pin of switch S3, the P4 pin and the P3 pin of switch S4, the P4 pin and the P3 pin of switch S5, and the P4 pin and the P3 pin of switch S6 are all connected to an external load; The switch matrix SW3 includes switches S11, S12, S13, S14, S15, S16, S17, S18, S19 and S20, wherein the COM pin of the switch S19 is connected to the FL_C terminal, the P1 pin is connected to the P4 pin of the switch S11, the P2 pin is connected to the P4 pin of the switch S12, the P3 pin is connected to the P4 pin of the switch S13, and the P4 pin is connected to the COM pin of the switch S18; The P1 pin of the switch S20 is connected to the COM pin of the switch S17, the P2 pin is connected to the P1 pin of the switch S14, the P3 pin is connected to the P1 pin of the switch S15, the P4 pin is connected to the P1 pin of the switch S16, and the COM pin is connected to the FL_D terminal; The P2 pin, the P3 pin and the P4 pin of the switch S17 are connected to the P3 pin of the switch S11, the P3 pin of the switch S12 and the P3 pin of the switch S13 respectively; The P1 pin, P2 pin and P3 pin of the switch S18 are connected to the P2 pin of the switch S14, the P2 pin of the switch S15 and the P2 pin of the switch S16 respectively; The COM pin of switch S11 is connected to the A7 terminal, the COM pin of switch S12 is connected to the A8 terminal, the COM pin of switch S13 is connected to the A9 terminal, the COM pin of switch S14 is connected to the A10 terminal, the COM pin of switch S15 is connected to the A11 terminal, and the COM pin of switch S16 is connected to the A12 terminal; Pin P1 of switch S17, pin P4 of switch S18, pin P2 and pin P1 of switch S11, pin P2 and pin P1 of switch S2, pin P2 and pin P1 of switch S13, pin P4 and pin P3 of switch S14, pin P4 and pin P3 of switch S15, and pin P4 and pin P3 of switch S16 are all connected to external loads.

5. A multi-port radio frequency transceiver switch synthesis module as claimed in claim 4, characterized in that: The switch S1, the switch S2, the switch S3, the switch S4, the switch S5, the switch S6, the switch S7, the switch S8, the switch S9, the switch S10, the switch S11, the switch S12, the switch S13, the switch S14, the switch S15, the switch S16, the switch S17, the switch S18, the switch S19 and the switch S20 are all single-pole four-throw switches.

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