Information processing method and apparatus, and communication device

Abstract

The invention discloses a coding method, a coding device, communication equipment and a communication system. An input bit sequence is encoded using a low density parity check (LDPC) matrix to obtain an encoded bit sequence for transmission. Wherein the LDPC matrix is obtained based on an expansion factor Z and a basis matrix. The invention also discloses the design of various different structures of the basis matrix. According to the coding method, the coding device, the communication equipment and the communication system, the coding requirements of information bit sequences with various lengths can be met.

Description

This application is a divisional application. The application number of the original application is 201880043727.4, and the original application date is June 27, 2018. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and in particular to an information processing method and a communication device. Background Art

[0002] Low density parity check (LDPC) code is a type of linear block code with a sparse check matrix, which has the characteristics of flexible structure and low decoding complexity. Because it uses a partially parallel iterative decoding algorithm, it has a higher throughput than traditional Turbo codes. LDPC codes can be used as error correction codes in communication systems, thereby improving the reliability and power utilization of channel transmission. LDPC codes can also be widely used in space communications, optical fiber communications, personal communication systems, ADSL and magnetic recording equipment. At present, LDPC codes have been considered as one of the channel coding methods in the fifth generation mobile communications.

[0003] In actual use, an LDPC matrix with special structural characteristics can be used. The LDPC matrix H with special structural characteristics can be expanded from an LDPC base matrix with a quasi cycle (QC) structure. QC-LDPC is suitable for hardware with high parallelism and provides a higher throughput. The LDPC matrix can be designed to be applied to channel coding.

[0004] QC-LDPC is suitable for hardware with high parallelism and provides higher throughput. It can be applied to channel coding by designing the LDPC matrix. Summary of the invention

[0005] The embodiments of the present invention provide an information processing method, a communication device and a system, which can support the encoding and decoding of information bit sequences of various lengths.

[0006] In a first aspect, a coding method and an encoder are provided, wherein the encoder encodes an input sequence using a low-density parity check (LDPC) matrix.

[0007] In a second aspect, a decoding method and a decoder are provided, wherein the decoder decodes an input sequence using a low-density parity check (LDPC) matrix.

[0008] In a first implementation of the first aspect or the second aspect above: the LDPC matrix is ​​obtained based on the expansion factor Z and the base matrix.

[0009] Based on the above implementation, the base matrix of the base graph 30a may include: Figure 3b-1 to Figure 3b-8 The 0th to 6th rows and the 0th to 16th columns of one of the matrices shown, or the base matrix comprises Figure 3b-1 to Figure 3b-8 The matrix 30a may be a matrix of rows 0 to 6 and columns 0 to 16. Figure 3b-1 to Figure 3b-8 The matrix after the row / column transformation of rows 0 to 6 and columns 0 to 16 of one of the matrices shown, or the base matrix can be Figure 3b-1 to Figure 3b-8 The matrix is ​​a matrix after row / column conversion of rows 0 to 6 and some of columns 0 to 16 of one of the matrices shown.

[0010] In order to support different block lengths, LDPC codes require different expansion factors Z. Based on the above implementation, in one possible implementation, a base matrix corresponding to the different expansion factors Z is used. For example, Z = a × 2 j , 0≤j<7, a∈{2,3,5,7,9,11,13,15}.

[0011] Further, optionally, based on the above implementation, the LDPC matrix can be obtained based on the expansion factor Z and the matrix Hs after compensating the aforementioned base matrices, or based on the expansion factor Z and the matrix Hs after row / column transformation of the matrix Hs after compensating the aforementioned base matrices. Compensating the aforementioned base matrices can be to increase or decrease the compensation value for the offset value greater than or equal to 0 in one or more columns.

[0012] The base graph and base matrix of the LDPC matrix in the above-mentioned implementations can meet the performance requirements of code blocks of various block lengths.

[0013] The expansion factor Z may be determined by the encoder or decoder according to the length K of the input sequence, or may be determined by other devices and provided to the encoder or decoder as an input parameter. Alternatively, the LDPC matrix may be obtained according to the acquired expansion factor Z and the base matrix corresponding to the expansion factor Z.

[0014] In a second implementation of the first aspect or the second aspect above: the LDPC matrix is ​​obtained based on the expansion factor Z and the parameters of the LDPC matrix.

[0015] The parameters of the LDPC matrix may include: row number, column where the non-zero element is located, non-zero element offset value, as shown in Table 2, Table 3b-1 to Table 3b-8, and stored in the manner of rows 0 to 6 of the table. Row weights may also be included. Each position in the column where the non-zero element is located and each offset value in the non-zero element offset value are in one-to-one correspondence.

[0016] For a communication device at a transmitting end, encoding the input sequence using an LDPC matrix may include: encoding the input sequence using an LDPC matrix corresponding to an expansion factor Z; or encoding the input sequence using a matrix after row / column transformation after the LDPC matrix corresponding to the expansion factor Z undergoes row / column transformation. In the present application, row / column transformation refers to row transformation, column transformation, or row transformation and column transformation.

[0017] For a communication device at a receiving end, decoding an input sequence using an LDPC matrix includes: decoding the input sequence using an LDPC matrix corresponding to an expansion factor Z; or decoding the input sequence using a matrix after a row / column transformation of the LDPC matrix corresponding to the expansion factor Z. In the present application, row / column transformation refers to row transformation, column transformation, or row transformation and column transformation.

[0018] In a possible implementation, an LDPC matrix may be saved and used to encode an input sequence, or an LDPC matrix that can be used for encoding may be obtained by transforming (row / column transformation) or extending the LDPC matrix.

[0019] In another possible implementation, parameters can be saved, and an LDPC matrix for encoding or decoding can be obtained according to the parameters, so that the input sequence can be encoded or decoded based on the LDPC matrix. The parameters include at least one of the following: a base graph, a base matrix, a transformation matrix after a base graph or base matrix row / column transformation, an extended matrix based on the base graph or base matrix, an offset value of a non-zero element in the base matrix, or any parameter related to obtaining the LDPC matrix.

[0020] In yet another possible implementation, the base matrix of the LDPC matrix may be stored in a memory.

[0021] In yet another possible implementation, a base graph of the LDPC matrix is ​​stored in a memory, and offset values ​​of non-zero elements in a base matrix of the LDPC matrix may be stored in the memory.

[0022] In another possible implementation, the parameters of the LDPC matrix are stored in a memory in the manner shown in Table 2 or Table 3b-1 to Table 3b-8, and a partial group of elements thereof may also be stored.

[0023] Based on the above possible implementation methods, in one possible design, at least one of the base graphs and base matrices used for LDPC encoding or decoding is obtained by performing row exchange, column exchange, or row and column exchange on at least one of the base graphs and base matrices of the above LDPC matrix.

[0024] In a third aspect, a communication device is provided that may include a module for executing the corresponding module in the above method design. The module may be software and / or hardware.

[0025] In one possible design, the communication device provided in the third aspect includes a processor and a transceiver component, which can be used to implement the functions of each part of the above-mentioned encoding or decoding method. In this design, if the communication device is a terminal, a base station or other network equipment, its transceiver component can be a transceiver, and if the communication device is a baseband chip or a baseband board, its transceiver component can be an input / output circuit of the baseband chip or the baseband board, which is used to realize the reception / transmission of input / output signals. The communication device can optionally also include a memory for storing data and / or instructions.

[0026] In one implementation, the processor may include an encoder as described in the first aspect and a determination unit. The determination unit is used to determine an expansion factor Z required for encoding an input sequence. The encoder is used to encode the input sequence using an LDPC matrix corresponding to the expansion factor Z.

[0027] In another implementation, the processor may include a decoder and an acquisition unit as described in the second aspect. The acquisition unit is used to acquire the soft value and the expansion factor Z of the LDPC code. The decoder is used to obtain the soft value and the expansion factor Z based on the base matrix H corresponding to the expansion factor Z. B The soft value decoding of the LDPC code obtains the information bit sequence.

[0028] In a fourth aspect, a communication device is provided, comprising one or more processors. In one possible design, one or more of the processors may implement the function of the encoder described in the first aspect, and in another possible design, the encoder described in the first aspect may be a part of the processor, and the processor may implement other functions in addition to the function of the encoder described in the first aspect. In one possible design, one or more of the processors may implement the function of the decoder described in the second aspect, and in another possible design, the decoder described in the second aspect may be a part of the processor.

[0029] Optionally, the communication device may further include a transceiver and an antenna. Optionally, the communication device may also include a device for generating a transmission block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, or a modulator for modulation processing, etc. In one possible design, the functions of these devices may be implemented by one or more processors.

[0030] Optionally, the communication device may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, or a device for rate matching, etc. The functions of these devices may be implemented by one or more processors.

[0031] In a fifth aspect, an embodiment of the present invention provides a communication system, which includes the communication device described in the third aspect.

[0032] In a sixth aspect, an embodiment of the present invention provides a communication system, which includes one or more communication devices described in the fourth aspect.

[0033] On the other hand, an embodiment of the present invention provides a computer storage medium having a program stored thereon, which, when executed, enables a computer to execute the method described in the above aspects.

[0034] Another aspect of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the methods described in the above aspects.

[0035] The information processing method, apparatus, communication device and communication system of the embodiments of the present invention can adapt to the flexible and changeable code length and code rate requirements of the system in terms of coding performance and error level. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a schematic diagram of a base graph, a base matrix and a circulant permutation matrix of an LDPC code;

[0037] Figure 2 is a schematic diagram of the structure of a base graph of an LDPC code;

[0038] Figure 3a A schematic diagram of a base graph of an LDPC code provided by an embodiment of the present invention;

[0039] Figure 3b-1 A schematic diagram of a base matrix provided by an embodiment of the present invention;

[0040] Figure 3b-2 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0041] Figure 3b-3 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0042] Figure 3b-4 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0043] Figure 3b-5 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0044] Figure 3b-6A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0045] Figure 3b-7 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0046] Figure 3b-8 A schematic diagram of another base matrix provided by an embodiment of the present invention;

[0047] Figure 4 A performance diagram provided for an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of an information processing flow provided by an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of an information processing flow provided by an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of the structure of a communication device is provided for an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of the system structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] To facilitate understanding, some terms involved in this application are explained below.

[0053] In this application, the terms "network" and "system" are often used interchangeably, "device" and "equipment" are often used interchangeably, and "information" and "data" are often used interchangeably, but those skilled in the art can understand their meanings. "Communication device" can be a chip (such as a baseband chip, or a data signal processing chip, or a general chip, etc.), a terminal, a base station, or other network equipment. A terminal is a device with a communication function, which may include a handheld device with a wireless communication function, a vehicle-mounted device, a wearable device, a computing device, or other processing devices connected to a wireless modem, etc. In different networks, the terminal can be called by different names, for example: user equipment, mobile station, user unit, station, cellular phone, personal digital assistant, wireless modem, wireless communication device, handheld device, laptop, cordless phone, wireless local loop station, etc. For the convenience of description, it is referred to as a terminal in this application. A base station (BS), also known as a base station device, is a device deployed in a wireless access network to provide wireless communication functions. The names of base stations may be different in different wireless access systems. For example, in the Universal Mobile Telecommunications System (UMTS) network, the base station is called NodeB, while the base station in the LTE network is called evolved NodeB (eNB or eNodeB), and the base station in the new radio (NR) network is called a transceiver point (TRP) or a next generation nodeB (gNB), or base stations in various other evolved networks may also use other names. The present invention is not limited to this.

[0054] The technical solutions in the embodiments of the present invention will be described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0055] LDPC codes can usually be represented by a parity check matrix H. In one implementation, the check matrix of the LDPC code can be simplified by a base graph, and each element in the base graph represents a Z*Z expansion matrix. Z is a positive integer, which can also be called an expansion factor, sometimes also called a lifting sizing factor or a lifting factor. The positions of zero elements and non-zero elements can be indicated by a base graph. The non-zero elements in the base graph correspond to offset values. The parity check matrix H of the LDPC code can be obtained by a base graph and an offset value. The base graph can usually include m*n matrix elements (entries or elements), which can be represented by a matrix form of m rows and n columns, and the values ​​of the matrix elements are 0 or 1, wherein the elements with a value of 0 are sometimes also called zero elements, indicating that the element can be replaced by a Z*Z all-zero matrix (zero matrix), and the elements with a value of 1 are sometimes also called non-zero elements, indicating that the element can be replaced by a Z*Z circulant permutation matrix (circulant permutation matrix). That is, each matrix element represents an all-zero matrix or a circulant permutation matrix. Figure 1 10a shows the elements in the base graph of an exemplary m=7, n=17 LDPC code with a QC structure. It should be noted that in this article, the row and column numbers of the base graph and the matrix are numbered from 0, just for the convenience of explanation, for example, the 0th column represents the first column of the base graph and the matrix, the 1st column represents the second column of the base graph and the matrix, the 0th row represents the first row of the base graph and the matrix, the 1st row represents the second row of the base graph and the matrix, and so on.

[0056] It can be understood that the row and column numbers can also be numbered starting from 1, and the corresponding row and column numbers are added by 1 based on the row and column numbers shown in this article. For example, if the row or column numbers are numbered starting from 1, the 1st column represents the first column of the base graph and the matrix, the 2nd column represents the second column of the base graph and the matrix, the 1st row represents the first row of the base graph and the matrix, the 2nd row represents the second row of the base graph and the matrix, and so on.

[0057] In another implementation, a base matrix with m rows and n columns can be defined, which is sometimes also called PCM (parity check matrix). For example, Figure 3b-1 to Figure 3b-8 Any matrix given, or Figure 3b-1 to Figure 3b-8The matrix is ​​composed of some rows and columns in the matrix in . Each element in the base matrix corresponds to each element in the base graph. The zero element in the base graph remains unchanged in the base matrix. In the base matrix, -1 or null value "null" can be used to represent zero elements. The non-zero element with a value of 1 in the i-th row and j-th column of the base graph remains unchanged in the base matrix, which is expressed as V i,j . V in the basis matrix can be defined by the system or predefined i,j The value of can also be obtained by the offset value P of the non-zero element in the base graph i,j and expansion factor Z to obtain V i,j .P i,j It can be an offset value defined relative to a predetermined or specific expansion factor Z. i,j Can be based on Z and V i,j Obtain, in one implementation, P i,j and V i,j Satisfies the following relationship: P i,j =mod(V i,j ,Z). i and j represent the row index (row number) and column index (column number) of the element to indicate the position of the element in the matrix.

[0058] In the embodiments of the present application, the base matrix is ​​sometimes referred to as the offset matrix of the base graph. The base matrix can be obtained by the base graph and the offset value. If the value of the element in the i-th row and j-th column of the base graph is 1, its offset value is P i,j , P i,j is an integer greater than or equal to 0, which means that the element with a value of 1 in the i-th row and j-th column can be i,j The cyclic permutation matrix is ​​sometimes referred to as a shift matrix. The cyclic permutation matrix can be obtained by performing P transformation on the Z*Z identity matrix. i,j In one implementation, P i,j =mod(V i,j ,Z). V i,j is the value of the base matrix corresponding to the non-zero element in the base graph. Sometimes it is also called the offset value, or the cyclic offset value, or the offset coefficient. For example, V i,j The maximum expansion factor Z can be max The corresponding offset value. Z max is the maximum value in the set of values ​​of Z. If the value of the element in the i-th row and j-th column of the base graph is 0, the element with value 0 can be replaced with a Z*Z all-zero matrix. Replace the element with value 0 in the base graph with a Z*Z all-zero matrix, and replace the element with value 1 with its offset value P i,jThe parity check matrix of the LDPC code can be obtained by replacing the corresponding Z*Z circulant permutation matrix. Z is a positive integer, which can also be called the expansion (lifting) factor, sometimes also called the lifting size or lifting factor. It can be determined according to the code block size supported by the system and the size of the information data. It can be seen that the size of the parity check matrix H is (m*Z)*(n*Z). For example, if the expansion factor Z=4, each zero element is replaced by a 4*4 all-0 matrix 11a. If P 2,3 =2, then the non-zero elements in the 2nd row and 3rd column are replaced by the 4*4 circulant permutation matrix 11d, which is obtained by 2 right circulant shifts of the 4*4 identity matrix 11b. If P 2,4 =0, then the non-zero element in the 2nd row and the 4th column is replaced by the unit matrix 11b. It should be noted that this is only an example and is not intended to be limiting.

[0059] Because P i,j It can be obtained based on the expansion factor Z. For the element with a value of 1 at the same position, different P values ​​may exist when different expansion factors Z are used. i,j .like Figure 1 10b shows a base matrix corresponding to the base graph 10a. For example, the value of the 3rd column in the 1st row of the base graph 10a is 1, which corresponds to the offset value V in the 3rd column in the 1st row of the base matrix 10b. i,j is 27. Using the formula P i,j =mod(V i,j ,Z) then we can know P i,j The value of . Thus, the elements of the 1st row and 3rd column can be P-ed by the unit matrix of Z*Z i,j It is replaced by the cyclic permutation matrix obtained by cyclic shifting to the right or left.

[0060] Usually, the base graph or base matrix of the LDPC code can also include p columns of built-in puncture bit columns, where p can be an integer from 0 to 2. These columns participate in the encoding, but the system bits corresponding to their encoding are not sent. Then the code rate of the LDPC code base matrix satisfies R = (nm) / (np). Taking base graph 10a as an example, if there are 2 columns of built-in puncture bit columns, the code rate is (17-7) / (17-2) = 0.667, which is approximately 2 / 3.

[0061] The LDPC code used in wireless communication systems is QC-LDPC code, whose check bit part has a dual diagonal structure or raptor-like structure, which can simplify coding and support incremental redundant hybrid retransmission. The decoder of QC-LDPC code usually uses QC-LDPC shift network (QSN), Banyan network or Benes network to realize the cyclic shift of information.

[0062] The matrix size of the base graph of a QC-LDPC code with a raptor-like structure is m rows and n columns, and may include five sub-matrices A, B, C, D, and E, where the weight of the matrix is ​​determined by the number of non-zero elements, the row weight (row weight) refers to the number of non-zero elements included in a row, and the column weight (column weight) refers to the number of non-zero elements included in a column. Figure 2 As shown in 200, wherein:

[0063] Submatrix A is m A Line n A A matrix of columns, whose size can be m A *n A , where each column corresponds to Z systematic bits in the LDPC code, and the systematic bits are sometimes also called information bits.

[0064] The submatrix B is m A Line m A A square matrix of columns, whose size can be m A *m A , each column corresponds to Z check bits in the LDPC code. The submatrix B includes a dual diagonal submatrix B' and a matrix column with a weight of 3 (referred to as a 3-column column), where the matrix column with a weight of 3 can be located before the submatrix B', such as Figure 2 As shown in 20a; the submatrix B may also include one or more matrix columns with a column weight of 1 (referred to as single column weight), for example, a possible implementation is as follows Figure 2 As shown in 20b or 20c.

[0065] Usually, a matrix generated based on sub-matrices A and B can be called a core matrix, which can be used to support high-rate encoding.

[0066] Submatrix C is an all-zero matrix with a size of m A ×m D .

[0067] Submatrix E is the identity matrix, whose size is m D ×m D .

[0068] The size of the submatrix D is m D ×(nA +m A ), which is usually used to generate low-rate check bits.

[0069] Since the structures of the sub-matrices C and E are relatively determined or clear, the structure of the sub-matrices A, B and D is one of the factors affecting the encoding and decoding performance of the LDPC code.

[0070] It is understandable that the structure of the base graph / base matrix is ​​described above from the perspective of principle. It is understandable that the division of submatrices A, B, C, D, and E is only to help understand from a principle perspective. The division of submatrices A, B, C, D, and E may not be limited to the above division method. In one implementation, since C is a full zero matrix and E is a unit matrix with a known structure, the LDPC matrix can be simplified without using the complete A, B, C, D, and E to represent the LDPC matrix. For example, submatrices A, B, and D can be used to simplify the representation of the LDPC matrix, or submatrices A, B, C, and D can be used to represent the LDPC matrix, or submatrices A, B, D, and E can be used to represent the LDPC matrix. In another implementation, since submatrix B includes one or more columns of single-column-heavy columns, for one column or a single-column-heavy column portion of submatrix B, the structure is also relatively fixed, so the one column or a single-column-heavy column may not be used to represent the LDPC matrix. For example, when used to represent an LDPC matrix, submatrix A, some columns in submatrix B, and corresponding columns in submatrix D can be used. When using a raptor-like structured LDPC matrix for encoding, a possible implementation is to first encode the matrix corresponding to submatrix A and part of B, that is, to encode the core matrix, to obtain the check bits corresponding to submatrix B, and then to encode the entire matrix to obtain the check bits corresponding to part of submatrix E. Since submatrix B may include a submatrix B' of a dual diagonal structure and a single-column re-column, in encoding, the check bits corresponding to the dual diagonal structure may be obtained first, and then the check bits corresponding to the single-column re-column may be obtained.

[0071] The following is an example of encoding. Assume that the core matrix composed of submatrices A and B is H core , H core Remove the last row and the last column from the matrix, that is, remove the single column and the row where the non-zero elements of the column are located, and the resulting matrix is ​​H core-dual , H core-dual The check bit part in is represented by H e =[H e1 H e2 ],H e1 For 3 columns, H e2 It is a dual diagonal structure. According to the definition of LDPC code matrix, H core-dual ·[SPe ] T =0, where S is the input sequence, represented by a vector consisting of information bits, and P e is the vector composed of check bits, [SP e ] T Represented by the input sequence S and P e The transposed matrix is ​​constructed. Therefore, we can first core-dual Calculate H core-dual The corresponding check bits, the input sequence S includes all information bits; then according to H core-dual The corresponding check bits and the input sequence S are used to calculate the check bits corresponding to the single column re-arrangement in the submatrix B. At this time, all the check bits corresponding to the submatrix B can be obtained. Then, according to the input sequence S and the check bits corresponding to the submatrix B, the submatrix D is partially encoded to obtain the check bits corresponding to the submatrix E, thereby obtaining all the information bits and all the check bits. These bits constitute the encoded sequence, which is an LDPC code sequence.

[0072] Optionally, LDPC code encoding may also include shortening and puncturing operations, and shortened bits and punctured bits are not sent.

[0073] The truncation is generally performed from the last bit of the information bit forward, and can be performed in different ways. For example, the number of bits to be truncated is s 0 , the last s in the input sequence S can be 0 bits are set to known bits to obtain the input sequence S', such as 0 or null, or some other value, and then the input sequence S' is encoded by the LDPC matrix. For example, the last (s 0 mod Z) bits are set to known bits to obtain the input sequence S', such as 0 or null, or some other value, and the last Column deletion obtains the LDPC matrix H', and uses the LDPC matrix H' to encode the input sequence S', or the last The columns do not participate in the encoding of the input sequence S'. After the encoding is completed, the truncated bits are not sent.

[0074] Among them, puncturing can be puncturing built-in puncturing bits or check bits in the input sequence. When puncturing the check bits, puncturing is usually performed from the last bit of the check bits. Of course, puncturing can also be performed according to the puncturing sequence preset by the system. One possible implementation method is to first encode the input sequence, and then select the last p bits of the check bits according to the number of bits p to be punctured, or select p bits according to the puncturing sequence preset by the system, and these p bits are not sent. In another possible implementation method, the p columns of the matrix corresponding to the punctured bits and the p rows where the non-zero elements in these columns are located can also be determined. These rows and columns do not participate in the encoding, and no corresponding check bits are generated.

[0075] It should be noted that the encoding method here is only an example. Based on the base graph and / or base matrix provided in this application, other encoding methods known to those skilled in the art can also be used, and this application is not limited. The decoding involved in this application can be a variety of decoding methods, for example, a min-sum (MS) decoding method can be used, and a beliefpropagation decoding method can also be used. The MS decoding method is sometimes also called the Flood MS decoding method. For example, the input sequence is initialized and iterative processing is performed. After the iteration, a hard decision detection is performed, and the hard decision result is verified. If the decoding result meets the verification equation, the decoding is successful, the iteration is terminated, and the judgment result is output. If it does not meet the verification equation, the iterative processing is performed again within the maximum number of iterations. If the maximum number of iterations is reached and the verification still fails, the decoding fails. It can be understood that the technical personnel in this field can understand the principle of MS decoding, which will not be described in detail here.

[0076] It should be noted that the decoding method is only an example. Other decoding methods known to those skilled in the art may also be used based on the base graph and / or base matrix provided in this application. This application does not limit the decoding method.

[0077] LDPC codes can usually be obtained by designing a base graph or base matrix. For example, the density evolution method can be used to determine the performance upper limit of the LDPC code, and the error floor of the LDPC code can be determined based on the offset value in the base matrix. By designing the base graph or base matrix, the encoding or decoding performance can be improved, and the error floor can be reduced. The code length in the wireless communication system is flexible and changeable, for example, it can be 2560 bits, 38400 bits, etc. Figure 3a is an example of a base graph of an LDPC code, Figure 3b-1 to Figure 3b-8 yes Figure 3a Each base matrix example of the base graph can meet the performance requirements of various block lengths. For ease of explanation and understanding, the column numbers and row numbers are shown at the top and left in 3a and 3b-1 to 3b-8 in the drawings, respectively.

[0078] Figure 4 The performance diagram of the LDPC code shown in 3a is given. Figure 4 In the performance diagram shown, based on Figure 3b-1 to Figure 3b-8 The performance curve of matrix coding shown in the figure shows that the horizontal axis represents the length of the information bit sequence in bits, and the vertical axis represents the symbol signal-to-noise ratio (Es / N0) required to achieve the corresponding BLER. The two lines for each code rate correspond to the BLER of 0.01 and 0.0001. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve. The curves are smooth, indicating that the matrix has better performance at different block lengths.

[0079] Figure 3a The figure shows an example of a base graph of an LDPC code, in which the top row 0 to 51 (i.e., columns 0 to 51) in the figure represent column numbers, and the leftmost column 0 to 41 (i.e., rows 0 to 41) represent row numbers, that is, the size of the base graph is 42 rows and 52 columns.

[0080] In one implementation, submatrix A and submatrix B can be considered as the core matrix of the base graph of the LDPC code, which can be used for high-rate coding. A matrix with 7 rows and 17 columns is formed, such as Figure 3a The matrix with 7 rows and 17 columns in the upper left corner of the base graph shown can be regarded as the core matrix part of the base graph. The core matrix part can include sub-matrix A and sub-matrix B. Sub-matrix A is Figure 3a The matrix of 7 rows and 10 columns consists of rows 0 to 6 and columns 0 to 9. Submatrix B is Figure 3a The 0th to 6th rows and the 10th to 16th columns form a 7-row and 7-column matrix.

[0081] In another implementation, Figure 3a The matrix consisting of 7 rows and 14 columns, or 7 rows and 15 columns, or 7 rows and 16 columns in the upper left corner of the base graph shown is regarded as the core part, that is, Figure 3a The matrix composed of rows 0 to 6 and columns 0 to 13 of the base graph shown in FIG. , or the matrix composed of rows 0 to 6 and columns 0 to 14, or the matrix composed of rows 0 to 6 and columns 0 to 15. Correspondingly, Figure 3b-1 to Figure 3b-8 The part of the matrix shown that corresponds to the base graph is regarded as the core part.

[0082] In one implementation, submatrix A may include one or more columns of built-in punctured bit columns, for example, two columns of built-in punctured bit columns, and after puncturing, the code rate supported by the core matrix is ​​2 / 3. Submatrix B may include one column and three columns of heavy columns, that is, the first column of submatrix B (the 10th column of the core matrix) has a column weight of 3, the second column of submatrix B (the 11th column of the core matrix) has a column weight of 5, the second to fourth columns of submatrix B (the 12th to 13th columns of the core matrix), and the 0th to 3rd rows are dual diagonal structures, wherein the third and fourth columns (the 12th to 13th columns of the core matrix) have a column weight of 2, and submatrix B also includes three columns of single-column heavy columns (the 14th to 16th columns of the core matrix).

[0083] In one implementation, the submatrix A may correspond to system bits, sometimes also referred to as information bits, and may have a size of m A 10 rows and 10 columns, where m A =5, which is composed of the elements of rows 0 to 4 and columns 0 to 9 in the base graph 30a;

[0084] In one implementation, the submatrix B may correspond to the check bits, and its size is m A Line m A The columns are composed of elements from the 0th to the 6th rows and the 10th to the 16th columns in the base graph 30a.

[0085] In order to obtain a flexible bit rate, sub-matrix C, sub-matrix D and sub-matrix E of corresponding sizes can be added based on the core matrix to obtain different bit rates. Since sub-matrix C is an all-zero matrix and the sub-matrix is ​​a unit matrix, its size is mainly determined by the bit rate and the structure is relatively fixed. The core matrix and sub-matrix D are the main parts that affect the encoding and decoding performance. Adding rows and columns on the basis of the core matrix to form the corresponding C, D and E parts can obtain different bit rates.

[0086] The number of columns m of the submatrix D D is the sum of the number of columns of submatrices A and B, and the number of rows is mainly related to the code rate. Taking base graph 30a as an example, the number of columns of submatrix D is 17. If the code rate supported by the LDPC code is R m , then the size of its base graph or base matrix is ​​m rows and n columns, where n = n A / R m +p,m=nn A =n A / R m +pn A . Where P is the built-in puncturing column. According to this formula, the code rate supported by the LDPC code can be obtained. If the minimum code rate R m = 1 / 3, the number of built-in puncturing columns p = 2, taking base image 30a as an example, n = 52, m = 42, and the number of rows of submatrix D is m DMaximum size can be mm A =42-7=35, so 0≤m D ≤35.

[0087] Taking the base graph 30a as an example, the submatrix D may include the m in the 7th to 41st rows of the base graph 30a. D OK.

[0088] In the present application, if the same column of two adjacent rows in the base graph has at most one non-zero element, the two rows are orthogonal to each other. If the same column of two adjacent rows in the base graph, except for some columns, has at most one non-zero element, the two adjacent rows are quasi-orthogonal. For example, for two adjacent rows, if there is only one non-zero element in the columns other than the built-in puncturing bit column, the two adjacent rows can be considered to be quasi-orthogonal.

[0089] The 7th to 41st rows in the base graph 30a may include multiple rows of quasi-orthogonal structures and at least two rows of orthogonal structures. For example, the 32nd row in the base graph 30a is orthogonal to the 33rd row, the 34th row is orthogonal to the 35th row, and the 36th, 37th, and 38th rows are orthogonal. For any two adjacent rows, except for the built-in puncturing bit column, there is at most one non-zero element in the same column, which meets the quasi-orthogonality. If the built-in puncturing bit column is included, any column has at most one non-zero element, which meets the orthogonal structure.

[0090] If m D =15, the size of the submatrix D in the LDPC code base graph is 15 rows and 17 columns, which can be composed of the matrix from the 7th row to the 21st row and the 0th column to the 16th column of the base graph 30a. The code rate supported by the corresponding LDPC code can be obtained by referring to the above calculation formula.

[0091] Submatrix E is a unit matrix with 15 rows and 15 columns, and submatrix C is a matrix with 7 rows and 15 columns and all zeros;

[0092] If m D =19, the size of the submatrix D in the LDPC code base graph is 19 rows and 17 columns, which can be composed of the matrix of the 7th row to the 25th row and the 0th column to the 16th column of the base graph 30a, and the code rate supported by the corresponding LDPC code can be obtained by referring to the above calculation formula. At this code rate, the base graph of the LDPC code corresponds to the matrix part composed of the 0th row to the 25th row and the 0th column to the 16th column of the base graph 30a, where the submatrix E is a unit matrix of 16 rows and 16 columns, and the submatrix C is a matrix of all 0s of 7 rows and 16 columns. And so on, it is not elaborated one by one.

[0093] In one design, the base graph and / or base matrix can be subjected to row / column exchange, that is, row exchange, column exchange, or row exchange and column exchange. The row / column exchange operation does not change the row weight and column weight, and the number of non-zero elements does not change. Therefore, the base graph and / or base matrix after row / column exchange has limited impact on system performance. That is to say, overall, the impact on system performance is acceptable and within the tolerance range. For example, the performance may decrease within the allowable range for some scenes or in some ranges, but the performance is improved in some scenes or in some ranges, and the overall performance is not greatly affected.

[0094] For example, the 34th row and the 36th row of the base graph 30a may be swapped, and the 44th column and the 45th column may be swapped. For another example, the submatrix D includes the matrix F in m D OK, this D The rows can be swapped without swapping, or one or more rows can be swapped. The submatrix E is still a diagonal structure, and rows and columns are not swapped. For example, the 27th and 29th rows of the matrix F are swapped, and the submatrix D includes the m rows in the matrix F. D The submatrix E still has a diagonal structure. It can be understood that if the base graph or base matrix includes the submatrix D, when the columns of the core matrix are exchanged, the columns in the corresponding submatrix D also need to be exchanged.

[0095] like Figure 3b-1 to Figure 3b-8 The matrices shown are respectively design examples of multiple base matrices of the base graph 30a. Among them, the non-zero elements in the i-th row and j-th column of the base graph 30a are Figures 3b-1 to 3b-8 The position in the matrix shown in the figure remains unchanged, and the value is the offset value V i,j , zero elements are represented by -1 or null in the offset matrix. The corresponding part of the submatrix D in the base matrix may include m in the 7th to 41st rows of any base matrix. D You can choose m according to the bit rate. D It can be understood that if the base graph is a matrix that has undergone row / column transformation relative to the base graph 30a, then the base matrix is ​​also a matrix that has undergone row / column transformation relative to any corresponding one.

[0096] In a possible design, since the structures of sub-matrices C and E are relatively fixed, sub-matrices A, B, and D can be used to represent the base graph / base matrix of LDPC, that is, Figure 3a or Figure 3b-1 to Figure 3b-8 Rows 0 to 41 and columns 0 to 16 of the matrix shown.

[0097] In a possible design, since the structure of 14 to 51 columns is relatively fixed, it is possible to use Figure 3a or Figure 3b-1 to Figure 3b-8The matrix with rows 0 to 41 and columns 0 to 13 in the shown matrix is ​​used to simplify the base graph / base matrix of LDPC.

[0098] In one possible design, you can use Figure 3a or Figure 3b-1 to Figure 3b-8 The 0 to 41 rows, 0 to 13 columns, and some of the 14 to 51 columns in the matrix shown represent the base graph / base matrix of LDPC. For example, you can use Figure 3a or Figure 3b-1 to Figure 3b-8 In the shown matrix, rows 0 to 41 and columns 0 to 15 represent the base graph / base matrix of LDPC, or rows 0 to 41 and columns 0 to 14 may be used to represent the base graph / base matrix of LDPC.

[0099] In one possible design, the basis matrix of the LDPC code may include Figure 3b-1 to Figure 3b-8 The 0th to 6th rows and the 0th to 16th columns of any matrix shown in FIG. Figure 3b-1 to Figure 3b-8 The matrix composed of rows 0 to 6 and columns 0 to 16 of the matrix shown can be used as the core part of the base matrix. In this design, the structure of other parts of the base matrix of the LDPC code, such as matrix C, D, and E, is not limited. For example, Figure 3b-1 to Figure 3b-8 Any of the structures shown may also be used in other matrix designs.

[0100] In another possible design, the basis matrix of the LDPC code may include: Figure 3b-1 to Figure 3b-8 The matrix consisting of the 0th to (m-1)th rows and the 0th to (n-1)th columns in any matrix shown, where 7≤m≤42, m is an integer, and 18≤n≤52, n is an integer.

[0101] In this design, the structure of other parts of the base matrix of the LDPC code is not limited. For example, Figure 3b-1 to Figure 3b-8 Any of the structures shown may also be used in other matrix designs.

[0102] In yet another possible design, a basis matrix of an LDPC code may include: Figure 3b-1 to Figure 3b-8 For example, some of the columns in rows 0 to 6 and columns 0 to 16 of any of the matrices 3b-1 to 3b-8 shown in FIG. Figure 3b-1 to Figure 3b-8 The core part (rows 0 to 6 and columns 0 to 16) of the matrix shown is shortened and / or punctured. In one implementation, the base matrix of the LDPC code may not include columns corresponding to the shortened and / or punctured bits.

[0103] In this design, other parts of the base matrix of the LDPC code are not limited. For example, Figure 3b-1 to Figure 3b-8 The structure shown can also be used in other structures.

[0104] In yet another possible design, a basis matrix of an LDPC code may include: Figure 3b-1 to Figure 3b-8 A matrix consisting of the 0th to (m-1)th rows and some of the 0th to (n-1)th columns in any matrix shown, where 7≤m≤42, m is an integer, and 18≤n≤52, n is an integer. For example, Figure 3b-1 to Figure 3b-8 The 0th to (m-1)th rows and the 0th to (n-1)th columns in any matrix shown are truncated and / or punctured. In one implementation, the base matrix of the LDPC code may not include the columns corresponding to the truncated and / or punctured bits. In this design, there is no limitation on other parts of the base matrix of the LDPC code. For example, reference may be made to Figure 3b-1 to Figure 3b-8 The structure shown can also be used in other structures.

[0105] In one implementation, the truncation operation may be to truncate the information bits. Figure 3b-1 to Figure 3b-8 Taking any matrix shown in the figure as an example, one or more columns from 0 to 9 are truncated, then the base matrix of the LDPC code may not include Figure 3b-1 to Figure 3b-8 The truncated column or columns in the matrix shown. For example, if the 9th column is truncated, the basis matrix of the LDPC code may include: Figures 3b-1 to 3b-8 For the 0th to 8th columns and the 10th to 16th columns of any matrix in . For the 0th to 6th rows, and the 0th to 8th columns and the 10th to 16th columns.

[0106] In another implementation, the puncturing may be puncturing of the check bits. Figure 3b-1 to Figure 3b-8 Take any matrix shown in the figure as an example, and puncture one or more columns from the 10th to the 16th columns. Then the base matrix of the LDPC code may not include Figure 3b-1 to Figure 3b-8 The punctured column or columns in the matrix shown. For example, if the 16th column is punctured, the base matrix of the LDPC code may include: 3b-1 to Figure 3b-8 Columns 0 to 15 of any matrix in .

[0107] Different expansion factors Z are designed for LDPC codes to support information bit sequences of different lengths. In one possible design, different base matrices can be used for different expansion factors to achieve better performance. For example, expansion factor Z = a × 2 j, 0≤j<7, a∈{2,3,5,7,9,11,13,15}. Table 1 shows a possible set of expansion factors {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22,24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}, where except for the top row and the leftmost column, each cell represents the value of Z corresponding to the corresponding values ​​of a and j, for example, a=2 in this column and j=1 in this row, Z=4, and for another example, a=11 and j=3, Z=88. And so on, I won’t go into details. Table 1 Z a＝2 a＝3 a＝5 a＝7 a＝9 a＝11 a＝13 a＝15 j＝0 2 3 5 7 9 11 13 15 j＝1 4 6 10 14 18 22 26 30 j＝2 8 12 20 28 36 44 52 60 j＝3 16 24 40 56 72 88 104 120 j＝4 32 48 80 112 144 176 208 240 j＝5 64 96 160 224 288 352 j＝6 128 192 320 j＝7 256 384

[0108] It can be understood that Table 1 is only a form of expressing the expansion factor. When the actual product is implemented, it is not limited to the form of Table 1 and can be expressed in other forms.

[0109] For example, each value of a corresponds to a group of expansion factors. The expansion factor group can be identified by a group index. For example, Table 1' gives another form of the expansion factor. It can be understood that in Table 1', the expansion factor group index is only illustrated by 1, 2, 3, 4, 5, 6, 7, and 8 as examples. The index values ​​of each group are not limited in this application. For example, 0, 1, 2, 3, 4, 5, 6, and 7 can be used to index eight expansion factor groups respectively, or other identifiable indexes can be used to index eight expansion factor groups respectively. Each group index corresponds to a base matrix. Taking Table 1' as an example, the values ​​of the expansion factor Z in different expansion factor groups are different. Once Z is determined, the base matrix corresponding to Z is also determined. Therefore, Z also corresponds to the base matrix. Table 1

[0110] Since the set of expansion factors supported by the base graph can be all the expansion factors in Table 1 or Table 1', or a part of the expansion factors, for example, it can be {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}, that is, Z is greater than or equal to 24. For another example, it can be the union of one or more of {2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,18,20,22} and {24,26,28,30,32,36,40,44,48,52,56,60,64,72,80,88,96,104,112,120,128,144,160,176,192,208,224,240,256,288,320,352,384}. It should be noted that this is only an example. The set of expansion factors supported by the base graph can be divided into different subsets according to the value of a. For example, a=2, the subset of the expansion factor Z may include one or more of {2, 4, 8, 16, 32, 64, 128, 256}. For another example, a=3, the subset of the expansion factor Z may include one or more of {3, 6, 12, 24, 48, 96, 192, 384}, and so on.

[0111] The set of expansion factors supported by the base graph can be divided according to different values ​​of a to determine the corresponding basis matrix:

[0112] If a=2, or the expansion factor Z is one of {2, 4, 8, 16, 32, 64, 128, 256}, the basis matrix can include Figure 3b-1 to Figure 3b-8 The matrix shown in FIG. 1 includes rows 0 to 6 and columns 0 to 16, or the base matrix includes Figure 3b-1 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-1 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer. .

[0113] If a=3, or the expansion factor Z is one of {3, 6, 12, 24, 48, 96, 192, 384}, the base matrix may include rows 0 to 6 and columns 0 to 16 of matrix 3b-2, or the base matrix may include Figure 3b-2The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-2 Some of the columns from the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, and n is an integer.

[0114] For example, the basis matrix PCM includes Figure 3b-2 0 to 41 rows, and 0 to 13 columns, or 0 to 14 columns, or 0 to 15 columns.

[0115] If a=5, or the expansion factor Z is one of {5, 10, 20, 40, 80, 160, 320}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-3, or the base matrix may include Figure 3b-3 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-1 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0116] If a=7, or the expansion factor Z is one of {7, 14, 28, 56, 112, 224}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-4, or the base matrix may include Figure 3b-4 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-4 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0117] If a=9, or the expansion factor Z is one of {9, 18, 36, 72, 144, 288}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-5, or the base matrix may include Figure 3b-5 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-5 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0118] If a=11, or the expansion factor Z is one of {11, 22, 44, 88, 176, 352}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-6, or the base matrix may include Figure 3b-6 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-6 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0119] If a=13, or the expansion factor Z is one of {13, 26, 52, 104, 208}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-7, or the base matrix may include Figure 3b-7 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-7 Some of the columns in the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0120] If a=15, or the expansion factor Z is one of {15, 30, 60, 120, 240}, the base matrix may include rows 0 to 6 and columns 0 to 16 in matrix 3b-8, or the base matrix may include Figure 3b-8 The 0th to (m-1)th rows and the 0th to (n-1)th columns in the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer; or, the base matrix includes Figure 3b-8 Some of the columns from the 0th to (m-1)th rows and the 0th to (n-1)th columns of the matrix shown, where 7≤m≤42, m is an integer, and 17≤n≤52, n is an integer.

[0121] Optionally, for a given base matrix of an LDPC code, the offset value Offset may be increased or decreased for the offset values ​​of one or more columns of non-zero elements in the matrix. s， The system performance is not greatly affected. The compensation values ​​of non-zero elements in different columns can be the same or different. For example, when compensating one or more columns of a matrix, the compensation values ​​of different columns can be the same or different, which is not limited in this application.

[0122] The impact on system performance is not significant, which means that the impact on system performance is acceptable and within the tolerance range. For example, in some scenarios or within some ranges, the performance may decrease within the allowable range, but in some scenarios or within some ranges, the performance may improve. Overall, the impact on performance is not significant.

[0123] For example, the offset value Offset is increased or decreased for each offset value greater than or equal to 0 in the sth column of any matrix in matrices 3b-1 to 3b-8. s The compensation matrix Hs of the matrix can be obtained, where Offset s is an integer greater than or equal to 0, wherein S is an integer greater than or equal to 0 and less than 11. The compensation values ​​Offsets of one or more columns may be the same or different.

[0124] Figure 4 The performance diagram shown is based on Figures 3b-1 to 3b-2 The performance curve of matrix coding shown in the figure shows that the horizontal axis represents the length of the information bit sequence in bits, and the vertical axis represents the symbol signal-to-noise ratio (Es / N0) required to achieve the corresponding BLER. The two lines for each code rate correspond to the BLER of 0.01 and 0.0001. At the same code rate, 0.01 corresponds to the upper curve and 0.0001 corresponds to the lower curve. The curves are smooth, indicating that the matrix has better performance at different block lengths.

[0125] Attached Figures 1 to 3a , Figures 3b-1 to 3b-8 The structure of the base graph and base matrix involved in the LDPC code is shown. In order to fully illustrate the design of the base graph and / or base matrix in the embodiments of the present invention. The structure of the base matrix can be expressed in other ways that can be recognized by the system. For example, it can be expressed in a table or other ways.

[0126] In one design, Figure 1 The base graph 10a in FIG. 1 is a matrix of 7 rows and 10 columns, and the parameters involved can be expressed in Table 2. Table 2

[0127] It is understandable that since the 14th to 16th columns in the base graph 10a are single-column columns, their positions are relatively fixed or easy to determine, and they may not be recorded in Table 2, but the positions of the non-zero elements of columns 14 to 16 may be recorded in other ways.

[0128] In one design, Figure 3b-1 to Figure 3b-8 Taking the basic matrix shown in FIG. 3 as an example, the parameters involved can be represented by Table 3b-1 to Table 3b-8 respectively. Table 3b-1 Table 3b-2 Table 3b-3 Table 3b-4 Table 3b-5 Table 3b-6 Table 3b-7 Table 3b-8

[0129] It is understandable that the above Figure 3a , Figures 3b-1 to 3b-8 As well as Table 2, Table 3b-1 to Table 3b-8 are intended to help understand the design of the base graph and matrix, and their representation is not limited to this representation. Other possible variations may also be included. For example, Tables 3b-1, 3b-3 to 3b-8 may also be deformed in the form of 3b-2'. For columns with relatively fixed structures and an offset value of 0, for example, the information of the elements of the 14th to 51st columns may be selectively included or not included in the table to save storage space.

[0130] In one design, for a relatively fixed structure of a base graph or base matrix, the positions of its non-zero elements can be calculated based on the row and column positions, and the positions of these non-zero elements may not be saved. Figure 3b-2 And Table 3b-2 as an example, Figure 3b-2 The positions of columns 14 to 51 in the matrix shown are relatively fixed, and the offset value V i,j The values ​​are all 0, and the positions of the non-zero elements can be calculated through the known non-zero elements. In the above Table 3b-2, the information of columns 14 to 51 may not be included. Or the information of some columns from 14 to 51 may not be included. For example, the non-zero elements in columns 16 to 51 and their corresponding offset values ​​are not included. For example Figure 3b-2The matrix shown can also be expressed as shown in Table 3b-2' below. Table 3b-2'

[0131] For example, Figure 3b-2 For example, for the offset value V of row 0 i,j It is also 0, and the information of the 0th row may not be saved but obtained through calculation.

[0132] In one implementation, the parameter "row weight" in Table 2, Table 3b-1 to Table 3b-8 and Table 3b-2' can also be omitted. The number of non-zero elements in a row can be known by the column where the non-zero elements are located, so the row weight is also known.

[0133] In one implementation, for the above Table 2, the parameter values ​​in the “column where the non-zero element is located” in Table 3b-1 to Table 3b-8 and Table 3b-2′, it is also possible not to arrange them in ascending order, as long as the parameter values ​​index the column where the non-zero element is located. In addition, for Table 2, the parameter values ​​in the “non-zero element offset value” in Table 3b-1 to Table 3b-8 are not necessarily arranged in the order of columns, as long as the parameter values ​​in the “non-zero element offset value” correspond one-to-one with the parameter values ​​in the “column where the non-zero element is located”.

[0134] In one implementation, the above different base matrices can be combined in one or more tables for representation. For example, the non-zero elements corresponding to different base matrices have the same position and row number, but the offset value V i,j Therefore, multiple base matrices can be represented by one table at the same time by listing the row number, the column where the non-zero element is located, and the offset value columns of multiple groups of non-zero elements. For example, two groups of non-zero element offset values ​​can be listed in different columns and indicated by indexes.

[0135] In one implementation, the positions of non-zero elements may be indicated by a base graph, and the parameter "column where the non-zero elements are located" in the above table may also be optional.

[0136] In one implementation, it can also be represented by parameters such as column number (column index), row where the non-zero element is located, and offset value of the non-zero element. Figure 3a , Figures 3b-1 to 3b-8 The matrix shown can optionally include column weights.

[0137] In another implementation, the base graph or base matrix can be regarded as binary numbers according to the 1 and 0 of each row or column, and the storage space can be saved by using decimal or hexadecimal numbers. Taking any of the above base graphs or base matrices as an example, the positions of the non-zero elements in the first 14 columns or the first 17 columns can be saved in hexadecimal numbers. For example, the first 14 columns of the 0th row are 11110010011100, and the positions of the non-zero elements in the 0th row can be recorded as 0xF2, 0x70, that is, every 8 columns form a hexadecimal number. For the last 2 columns, the corresponding hexadecimal numbers can be obtained by filling 0 to an integer multiple of 8 bits. Of course, the corresponding hexadecimal numbers can also be obtained by filling 0 to an integer multiple of 8 bits in front of it. The same is true for other rows, which will not be repeated here.

[0138] Figure 5 The design of the data processing process is given. The data processing process can be implemented by a communication device, which can be a base station, a terminal or other entities, such as a communication chip, an encoder / decoder, etc.

[0139] Part 501, obtain an input sequence. In one implementation, the encoded input sequence may be an information bit sequence, or an information bit sequence after padding, or a sequence after adding CRC. The information bit sequence is sometimes also referred to as a code block, for example, it may be an output sequence after the transmission block is divided into code blocks. In one implementation, the decoded input sequence may be a soft value sequence of an LDPC code. In this application, a sequence may sometimes be referred to as a bit sequence, for example, an input sequence may sometimes be referred to as an input bit sequence, a bit sequence to be encoded. An output sequence may sometimes be referred to as an output bit sequence, an encoded sequence, an encoded bit sequence. A check sequence may sometimes be referred to as a check bit sequence, etc.

[0140] In part 502, the input sequence is encoded / decoded based on an LDPC matrix; a base matrix of the LDPC matrix may be any base matrix in the aforementioned examples.

[0141] In one implementation, the LDPC matrix may be obtained based on the expansion factor Z and the base matrix.

[0142] In one implementation, the relevant parameters of the LDPC matrix may be saved, and these parameters may include one or more of the following: a) is used to obtain parameters in any base matrix listed in the above-mentioned implementation methods, and the base matrix can be obtained based on the parameters; for example, the parameters may include one or more of the following: row number, row weight, column number, column weight, position of non-zero elements (such as the row where the non-zero element is located, or the column where the non-zero element is located), offset value in the base matrix, non-zero element offset value and corresponding position, compensation value, expansion factor Z, base map, code rate, etc. b) any basis matrix listed in the above implementations; c) a compensation matrix Hs after at least one column of any base matrix listed in the above implementations is compensated; d) a matrix expanded based on the base matrix or its compensation matrix Hs; e) A base matrix after row / column transformation based on any base matrix or compensation matrix Hs listed in the above implementations. f) A matrix expanded based on the base matrix or the compensation matrix Hs after the row / column transformation. g) A matrix after truncating or puncturing any base matrix or compensation matrix Hs listed in the above implementations.

[0143] In a possible implementation, encoding / decoding the input sequence based on the low-density parity check LDPC matrix may be performed in one or more of the following ways during the encoding / decoding process: i. Based on the above a), a base matrix is ​​obtained, and encoding / decoding is performed based on the obtained base matrix; or rows / columns are exchanged based on the obtained base matrix, and encoding / decoding is performed based on the base matrix after row / column transformation, or encoding / decoding is performed based on the compensation matrix of the obtained base matrix, or encoding / decoding is performed based on the matrix after row / column transformation of the compensation matrix Hs of the obtained base matrix. Here, encoding / decoding based on the base matrix or the compensation matrix Hs may optionally include encoding / decoding based on the extended matrix of the base matrix or the extended matrix of the compensation matrix Hs, or encoding / decoding based on the matrix after truncating or puncturing the base matrix or the compensation matrix; ii. Encoding / decoding based on the base matrix stored in b), c), d), or e) (storing the base matrix H or Hs, or storing the base matrix after the row / column transformation based on the base matrix H or Hs), or performing row / column transformation based on the stored base matrix, and encoding / decoding based on the base matrix after the row / column transformation. Here, encoding / decoding based on the base matrix or the compensation matrix Hs may optionally include encoding / decoding based on the extended matrix of the base matrix or the extended matrix of the compensation matrix Hs, or encoding / decoding based on the matrix after truncating or puncturing the base matrix or the compensation matrix; iii. Encode / decode based on d), f) or g).

[0144] In part 503, the encoded / decoded bit sequence is output. In one design, the input sequence c={c 0 ,c 1 ,c 2 ,...,c K-1} is encoded to obtain the output sequence d = {d 0 ,d 1,d 2 ,...,d N-1}, where K and N are integers greater than 0; the output sequence d includes K in the input sequence c 0 bits and the check bits in the check sequence w, K 0 is an integer, and 0 <K 0 ≤K; the check sequence w and the input sequence c satisfy the formula Among them, c T =[c 0 ,c 1 ,c 2 ,...,c K-1 ] T , is the transposed vector of the vector composed of each bit in the input sequence c, is the transposed vector of the vector composed of each bit in the check sequence w, 0 T is a column vector, all elements of which have a value of 0; H is a low-density parity check LDPC matrix, and the base graph of H includes H BG and H BG,EXT ,in Indicates m c ×n c An all-zero matrix of size , Indicates n c ×n c The identity matrix of size, H BG Including H BG2 The columns corresponding to the Kb columns of information bits, and H BG2 10th to 10+m A -1 column, H BG2 The number of columns is 10+m A Column, 4≤m A ≤7, where Kb∈{6,8,9,10}; where m c =7,0≤n c ≤35, H BG2 The number of columns is equal to 17, or m c =6,0≤n c ≤36, H BG2 The number of columns is equal to 16, or, m c =5,0≤n c ≤37, H BG2 The number of columns is equal to 15, or m c =4,0≤n c ≤38, H BG2 The number of columns is equal to 14.

[0145] Figure 6 A design for processing data is given, which can be used to Figure 5 502 section.

[0146] In part 601, an expansion factor Z is obtained. In a possible design, the information bit sequence may be padded to obtain an input sequence, so that the length of the input sequence K=K b ·Z, Z=K / K b . In another possible design, the bits that need to be punctured or truncated in the information bit sequence can be padded, that is, the bits that need to be punctured or truncated can be replaced with padding bits. After encoding, these padding bits can be identified and not sent. For example, Null, or a value of 0, or a system-agreed value, or a predetermined value can be used as the value of the padding bit. In one design, the bits that need to be punctured do not need to be padded and can be directly punctured. Punctured bits can also be padded with null to occupy placeholders during encoding. In one possible design, padding is performed after the information bit sequence.

[0147] In one implementation, the expansion factor Z may be determined based on the length K of the input sequence. For example, the smallest Z may be found in the set of supported expansion factors. 0 As the size of the expansion factor Z, and satisfy Kb·Z 0 ≥ K. In one possible design, Kb may be the number of columns of information bits in the base matrix of the LDPC code. For base graph 30a, the number of columns of information bits Kb max =10, assuming that the expansion factor set supported by base graph 30a is {24, 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96, 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288, 320, 352, 384}. If the length of the input sequence K = 529 bits, Z is 26, and if the length of the input sequence K = 5000 bits, Z is 240. It should be noted that this is only an example and is not intended to be limiting.

[0148] For another example, the value of Kb may also vary according to the value of K, but may not exceed the number of information bit columns in the base matrix of the LDPC code. For example, different thresholds may be set for Kb.

[0149] In one design, it should be noted that the threshold values ​​640, 560, and 192 are only examples and can also be designed to other values ​​according to system design requirements. if(K>640),Kb=10; elseif(K>560),Kb=9; elseif(K>192),Kb=8; else Kb=6;end

[0150] The expansion factor Z may be determined by the communication device according to the length K of the input sequence, or may be obtained by the communication device from other entities (such as a processor).

[0151] In part 602, an LDPC matrix is ​​obtained based on the expansion factor and the base matrix. The base matrix is ​​any base matrix listed in the foregoing embodiments, or a compensation matrix obtained by compensating at least one column of any base matrix listed in the foregoing embodiments, or a base matrix in which the row order is changed, the column order is changed, or both the row order and the column order are changed relative to any base matrix or compensation matrix listed in the foregoing embodiments, and its base graph includes at least submatrix A and submatrix B. Optionally, submatrix C, submatrix D and submatrix E may also be included, and each part may refer to the description in the foregoing embodiments, which will not be repeated here. The base matrix may be obtained based on the base graph and the offset value, or may be obtained by storing any base matrix listed in the foregoing embodiments, or may be obtained by deforming any base matrix listed in the foregoing embodiments.

[0152] In a possible implementation, a corresponding base matrix is ​​determined according to the expansion factor Z, and the base matrix is ​​permuted according to the expansion factor Z to obtain an LDPC matrix.

[0153] In one implementation, the LDPC matrix H may be obtained based on the correspondence between the extension factor and the base matrix. For example, based on the extension factor Z obtained in part 601, the corresponding base matrix is ​​determined.

[0154] For example, if Z is 26 and a=13, the basis matrix may include Figure 3b-7 The matrix shown in FIG. 1 includes rows 0 to 6 and columns 0 to 16, or the base matrix includes Figure 3b-7 The matrix shown in FIG. 1 may further include rows 0 to 6 and columns 0 to 16 of the matrix; further, or the base matrix also includes rows 0 to m-1 and columns 0 to n-1 of the matrix, wherein 7≤m≤42, m is an integer, 17≤n≤52, n is an integer, or the base matrix includes Figure 3b-7 The 0th to m-1th rows and the 0th to n-1th columns of the matrix shown, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer, Figure 3b-7 The rows from row 7 to row 41 and the columns from column 17 to column 61 of the matrix shown in FIG. The LDPC matrix is ​​obtained by permuting the base matrix according to the expansion factor Z. It should be noted that here only Z=26, a=13, Figure 3b-7 The matrix shown is used as an example. This is only an example, and the present invention is not limited thereto. It can be understood that different expansion factors will result in different base matrices.

[0155] In a possible implementation, the correspondence between the expansion factor and the base matrix can be shown in Table 4, and the base matrix index corresponding to the expansion factor is determined according to Table 4. In a possible design, PCM1 can be as follows Figure 3b-1 The matrix shown; PCM2 can be Figure 3b-2 The matrix shown; PCM3 can be Figure 3b-3 The matrix shown; PCM4 can be Figure 3b-4 The matrix shown; PCM5 can be as follows Figure 3b-5 The matrix shown; PCM6 can be as follows Figure 3b-6 The matrix shown; PCM7 can be as follows Figure 3b-7 The matrix shown; PCM8 can be as Figure 3b-8 The matrix shown here is only an example and is not intended to be limiting. Table 4

[0156] In another design, the following method can also be adopted:

[0157] Furthermore, in a possible design, for the expansion factor Z, the element P in the i-th row and j-th column of the basis matrix is i,j The following relationship can be satisfied: Among them, V i,j It can be the offset value of the element in the i-th row and j-th column in the basis matrix of the set where the expansion factor Z is located, or the offset value of the non-zero element in the i-th row and j-th column of the basis matrix of the maximum expansion factor in the set where the expansion factor Z is located.

[0158] For example, taking Z as 13, the element P in the i-th row and j-th column of the basis matrix is i,j satisfy Among them, V i,j is the offset value of the non-zero element in the i-th row and j-th column of PCM7 matrix 3b-7. For Z=13, the offset value V of the non-zero element in the i-th row and j-th column of matrix 3b-7 needs to be i,j Modulo Z = 13. It should be noted that this is only an example and the present invention is not limited thereto.

[0159] In section 603, the input sequence is encoded / decoded based on the LDPC matrix.

[0160] In one implementation, the input sequence for encoding may be an information bit sequence. In another implementation, the input sequence for decoding may be a soft value sequence of an LDPC code, which may be referred to as Figure 5 When encoding / decoding the input sequence, the LDPC matrix H can be obtained by expanding the base matrix according to Z. For each non-zero element P in the base matrix i,j , determine the circulant permutation matrix h of size Z*Z i,j , where h i,j The identity matrix is ​​P i,j The cyclic permutation matrix obtained by cyclic shift is h i,j Replace the non-zero elements P i,j , replace the basis matrix H with a Z*Z size all-zero matrix B The zero elements in , thus obtaining the parity check matrix H;

[0161] In a possible implementation, the base matrix of the LDPC code may be stored in a memory, and the communication device obtains the LDPC matrix corresponding to the expansion factor Z, thereby encoding / decoding the input sequence.

[0162] In one possible implementation, since there are multiple basis matrices of the LDPC code, saving them in a matrix structure will take up a large storage space. Alternatively, the base graph of the LDPC code can be saved in a memory, and the offset values ​​of the non-zero elements in each basis matrix can be saved row by row or column by column. Then, the LDPC matrix is ​​obtained according to the offset value of the base matrix corresponding to the base graph and the expansion factor Z.

[0163] In a possible implementation, the offset values ​​of the non-zero elements in each base matrix can also be saved in the manner of Table 2, Table 3b-1 to Table 3b-8 as the parameters of the LDPC matrix. The "row weight" column is optional, that is, the "row weight" column can be optionally saved or not saved. Through the column where the non-zero elements of a row are located, it is known how many non-zero elements there are in this row, so the row weight is also known. In a possible implementation, for the above Table 2, Table 3b-1 to Table 3b-8, the parameter values ​​in the "column where the non-zero elements are located" may not be arranged in order from small to large, as long as the parameter value indexes the column where the non-zero elements are located. In addition, for Table 2, the parameter values ​​in the "non-zero element offset value" in Table 3b-1 to Table 3b-8 are not necessarily arranged in the order of columns, as long as the parameter values ​​in the "non-zero element offset value" correspond one-to-one with the parameter values ​​in the "column where the non-zero elements are located", the communication device can know which row and column the non-zero element offset value corresponds to. For example, in one implementation, the column number, the row where the non-zero element is located, or the row where the zero element is located can be used. Similar to Table 2, the formats of Tables 3b-1 to 3b-8 are not listed here one by one.

[0164] In one possible implementation, reference may be made to Figure 5 The relevant description in saves the relevant parameters of the LDPC matrix.

[0165] In a possible implementation, when saving the relevant parameters of the LDPC matrix, it is also possible not to save Figure 3a , all rows of the matrices shown in Table 2, Table 3b-1 to Table 3b-8, or all rows of the matrices shown in Table 2, Table 3b-1 to Table 3b-8, can save the parameters indicated by the corresponding rows in the table according to the rows included in the base matrix. For example, the matrix composed of the rows and columns included in the base matrix of the LDPC matrix described in the above embodiment, or the relevant parameters involved in the matrix composed of the rows and columns can be saved.

[0166] For example, if Figure 3b-1 to Figure 3b-8 The 0th to 6th rows and the 0th to 16th columns in the matrix, then, the matrix composed of the 0th to 6th rows and the 0th to 16th columns can be saved, and / or the relevant parameters of the matrix composed of the 0th to 6th rows and the 0th to 16th columns can be saved, and the parameters shown in Tables 3b-1 to 3b-8 and the above partial description can be referred to.

[0167] if Figure 3b-1 to Figure 3b-8 In any matrix of the 0th to (m-1)th rows and the 0th to (n-1)th columns, where 7≤m≤42, m is an integer, 17≤n≤52, n is an integer, then, the matrix formed by the 0th to (m-1)th rows and the 0th to (n-1)th columns can be saved, and / or the relevant parameters of the matrix formed by the 0th to (m-1)th rows and the 0th to (n-1)th columns can be saved, and reference can be made to the parameters shown in Tables 3b-1 to 3b-8 and the description of the above part.

[0168] In a possible implementation, the compensation value Offset may be increased or decreased for each offset value greater than or equal to 0 indicated by position s in at least one “column where the non-zero element is located” in any of Table 2, Table 3b-1 to Table 3b-8. s It should be noted that these are just examples and are not intended to be limiting.

[0169] by Figure 1 For example, in one implementation, the basis matrix H is determined B After that, we can first pass the input sequence and the 0th to 3rd rows and 0th to 9th columns of the basis matrix, that is, H core-dual The parity bits corresponding to the 10th to 15th columns are obtained; then according to the input sequence and H core-dualThe corresponding check bits are obtained in the 16th column, that is, the check bits corresponding to the single column re-column; then, the check bits corresponding to the submatrix E are obtained according to the input sequence and the check bits corresponding to the 10th to 16th columns and the partial coding corresponding to the submatrix D, thereby completing the encoding. The encoding process of the LDPC code can be described with reference to the aforementioned implementation method, which will not be repeated here.

[0170] In one design, the above-mentioned parts 502 and 603 encode / decode the input sequence based on the LDPC matrix, and can use the LDPC matrix H corresponding to the expansion factor Z to encode the input sequence.

[0171] In a possible implementation, LDPC encoding may be implemented in the following manner.

[0172] 1) The input sequence to be encoded is represented as c = {c 0 ,c 1 ,c 2 ,...,c K-1}, the length of the input sequence c is K, and the output sequence obtained after the input sequence c is encoded by the encoder is expressed as d = {d 0 ,d 1 ,d 2 ,...,d N-1}, K is an integer greater than 0, and K can be an integer multiple of the expansion factor Z, for example, 5 times, 6 times, 7 times, 8 times, 9 times, 10 times, 19 times, 20 times, 21 times, 22 times, etc. The expansion factor of the input sequence c can be expressed as Z or Z c , the subscript c is used to indicate the input sequence c. c Sometimes mixed, the technical personnel in this field can understand its meaning. Optionally, other parameters in this implementation can also be added or not added with subscript index. It does not affect the essential meaning of the parameter. The technical personnel in this field can understand its meaning. Where N = 50Z, or N = (40 + K b )·Z. The length of the input sequence c is K, and the length of the output sequence d is N. The output sequence N can include K of the input sequence c. 0 bits and check sequence w in NK 0 K 0 is an integer, and 0 <K 0 ≤K. The check sequence w can be expressed as {w 0 ,w 1 ,w 2 ,…,w N-K0-1}, length is NK 0In one design, if the LDPC matrix H includes p columns of built-in puncturing columns, p is an integer greater than or equal to 0, the p columns of built-in puncturing columns do not participate in encoding, or participate in encoding but the information bits corresponding to the p columns of built-in puncturing columns are not output. That is, the output sequence does not include the information bits corresponding to the p columns of built-in puncturing columns, then K 0 =KP*Z. For example, p=2, and the output sequence d includes K-2Z bits in c, then the length of the check sequence w is N+2Z-K, and the check sequence w can be expressed as {w 0 ,w 1 ,w 2 ,…,w N+2Z-K-1 If the p-column internal puncturing column participates in the encoding, the length of the check sequence w is NK, and the check sequence w can be expressed as {w 0 ,w 1 ,w 2 ,…,w N-K-1}.

[0173] The value of Kb can refer to the above design. For example: if(K>640),K b =10; elseif(K>560),K b =9; elseif(K>192),K b =8; else K b =6; end

[0174] 2) According to Z c =K / K b , determine the PCM index corresponding to the bit segment length K, or the expansion factor group index, for example, you can refer to Table 1 and Table 2 to determine the expansion factor Z c (Also can be expressed as Z).

[0175] 3) Give the encoded bit sequence d = {d 0 ,d 1 ,d 2 ,...,d N-1}Middle front K-2Z c Here, we need to skip the first 2Z bits of the bit segment to be encoded. c padding bits, and it is necessary to consider that the bit segment to be encoded may contain padding bits.

[0176] In one implementation, the following method can be used for assignment: Where k is an index value, and k is an integer, and <NULL> indicates padding bits. In one implementation, the padding bits are filled with null to occupy a place, so the padding bits are sometimes also called placeholder bits. The value of the padding bits can be 0 or other predetermined values, which are not limited in this application. Optionally, the padding bits may not be sent.

[0177] 4) Generate a check bit sequence w so that the check bit sequence w satisfies the following formula: In formula (1), c=[c 0 ,c 1 ,c 2 ,...,c K-1 ] T , 0 represents a column vector, in which all elements have a value of 0, and the matrix H represents the LDPC check matrix. c=[c 0 ,c 1 ,c 2 ,...,c K-1 ] T is the transposed vector of the vector composed of each bit in the input sequence. In formula (1), w=w T , is the transposed vector of the vector composed of each bit in the check sequence w. For example, the length is N+2Z c -K's check sequence w is represented by {w 0 ,w 1 ,w 2 ,…,w N+2Zc-K-1}, w in formula 1 = [w 0 ,w 1 ,w 2 ,…,w N+2Zc-K-1 ] T For another example, the check sequence with a length of NK-1 is expressed as {w 0 ,w 1 ,w 2 ,…,w N-K-1}, w in formula 1 = [w 0 ,w 1 ,w 2 ,...,w N-K-1 ] T In formula (1), H is any LDPC matrix based on the examples in the above embodiments. In a possible implementation, H can be divided into H 1 and H 2 Two parts are used to represent, for example, H = [H 1 H 2 ].

[0178] In one implementation, H can be obtained based on any base graph listed in the above embodiments and the extended matrix of Zc*Zc. Each zero element in the base graph is replaced by the all-zero matrix of Zc*Zc, and the elements with a value of 1 in the base graph are replaced by their offset value P i,j The corresponding Z*Z circulant permutation matrix I(P i,j ) is replaced, where i and j represent the row index and column index of the element. The circulant permutation matrix I(P i,j ) By moving the matrix Zc*Zc to the right or left i,j The result is obtained by cyclic shift. i,j =mod(V i,j ,Z c ), V i,j are the offset values ​​in the basis matrix corresponding to the non-zero elements in the basis graph.

[0179] In one implementation, H 1 The part may be the A, B, D part of the base graph or base matrix listed in the above embodiment, that is, Figure 3a , rows 0 to 41 and columns 0 to 16 in 3b-1 to 3b-8.

[0180] In one implementation, H 1 The part may be a part of the rows and columns in the A, B, and D parts of the base graph or base matrix listed in the above embodiments, for example, rows 0 to 41 and columns 0 to 13, or rows 0 to 41 and columns 0 to 14, or rows 0 to 41 and columns 0 to 15, or rows 1 to 41 and columns 0 to 13, etc.

[0181] In one implementation, H 1 The part may be m rows and n columns of the base graph or base matrix listed in the above embodiments, for example, m=7, n=35; or m=4, n=38; or m=5, n=37; or m=6, n=36.

[0182] In one implementation, according to the value of Kb, the input length of the encoder is Kb*Z. If Kb<9, the matrix H is deleted. 1 The first {K b ,K b+1 ,...,9} columns and then encode them.

[0183] In one implementation, H may be M rows and (N+p·Z) columns or M rows and N columns, and the size of its basis matrix is ​​m=M / Z. Or n=N / Z.

[0184] In one implementation, H 2 Part can be expressed as Where 0 m×nRepresents an m×n matrix of all zeros (m rows, n columns), for example, 7 rows and 35 columns, or 4 rows and 38 columns, or 5 rows and 37 columns, or 6 rows and 36 columns, etc. n×n Represents an n×n (n rows, n columns) matrix, for example, it can be 35 rows and 35 columns, or 36 rows and 36 columns, or 37 rows and 37 columns, or 38 rows and 38 columns, etc.

[0185] In one implementation, when encoding is performed using the H matrix, the encoding may be performed based on any of the base graphs or base matrices described above. Figure 3a ,or Figures 3b-1 to 3b-8 The matrix with rows 0 to 41 and columns 0 to 16 in any matrix in can also be based on Figure 3a ,or Figures 3b-1 to 3b-8 The matrix with rows 0 to 41 and columns 0 to 13 in any matrix in , etc.

[0186] In one design, for K b ∈{6,8,9}, the H matrix can be any of the above-mentioned base graphs or base matrices by removing {K b ,K b +1,...,9} columns, for K b =10, which can be any of the aforementioned base graphs or base matrices.

[0187] The offset value V in the check matrix H i,j Through the above Figures 3b-1 to 3b-8 , or Table 3b-1 to Table 3b-8 and 3b-2', or any of the above described methods. Based on the index of the check matrix, which can sometimes be considered as the group index of the extension factor, it is possible to know which check matrix it corresponds to, and thus know the corresponding offset value V i,j .

[0188] In one design, H includes p columns of built-in puncturing columns, where p is an integer greater than or equal to 0, and the p columns of built-in puncturing columns do not participate in encoding. Or they participate in encoding but the information bits corresponding to the p columns of built-in puncturing columns are not output. That is, the output sequence d does not include the information bits corresponding to the p columns of built-in puncturing columns, then K 0 =Kp·Z. For example, p = 2, then K 0 =K-2·Z, the output sequence d includes K-2Z bits in the input sequence c, and the length of the check sequence w is N+2Z c -K. If the p column contains a punctured column, the length of the check sequence w is NK.

[0189] In one design, 0 m×nIt can be the submatrix C in the aforementioned embodiments, or the submatrix C plus the last column of the submatrix B, or the submatrix C plus the last two columns of the submatrix B, or the submatrix C plus the last three columns of the submatrix B.

[0190] I n×n It can be the submatrix E in the aforementioned embodiments, or the submatrix E plus the last column of the submatrices B and D, or the submatrix E plus the last two columns of the submatrices B and D, or the submatrix E plus the last three columns of the submatrices B and D.

[0191] 5) Optional, for k = K to N + 2Z c -1,d k-2Zc =w k-K .

[0192] In the above various implementations, the encoder can use a variety of methods to encode and output. Figure 3a , Figures 3b-1 to 3b-8 Any of the base graphs or base matrices shown is taken as an example for explanation, wherein the maximum number of base graph rows is 42, and the maximum number of columns is 52, including 2 built-in perforated columns. For the convenience of description, in the present invention, the base graph / base matrix with the largest number of rows and the largest number of columns is sometimes referred to as a complete base graph or base matrix, and the base graph / base matrix from which 2 built-in perforated columns are deleted from the complete base graph / base matrix is ​​referred to as a complete base graph / base matrix without built-in perforated columns.

[0193] Method 1: Based on the complete basemap / base matrix or the complete basemap / base matrix without the built-in puncturing column, the encoding is performed to obtain as many check bits as possible. At this time, m=42. If the built-in puncturing column is involved in the encoding, then n=52, which is the above Figure 3a , Figures 3b-1 to 3b-8 The 0th to 41st rows and the 0th to 51st columns of any matrix in ; if the built-in punctured columns are not involved in the encoding, then n = 51, that is, the 0th to 41st rows and the 2nd to 51st columns. Correspondingly, for the LDPC matrix H, M = 41Z, N = 52Z or N = 51Z. The information bits and check bits to be sent can be determined from the output sequence generated by the encoder in the subsequent processing link.

[0194] Method 2: Based on partial row and column coding of the complete base image. Row and column coding can be selected from the complete base image or the complete base image without built-in puncturing columns according to the code rate required to be sent, or the number of information bits and check bits. For example, the code rate is 2 / 3, m = 7, if the built-in puncturing columns are involved in the coding, then n = 17, that is, based on the above Figure 3a , Figures 3b-1 to 3b-8Partial encoding of rows 0 to 6 and columns 0 to 16 of any matrix in ; if the built-in punctured columns are not involved in the encoding, then n = 15, that is, Figure 3a , Figures 3b-1 to 3b-8 The 0th to 6th rows and the 2nd to 16th columns of any matrix in .

[0195] In one possible design, the above example Figure 3a , Figures 3b-1 to 3b-8 The 14th to 51st columns of any matrix in the core matrix are single-column re-columns. One or more columns of the single-column re-columns in the core matrix can be punctured so that the core matrix corresponds to one or more columns. For example, if m is 6, if the built-in punctured columns are involved in the encoding, n = 16, based on the above Figure 3a , Figures 3b-1 to 3b-8 Partial coding of rows 0 to 6 and columns 0 to 15 in any matrix in the matrix. In one implementation, the internal puncturing columns may not be involved in the coding, so that a higher code rate can be obtained.

[0196] It should be noted that the above is an explanation of the principle of the H matrix. When adopting the solution provided by the embodiment of the present invention, the H matrix can also be transformed in various ways to achieve the desired result, as long as the generated check bits satisfy formula (1):

[0197] One possible implementation is that the H matrix is ​​Quasi-Cycle (QC) expanded before use. Another possible implementation is that the H matrix is ​​Quasi-Cycle (QC) expanded on the part corresponding to the current element to be processed during use.

[0198] One possible implementation method is (directly calculating the offset value) that the H matrix is ​​not directly expanded during use, but an expandable equivalent formula method is used to calculate the connection relationship between the rows and columns of the matrix.

[0199] One possible implementation method is that the H matrix may not be expanded. During the encoding process, for each element to be processed, the corresponding bit segment to be encoded is shifted according to the offset value of the element; then, the encoding operation is directly performed on all the bit segments that have undergone the shift operation.

[0200] One possible implementation method is to predefine or system-define the basis matrix PCM without obtaining the basis matrix based on the basis graph. Figures 3b-1 to 3b-8 The provided base matrix obtains the matrix of LDPC, or the matrix of LDPC is obtained based on the corresponding Tables 3b-1 to 3b-8.

[0201] In the implementation process, the transmitting end or the receiving end can store the complete matrix, that is, all parts of ABCDE. It is also possible not to store the complete matrix to save storage space. For example, only a part of it or its corresponding parameters need to be stored to implement encoding and decoding. Compared with the method of storing the complete matrix, storing only a part of the matrix can reduce the overhead of the storage device in the encoder. For details, please refer to the description in the above embodiment.

[0202] For example, in one implementation, the ABD part of the matrix is ​​stored, or the single-column re-part is not included in ABD. In the actual encoding and decoding process, the values ​​of the C and E parts or the single-column re-part are calculated by formula. That is, only the first 17 columns or the first 14 columns of the original complete matrix are saved. Since the C part is an all-zero matrix, it can be directly obtained, and the E part is a unit matrix. The position of its non-0 elements can be calculated according to the row number currently being processed to obtain the corresponding column number. For example, when the current processing behavior is the 18th row, the corresponding non-0 element of the E part is located in the 28th column. When the current processing behavior is the 19th row, the corresponding non-0 element of the E part is located in the 29th column, and so on. When the positions of all non-zero elements of the E part are obtained by calculation, the calculation results can be saved or not saved, and then calculated when the corresponding rows and columns are calculated during the encoding or decoding process.

[0203] In another implementation, the first 14 columns of the original complete matrix are stored. In the unstored portion on the right side of the matrix, the position of the non-zero element in the unstored portion can be directly obtained by calculation. For example, when the current processing behavior is the 4th row, the non-zero element corresponding to the stored portion is located in the 14th column, and when the current processing behavior is the 5th row, the non-zero element corresponding to the stored portion is located in the 15th column, and so on. When the positions of all non-zero elements in the unstored portion of the matrix are obtained by calculation, the calculation results can be saved or not saved, and then calculated when the corresponding rows and columns are calculated during the encoding or decoding process.

[0204] In another implementation, the first 14+x columns of the original complete matrix are stored. In the unstored portion on the right side of the matrix, the first 4 rows are a full-zero matrix, and the rest are a unit matrix. The positions of the non-zero elements in the unstored portion can be directly obtained by calculation. For example, when the current processing line is the (3+x)th row, the non-zero elements corresponding to the bit storage part are located in the (14+x)z column, and when the current processing line is the (3+x)+1th row, the non-zero elements corresponding to the E part are located in the (14+x)z+1 column, and so on. When the positions of all the non-zero elements in the unstored portion of the matrix are obtained by calculation, the calculation results can be saved or not saved, and then calculated when the corresponding rows and columns are calculated during the encoding or decoding process.

[0205] In yet another implementation, when storing the offset value matrix, the values ​​recorded in the offset value matrix may be directly stored, or the values ​​obtained by performing a simple mathematical transformation on the offset value matrix values ​​described in the present application may be stored.

[0206] In one implementation, the values ​​of the offset value matrix are transformed before being stored. When transforming, the transformation is performed row by row starting from the first row in the current offset value matrix. If the element encountered represents an all-zero matrix (such as -1), it is directly stored without transformation; if the element encountered represents a non-all-zero matrix (non-negative element), and the element is the first element in the column that represents a non-all-zero matrix (non-negative element), it is directly stored without transformation; if the element encountered represents a non-all-zero matrix (non-negative element), and the element is not the first element in the column that represents a non-all-zero matrix (non-negative element), the difference between the non-negative element and the previous element in the same column that represents a non-all-zero matrix is ​​saved, and the difference is positive, indicating a right shift, and if the difference is negative, it indicates a left shift.

[0207] It should be noted that similar transformations do not have to start from the first row in the offset value matrix, but can start from any row. After similar transformations are performed to the last row of the matrix, the loop returns to the first row and continues to transform downwards. And this way of storing the difference may be different for different expansion factors Z, and needs to be changed through P i,j =mod(V i,j ,Z c ) calculates the actual offset value and then calculates the difference.

[0208] During the encoding and decoding process, the offset value before the transformation can be restored by recursive calculation based on the value of the previous element in the same column; or the relative offset value can be directly used for encoding and decoding.

[0209] In one implementation, the values ​​of the value matrix V may also be offset i,j The transformation is performed before storage. During the transformation operation, the positions and values ​​of all elements in the matrix representing all-zero matrices (such as -1) are kept unchanged. For elements representing non-all-zero matrices (non-negative elements), assuming that their original values ​​are Vij, the transformed values ​​are (z-Vij) mod z. In the actual encoding and decoding process, the unit matrix is ​​left-shifted (originally right-shifted) based on the transformed offset value to achieve normal encoding and decoding.

[0210] In one implementation, the value V of the offset value matrix i,j After transformation, the data is stored. During the transformation operation, the original decimal offset value is transformed into other bases, such as binary, octal, hexadecimal, etc. During the encoding and decoding process, the transformed offset value matrix can be restored and then encoded and decoded; or the transformed offset value matrix can be directly used for encoding and decoding.

[0211] In one implementation, the encoding end does not store the check matrix, but stores the generator matrix that may be needed for encoding. Assume that the bit segment to be encoded is c=c 0 ,c 1 ,c 2 ,c 3 ,...,c K-1 , the encoded bit segment is d = d 0 ,d 1 ,d 2 ,...,d N-1 , then the generator matrix G satisfies: d = c·G Among them, the generator matrix can be obtained by transforming the check matrix H. For the check matrix H, the right side can be transformed into a diagonal matrix form by row-column transformation, which is expressed as: H=[PI] (2) Then, the corresponding generator matrix G satisfies: G=[IP T ] (3) The check matrix H can be any check matrix or base matrix described in the above embodiments, or an LDPC matrix. When encoding, the stored generator matrix G can be used, and the bit segment to be encoded is c=c 0 ,c 1 ,c 2 ,c 3 ,...,c K-1 Directly calculate the encoded bit segment d = d 0 ,d 1 ,d 2 ,...,d N-1 .

[0212] In one implementation, when encoding, the dual diagonal part of the matrix may be encoded using any of the above methods, or may be encoded using a method of storing a matrix with multiple rows superimposed.

[0213] In one implementation, for each expansion factor Z, according to P i,j =mod(V i,j ,Z c ) calculates the corresponding offset value matrix, and then stores the matrices corresponding to the 51 expansion factors for encoding and decoding.

[0214] Optionally, in a communication system, the above method may be used to encode and obtain an LDPC code. After obtaining the LDPC code, the communication device may also perform one or more of the following operations: rate matching the LDPC code; interleaving the rate-matched LDPC code according to an interleaving scheme; modulating the interleaved LDPC code according to a modulation scheme to obtain a bit sequence X; and sending the bit sequence X.

[0215] Decoding is the inverse process of encoding, and the base matrix used in the decoding process has the same characteristics as the base matrix used in the encoding process. The encoding process of the LDPC code can refer to the aforementioned implementation description and will not be repeated here. In one implementation, before decoding, the communication device may also perform one or more of the following operations: receiving a signal, the signal containing information based on LDPC encoding, demodulating the signal, deinterleaving and rate matching to obtain a soft value sequence of the LDPC code, and decoding the soft value sequence of the LDPC code. When decoding, decoding may also be performed based on a complete base graph or a complete base graph that does not include built-in punctured columns, or decoding may be performed based on partial rows and columns of the complete base graph.

[0216] The storage involved in this application may refer to storage in one or more memories. The one or more memories may be set separately or integrated in an encoder or decoder, a processor, a chip, a communication device, or a terminal. The one or more memories may also be partially set separately and partially integrated in a decoder, a processor, a chip, a communication device, or a terminal. The type of memory may be any form of storage medium, which is not limited by this application.

[0217] Corresponding to Figure 5 , Figure 6 The embodiment of the present invention also provides a corresponding communication device, which includes a communication device for executing Figure 5 or Figure 6 The module may be software, hardware, or a combination of software and hardware. For example, the module may include a memory, an electronic device, an electronic component, a logic circuit, etc., or any combination thereof. Figure 7 A schematic diagram of the structure of a communication device 700 is provided, and the device 700 can be used to implement the method described in the above method embodiment, and the description in the above method embodiment can be referred to. The communication device 700 can be a chip, a base station, a terminal or other network equipment.

[0218] The communication device 700 includes one or more processors 701. The processor 701 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process the communication protocol and communication data, and the central processing unit may be used to control the communication device (such as a base station, a terminal, or a chip, etc.), execute a software program, and process the data of the software program.

[0219] In one possible implementation, such as 5, Figure 6 One or more modules in the embodiment may be implemented by one or more processors, or one or more processors and memories.

[0220] In one possible design, the communication device 700 includes one or more processors 701, and the one or more processors 701 can implement the above-mentioned encoding / decoding functions. For example, the communication device can be an encoder or a decoder. In another possible design, the processor 701 can implement other functions in addition to implementing the encoding / decoding function.

[0221] The communication device 700 encodes / decodes the input sequence based on the LDPC matrix; the base matrix of the LDPC matrix can be any base matrix in the aforementioned examples, or a base matrix with a row order changed, a column order changed, or both a row order and a column order changed relative to any base matrix in the aforementioned examples, or a base matrix that is truncated or punctured based on any base matrix in the aforementioned examples, or a matrix that is expanded based on any base matrix in the aforementioned examples. For information on the encoding / decoding process, please refer to Figure 5 and Figure 6 The description of the relevant parts will not be repeated here.

[0222] Optionally, in one design, the processor 701 may include instructions 703 (sometimes also referred to as codes or programs), which may be executed on the processor so that the communication device 700 performs the methods described in the above embodiments. In another possible design, the communication device 700 may also include a circuit, which may implement the encoding / decoding functions in the above embodiments.

[0223] Optionally, in one design, the communication device 700 may include one or more memories 702 on which instructions 704 are stored. The instructions may be executed on the processor so that the communication device 700 performs the method described in the above method embodiment.

[0224] Optionally, data may also be stored in the memory. The optional processor may also store instructions and / or data. The processor and memory may be provided separately or integrated together.

[0225] Optionally, the “saving” described in the above embodiment may be saving in the memory 702 , or saving in the memory or storage device of other peripherals.

[0226] For example, one or more storages 702 may store parameters related to the LDPC matrix listed above, such as a base matrix, or a matrix expanded based on the base matrix, or parameters related to the base matrix, such as an offset value, a base graph, a matrix expanded based on the base graph, each row in the base matrix, an expansion factor, the position of non-zero elements, the offset value corresponding to the non-zero element, etc. For details, see the above Figure 5 Part of the description.

[0227] Optionally, the communication device 700 may further include a transceiver 705 and an antenna 706. The processor 701 may be referred to as a processing unit, which controls the communication device (terminal or base station). The transceiver 505 may be referred to as a transceiver unit, a transceiver, a transceiver circuit, or a transceiver, etc., which is used to implement the transceiver function of the communication device through the antenna 506.

[0228] Optionally, the communication device 700 may further include a device for generating a transport block CRC, a device for code block segmentation and CRC checking, an interleaver for interleaving, a device for rate matching, or a modulator for modulation processing, etc. The functions of these devices may be implemented by one or more processors 701.

[0229] Optionally, the communication device 700 may further include a demodulator for demodulation operation, a deinterleaver for deinterleaving, a device for rate matching, or a device for code block concatenation and CRC check, etc. The functions of these devices may be implemented by one or more processors 701 .

[0230] Figure 8 A schematic diagram of a communication system 800 is provided, wherein the communication system 800 includes a communication device 80 and a communication device 81, wherein information data is received and sent between the communication device 80 and the communication device 81. The communication devices 80 and 81 may be the communication device 700, or the communication devices 80 and 81 may include the communication device 700 respectively, and receive and / or send information data. In one example, the communication device 80 may be a terminal, and the corresponding communication device 81 may be a base station; in another example, the communication device 80 may be a base station, and the corresponding communication device 81 may be a terminal.

[0231] It is also known to those skilled in the art that the various illustrative logical blocks and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art can use various methods to implement the functions described for each specific application, but such implementation should not be understood as exceeding the scope of protection of the embodiments of the present invention.

[0232] The technology described in this application can be realized in various ways. For example, these technologies can be realized in a combination of hardware, software or hardware. For hardware implementation, the processing unit for executing these technologies at a communication device (for example, a base station, a terminal, a network entity or a chip) can be implemented in one or more general-purpose processors, digital signal processors (DSPs), digital signal processing devices (DSPDs), application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any traditional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration to implement.

[0233] The steps of the method or algorithm described in the embodiments of the present invention may be directly embedded in hardware, instructions executed by a processor, or a combination of the two. The memory may be a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. For example, the memory may be connected to the processor so that the processor can read information from the memory and write information to the memory. Optionally, the memory may also be integrated into the processor. The processor and the memory may be arranged in an ASIC, and the ASIC may be arranged in a UE. Optionally, the processor and the memory may also be arranged in different components in the UE.

[0234] Through the description of the above embodiments, it is clear to those skilled in the art that the present invention can be implemented in hardware, firmware, or a combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product, which includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in accordance with the embodiment of the present invention is generated in whole or in part. When implemented using a software program, the above functions can also be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. Computer-readable media include computer storage media and communication media, wherein the communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a computer can access. By way of example but not limitation: computer readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer. In addition. Any connection can be appropriately a computer readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwave, then coaxial cable, optical fiber cable, twisted pair, DSL or wireless technologies such as infrared, wireless and microwave are included in the definition of the medium. As used in the present invention, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks and blue-ray discs, where disks usually copy data magnetically, while discs use lasers to optically copy data. The above combination should also be included in the scope of protection of computer readable media.

[0235] It should be noted that, in the present application, “ / ” represents and / or, for example, “encoding / decoding (encoding and / or decoding)” refers to encoding, or decoding, or encoding and decoding.

[0236] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of information processing, comprising: Obtain an input sequence to be encoded / an input sequence to be decoded; as well as Encoding / decoding the input sequence to be encoded / the input sequence to be decoded based on a low-density parity check LDPC matrix to obtain an encoded sequence / a decoded sequence, The LDPC matrix is ​​obtained by expanding each element of the base matrix according to the expansion factor Z in the following manner: Each zero element of the basis matrix is ​​replaced by a full zero matrix of size Z*Z; Each non-zero element of the base matrix is ​​replaced by a Z*Z size circulant permutation matrix, which is obtained by P-ing the Z*Z size identity matrix i,j It is obtained by circularly shifting right or left times, where i and j represent the row and column numbers of the non-zero element respectively.

2. The method according to claim 1, characterized in that P i,j =mod(V i,j ,Z), where V i,j The values ​​of and the row and column numbers where the non-zero elements are located are shown below, and all other elements of the basis matrix are zero elements:

3. The method according to claim 1 or 2, further comprising: An expansion factor Z is determined, and the base matrix is ​​determined according to a group index of the expansion factor Z.

4. The method according to any one of claims 1 to 3, characterized in that: The value of Z is one of {5, 10, 20, 40, 80, 160, 320}.

5. The method according to any one of claims 1 to 4, characterized in that: The expansion factor Z satisfies K b The minimum value of Z ≥ K, where K is the length of the input sequence to be encoded, K b is one of {6,8,9,10}.

6. The method according to claim 5, characterized in that K b satisfy:

7. The method according to any one of claims 1 to 6, characterized in that: The input sequence to be encoded is denoted as c, and the encoded sequence is denoted as d, which satisfies: For k = 2Z to K-1, If c k ≠ <null>, then d k-2Z =c k ;< / null> Otherwise, c k = 0, and d k-2Z = <null> , where Z is the expansion factor and K is the length of the input sequence c to be encoded.< / null> 8. The method according to claim 7, further comprising: Generate a check sequence w, the check sequence w includes N+2Z-K check bits, N is the length of the encoded sequence d, and the check sequence w is represented by w0, w1, w2, ..., w N+2Z-K-1 .

9. The method according to claim 8, characterized in that: The LDPC matrix is ​​represented as H, where the LDPC matrix H, the check sequence w and the input sequence to be encoded c satisfy: where c=[c0,c1,c2,...,c K-1 ] T ,w=[w0,w1,w2,…,w N+2Z-K-1 ] T ,0 represents a column vector where all elements have the value 0.

10. The method according to claim 9, characterized in that The encoded sequence d and the check sequence w satisfy: For k=K to N+2Z-1,d k-2Z =w k-K .

11. The method according to any one of claims 1 to 10, characterized in that: The LDPC matrix is ​​obtained based on the expansion factor Z and a transformation matrix of the base matrix, wherein the transformation matrix of the base matrix corresponds to a matrix of the base matrix after row exchange, column exchange, or row exchange and column exchange.

12. A method for use in a communication system, comprising: Determine the expansion factor Z; Encode / decode an input sequence based on at least a portion of a low density parity check LDPC matrix corresponding to the spreading factor Z The expansion factor Z is included in one of the multiple expansion factor groups, and each of the multiple expansion factor groups corresponds to a different group of offset values ​​V. i,j , Wherein, the LDPC matrix is ​​based on the base graph, the expansion factor Z, and the offset value V corresponding to the expansion factor i,j get, The different groups of V i,j The value of is any set of offset values ​​V shown in Figures 3b-1 to 3b-8 i,j .

13. The method according to claim 12, characterized in that In the case where the expansion factor Z is one of {5, 10, 20, 40, 80, 160, 320}, based on the following V i,j Determine at least a portion of the LDPC matrix, where i represents a row number and j represents a column number:

14. The method according to claim 12 or 13, characterized in that The LDPC matrix is ​​obtained by replacing each element of the base graph with a Z*Z matrix in the following way, where each V in the base graph i,j The corresponding element (i, j) is replaced by a Z*Z size circulant permutation matrix, and all other elements in the base graph are replaced by a Z*Z size all-zero matrix.

15. The method according to claim 14, characterized in that The circulant permutation matrix corresponding to the element (i, j) is obtained by performing P on the Z*Z identity matrix i,j Circular shift to the right or left times to obtain, where P i,j =mod(V i,j ,Z).

16. The method according to any one of claims 12 to 15, characterized in that The LDPC matrix includes m rows and n columns, where 7≤m≤42 and 17≤n≤52.

17. A communication device, comprising a processor and a memory coupled to the processor, wherein the processor is configured to execute the method according to any one of claims 1 to 16.

18. The communication device according to claim 17, characterized in that: The memory is used to store one or more of the following: Expansion factor Z, base graph of base matrix, parameters related to base graph of base matrix, base matrix, parameters related to base matrix, transformation matrix of base matrix, LDPC matrix, generator matrix of LDPC matrix, or parameters related to LDPC matrix.

19. The communication device according to claim 18, characterized in that: The parameters related to the base matrix include one or more of the following: the position of the element representing the circulant permutation matrix in the base matrix, or the V of the element representing the circulant permutation matrix in the base matrix. i,j value, or each row in the base matrix represents the row weight of the elements of the circulant permutation matrix, or each column in the base matrix represents the column weight of the elements of the circulant permutation matrix, or, the code rate.

20. The communication device according to any one of claims 17 to 19, characterized in that: The processor is further configured to perform rate matching, interleaving, or modulation on the encoded sequence.

21. The communication device according to any one of claims 17 to 20, characterized in that: The processor is also used to receive a signal and perform one or more of the following operations on the received signal: demodulation, deinterleaving, rate matching, code block concatenation, and cyclic redundancy check.

22. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to perform the method according to any one of claims 1 to 16.

23. A computer program product, causing a computer to execute the method according to any one of claims 1 to 16.

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