Memory access verification method, memory access verification system and related equipment

Abstract

The embodiment of the invention provides a memory access verification method, a memory access verification system and related equipment. The method comprises the following steps: acquiring request processing information of a to-be-tested design; according to the request processing information, in a request queue in which a first memory access request with a first data volume and a second memory access request with a second data volume created based on the first memory access request are recorded, determining a memory access request which corresponds to the first memory access request and serves as an expected memory access request; if the expected memory access request meets a preset condition, recording the request into a response queue; obtaining memory response data of the to-be-tested design, and updating the memory response data to a data field corresponding to the expected memory access request in the response queue; sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; the first memory access request is recorded to a sequence request queue while being recorded to the request queue; and comparing whether the reference data is the same as the memory response data, and if yes, passing the verification.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a memory access verification method, a memory access verification system, and related equipment. Background Art

[0002] With the rapid development of artificial intelligence, people have higher and higher requirements for the data processing capabilities of computers. Among them, the existing cache can perform access with a first data volume (for example, 64B). However, for the performance optimization of the cache, when performing a data read operation, a data read function with a second data volume (for example, 128B) may also be introduced, that is, the upstream device of the cache can send a memory access request with a byte number of the second data volume to the cache, and can also send a memory access request with a byte number of the first data volume to the cache.

[0003] Therefore, providing a memory access verification scheme to verify the data processing flow of the cache that simultaneously adapts to memory access requests of two different data amounts has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a memory access verification method, a memory access verification system and related equipment to realize the verification of the cache data processing flow that simultaneously adapts to memory access requests of two different data amounts, thereby ensuring the accuracy of data processing.

[0005] In a first aspect, an embodiment of the present application provides a memory access verification method, including:

[0006] Obtaining request processing information of the design under test, wherein the request processing information is the content of the memory access request currently processed by the design under test;

[0007] According to the request processing information, a memory access request corresponding to the request processing information is determined in a request queue, and the memory access request is used as an expected memory access request; wherein the request queue records a first memory access request with a first data amount, and a second memory access request with a second data amount created by the design under test based on the first memory access request;

[0008] If the expected memory access request meets the preset condition, the expected memory access request is recorded in the response queue;

[0009] Acquire memory response data of the design to be tested, and update the memory response data to a data field in the response queue corresponding to the expected memory access request;

[0010] sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; wherein the first memory access request is recorded in the sequential request queue while being recorded in the request queue;

[0011] Compare the reference data with the memory response data to see if they are the same, and if so, the verification is successful.

[0012] Optionally, the request processing information includes an address tag, where the address tag is used to indicate a data address corresponding to the memory access request;

[0013] The method of determining a memory access request corresponding to the request processing information in the request queue and using the memory access request as the expected memory access request is specifically as follows: determining a memory access request having the same address tag as that in the request processing information in the request queue according to the address tag and using the memory access request as the expected memory access request.

[0014] Optionally, the request processing information further includes a hit flag, and the hit flag is used to mark a hit status of the memory access request in the cache;

[0015] After determining, according to the address tag, in the request queue, a memory access request with the same address tag as that in the request processing information and taking the memory access request as the expected memory access request, and before recording the expected memory access request into the response queue if the expected memory access request meets a preset condition, the method further includes:

[0016] If the hit flag indicates that the memory access request does not hit in the cache, recording the expected memory access request into a memory request queue;

[0017] If the expected memory access request is a second memory access request, the first memory access request corresponding to the second memory access request is simultaneously recorded in a memory request queue.

[0018] Optionally, the preset condition is that the expected memory access request is identical to the address bit of the memory access request currently processed by the design under test indicated by the request processing information;

[0019] If the expected memory access request meets a preset condition, recording the expected memory access request into a response queue includes:

[0020] Comparing whether the address bit of the expected memory access request is the same as the address bit in the request processing information;

[0021] If they are the same, the expected memory access request is recorded in the response queue.

[0022] Optionally, the expected memory access request is obtained from the memory request queue.

[0023] Optionally, while recording the expected memory access request into the response queue, expected reference data is also calculated according to the expected memory access request.

[0024] Optionally, after acquiring the memory response data of the design to be tested and before updating the memory response data to the data field corresponding to the expected memory access request in the response queue, the method further includes:

[0025] comparing whether the memory response data is the same as the expected reference data;

[0026] If they are the same, the memory response data is updated to the data field in the response queue corresponding to the expected memory access request.

[0027] Optionally, the memory response data corresponds to a response address tag, and the response address tag corresponds to an address tag of the memory access request;

[0028] The determining reference data according to the first memory access request includes:

[0029] comparing whether the address tag of the first memory access request is the same as the response address tag;

[0030] If they are the same, the memory response data in the data field corresponding to the expected memory access request in the response queue is used as the reference data.

[0031] Optionally, the request queue includes a first sub-request queue and a second sub-request queue; the first sub-request queue and the second sub-request queue both record the first memory access request and the second memory access request;

[0032] The determining, according to the address tag, in the request queue, a memory access request with the same address tag as that in the request processing information, and using the memory access request as the expected memory access request, specifically comprises: determining, according to the address tag, in the first sub-request queue, a memory access request with the same address tag as that in the request processing information, and using the memory access request as the expected memory access request;

[0033] If the hit flag indicates that the memory access request does not hit in the cache, after recording the expected memory access request into the memory request queue, the method further includes:

[0034] The expected memory access request is obtained in the second sub-request queue.

[0035] Optionally, corresponding to the indication of the hit flag, an address index array corresponding to the memory access request is provided, the address index array using the address bit and address tag of the memory access request as indexes; wherein the address index array includes a first address index array corresponding to the first memory access request and a second address index array corresponding to the second memory access request;

[0036] If the hit flag indicates that the memory access request does not hit in the cache, when the memory access request is the first memory access request and / or the second memory access request, a first missing memory access request corresponding to the first memory access request and / or a second missing memory access request corresponding to the second memory access request is created, and the first missing memory access request and / or the second missing memory access request are recorded in the address bits of the corresponding first address index array and / or the address bits of the second address index array; or,

[0037] If the hit flag indicates that the memory access request hits in the cache, when the memory access request includes a first memory access request and a second memory access request, the expected memory access request includes a first expected memory access request and a second expected memory access request, and corresponding data are read from the address bits of the first address index array and the second address index array to the corresponding data objects of the first expected memory access request and the second expected memory access request, respectively.

[0038] Optionally, an expected address index array is provided corresponding to the first expected memory access request and the second expected memory access request;

[0039] When the address bit of the expected memory access request is the same as the address bit in the request processing information, the data objects of the first expected memory access request and the second expected memory access request are read respectively and saved to the address bits of the expected address index array accordingly.

[0040] Optionally, updating the memory response data to the data field in the response queue corresponding to the expected memory access request is specifically: updating the memory response data to the first expected memory access request and the second expected memory access request read from the expected address index array until it is updated to the data field in the response queue corresponding to the expected memory access request.

[0041] Optionally, before obtaining the request processing information of the design to be tested, the method further includes:

[0042] Obtaining a memory access request of the design to be tested, where the memory access request is a first memory access request or a second memory access request, where the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created by the design to be tested based on the first memory access request;

[0043] If the memory access request is the first memory access request, recording the memory access request into a sequential request queue and a request queue respectively;

[0044] If the memory access request is the second memory access request, the memory access request is recorded in a request queue.

[0045] Optionally, the amount of data corresponds to the number of bytes;

[0046] The second memory access request with the second data amount corresponds to a second memory access request with a byte number of the second data amount, and the byte number of the second data amount at least includes a byte number of 128B.

[0047] In a second aspect, an embodiment of the present application provides a memory access verification system, including: a design to be tested and a verification reference model;

[0048] The design under test is used to execute a memory access request, the memory access request is a first memory access request or a second memory access request, the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created based on the first memory access request; and based on the execution of the memory access request, request processing information and memory response data of the currently processed memory access request are sent to the verification reference model;

[0049] The verification reference model is used to obtain request processing information and memory response data of the design to be tested, and perform memory access verification based on the request processing information and the memory response data.

[0050] Optionally, the verification reference model, obtaining request processing information and memory response data of the design to be tested, and performing memory access verification according to the request processing information and the memory response data, comprises:

[0051] Obtaining request processing information of the design under test, wherein the request processing information is the content of the memory access request currently processed by the design under test;

[0052] According to the request processing information, a memory access request corresponding to the request processing information is determined in a request queue, and the memory access request is used as an expected memory access request; wherein the request queue records a first memory access request with a first data amount, and a second memory access request with a second data amount created by the design under test based on the first memory access request;

[0053] If the expected memory access request meets the preset condition, the expected memory access request is recorded in the response queue;

[0054] Acquire memory response data of the design to be tested, and update the memory response data to a data field in the response queue corresponding to the expected memory access request;

[0055] sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; wherein the first memory access request is recorded in the sequential request queue while being recorded in the request queue;

[0056] Compare the reference data with the memory response data to see if they are the same, and if so, the verification is successful.

[0057] In a third aspect, an embodiment of the present application provides a chip verification platform, which includes the memory access verification system as described in the second aspect above.

[0058] In a fourth aspect, an embodiment of the present application provides a computing device, including a processor and a memory, wherein the hardware logic design of the memory is verified by the memory access verification method described in the first aspect above.

[0059] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising one or more computer executable instructions, which, when executed, implement the memory access verification method as described in the first aspect above.

[0060] It can be seen that the embodiment of the present application obtains the request processing information of the design to be tested, and the request processing information is the content of the memory access request currently processed by the design to be tested; then, according to the request processing information, the memory access request corresponding to it is determined in the request queue, and the memory access request is used as the expected memory access request; wherein, the request queue records a first memory access request with a first data volume, and a second memory access request with a second data volume created by the design to be tested based on the first memory access request, thereby covering two memory access requests with different data volumes, providing technical support for the memory access verification of the chip. Moreover, if the expected memory access request meets the preset conditions, the expected memory access request is recorded in the response queue; then, by obtaining the memory response data of the design to be tested, the memory response data can be updated to the data field corresponding to the expected memory access request in the response queue. When a first memory access request is read sequentially in the sequential request queue, and the reference data is determined according to the first memory access request, the reference data can be compared with the memory response data to see if they are the same. If so, the verification is passed, thereby realizing the data processing flow verification of the memory access request in the cache that simultaneously adapts to two different data volumes, and ensuring the accuracy of data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0062] Figure 1 is an optional structural diagram of a memory access verification system provided in an embodiment of the present application;

[0063] Figure 2 It is an optional flow chart of the memory access verification method provided in the embodiment of the present application;

[0064] Figure 3 This is another optional flow chart of the memory access verification method provided in the embodiment of the present application;

[0065] Figure 4 It is another optional flow chart of the memory access verification method provided in the embodiment of the present application;

[0066] Figure 5 This is another optional flow chart of the memory access verification method provided in the embodiment of the present application. DETAILED DESCRIPTION

[0067] With the rapid development of artificial intelligence, people have higher and higher requirements for the data processing capabilities of computers. Among them, the existing cache can perform access with a first data volume (for example, 64B). However, for the performance optimization of the cache, when performing a data read operation, a data read function with a second data volume (for example, 128B) may also be introduced, that is, the upstream device of the cache can send a memory access request with a byte number of the second data volume to the cache, and can also send a memory access request with a byte number of the first data volume to the cache.

[0068] However, for example, verification of the data processing flow of a 64B memory access request in the cache, since each address of the cache is usually composed of 64 bits, the data processing flow of the cache of the 64B memory access request can be effectively verified, but it is not applicable to the verification of the data processing flow of the introduced 128B memory access request in the cache. Therefore, it is necessary to provide a memory access verification scheme to verify the data processing flow of the cache that simultaneously adapts to memory access requests of two different data amounts to ensure the accuracy of data processing.

[0069] In view of this, an embodiment of the present application provides an improved memory access verification scheme, by obtaining the request processing information of the design to be tested, the request processing information is the content of the memory access request currently processed by the design to be tested; then, according to the request processing information, the memory access request corresponding to it is determined in the request queue, and the memory access request is used as the expected memory access request; wherein, the request queue records a first memory access request with a first data volume, and a second memory access request with a second data volume created by the design to be tested based on the first memory access request, thereby covering two memory access requests with different data volumes, providing technical support for the memory access verification of the chip. Moreover, if the expected memory access request meets the preset conditions, the expected memory access request is recorded in the response queue; then, by obtaining the memory response data of the design to be tested, the memory response data can be updated to the data field corresponding to the expected memory access request in the response queue. When a first memory access request is read sequentially in a sequential request queue and reference data is determined based on the first memory access request, the reference data can be compared to see whether they are the same as the memory response data. If so, the verification is successful, thereby realizing the verification of the data processing flow of the cache that simultaneously adapts to memory access requests of two different data amounts, thereby ensuring the accuracy of data processing.

[0070] Based on the above-mentioned inventive concept, the embodiments of the present application provide a memory access verification method, a memory access verification system and related equipment. The technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0071] The adoption of verification methodology is one of the trends in chip verification, and the Universal Verification Methodology (UVM) is a typical representative. UVM is a universal verification methodology based on SystemVerilog class. Its Universal Verification Component (UVC) can be used to build a functional verification environment. Among them, the Universal Verification Component (UVC) is an important component of the universal verification platform, which can be used to verify the relevant functions of the design under test. It can include the design of the universal verification component (design uvc) to realize the data processing of the design under test (DUT); wherein, the design under test can be a chip that executes a memory access request, which can include components such as a router, an arbitration module (Arbiter), a cache (Cache) and a system storage model (Sysmem).

[0072] In order to realize the memory access verification of the chip, the embodiment of the present application is provided with a verification reference model component (Refmem_uvc) for the design to be tested, which may include an interface component (interface) used to connect with the design to be tested to obtain relevant information of the memory access request executed by the design to be tested; a monitor component (Monitor) used to collect the interface information of the design to be tested; a transaction component (transaction) used to store the interface information collected by the monitor; an agent component (agent) used to instantiate uvc and connect the monitor and other components to ensure that the collected data is connected through the interface component and sent to other components for subsequent processing. Moreover, the design to be tested can exchange information with the verification reference model component through the interface component to verify the data processing performed by the design to be tested based on the memory access request.

[0073] As an optional implementation, Figure 1 The following is an exemplary diagram of an optional structure of a memory access verification system according to an embodiment of the present application. Figure 1 As shown, the memory access verification system may include: a design to be tested and a verification reference model.

[0074] The design to be tested is used to execute a memory access request. Specifically, the memory access request may be executed based on a cache. In a multi-level cache structure, the cache may be, for example, an L2 cache.

[0075] There may be one or more routers in the design to be tested. In the case of multiple routers, the multiple routers may send memory access requests to the arbitration module, which arbitrates the memory access requests and sends them to the L2 cache and the system storage module for execution. The system storage module is, for example, a memory. In an optional example, the memory access request sent from the L2 cache to the system storage module may be implemented by a bus functional model (BFM).

[0076] The memory access request may be a first memory access request or a second memory access request, wherein the first memory access request has a first data volume, the second memory access request has a second data volume, and the second memory access request is created based on the first memory access request. In a specific example, after obtaining the first memory access request with the first data volume sent by the router, the arbitration module of the design to be tested may create a second memory access request with the second data volume according to the address information of the first memory access request. Wherein, based on the second memory access request being created based on the first memory access request of the design to be tested, the information of the second memory access request may be a memory access request with a different data volume from the first memory access request but the same information content. Taking the data volume of the first memory access request as 64B and the data volume of the second memory access request as 128B as an example, after obtaining the 64B memory access request sent by the router, the arbitration module may, on the basis of the 64-bit address corresponding to the 64B memory access request, add one bit to create a 128B memory access request with the same information content as the 64B memory access request but a different data volume.

[0077] Based on the execution of the memory access request, the request processing information and memory response data of the memory access request currently processed by the design under test can be obtained, and then the request processing information and memory response data can be sent to the verification reference model so that the verification reference model can perform subsequent verification operations.

[0078] The request processing information may be relevant information content when the cache executes the memory access request processing flow, such as the address tag Tag of the data corresponding to the memory access request, the operation code Op indicating the operation type of the memory access request, the address addr of the data corresponding to the memory access request, the hit or miss signal of the memory access request, and other signals.

[0079] The memory response data may be response data information returned by the memory when the memory access request does not hit in the cache and the cache sends the access request to the memory.

[0080] Based on the execution of the memory access request by the design under test, the verification reference model can obtain the request processing information and memory response data of the design under test, and perform memory access verification according to the request processing information and the memory response data.

[0081] As an optional implementation, Figure 2 The optional flow chart of the memory access verification method of the embodiment of the present application is exemplarily shown. The flow can be implemented based on the above-mentioned memory access verification system, and can be implemented by the verification reference model. Figure 2 As shown, the process may include the following steps:

[0082] Step S10, obtaining request processing information of the design to be tested.

[0083] The request processing information is the content of the memory access request currently being processed by the design under test, for example: in the cache of the design under test, the content of the memory access request currently being processed includes the address tag Tag of the data corresponding to the memory access request, the operation code Op indicating the operation type of the memory access request, the address addr of the data corresponding to the memory access request, the hit or miss signal of the memory access request in the cache, and other signals.

[0084] Step S20: determining a corresponding memory access request in a request queue according to the request processing information, and using the memory access request as an expected memory access request.

[0085] The request queue is used by the verification reference model to record memory access requests of the design under test. Optionally, when the design under test obtains the memory access request, the memory access request can be simultaneously sent to the verification reference model for recording. The request queue records a first memory access request with a first data volume, and a second memory access request with a second data volume created by the design under test based on the first memory access request.

[0086] The expected memory access request may be understood as a memory access request used for memory access verification.

[0087] By acquiring the request processing information of the design to be tested, the corresponding memory access request can be determined in the request queue according to the request processing information, so that the memory access request can be used as the expected memory access request to execute the subsequent memory access verification process.

[0088] In an optional example, if the expected memory access request meets a preset condition, step S30 may be executed to record the expected memory access request into a response queue.

[0089] To implement memory access verification of the design under test, the preset condition may be, for example, that the memory access request is expected to not hit the cache; or, for example, that the memory access request is expected to have the same address bit as the memory access request currently processed by the design under test indicated by the request processing information.

[0090] The response queue is used by the verification reference model to record the response data obtained by the memory in the design under test based on the execution of the memory access request. Optionally, when the memory of the design under test returns the response data of the memory access request, the response data of the memory access request can be simultaneously sent to the verification reference model for recording, so as to be used for the verification reference model to verify the memory access request.

[0091] Step S40, obtaining memory response data of the design to be tested, and updating the memory response data to the data field corresponding to the expected memory access request in the response queue.

[0092] The memory response data may be understood as memory response data obtained by executing the design under test in the memory based on the memory access request.

[0093] Based on the expected memory access request recorded in the response queue, after the verification reference model obtains the memory response data of the design to be tested, the memory response data can be updated to the data field corresponding to the expected memory access request in the response queue to indicate that the memory response data is the data obtained by the memory executing the expected memory access request.

[0094] Step S50 , sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request.

[0095] The sequential request queue is used to record the memory access requests based on the order of the memory access requests obtained by the design under test. Among them, since the second memory access request is created by the design under test based on the first memory access request, the memory access request obtained by the design under test may be only the first memory access request, and the memory access request recorded in order in the sequential request queue is only the first memory access request.

[0096] Based on the first memory access request recorded in the sequential request queue, a first memory access request can be read sequentially in the sequential request queue, so that a reference data can be determined according to the first memory access request. The reference data can be understood as data used by the verification reference model to compare with the memory response data in the response queue.

[0097] It can be understood that only the first memory access request is recorded in the sequential request queue, and the order of the first memory access request recorded therein is consistent with the order of issuance of the router in the design to be tested. The first memory access request and the second memory access request are recorded in the request queue at the same time, and the first memory access request and the second memory access request are different based on the order of recording, so that in the request queue, the first memory access request is always in front of the second memory access request. Therefore, when performing memory access verification on the memory access request, the verification reference model can perform processing verification based on the order of the first memory access request recorded in the sequential request queue corresponding to the original order of the request.

[0098] Step S60, comparing the reference data and the memory response data to see if they are the same.

[0099] If the comparison reference data is the same as the memory response data, it means that no data error occurs in the execution of the memory access request by the design under test, and the verification passes.

[0100] It can be seen that the embodiment of the present application obtains the request processing information of the design to be tested, and the request processing information is the content of the memory access request currently processed by the design to be tested; then, according to the request processing information, the memory access request corresponding to it is determined in the request queue, and the memory access request is used as the expected memory access request; wherein, the request queue records a first memory access request with a first data volume, and a second memory access request with a second data volume created by the design to be tested based on the first memory access request, thereby covering two memory access requests with different data volumes, providing technical support for the memory access verification of the chip. Moreover, if the expected memory access request meets the preset conditions, the expected memory access request is recorded in the response queue; then, by obtaining the memory response data of the design to be tested, the memory response data can be updated to the data field corresponding to the expected memory access request in the response queue. When a first memory access request is read sequentially in the sequential request queue, and the reference data is determined according to the first memory access request, the reference data can be compared with the memory response data to see if they are the same. If so, the verification is passed, thereby realizing the verification of the data processing flow of the cache that simultaneously adapts to the memory access requests of two different data volumes, and ensuring the accuracy of data processing.

[0101] In some embodiments, corresponding to the content information of the memory access request, the request processing information of the design under test acquired by the verification reference model may include an address tag, where the address tag is used to indicate a data address corresponding to the memory access request.

[0102] Thus, refer to Figure 3 Another optional flow chart of the memory access verification method shown, step S20 may specifically be: according to the address tag, determine in the request queue a memory access request with the same address tag as that in the request processing information, and use the memory access request as the expected memory access request.

[0103] Further in some embodiments, based on the execution of the memory access request by the cache, the request processing information of the design under test obtained by the verification reference model may also include a hit flag, and the hit flag is used to mark the hit status of the memory access request in the cache.

[0104] Based on the hit flag, see Figure 3 As shown, after step S20 and before step S30, step S21 may be further included, where if the hit flag indicates that the memory access request does not hit in the cache, the expected memory access request is recorded in a memory request queue.

[0105] It is understandable that when a memory access request does not hit in the cache, the memory access request can be passed to the memory for processing. Thus, if the hit flag in the request processing information obtained by the verification reference model indicates that the memory access request does not hit in the cache, the expected memory access request determined in the request queue according to the address tag can be recorded in the memory request queue. The memory request queue is used to record the memory access request that needs to be passed to the memory for processing.

[0106] Among them, if the expected memory access request is a second memory access request, that is, a memory access request with a second data amount, based on the second memory access request being created based on the first memory access request, the first memory access request corresponding to the second memory access request can be simultaneously recorded in the memory request queue.

[0107] In some embodiments, the preset condition for judging the expected memory access request may be that the address bit of the expected memory access request is the same as the address bit of the memory access request currently being processed by the design under test indicated by the request processing information, that is, through the corresponding address bit, it is judged that the memory access request currently being processed is the memory access request obtained in the request queue as the expected memory access request.

[0108] Therefore, if the expected memory access request meets the preset conditions, when the expected memory access request is recorded in the response queue, it can be achieved by comparing the address bits of the expected memory access request with the address bits in the request processing information to see if they are the same. If they are the same, step S30 is executed to record the expected memory access request in the response queue.

[0109] In some embodiments, to ensure the accuracy of data stream processing, the expected memory access request for executing the preset condition judgment may be obtained from the memory request queue.

[0110] It should be noted that, in order to improve the query performance of the cache and reduce the frequency of data updates, all memory access requests sent by the router will be processed through the cache. If the memory access request does not hit the cache, it will be sent to the memory, and the data in the memory will be read into the cache for processing. This type of cache is called a non-coherently cached (NC). The above steps can be implemented based on the direct cache.

[0111] When the real-time and security requirements for data are high, memory access requests can directly access the storage device without going through the cache (Uncached, UC). Figure 4 Another optional flow chart of the memory access verification method in the embodiment of the present application is exemplarily shown.

[0112] like Figure 4As shown, while executing step S30, step S31 may also be executed to calculate and obtain expected reference data according to the expected memory access request.

[0113] As an optional implementation, a function call can be made based on the content of the expected memory access request, such as an opcode, to calculate expected reference data, where the expected reference data is used to compare and judge the memory response data to verify that the memory response data is the data corresponding to the expected memory access request.

[0114] In some embodiments, based on the calculated expected reference data, see Figure 4 As shown, step S40, after acquiring the memory response data of the design to be tested and before updating the memory response data to the corresponding expected memory access request in the response queue, may also include:

[0115] The memory response data is compared with the expected reference data to see if they are the same.

[0116] If they are the same, the memory response data is updated to the data field in the response queue corresponding to the expected memory access request.

[0117] As an optional implementation, based on the address tag of the memory access request, the memory response data may correspond to a response address tag, and the response address tag corresponds to the address tag of the memory access request.

[0118] Therefore, when determining the reference data based on the first memory access request, the address tag of the first memory access request can be compared to see if it is the same as the response address tag. If they are the same, the memory response data in the data field corresponding to the expected memory access request in the response queue is used as the reference data.

[0119] It should be noted that for a distributed system, while improving access speed, it is necessary to minimize real-time synchronization with the database or other original data sources, so it is necessary to maintain cache consistency (Coherence Cache, CC). In the cache consistency scenario, when performing memory access verification, different request queues can be divided according to different purposes in the embodiment of the present application.

[0120] In some embodiments, the request queue of the embodiment of the present application may include a first sub-request queue and a second sub-request queue, wherein the first sub-request queue and the second sub-request queue both record the first memory access request and the second memory access request.

[0121] It should be noted that since the first sub-request queue and the second sub-request queue both record the first memory access request and the second memory access request, in order to fully realize the memory access verification of the memory access request in the cache consistency scenario, the memory access request recorded in the first sub-request queue can be used in different verification steps with the memory access request recorded in the second sub-request queue.

[0122] As an optional implementation, based on different sub-request queues, according to the address tag, a memory access request with the same address tag as that in the request processing information is determined in the request queue, and the memory access request is used as the expected memory access request. Specifically, the following steps can be performed: according to the address tag, a memory access request with the same address tag as that in the request processing information is determined in the first sub-request queue, and the memory access request is used as the expected memory access request.

[0123] As an optional implementation, if the hit flag indicates that the memory access request does not hit in the cache, after the expected memory access request is recorded in the memory request queue, the expected memory access request can also be obtained in the second sub-request queue.

[0124] In some embodiments, corresponding to the indication of the hit flag in the request processing information, an address index array corresponding to the memory access request may be provided in a cache consistency scenario, and the address index array may be indexed by the address bit and address tag of the memory access request.

[0125] Wherein, corresponding to the first memory access request and the second memory access request, the address index array may include a first address index array corresponding to the first memory access request and a second address index array corresponding to the second memory access request.

[0126] As an optional implementation, if the hit flag indicates that the memory access request does not hit in the cache, when the memory access request is the first memory access request and / or the second memory access request, a first missing memory access request corresponding to the first memory access request and / or a second missing memory access request corresponding to the second memory access request may be created, and the first missing memory access request and / or the second missing memory access request may be recorded in the address bits of the corresponding first address index array and / or the address bits of the second address index array.

[0127] As another optional implementation, if the hit flag indicates that the memory access request hits in the cache, when the memory access request includes a first memory access request and a second memory access request, the expected memory access request may include a first expected memory access request and a second expected memory access request, and corresponding data are read from the address bits of the first address index array and the second address index array to the corresponding data objects of the first expected memory access request and the second expected memory access request, respectively.

[0128] In some embodiments, an expected address index array is set corresponding to the first expected memory access request and the second expected memory access request. When the address bit of the expected memory access request is the same as the address bit in the request processing information, the data objects of the first expected memory access request and the second expected memory access request can be read respectively and saved accordingly to the address bits of the expected address index array.

[0129] In some embodiments, based on the creation of the expected address index array, when the memory response data is updated to the data field in the response queue corresponding to the expected memory access request, it can be specifically as follows: the memory response data is updated to the first expected memory access request and the second expected memory access request read from the expected address index array until it is updated to the data field in the response queue corresponding to the expected memory access request for comparison and judgment with reference data.

[0130] In some embodiments, Figure 5 Another optional flow chart of the memory access verification method of the embodiment of the present application is shown as an example. Figure 5 As shown, in order to verify the memory access request, before step S10, step S00 may be further included to obtain the memory access request of the design to be tested.

[0131] The memory access request is a first memory access request or a second memory access request, the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created by the design under test based on the first memory access request.

[0132] As an optional implementation, if the memory access request is the first memory access request, the memory access request may be recorded in a sequential request queue and a request queue respectively.

[0133] As another optional implementation, if the memory access request is the second memory access request, the memory access request may be recorded in a request queue.

[0134] In some embodiments, the data amount may correspond to the number of bytes, so that the second memory access request with the second data amount may be a second memory access request corresponding to the second data amount in bytes, and the second data amount in bytes may at least include a byte number of 128 B. In a specific example, the second memory access request with the second data amount is created based on the first memory access request with the first data amount. In the embodiment of the present application, the first memory access request with the first data amount may be a 64 B memory access request, and the second memory access request with the second data amount may be a 128 B memory access request.

[0135] It can be seen that the embodiment of the present application obtains the request processing information of the design to be tested, and the request processing information is the content of the memory access request currently processed by the design to be tested; then, according to the request processing information, the memory access request corresponding to it is determined in the request queue, and the memory access request is used as the expected memory access request; wherein, the request queue records a first memory access request with a first data volume, and a second memory access request with a second data volume created by the design to be tested based on the first memory access request, thereby covering two memory access requests with different data volumes, providing technical support for the memory access verification of the chip. Moreover, if the expected memory access request meets the preset conditions, the expected memory access request is recorded in the response queue; then, by obtaining the memory response data of the design to be tested, the memory response data can be updated to the data field corresponding to the expected memory access request in the response queue. When a first memory access request is read sequentially in the sequential request queue, and the reference data is determined according to the first memory access request, the reference data can be compared with the memory response data to see if they are the same. If so, the verification is passed, thereby realizing the verification of the data processing flow of the cache that simultaneously adapts to the memory access requests of two different data volumes, and ensuring the accuracy of data processing.

[0136] The present application also provides a chip memory access verification system, the structure of which can refer to Figure 1 As shown, the content described below can be regarded as the functional modules that need to be set up by the chip memory access verification system to implement the memory access verification method provided by the embodiment of the present application, and the content described below can be referred to in correspondence with the content described above. The memory access verification system includes: a design to be tested and a verification reference model;

[0137] The design under test is used to execute a memory access request, the memory access request is a first memory access request or a second memory access request, the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created based on the first memory access request; and based on the execution of the memory access request, request processing information and memory response data of the currently processed memory access request are sent to the verification reference model;

[0138] The verification reference model is used to obtain request processing information and memory response data of the design to be tested, and perform memory access verification based on the request processing information and the memory response data.

[0139] Optionally, the verification reference model, obtaining request processing information and memory response data of the design to be tested, and performing memory access verification according to the request processing information and the memory response data, comprises:

[0140] Obtaining request processing information of the design under test, wherein the request processing information is the content of the memory access request currently processed by the design under test;

[0141] According to the request processing information, a memory access request corresponding to the request processing information is determined in a request queue, and the memory access request is used as an expected memory access request; wherein the request queue records a first memory access request with a first data amount, and a second memory access request with a second data amount created by the design under test based on the first memory access request;

[0142] If the expected memory access request meets the preset condition, the expected memory access request is recorded in the response queue;

[0143] Acquire memory response data of the design to be tested, and update the memory response data to a data field in the response queue corresponding to the expected memory access request;

[0144] sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; wherein the first memory access request is recorded in the sequential request queue while being recorded in the request queue;

[0145] Compare the reference data with the memory response data to see if they are the same, and if so, the verification is successful.

[0146] Optionally, the request processing information includes an address tag, where the address tag is used to indicate a data address corresponding to the memory access request;

[0147] The verification reference model determines, in the request queue according to the request processing information, a memory access request corresponding to the request processing information, and uses the memory access request as the expected memory access request. Specifically, according to the address tag, a memory access request with the same address tag as that in the request processing information is determined in the request queue, and uses the memory access request as the expected memory access request.

[0148] Optionally, the request processing information further includes a hit flag, and the hit flag is used to mark a hit status of the memory access request in the cache;

[0149] The verification reference model, after determining, according to the address tag, in the request queue, a memory access request with the same address tag as that in the request processing information and taking the memory access request as the expected memory access request, and before recording the expected memory access request into the response queue if the expected memory access request meets a preset condition, further includes:

[0150] If the hit flag indicates that the memory access request does not hit in the cache, recording the expected memory access request into a memory request queue;

[0151] If the expected memory access request is a second memory access request, the first memory access request corresponding to the second memory access request is simultaneously recorded in a memory request queue.

[0152] Optionally, the preset condition is that the expected memory access request is identical to the address bit of the memory access request currently processed by the design under test indicated by the request processing information;

[0153] If the expected memory access request meets the preset condition, the verification reference model records the expected memory access request into a response queue, including:

[0154] Comparing whether the address bit of the expected memory access request is the same as the address bit in the request processing information;

[0155] If they are the same, the expected memory access request is recorded in the response queue.

[0156] Optionally, the expected memory access request is obtained from the memory request queue for the verification reference model.

[0157] Optionally, the verification reference model calculates expected reference data based on the expected memory access request while recording the expected memory access request into the response queue.

[0158] Optionally, after the verification reference model obtains the memory response data of the design to be tested and before updating the memory response data to the data field corresponding to the expected memory access request in the response queue, it further includes:

[0159] comparing whether the memory response data is the same as the expected reference data;

[0160] If they are the same, the memory response data is updated to the data field in the response queue corresponding to the expected memory access request.

[0161] Optionally, the memory response data corresponds to a response address tag, and the response address tag corresponds to an address tag of the memory access request;

[0162] The verification reference model determines reference data according to the first memory access request, including:

[0163] comparing whether the address tag of the first memory access request is the same as the response address tag;

[0164] If they are the same, the memory response data in the data field corresponding to the expected memory access request in the response queue is used as the reference data.

[0165] Optionally, the request queue includes a first sub-request queue and a second sub-request queue; the first sub-request queue and the second sub-request queue both record the first memory access request and the second memory access request;

[0166] The verification reference model determines, in the request queue, a memory access request with the same address tag as that in the request processing information according to the address tag, and uses the memory access request as the expected memory access request, specifically: determining, in the first sub-request queue, a memory access request with the same address tag as that in the request processing information according to the address tag, and using the memory access request as the expected memory access request;

[0167] If the hit flag indicates that the memory access request does not hit in the cache, after the verification reference model records the expected memory access request into the memory request queue, it also includes:

[0168] The expected memory access request is obtained in the second sub-request queue.

[0169] Optionally, corresponding to the indication of the hit flag, an address index array corresponding to the memory access request is provided, the address index array using the address bit and address tag of the memory access request as indexes; wherein the address index array includes a first address index array corresponding to the first memory access request and a second address index array corresponding to the second memory access request;

[0170] If the hit flag indicates that the memory access request does not hit in the cache, when the memory access request is the first memory access request and / or the second memory access request, the verification reference model correspondingly creates a first missing memory access request corresponding to the first memory access request and / or a second missing memory access request corresponding to the second memory access request, and records the first missing memory access request and / or the second missing memory access request into the address bits of the corresponding first address index array and / or the address bits of the second address index array; or,

[0171] If the hit flag indicates that the memory access request hits in the cache, when the memory access request includes a first memory access request and a second memory access request, the expected memory access request obtained by the verification reference model includes a first expected memory access request and a second expected memory access request, and corresponding data are read from the address bits of the first address index array and the second address index array to the corresponding data objects of the first expected memory access request and the second expected memory access request, respectively.

[0172] Optionally, an expected address index array is provided corresponding to the first expected memory access request and the second expected memory access request;

[0173] When the address bit of the expected memory access request is the same as the address bit in the request processing information, the verification reference model reads the data objects of the first expected memory access request and the second expected memory access request respectively, and saves them to the address bits of the expected address index array accordingly.

[0174] Optionally, the verification reference model updates the memory response data to the data field in the response queue corresponding to the expected memory access request, specifically: updating the memory response data to the first expected memory access request and the second expected memory access request read from the expected address index array until it is updated to the data field in the response queue corresponding to the expected memory access request.

[0175] Optionally, before the verification reference model obtains the request processing information of the design to be tested, the verification reference model further includes:

[0176] Obtaining a memory access request of the design to be tested, where the memory access request is a first memory access request or a second memory access request, where the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created by the design to be tested based on the first memory access request;

[0177] If the memory access request is the first memory access request, recording the memory access request into a sequential request queue and a request queue respectively;

[0178] If the memory access request is the second memory access request, the memory access request is recorded in a request queue.

[0179] Optionally, the amount of data corresponds to the number of bytes;

[0180] The second memory access request with the second data amount corresponds to a second memory access request with a byte number of the second data amount, and the byte number of the second data amount at least includes a byte number of 128B.

[0181] It can be seen that the memory access verification system of the embodiment of the present application can cover memory access requests of two different data amounts, provides technical support for the memory access verification of the chip, and realizes the verification of the data processing flow of the cache that simultaneously adapts to memory access requests of two different data amounts, ensuring the accuracy of data processing.

[0182] A verification platform is also provided in an embodiment of the present application. The verification platform may include the above-mentioned memory access verification system to execute the above-mentioned memory access verification method.

[0183] An embodiment of the present application also provides a computing device, which includes a processor and a memory, and the hardware logic design of the memory is verified by the memory access verification method described above.

[0184] An embodiment of the present application also provides a computer program, including one or more computer executable instructions, which, when executed, implement the memory access verification method described above.

[0185] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0186] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A memory access verification method, characterized in that: include: Obtaining request processing information of the design under test, wherein the request processing information is the content of the memory access request currently processed by the design under test; According to the request processing information, a memory access request corresponding to the request processing information is determined in a request queue, and the memory access request is used as an expected memory access request; wherein the request queue records a first memory access request with a first data amount, and a second memory access request with a second data amount created by the design under test based on the first memory access request; If the expected memory access request meets the preset condition, the expected memory access request is recorded in the response queue; Acquire memory response data of the design to be tested, and update the memory response data to a data field in the response queue corresponding to the expected memory access request; sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; wherein the first memory access request is recorded in the sequential request queue while being recorded in the request queue; Compare the reference data with the memory response data to see if they are the same, and if so, the verification is successful.

2. The method according to claim 1, characterized in that The request processing information includes an address tag, and the address tag is used to indicate a data address corresponding to the memory access request; The method of determining a memory access request corresponding to the request processing information in the request queue and using the memory access request as the expected memory access request is specifically as follows: determining a memory access request having the same address tag as that in the request processing information in the request queue according to the address tag and using the memory access request as the expected memory access request.

3. The method according to claim 2, characterized in that The request processing information also includes a hit flag, and the hit flag is used to mark the hit status of the memory access request in the cache; After determining, according to the address tag, in the request queue, a memory access request with the same address tag as that in the request processing information and taking the memory access request as the expected memory access request, and before recording the expected memory access request into the response queue if the expected memory access request meets a preset condition, the method further includes: If the hit flag indicates that the memory access request does not hit in the cache, recording the expected memory access request into a memory request queue; If the expected memory access request is a second memory access request, the first memory access request corresponding to the second memory access request is simultaneously recorded in a memory request queue.

4. The method according to claim 3, characterized in that The preset condition is that the expected memory access request is identical to the address bit of the memory access request currently processed by the design under test indicated by the request processing information; If the expected memory access request meets a preset condition, recording the expected memory access request into a response queue includes: Comparing whether the address bit of the expected memory access request is the same as the address bit in the request processing information; If they are the same, the expected memory access request is recorded in the response queue.

5. The method according to claim 4, characterized in that The expected memory access request is obtained from the memory request queue.

6. The method according to claim 4, characterized in that While recording the expected memory access request into the response queue, the expected reference data is calculated according to the expected memory access request.

7. The method according to claim 6, characterized in that After acquiring the memory response data of the design to be tested and before updating the memory response data to the data field corresponding to the expected memory access request in the response queue, the method further includes: comparing whether the memory response data is the same as the expected reference data; If they are the same, the memory response data is updated to the data field in the response queue corresponding to the expected memory access request.

8. The method according to claim 7, characterized in that The memory response data corresponds to a response address tag, and the response address tag corresponds to the address tag of the memory access request; The determining reference data according to the first memory access request includes: comparing whether the address tag of the first memory access request is the same as the response address tag; If they are the same, the memory response data in the data field corresponding to the expected memory access request in the response queue is used as the reference data.

9. The method according to claim 3, characterized in that: The request queue includes a first sub-request queue and a second sub-request queue; the first sub-request queue and the second sub-request queue both record the first memory access request and the second memory access request; The determining, according to the address tag, in the request queue, a memory access request with the same address tag as that in the request processing information, and using the memory access request as the expected memory access request, specifically comprises: determining, according to the address tag, in the first sub-request queue, a memory access request with the same address tag as that in the request processing information, and using the memory access request as the expected memory access request; If the hit flag indicates that the memory access request does not hit in the cache, after recording the expected memory access request into the memory request queue, the method further includes: The expected memory access request is obtained in the second sub-request queue.

10. The method according to claim 9, characterized in that Corresponding to the indication of the hit flag, an address index array corresponding to the memory access request is provided, the address index array uses the address bit and address tag of the memory access request as index; wherein the address index array includes a first address index array corresponding to the first memory access request and a second address index array corresponding to the second memory access request; If the hit flag indicates that the memory access request does not hit in the cache, when the memory access request is the first memory access request and / or the second memory access request, a first missing memory access request corresponding to the first memory access request and / or a second missing memory access request corresponding to the second memory access request are created, and the first missing memory access request and / or the second missing memory access request are recorded in the address bits of the corresponding first address index array and / or the address bits of the second address index array; or, If the hit flag indicates that the memory access request hits in the cache, when the memory access request includes a first memory access request and a second memory access request, the expected memory access request includes a first expected memory access request and a second expected memory access request, and corresponding data are read from the address bits of the first address index array and the second address index array to the corresponding data objects of the first expected memory access request and the second expected memory access request, respectively.

11. The method according to claim 10, characterized in that An expected address index array is provided corresponding to the first expected memory access request and the second expected memory access request; When the address bit of the expected memory access request is the same as the address bit in the request processing information, the data objects of the first expected memory access request and the second expected memory access request are read respectively and saved to the address bits of the expected address index array accordingly.

12. The method according to claim 11, characterized in that The updating of the memory response data to the data field corresponding to the expected memory access request in the response queue is specifically: updating the memory response data to the first expected memory access request and the second expected memory access request read from the expected address index array until it is updated to the data field corresponding to the expected memory access request in the response queue.

13. The method according to claim 1, characterized in that Before obtaining the request processing information of the design to be tested, the method further includes: Obtaining a memory access request of the design to be tested, where the memory access request is a first memory access request or a second memory access request, where the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created by the design to be tested based on the first memory access request; If the memory access request is the first memory access request, recording the memory access request into a sequential request queue and a request queue respectively; If the memory access request is the second memory access request, the memory access request is recorded in a request queue.

14. The method according to claim 1, characterized in that The amount of data corresponds to the number of bytes; The second memory access request with the second data amount corresponds to a second memory access request with a byte number of the second data amount, and the byte number of the second data amount at least includes a byte number of 128B.

15. A memory access verification system, characterized in that: include: Design under test and verification reference model; The design under test is used to execute a memory access request, the memory access request is a first memory access request or a second memory access request, the first memory access request has a first data amount, the second memory access request has a second data amount, and the second memory access request is created based on the first memory access request; and based on the execution of the memory access request, sending request processing information and memory response data of the currently processed memory access request to the verification reference model; The verification reference model is used to obtain request processing information and memory response data of the design to be tested, and perform memory access verification based on the request processing information and the memory response data.

16. The memory access verification system according to claim 15, characterized in that: The verification reference model obtains request processing information and memory response data of the design to be tested, and performs memory access verification according to the request processing information and the memory response data, including: Obtaining request processing information of the design under test, wherein the request processing information is the content of the memory access request currently processed by the design under test; According to the request processing information, a memory access request corresponding to the request processing information is determined in a request queue, and the memory access request is used as an expected memory access request; wherein the request queue records a first memory access request with a first data amount, and a second memory access request with a second data amount created by the design under test based on the first memory access request; If the expected memory access request meets the preset condition, the expected memory access request is recorded in the response queue; Acquire memory response data of the design to be tested, and update the memory response data to a data field in the response queue corresponding to the expected memory access request; sequentially reading a first memory access request in the sequential request queue, and determining reference data according to the first memory access request; wherein the first memory access request is recorded in the sequential request queue while being recorded in the request queue; Compare the reference data with the memory response data to see if they are the same, and if so, the verification is successful.

17. A verification platform, characterized in that: It comprises a memory access verification system as described in any one of claims 15 to 16.

18. A computing device comprising a processor and a memory, characterized in that: The hardware logic design of the memory is verified by the memory access verification method according to any one of claims 1 to 14.

19. A computer program product, characterized in that It comprises one or more computer executable instructions, and when the one or more computer executable instructions are executed, the memory access verification method according to any one of claims 1 to 14 is implemented.

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