A message processing and transmission device on a CXL switching chip

Abstract

The present invention belongs to the field of switching chips, and relates to a message processing and transmission device on a CXL switching chip, including a CXL switching interface unit module, a ring topology on-chip network, and a CXL management unit module; the CXL switching interface unit module is used to receive and parse messages of two sub-protocols, .cache and .mem, sent by a CXL device directly connected to the CXL switching chip, and then convert and encapsulate these messages into message formats that comply with the ring topology on-chip network standard, and then transmit them through the ring topology on-chip network; at the same time, the CXL switching interface unit module also needs to receive messages from the ring topology on-chip network, convert and encapsulate them into corresponding CXL sub-protocol message formats, and then distribute them to other CXL devices. The present invention has the characteristics of high bandwidth, low latency, and multi-channel concurrency, and provides an efficient transmission channel for a large number of memory data access scenarios; it also has the advantages of high scalability and friendliness to chip back-end physical implementation.

Description

Technical Field

[0001] The invention relates to a message processing and transmission device on a CXL switching chip, belonging to the technical field of switching chips. Background Art

[0002] The existing CXL switching chip only supports the CXL 2.0 protocol, and its message processing and transmission process is still carried out according to the PCIe tree structure, which has great limitations. At the same time, the existing CXL switching chip interconnection is mainly based on the switching matrix, which cannot cope with the increase in the number of ports.

[0003] Based on this, the present invention is proposed. Summary of the invention

[0004] The present invention provides a message processing and transmission device on a CXL switch chip, which supports the transmission and routing of the CXL3.0 protocol, and at the same time greatly expands the data processing capability of the switch chip through a ring topology on-chip network, thereby improving the overall transmission performance. The specific technical solution is as follows:

[0005] A message processing and transmission device on a CXL switching chip, comprising a CXL switching interface unit module, a ring topology on-chip network and a CXL management unit module;

[0006] The CXL switch interface unit module is used to receive and parse the .cache and .mem sub-protocol messages sent by the CXL device directly connected to the CXL switch chip, and then convert and encapsulate these messages into a message format that complies with the ring topology on-chip network standard, and then transmit them through the ring topology on-chip network; at the same time, the CXL switch interface unit module also needs to receive messages from the ring topology on-chip network, convert and encapsulate them into the corresponding CXL sub-protocol message format, and then distribute them to other CXL devices;

[0007] The circular ring topology on-chip network includes routing nodes and interconnection paths, wherein the interconnection paths are transmission channels between routing nodes, and the interconnection paths are responsible for point-to-point interconnection between two routing nodes;

[0008] The CXL management unit module is responsible for initializing and configuring all CXL switch interface unit modules and the ring topology network on chip.

[0009] As a further improvement, the CXL switch interface unit module includes a PCIe physical layer, a CXL controller, a .cache protocol processing unit, and a .mem protocol processing unit;

[0010] The PCIe physical layer is responsible for implementing the physical layer functions defined in the PCIe protocol standard, covering data transmission / reception, encoding / decoding, link training, scrambling / descrambling, and state machine initialization on a high-speed serial link;

[0011] The CXL controller is responsible for implementing the functional requirements of the data link layer and the transaction layer in the CXL protocol standard, and also covers the creation / parsing of transaction layer messages, QoS management, and transaction order preservation tasks;

[0012] The CXL controller is connected to the PCIe physical layer via a standard PIPE interface; the CXL controller also has two sets of parallel data interfaces, which are respectively connected to the .cache protocol processing unit and the .mem protocol processing unit to realize message interaction.

[0013] As a further improvement, the .cache protocol processing unit includes a .cache uplink processing module and a .cache downlink processing module;

[0014] The .cache uplink processing module is responsible for receiving and forwarding .cache messages from the CXL controller. The functions of the .cache uplink processing module include .cache message parsing, Cache ID routing table, and TLP encapsulation module. The .cache uplink processing module needs to simultaneously obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information.

[0015] The function of the Cache ID routing table is to find the destination ID of the target port according to the Cache ID information, and the SPID is obtained through the port binding information;

[0016] The TLP encapsulation module is responsible for packaging and outputting the D2H_REQ / D2H_RSP / D2H_DATA TLP messages and the corresponding DPID, and at the same time obtaining the target node ID of the ring topology network-on-chip according to the DPID and outputting it to the ring topology network-on-chip;

[0017] The .cache downlink processing module is responsible for receiving and forwarding .cache messages from the ring topology on-chip network. The functions of the .cache downlink processing module include extracting the H2D_REQ / H2D_RSP / D2H_REQ / D2H_RSP message header, message data, and Cache ID in the message, and judging whether the CXL switch interface unit module ID in the message is consistent with the CXL switch interface unit module where the module is located; if they are consistent, the message header, message data, and Cache ID are output to the downstream TLP encapsulation module; if they are inconsistent, the message is discarded as an illegal message and an error is reported; and then the received message header, message data, and Cache ID are divided into six channel types of H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP, and D2H_DATA for encapsulation.

[0018] For further improvement, the .cache message parsing needs to receive and parse the messages of the six channels of .cache, namely H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP and D2H_DATA. The messages of each channel are transmitted independently and parsed separately. It is necessary to extract the Cache ID field in the message and output the following information respectively:

[0019] H2D_REQ, H2D_RSP, H2D_DATA channels: output Cache ID and the corresponding TLP message containing the Cache ID to the Cache ID routing table;

[0020] D2H_REQ, D2H_RSP, D2H_DATA channels: The D2H_REQ channel obtains the CacheID according to the bound port information and adds it to the message, and then sends the corresponding message containing the Cache ID to the TLP encapsulation module; D2H_RSP and D2H_DATA obtain the corresponding DPID according to the port binding information.

[0021] In a further improvement, the .cache message processing flow of the message processing and transmission device on the CXL switch chip includes the following steps: the .cache message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller, and then the CXL switch interface unit module parses the message; the H2D_REQ / H2D_RSP / H2D_DATA message extracts the corresponding cache ID and TLP and inputs it into the Cache The ID routing table is looked up to obtain the DPID and send the message to the TLP encapsulation module; the D2H_REQ / D2H_RSP / D2H_DATA message obtains the CacheID and DPID according to the information of the bound port, and sends the message to the TLP encapsulation module; the message sent to the TLP encapsulation module is TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until it reaches the destination CXL switching interface unit module, and then the .cache message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, thus completing the transmission of the entire .cache message.

[0022] As a further improvement, the .mem protocol processing unit includes a .mem uplink processing module and a .mem downlink processing module;

[0023] The .mem uplink processing module is responsible for receiving and parsing the .mem messages input from the .mem message interface of the CXL controller according to the six channel types of M2S_REQ, M2S_RWQ, M2S_BIRSP, S2M_DRS, S2M_NDR, and S2M_BISNP;

[0024] The .mem uplink processing module also needs to obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information;

[0025] The .mem message parsing module extracts each valid field in the message according to the channel type and outputs the following information respectively:

[0026] Both the M2S_REQ channel and the M2S_RWD channel output the HDM address and the corresponding channel message containing the HDM address to the FAST routing table. After the FAST routing table is looked up, the destination port DPID is output. Then, the TLP encapsulation module obtains the TDID of the donut topology on-chip network according to the DPID, and packages the message and outputs it to the donut topology on-chip network.

[0027] The S2M_DRS channel, S2M_NDR channel, and S2M_BISNP channel output DPID information and corresponding TDID to the ring topology on-chip network for direct routing according to the port binding information;

[0028] The M2S_BIRSP channel outputs the BI ID, converts the BI ID into the corresponding DPID and TDID, and outputs the corresponding channel message containing the BIID to the ring topology on-chip network;

[0029] The .mem downstream processing module is used to receive the transaction packet transmitted from the ring topology on-chip network, unpack the transaction packet and reorganize it into the format of each CXL channel, and decode and forward it according to the different ports of the downstream connection; the .mem downstream processing module extracts the M2S_REQ / M2S_RWD / S2M_DRS / S2M_NDR / S2M_BISNP / M2S_BIRSP message header, message data, and device ID in the message, and determines whether the DPID in the message is consistent with the CXL switching interface unit module where it is located. If consistent, the above message header, message data, and logical device ID are output to the downstream .mem message encapsulation module; if inconsistent, the message is discarded as an illegal message and an error is reported;

[0030] The .mem message encapsulation module is responsible for encapsulating the message header, message data and device ID into six channel types: M2S_REQ, M2S_RWD, S2M_DRS, S2M_NDR, S2M_BISNP and M2S_BIRSP.

[0031] Further improvement, the .mem message processing flow of the message processing and transmission device on the CXL switch chip includes the following steps: the .mem message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller, and then the CXL switch interface unit module parses the message; the M2S_REQ / M2S_RWD message extracts the corresponding HDM address and TLP, inputs it into the FAST routing table for table lookup, obtains the DPID and sends the message to the TLP encapsulation module; M2S_BIRSP extracts the corresponding HDM address and TLP according to the BI The DPID is directly obtained from the ID. The S2M_DRS / S2M_NDR / S2M_BISNP message obtains the DPID according to the information of the bound port and sends the message to the TLP encapsulation module. The messages sent to the TLP encapsulation module are all TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until they reach the destination CXL switching interface unit module, and then the .mem message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, thus completing the transmission of the entire .mem message.

[0032] As a further improvement, the routing node is used to connect the .cache uplink processing module and the .cache downlink processing module of the .cache protocol processing unit and the .mem uplink processing module and the .mem downlink processing module of the .mem protocol processing unit, and is also responsible for the routing transmission of the TLP message in the network;

[0033] The routing node supports a maximum of 2 ports connected to the CXL switching interface unit module. Each routing node is connected to 1 CXL switching interface unit module or 2 CXL switching interface unit modules. There are 6 bidirectional channels between the routing node and the CXL switching interface unit module or between the routing nodes. Each routing node is numbered according to the coordinates according to its location. The CXL switching interface unit module inputs the coordinates of the target node, and the routing node adds the coordinates of the current node as the source node coordinates. For a specific source node and destination node, routing is performed according to the source coordinate TSID and the destination coordinate TDID.

[0034] A further improvement is that the shortest path routing is followed when routing, that is, the routing with the shortest number of hops from the source node to the destination node is performed; if there are multiple paths with the shortest number of hops at the same time, the super-path routing is given priority by default; the routing rules are configured through the CXL management unit module.

[0035] As a further improvement, the initialization and configuration of the CXL management unit module includes:

[0036] 1) Cache ID routing table and TLP encapsulation module in the cache protocol processing unit;

[0037] 2) FAST routing table and port ID register in the .mem protocol processing unit;

[0038] 3) Ring topology on-chip network routing control register group, this register group controls the routing algorithm and rules.

[0039] Beneficial effects of the present invention:

[0040] 1. The circular ring topology on-chip network provided by the present invention has the characteristics of high bandwidth, low latency, and multi-channel concurrency, and provides an efficient transmission channel for a large number of memory data access scenarios.

[0041] 2. The present invention is highly scalable, and the number of CXL switch interface unit modules and the size of the circular ring topology on-chip network can be very efficiently expanded according to actual needs.

[0042] 3. The present invention is friendly to the physical implementation of the chip backend, is conducive to the layout and wiring work on the chip, and can achieve a higher operating frequency, thereby obtaining higher performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is a top-level architecture diagram of the message processing and transmission device on the CXL switch chip of the present invention;

[0044] Figure 2 This is the architecture diagram of the CXL switch interface unit module;

[0045] Figure 3 This is the structure diagram of the Cache ID routing table;

[0046] Figure 4 This is the structural diagram of the TLP packaging module;

[0047] Figure 5 This is the structural diagram of the FAST routing table;

[0048] Figure 6 It is a structural diagram of a ring topology network on chip;

[0049] Figure 7 This is a diagram of the transmission channel structure between routing nodes on a circular ring topology network.

[0050] Figure 8 .cache message processing flow;

[0051] Fig. 9 This is the processing flow of .mem messages. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0053] Definitions of Abbreviations and Key Terms

[0054] CXL: Compute Express Link, a cache-coherent interconnect protocol standard for processors, memory extensions, and accelerators;

[0055] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard;

[0056] FM: Fabric Manager, network manager;

[0057] SLD: Single Logical Device, single logical device;

[0058] MLD: Multi Logical Device, multiple logical devices;

[0059] TLP: Transaction Layer Packet, transaction layer message;

[0060] PIPE: Physical Interface for PCI Express, PCIe physical layer interface;

[0061] ID: Identifier, identifier;

[0062] Cache ID, CXL cache device ID;

[0063] HDM: Host-managed Device Memory, device memory managed by the host;

[0064] BI: Back-Invalidate, back-invalidation;

[0065] BI ID: CXL.mem device ID that initiated the BI;

[0066] UR: Unsupported Request, illegal request response message;

[0067] USP: Upstream Port, the upstream port of the switching chip;

[0068] .io: CXL input and output subprotocol;

[0069] .mem: CXL memory subprotocol;

[0070] .cache: CXL cache subprotocol;

[0071] P2P: Peer-to-Peer, point-to-point transmission;

[0072] cache: cache;

[0073] Host: host;

[0074] D2H: Device to Host;

[0075] H2D: Host to Device;

[0076] M2S: Master to Slave, master device to slave device;

[0077] S2M: Slave to Master, from device to master device;

[0078] M2S_REQ: Master to slave request

[0079] M2S_RWQ: Master device requests data from slave device

[0080] M2S_BIRSP: Master to slave return invalid channel response

[0081] S2M_DRS: slave to master data response

[0082] S2M_NDR: No data response from slave to master

[0083] S2M_BISNP: Invalid channel monitoring request returned from the slave to the master

[0084] D2H_REQ: device to host request;

[0085] H2D_RSP: host to device response;

[0086] H2D_DATA: host to device data;

[0087] D2H_REQ: Host to device request;

[0088] D2H_RSP: device to host response;

[0089] D2H_DATA: device to host data;

[0090] Mem.req: CXL.mem protocol request channel;

[0091] Mem.rsp: CXL.mem protocol response channel;

[0092] Mem.dat: CXL.mem protocol data channel;

[0093] Cache.req: CXL.cache protocol request channel;

[0094] Cache.rsp: CXL.cache protocol response channel;

[0095] Cache.dat: CXL.cache protocol data channel;

[0096] PBR: Port Based Routing, port-based routing

[0097] SPID: Source Port ID, source node ID

[0098] DPID: Destination Port ID, destination node ID

[0099] PortID: port ID;

[0100] TDID: Torus Destination ID, torus topology destination node ID;

[0101] TSID: Torus Source ID, torus topology source node ID;

[0102] FAST: Fabric-attached Segment Table, interconnected segment table;

[0103] Torus: a torus topology network-on-chip.

[0104] SIU: Switch Interface Unit, switch interface unit;

[0105] XID: X-axis coordinate;

[0106] YID: Y-axis coordinate. Example 1

[0107] The present invention provides a message processing and transmission device on a CXL switch chip, which implements a high-bandwidth, low-latency, and highly scalable ring-shaped topology network-on-chip for CXL .cache subprotocol and .mem subprotocol messages, completes message transmission and forwarding, and effectively improves the performance of the shared memory system. All nodes on the CXL switch chip are identified by a unique ID, and the routing method is PBR routing.

[0108] like Figure 1 , 2 As shown, the message processing and transmission device on the CXL switch chip of the present invention includes a CXL switch interface unit module, a ring topology network on chip and a CXL management unit module;

[0109] 1. The CXL switch interface unit module includes a PCIe physical layer, a CXL controller, a .cache protocol processing unit, and a .mem protocol processing unit; the main responsibilities of the CXL switch interface unit module include: receiving and parsing messages of two sub-protocols (.cache and .mem) sent by the CXL device directly connected to the CXL switch chip, and then converting and encapsulating these messages into a message format that complies with the ring topology on-chip network standard, and then transmitting them through the ring topology on-chip network. At the same time, the CXL switch interface unit module also needs to receive messages from the ring topology on-chip network, convert and encapsulate them into the corresponding CXL sub-protocol (.cache and .mem) message format, and then distribute them to other CXL devices.

[0110] 1.1. The PCIe physical layer is responsible for implementing the physical layer functions defined in the PCIe protocol standard, covering key links such as data transmission / reception, encoding / decoding, link training, scrambling / descrambling, and state machine initialization on high-speed serial links, such as Figure 2 As shown in the figure. Since the CXL protocol reuses the protocol standard of the PCIe physical layer, the communication between the CXL switch chip and other CXL devices is achieved through the high-speed serial link provided by the PCIe physical layer. The logical sublayer of the PCIe / CXL physical layer (referred to as the PCIe / CXL logical sublayer) is responsible for data encoding and link training. The electrical sublayer of the PCIe / CXL physical layer (referred to as the PCIe / CXL electrical sublayer) is responsible for driving and receiving signals to meet the electrical characteristics specifications.

[0111] 1.2. The CXL controller is responsible for implementing the functional requirements of the data link layer and transaction layer in the CXL protocol standard. These functions include but are not limited to link management, flow control, power management, frame error detection, and reliable message transmission, as well as key tasks such as transaction layer message creation / parsing, QoS (Quality of Service) management, and transaction order preservation. The CXL controller is connected to the PCIe physical layer through a standard PIPE interface; at the same time, the CXL controller also has two sets of parallel data interfaces, which are connected to different protocol processing units to realize message interaction: one set of parallel data interfaces is used for the .cache message interface, which is connected to the .cache protocol processing unit; the other set of parallel data interfaces is used for the .mem message interface, which is connected to the .mem protocol processing unit.

[0112] 1.3. The .cache protocol processing unit includes a .cache uplink processing module and a .cache downlink processing module.

[0113] 1.3.1, the .cache protocol uplink processing module is responsible for receiving and forwarding .cache messages from the CXL controller, and its main functions include .cache message parsing, Cache ID routing table, and TLP encapsulation module functions. In addition, it is necessary to obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information.

[0114] .cache message parsing requires receiving and parsing messages from the six channels of .cache (H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP, D2H_DATA). The messages of each channel are transmitted and parsed separately. The Cache ID field in the message needs to be extracted and the following information needs to be output respectively:

[0115] H2D_REQ, H2D_RSP, H2D_DATA channels: output Cache ID and the corresponding TLP message containing the Cache ID to the Cache ID routing table;

[0116] D2H_REQ, D2H_RSP, D2H_DATA channels: D2H_REQ channel obtains CacheID according to the bound port information and adds it to the message, and then sends the corresponding message containing the Cache ID to the TLP encapsulation module. D2H_RSP and D2H_DATA obtain the corresponding DPID according to the port binding information.

[0117] The main function of the Cache ID routing table is to find the destination ID (DPID) of the target port based on the Cache ID information. The SPID is obtained through the port binding information. The structure of the Cache ID routing table is as follows: Figure 3 As shown in the figure, the routing table has n indexes in total, which record the DPID and TDID information corresponding to different cache IDs. The message is subsequently routed in the chip according to the DPID and TDID, and the valid bit indicates whether the entry of the index is valid.

[0118] The TLP encapsulation module is responsible for packaging and outputting the D2H_REQ / D2H_RSP / D2H_DATA TLP messages and the corresponding DPIDs, and at the same time obtaining the target node ID (X, Y) of the ring topology network-on-chip according to the DPID and outputting it to the ring topology network-on-chip. The structure of the TLP encapsulation module is as follows: Figure 4 The function of the TLP encapsulation module is mainly to encapsulate the message in the CXL protocol standard format into a message format that can be transmitted by the ring topology on-chip network. The port binding register group mainly includes the registers required for each port to complete the binding function.

[0119] 1.3.2. The .cache downlink processing module is responsible for receiving and forwarding .cache messages from the ring topology on-chip network. Its main functions include extracting the H2D_REQ / H2D_RSP / D2H_REQ / D2H_RSP message header, message data, and Cache ID in the message, and determining whether the CXL switch interface unit module ID in the message is consistent with the CXL switch interface unit module where it is located; if consistent, the message header, message data, and Cache ID are output to the downstream TLP encapsulation module; if inconsistent, the message is discarded as an illegal message and an error is reported; then the received message header, message data, and Cache ID are divided into six channel types: H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP, and D2H_DATA for encapsulation. Example 2

[0120] The message processing on the CXL switch chip and the .cache message processing flow of the transmission device are as follows: Figure 8 As shown in the figure: the .cache message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller. Then the CXL switch interface unit module will parse the message. According to different message types, the H2D_REQ / H2D_RSP / H2D_DATA message extracts the corresponding cache ID and TLP, inputs them into the Cache ID routing table for table lookup, obtains the DPID and sends the message to the TLP encapsulation module; the D2H_REQ / D2H_RSP / D2H_DATA message obtains the CacheID and DPID according to the information of the bound port, and sends the message to the TLP encapsulation module; both types of messages sent to the TLP encapsulation module are TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until they reach the destination CXL switch interface unit module, and then the .cache message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, and the transmission of the entire .cache message is completed. Example 3

[0121] 1.4. The .mem protocol processing unit includes a .mem uplink processing module and a .mem downlink processing module.

[0122] 1.4.1. The .mem uplink processing module is mainly responsible for receiving and parsing the .mem messages input from the .mem message interface of the CXL controller according to the six channel types of M2S_REQ, M2S_RWQ, M2S_BIRSP, S2M_DRS, S2M_NDR, and S2M_BISNP; each channel maintains the independence of .mem message parsing and data transmission, and the channels do not interfere with each other. In addition, it is necessary to obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information.

[0123] .mem message parsing extracts each valid field in the message according to the channel type and outputs the following information respectively:

[0124] Both the M2S_REQ channel and the M2S_RWD channel output the HDM address and the corresponding channel message containing the HDM address to the FAST routing table. After looking up the FAST routing table, the destination port DPID is output. The TLP encapsulation module then obtains the TDID of the donut-shaped topology network-on-chip based on the DPID, and packages the message and outputs it to the donut-shaped topology network-on-chip.

[0125] The FAST routing table structure is as follows Figure 5 As shown in the figure, the routing table has n indexes, which record the DPID and TDID information corresponding to different message addresses. The message is subsequently routed in the chip according to the DPID and TDID, and the valid bit indicates whether the entry of the index is valid. The interleaving bit is 4 bits wide, which defines how many targets the request will be interleaved between, and the interleaving granularity defines the unit size of its interleaving behavior conversion.

[0126] The S2M_DRS channel, S2M_NDR channel and S2M_BISNP channel output DPID information and corresponding TDID to the ring topology on-chip network for direct routing according to the port binding information.

[0127] The M2S_BIRSP channel outputs the BI ID, converts the BI ID into the corresponding DPID and TDID, and outputs the corresponding channel message containing the BIID to the ring topology on-chip network.

[0128] 1.4.2. The function of the .mem downstream processing module is to receive the transaction packet transmitted from the ring topology on-chip network, unpack the transaction packet and reorganize it into the format of each CXL channel, and decode and forward it according to the different ports of the downstream connection. The .mem downstream processing module extracts the M2S_REQ / M2S_RWD / S2M_DRS / S2M_NDR / S2M_BISNP / M2S_BIRSP message header, message data, and device ID in the message, and determines whether the DPID in the message is consistent with the CXL switch interface unit module where it is located. If consistent, the above message header, message data, and logical device ID are output to the downstream .mem message encapsulation module; if inconsistent, the message is discarded as an illegal message and an error is reported.

[0129] The .mem message encapsulation module is responsible for encapsulating the message header, message data and device ID into six channel types: M2S_REQ, M2S_RWD, S2M_DRS, S2M_NDR, S2M_BISNP and M2S_BIRSP. Example 4

[0130] The message processing on the CXL switch chip and the .mem message processing flow of the transmission device are as follows: Fig. 9As shown in the figure: The .mem message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller. Then the CXL switch interface unit module parses the message. According to different message types, the M2S_REQ / M2S_RWD message extracts the corresponding HDM address and TLP, inputs it into the FAST routing table for table lookup, obtains the DPID and sends the message to the TLP encapsulation module; M2S_BIRSP extracts the corresponding HDM address and TLP according to the BI The DPID is directly obtained from the ID. The S2M_DRS / S2M_NDR / S2M_BISNP message obtains the DPID according to the information of the bound port and sends the message to the TLP encapsulation module. The three types of messages sent to the TLP encapsulation module are all TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until it reaches the destination CXL switching interface unit module, and then the .mem message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, thus completing the transmission of the entire .mem message. Example 5

[0131] 2. Ring topology network on chip

[0132] The ring topology on-chip network consists of routing nodes and interconnection paths (i.e., transmission channels between routing nodes). Routing nodes are mainly used to connect the .cache uplink processing module and .cache downlink processing module of the .cache protocol processing unit and the .mem uplink processing module and .mem downlink processing module of the .mem protocol processing unit, and are also responsible for the routing transmission of TLP messages in the network; the interconnection path is mainly responsible for point-to-point interconnection between two routing nodes. A source node and a destination node may have multiple paths, and the actual TLP routing line is determined by the routing algorithm.

[0133] The routing node supports up to 2 ports connected to the CXL switch interface unit module, such as Figure 6 As shown, each routing node is connected to one CXL switch interface unit module or two CXL switch interface unit modules, and between the routing node and the CXL switch interface unit module or between the routing node and the routing node, as shown in FIG. Figure 7As shown, all of them are bidirectional 6 channels (Mem.req, Mem.rsp, Mem.dat, Cache.req, Cache.rsp, Cache.dat). Each routing node is numbered according to its location according to the (X, Y) coordinates. The CXL switching interface unit module inputs the (X, Y) coordinates of the target node, and the routing node adds the (X, Y) coordinates of the current node as the source node coordinates. Therefore, for a specific source node and destination node, routing is performed according to the source coordinates TSID (X0, Y0) and the destination coordinates TDID (X1, Y1). Since there is a superpath in the ring topology (the path directly connected to the 4 vertex nodes is called a superpath), there is a possibility of multiple paths when routing the source node and the destination node.

[0134] in, Figure 6 The numbers in the box represent the X and Y coordinates.

[0135] The routing method follows static XY routing and shortest path routing. XY routing means routing by X coordinate first, and when the X coordinates are the same, routing by Y coordinate.

[0136] When the XID of the destination node is different from the XID of the current routing node, if the destination node XID is greater than the current XID, route to the east; otherwise, route to the west;

[0137] When the XID of the destination node is the same as the XID of the current routing node, if the YID of the destination node is greater than the current YID, the route is to the north; otherwise, the route is to the south.

[0138] When the XID and YID of the routing node are the same as the destination node ID, the destination is reached.

[0139] Since there may be multiple paths between the source node and the destination node of the ring topology on-chip network, the shortest path routing is followed during routing, that is, the route with the shortest hop count from the source node to the destination node is routed; if there are multiple paths with the shortest hop count at the same time, the hyperpath routing is prioritized by default. For example, when routing from the source node (0,0) to the destination node (2,0), there are two shortest paths, which can be routed from (0,0)→(1,0)→(2,0) or (0,0)→(3,0)→(2,0). In this case, the second path is selected for routing. Routing rules can be configured through the CXL management unit module, such as setting the hyperpath to a low priority or dynamically routing based on traffic. Example 6

[0140] 3) CXL management unit module

[0141] The CXL management unit module is responsible for initializing and configuring all CXL switch interface unit modules and the ring topology on-chip network. The initialization and configuration content specifically includes:

[0142] 1) Cache ID routing table, TLP encapsulation module, and port binding register group in the cache protocol processing unit;

[0143] 2) FAST routing table and port ID register in the .mem protocol processing unit;

[0144] 3) Ring topology on-chip network routing control register group, this register group mainly controls the routing algorithm and rules.

[0145] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A message processing and transmission device on a CXL switching chip, characterized in that: It includes a CXL switch interface unit module, a ring topology network on chip and a CXL management unit module; The CXL switch interface unit module is used to receive and parse the .cache and .mem sub-protocol messages sent by the CXL device directly connected to the CXL switch chip, and then convert and encapsulate these messages into a message format that complies with the ring topology on-chip network standard, and then transmit them through the ring topology on-chip network; at the same time, the CXL switch interface unit module also needs to receive messages from the ring topology on-chip network, convert and encapsulate them into the corresponding CXL sub-protocol message format, and then distribute them to other CXL devices; The circular ring topology on-chip network consists of nodes and interconnection paths, wherein the interconnection path is a transmission channel between routing nodes, and the interconnection path is responsible for point-to-point interconnection between two routing nodes; The CXL management unit module is responsible for initializing and configuring all CXL switch interface unit modules and the ring topology on-chip network; The CXL switch interface unit module includes a PCIe physical layer, a CXL controller, a .cache protocol processing unit, and a .mem protocol processing unit; The PCIe physical layer is responsible for implementing the physical layer functions defined in the PCIe protocol standard, covering data transmission / reception, encoding / decoding, link training, scrambling / descrambling, and state machine initialization on a high-speed serial link; The CXL controller is responsible for implementing the functional requirements of the data link layer and the transaction layer in the CXL protocol standard, and also covers the creation / parsing of transaction layer messages, QoS management, and transaction order preservation tasks; The CXL controller is connected to the PCIe physical layer via a standard PIPE interface; the CXL controller also has two sets of parallel data interfaces, which are respectively connected to the .cache protocol processing unit and the .mem protocol processing unit to realize message interaction.

2. The message processing and transmission device on a CXL switch chip according to claim 1, characterized in that: The .cache protocol processing unit includes a .cache uplink processing module and a .cache downlink processing module; The .cache uplink processing module is responsible for receiving and forwarding .cache messages from the CXL controller. The functions of the .cache uplink processing module include .cache message parsing, Cache ID routing table, and TLP encapsulation module. The .cache uplink processing module needs to simultaneously obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information. The function of the Cache ID routing table is to find the destination ID of the target port according to the Cache ID information, and the SPID is obtained through the port binding information; The TLP encapsulation module is responsible for packaging and outputting the D2H_REQ / D2H_RSP / D2H_DATA TLP messages and the corresponding DPID, and at the same time obtaining the target node ID of the ring topology network-on-chip according to the DPID and outputting it to the ring topology network-on-chip; The .cache downlink processing module is responsible for receiving and forwarding .cache messages from the ring topology on-chip network. The functions of the .cache downlink processing module include extracting the H2D_REQ / H2D_RSP / D2H_REQ / D2H_RSP message header, message data, and Cache ID in the message, and judging whether the CXL switch interface unit module ID in the message is consistent with the CXL switch interface unit module where the module is located; if they are consistent, the message header, message data, and Cache ID are output to the downstream TLP encapsulation module; if they are inconsistent, the message is discarded as an illegal message and an error is reported; and then the received message header, message data, and Cache ID are divided into six channel types of H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP, and D2H_DATA for encapsulation.

3. The message processing and transmission device on a CXL switch chip according to claim 2, characterized in that: The .cache message parsing needs to receive and parse the messages of the six channels of .cache, namely H2D_REQ, H2D_RSP, H2D_DATA, D2H_REQ, D2H_RSP and D2H_DATA. The messages of each channel are transmitted independently and parsed separately. It is necessary to extract the Cache ID field in the message and output the following information respectively: H2D_REQ, H2D_RSP, H2D_DATA channels: output Cache ID and the corresponding TLP message containing the Cache ID to the Cache ID routing table; D2H_REQ, D2H_RSP, D2H_DATA channels: The D2H_REQ channel obtains the Cache ID according to the bound port information and adds it to the message, and then sends the corresponding message containing the Cache ID to the TLP encapsulation module; D2H_RSP and D2H_DATA obtain the corresponding DPID according to the port binding information.

4. The message processing and transmission device on a CXL switch chip according to claim 3, characterized in that: The .cache message processing flow of the message processing and transmission device on the CXL switch chip includes the following steps: the .cache message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller, and then the CXL switch interface unit module parses the message; the H2D_REQ / H2D_RSP / H2D_DATA message extracts the corresponding cache ID and TLP and inputs them into the Cache The ID routing table is looked up to obtain the DPID and send the message to the TLP encapsulation module; the D2H_REQ / D2H_RSP / D2H_DATA message obtains the CacheID and DPID according to the information of the bound port, and sends the message to the TLP encapsulation module; the message sent to the TLP encapsulation module is TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until it reaches the destination CXL switching interface unit module, and then the .cache message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, thus completing the transmission of the entire .cache message.

5. The message processing and transmission device on a CXL switch chip according to claim 2, characterized in that: The .mem protocol processing unit includes a .mem uplink processing module and a .mem downlink processing module; The .mem uplink processing module is responsible for receiving and parsing the .mem messages input from the .mem message interface of the CXL controller according to the six channel types of M2S_REQ, M2S_REQ, M2S_BIRSP, S2M_DRS, S2M_NDR, and S2M_BISNP; The .mem uplink processing module also needs to obtain the (X, Y) coordinates of the destination node on the ring topology on-chip network according to the address and output the TDID information; .mem message parsing extracts each valid field in the message according to the channel type and outputs the following information respectively: Both the M2S_REQ channel and the M2S_RWD channel output the HDM address and the corresponding channel message containing the HDM address to the FAST routing table. After the FAST routing table is looked up, the destination port DPID is output. Then, the TLP encapsulation module obtains the TDID of the donut topology on-chip network according to the DPID, and packages the message and outputs it to the donut topology on-chip network. The S2M_DRS channel, S2M_NDR channel, and S2M_BISNP channel output DPID information and corresponding TDID to the ring topology on-chip network for direct routing according to the port binding information; The M2S_BIRSP channel outputs the BI ID, converts the BI ID into the corresponding DPID and TDID, and outputs the corresponding channel message containing the BI ID to the ring topology on-chip network; The .mem downstream processing module is used to receive the transaction packet transmitted from the ring topology on-chip network, unpack the transaction packet and reorganize it into the format of each CXL channel, and decode and forward it according to the different ports of the downstream connection; the .mem downstream processing module extracts the M2S_REQ / M2S_RWD / S2M_DRS / S2M_NDR / S2M_BISNP / M2S_BIRSP message header, message data, and device ID in the message, and determines whether the DPID in the message is consistent with the CXL switching interface unit module where it is located. If consistent, the above message header, message data, and logical device ID are output to the downstream .mem message encapsulation module; if inconsistent, the message is discarded as an illegal message and an error is reported; The .mem message encapsulation module is responsible for encapsulating the message header, message data and device ID into six channel types: M2S_REQ, M2S_RWD, S2M_DRS, S2M_NDR, S2M_BISNP and M2S_BIRSP.

6. The message processing and transmission device on a CXL switch chip according to claim 5, characterized in that: The .mem message processing flow of the message processing and transmission device on the CXL switch chip includes the following steps: the .mem message is first received and processed by the PCIe physical layer of the source CXL switch interface unit module, and then received and processed by the CXL controller, and then the CXL switch interface unit module parses the message; the M2S_REQ / M2S_RWD message extracts the corresponding HDM address and TLP, inputs it into the FAST routing table for table lookup, obtains the DPID and sends the message to the TLP encapsulation module; M2S_BIRSP extracts the corresponding HDM address and TLP according to the BI The DPID is directly obtained from the ID. The S2M_DRS / S2M_NDR / S2M_BISNP message obtains the DPID according to the information of the bound port and sends the message to the TLP encapsulation module. The messages sent to the TLP encapsulation module are all TLP encapsulated and TDID is output, and sent to the ring topology on-chip network for routing, switching and order preservation until they reach the destination CXL switching interface unit module, and then the .mem message is encapsulated and sent. After the CXL controller obtains the message, it is transmitted to the PCIe physical layer, thus completing the transmission of the entire .mem message.

7. The message processing and transmission device on a CXL switch chip according to claim 2, characterized in that: The routing node is used to connect the .cache uplink processing module and the .cache downlink processing module of the .cache protocol processing unit and the .mem uplink processing module and the .mem downlink processing module of the .mem protocol processing unit, and is also responsible for the routing transmission of the TLP message in the network; The routing node supports a maximum of 2 ports connected to the CXL switching interface unit module. Each routing node is connected to 1 CXL switching interface unit module or 2 CXL switching interface unit modules. There are 6 bidirectional channels between the routing node and the CXL switching interface unit module or between the routing nodes. Each routing node is numbered according to the coordinates according to its location. The CXL switching interface unit module inputs the coordinates of the target node, and the routing node adds the coordinates of the current node as the source node coordinates. For a specific source node and destination node, routing is performed according to the source coordinate TSID and the destination coordinate TDID.

8. The message processing and transmission device on a CXL switch chip according to claim 7, characterized in that: The shortest path routing is followed during routing, that is, the routing with the shortest number of hops from the source node to the destination node is performed; if there are multiple paths with the shortest number of hops at the same time, the superpath routing is given priority by default; the routing rules are configured through the CXL management unit module.

9. The message processing and transmission device on a CXL switch chip according to claim 2, characterized in that: The initialization and configuration of the CXL management unit module includes: 1) Cache ID routing table and TLP encapsulation module in the cache protocol processing unit; 2) FAST routing table and port ID register in the .mem protocol processing unit; 3) Ring topology on-chip network routing control register group, this register group controls the routing algorithm and rules.

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