Scheduling method for three-level non-blocking switching networks

Abstract

The invention belongs to the field of switching chip data communication, and relates to a three-level non-blocking switching network scheduling method. A three-level non-blocking switching network is first constructed, and N*N non-blocking switching is realized through a three-level crossbar architecture; the input switching L1 layer is k n*m fully interconnected switching nodes, the intermediate switching L2 layer is m k*k fully interconnected switching nodes, and the output switching L3 layer is k m*n fully interconnected switching nodes; the switching nodes of the output switching L3 layer are scheduled by a fair polling arbitration method; the switching nodes of the intermediate switching L2 layer adopt a fair polling arbitration method, and at the same time, OPstatus needs to be fed back to the switching nodes of the input switching L1 layer; the switching nodes of the input switching L1 layer select a sending path according to the flow control indication of the switching nodes of the intermediate switching L2 layer and the OPstatus of the switching nodes of the intermediate switching L2 layer in combination with fair polling arbitration. The invention has flexible scalability, realizes non-blocking switching of any input and output ports, and thus realizes multi-port non-blocking data exchange with high bandwidth and low latency.

Description

Technical Field

[0001] The invention relates to a three-level non-blocking switching network scheduling method, belonging to the technical field of switching chip data communication. Background Art

[0002] With the rapid advancement of information technology, big data has become a key force driving the development of all industries. The rapid development of big data has also posed new challenges to the underlying hardware architecture, especially the switching technology of the Network-on-Chip (NoC). The traditional crossbar architecture has dominated the early chip design due to its simplicity, directness and easy implementation. However, in the face of multi-port, high concurrency, low latency and dynamically changing data exchange requirements in big data scenarios, the limitations of the traditional crossbar architecture are becoming increasingly prominent.

[0003] Specifically, with the rapid growth of data volume, the traditional crossbar architecture has encountered bottlenecks in bandwidth expansion and the increase in the number of ports, making it difficult to meet the growing data processing needs. At the same time, when processing complex data streams and real-time communication tasks, the traditional crossbar architecture often cannot achieve efficient resource allocation and path optimization, resulting in increased data transmission delays and limited overall system performance.

[0004] At present, the research on three-level non-blocking switching network architecture mainly focuses on the field of Ethernet switching network, which has extremely high requirements for high reliability and high performance data transmission. The three-level non-blocking switching network architecture can effectively avoid network congestion and improve overall network performance while ensuring data transmission efficiency through its unique multi-level design and optimized routing algorithm.

[0005] Introducing the three-level non-blocking switching network architecture into the on-chip network design and implementation can not only significantly improve the switching capacity and port expansion capabilities, but also realize more flexible and configurable switching paths and resource allocation strategies. In the three-level non-blocking switching network architecture, data exchange is divided into multiple levels, and each level is responsible for data transmission and routing decisions in different ranges. This hierarchical design not only improves the parallelism and efficiency of data transmission, but also enables the system to dynamically adjust the switching logic and resource allocation according to the actual application scenarios and data flow characteristics, thereby optimizing the data transmission path, reducing latency, and improving overall performance.

[0006] Based on this, the present invention is proposed. Summary of the invention

[0007] The present invention provides a three-level non-blocking switching network scheduling method, and the specific technical scheme is as follows:

[0008] The three-level non-blocking switching network scheduling method comprises the following steps:

[0009] First, a three-level non-blocking switching network is constructed, which has N input ports and N output ports, and N*N non-blocking switching is realized through a three-level crossbar architecture;

[0010] When N ports are divided into k groups, that is, N=k*n, each group has n ports, namely P0, P1...Pn; the input switching L1 layer is k n*m fully interconnected switching nodes, the intermediate switching L2 layer is m k*k fully interconnected switching nodes, and the output switching L3 layer is k m*n fully interconnected switching nodes; N, k, n, m are all integers greater than 2;

[0011] The switch nodes at the output switching L3 layer are scheduled using fair round-robin arbitration;

[0012] The switch nodes at the intermediate switching L2 layer adopt fair polling arbitration and need to feed back the OPstatus to the switch nodes at the input switching L1 layer.

[0013] The switching node of the input switching L1 layer selects a sending path according to the flow control indication of the switching node of the intermediate switching L2 layer and the OPstatus of the switching node of the intermediate switching L2 layer in combination with fair polling arbitration.

[0014] Further improvement, m≥2n-1.

[0015] As a further improvement, the OPstatus of the switching node of the intermediate switching L2 layer is fed back to the switching node of the input switching L1 layer by adopting a specific coding method.

[0016] As a further improvement, the specific encoding method is one-hot encoding.

[0017] As a further improvement, the arbitration modules between the switching nodes of the input switching L1 layer are cascaded, avoiding the selected switching nodes of the intermediate switching L2 layer during fair polling; at the same time, the initial value of the fair polling module of the switching node of the input switching L1 layer is set to an incremental mode.

[0018] As a further improvement, a VOQ implementation is selected to be added to the input port of the switching node, and the scheduling method adds arbitration of the VOQ, wherein the arbitration is a polling scheduling algorithm or a specific scheduling algorithm based on the order requirement of the transmission protocol.

[0019] As a further improvement, the switching nodes of the input switching L1 layer, the switching nodes of the intermediate switching L2 layer and the switching nodes of the output switching L3 layer all include multiple input ports for accessing the switching network, a routing module, a switching network, and multiple switching node output ports. The routing module is responsible for distributing and scheduling input data requests, the switching network is a data path, transmitting input requests to the switching node output ports, and the flow control information is the flow control information from the switching nodes of the next layer.

[0020] Beneficial effects of the present invention:

[0021] 1. The present invention provides a three-level non-blocking switching network scheduling method, which has flexible scalability and can flexibly design the switching topology and flexibly configure the number of switching ports according to application requirements. Under the condition of meeting the switching topology requirements, non-blocking switching of any input and output ports can be realized, thereby realizing high-bandwidth and low-latency multi-port non-blocking data exchange; at the same time, the method solves the demand for high-bandwidth multi-port data exchange within the chip.

[0022] 2. The present invention aims at the link characteristics of the three-level non-blocking switching network, takes the arbitration status information of the intermediate-level switching as the routing selection strategy, and realizes efficient data exchange by combining routing scheduling and flow control mechanism.

[0023] 3. The present invention proposes a solution of increasing the RR initial value and cascading the RR state to avoid the input-level polling algorithm from selecting the same intermediate-level switching module at the same time.

[0024] 4. The present invention has the characteristic of being easy to implement in hardware.

[0025] 5. The present invention is friendly to the physical implementation of the chip backend, solves the problem of difficult large-scale switching layout and wiring, and meets the chip switching performance requirements through an achievable multi-level switching network. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A topological diagram of a three-level non-blocking switching network according to the present invention;

[0027] Figure 2 The architecture diagram of the switching node;

[0028] Figure 3 This is the topology diagram of the 12*12 non-blocking switching network in Example 2. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] Definitions of Abbreviations and Key Terms

[0031] RR: Round Robin, polling scheduling algorithm.

[0032] Crossbar architecture: a topology used to achieve efficient data exchange and communication in computer systems.

[0033] Node: A node is a connection point or endpoint in a network, which can be a processor, controller, or workstation, etc.

[0034] Switching node: A module that can interconnect multiple nodes in an on-chip switching network. Example 1

[0035] like Figure 1 As shown in the figure, the scheduling method of the three-level non-blocking switching network first constructs a three-level non-blocking switching network with N input ports and N output ports, and realizes N*N non-blocking switching through a three-level crossbar architecture. Assume that the N ports are divided into k groups, that is, N=k*n, and each group has n ports, namely P0, P1...Pn. The input switching L1 layer is k n*m fully interconnected switching nodes, the intermediate switching L2 layer is m k*k fully interconnected switching nodes, and the output switching L3 layer is k m*n fully interconnected switching nodes. By setting parameters reasonably (such as m≥2n-1), a strictly non-blocking switching network can be realized, that is, it is guaranteed that any unoccupied input and output ports can have a path to use. Among them, N, k, n, and m are all integers greater than 2.

[0036] The core scheduling method adopted by the switching nodes at different switching levels in the present invention is as follows:

[0037] The switching nodes at the output switching L3 layer adopt fair polling arbitration.

[0038] The switching nodes of the intermediate switching L2 layer adopt fair polling arbitration, and need to feed back OPstatus (output port status) to the switching nodes of the input switching L1 layer. The OPstatus of the switching nodes of the intermediate switching L2 layer can be fed back to the switching nodes of the input switching L1 layer using a specific encoding method (such as one-hot encoding).

[0039] The switching node of the input switching L1 layer selects a sending path according to the flow control indication of the switching node of the intermediate switching L2 layer and the OPstatus of the switching node of the intermediate switching L2 layer in combination with fair polling arbitration.

[0040] In particular, in order to prevent the switching nodes of the input switching L1 layer from randomly switching to the same switching node of the intermediate switching L2 layer at the same time, the arbitration modules between the switching nodes of the input switching L1 layer adopt a cascade mode, and avoid the selected switching nodes of the intermediate switching L2 layer during fair polling. The initial value of the fair polling module of the switching nodes of the input switching L1 layer is set to an incremental mode.

[0041] In addition, in order to prevent deadlock, the present invention can choose to add VOQ (virtual output queue) implementation at the input port of the switching node. The scheduling method needs to add VOQ arbitration, which can be a polling scheduling algorithm or a specific scheduling algorithm based on the transmission protocol sequence requirements.

[0042] like Figure 2 As shown in the figure, it is a switching node architecture that supports VOQ. In the figure, P0, P1, and P2 are three input ports for accessing the switching network. The routing module is responsible for distributing and scheduling input data requests. The switching network is the data path, which transmits the input request to the output port 0 / 1 / 2 / 3 of the switching node. The flow control information is the flow control information from the next layer of switching nodes. Figure 2 The switching node architecture shown can be implemented as a switching node of the input switching L1 layer, the intermediate switching L2 layer, and the output switching L3 layer in the proposed three-level switching network architecture. Example 2

[0043] Figure 3 The 12*12 switching network implemented by the present invention, wherein the input switching L1 layer is composed of four 3*5 switching nodes (the Figure 2 The intermediate switching L2 layer consists of five 4*4 switching nodes (the switching nodes of Example 1). Figure 2 The output switching L3 layer consists of 4 5*3 switching nodes (the switching nodes of Example 1). Figure 2 The switching node).

[0044] If the first port P0 of the first switching node of the input switching L1 layer, that is, the L1(0.0) port, requests to send data to the second port P1 of the third switching node of the output switching L3 layer, that is, the L3(2.1) port, the data transmission process in the switching network is as follows:

[0045] First, the input switching L1(0.0) data packet enters the input cache (which can be combined with VOQ) of the switching node numbered L1(0) of the input switching L1 layer, and initiates a data transmission request to the routing module of the L1(0) switching node; then, the routing module of the L1(0) switching node checks the port status information Opstatus and flow control information of all switching nodes of the intermediate switching L2 layer, excludes all the switching nodes of the intermediate switching L2 layer that are connected to the output switching L3(2) switching node where the target port is located, and searches for an available intermediate switching L2 layer switching node connected to the L1(0) output port of the input switching L1 layer among the remaining available intermediate switching L2 layer switching nodes. If there are multiple available intermediate switching L2 layer switching nodes, the routing module of the L1(0) switching node of the input switching L1 layer selects one randomly using a polling algorithm.

[0046] In particular, if at the initial moment, or when the links are mostly idle, the switching nodes of the input switching L1 layer randomly select output ports, and try to select the switching node ports of the intermediate switching L2 layer that are not used by other switching nodes of the input switching L1 layer. That is, the polling initial values ​​of the switching nodes of the input switching L1 layer should be different, and the switching nodes of the input switching L1 layer can observe each other's current arbitration status, so that the switching nodes of the intermediate switching L2 layer can be used more evenly.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-level non-blocking switching network scheduling method, characterized in that: The following steps are involved: First, a three-level non-blocking switching network is constructed, which has N input ports and N output ports, and N*N non-blocking switching is realized through a three-level crossbar architecture; When N ports are divided into k groups, that is, N=k*n, each group has n ports, namely P0, P1...Pn; the input switching L1 layer is k n*m fully interconnected switching nodes, the intermediate switching L2 layer is m k*k fully interconnected switching nodes, and the output switching L3 layer is k m*n fully interconnected switching nodes; N, k, n, m are all integers greater than 2; The switch nodes at the output switching L3 layer are scheduled using fair round-robin arbitration; The switch nodes at the intermediate switching L2 layer adopt fair polling arbitration and need to feed back the OPstatus to the switch nodes at the input switching L1 layer. The switch node of the input switching L1 layer selects a sending path according to the flow control indication of the switch node of the intermediate switching L2 layer and the OPstatus of the switch node of the intermediate switching L2 layer combined with fair polling arbitration; The arbitration modules between the switching nodes of the input switching L1 layer are cascaded, and the selected switching nodes of the intermediate switching L2 layer are avoided during fair polling; at the same time, the initial value of the fair polling module of the switching node of the input switching L1 layer is set to an incremental mode.

2. The three-stage non-blocking switching network scheduling method according to claim 1, characterized in that: m≥2n-1.

3. The three-stage non-blocking switching network scheduling method according to claim 1, characterized in that: The OPstatus of the switching node of the intermediate switching L2 layer is fed back to the switching node of the input switching L1 layer by adopting a specific encoding method.

4. The three-stage non-blocking switching network scheduling method according to claim 3 is characterized in that: The specific encoding method is one-hot encoding.

5. The three-stage non-blocking switching network scheduling method according to claim 1, characterized in that: The implementation of adding VOQ at the input port of the switching node is selected, and the scheduling method adds arbitration of VOQ. The arbitration is a polling scheduling algorithm or a specific scheduling algorithm based on the order requirement of the transmission protocol.

6. The three-stage non-blocking switching network scheduling method according to claim 1, characterized in that: The switching nodes of the input switching L1 layer, the switching nodes of the intermediate switching L2 layer, and the switching nodes of the output switching L3 layer all include multiple input ports for accessing the switching network, a routing module, a switching network, and multiple switching node output ports. The routing module is responsible for distributing and scheduling input data requests. The switching network is a data path that transmits input requests to the switching node output ports. The flow control information is the flow control information from the switching nodes of the next layer.

Images