Image sensing circuit and comparator thereof

Abstract

The invention discloses a comparator and an image sensing circuit. The comparator comprises an input stage, a gain stage, an output stage and a clamping circuit. The input stage is used for receiving an input signal and a ramp signal and generating a first output signal. The gain stage is coupled to the input stage and is used for receiving the first output signal and generating a second output signal. The output stage is coupled to the gain stage for receiving the second output signal and generating a third output signal. The clamping circuit is coupled to the gain stage and the output stage.

Description

Technical Field

[0001] The invention relates to an image sensing circuit, and in particular to an image sensing circuit with a novel comparator structure. Background Art

[0002] Image sensors are devices that can convert optical images into electrical signals. They are widely used in various electronic products, such as digital cameras, medical imaging products, display devices, and video phones. Currently, image sensors on the market can be divided into charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. With the advancement of integrated circuit process technology, CMOS image sensors are more common in the market than charge coupled device image sensors.

[0003] In recent years, the frame rate and resolution requirements of image sensors have gradually increased, so the corresponding image sensor circuits are required to have more comparators to process a larger number of input image signals. Since these comparators need to receive image signals and perform comparisons at the same time, the transition of the comparators may cause a larger peak current, resulting in unnecessary voltage degradation (IR-drop) on the power supply voltage for these comparators and generating electromagnetic interference (EMI) that cannot be ignored. Summary of the invention

[0004] Therefore, the main purpose of the present invention is to provide an image sensor circuit with a novel comparator structure to solve the above problems.

[0005] An embodiment of the present invention discloses a comparator, which includes an input stage, a gain stage, an output stage and a clamping circuit. The input stage is used to receive an input signal and a ramp signal and generate a first output signal. The gain stage is coupled to the input stage, used to receive the first output signal and generate a second output signal. The output stage is coupled to the gain stage, used to receive the second output signal and generate a third output signal. The clamping circuit is coupled to the gain stage and the output stage.

[0006] Another embodiment of the present invention discloses an image sensor circuit having multiple input channels. The image sensor circuit includes a ramp generator and multiple comparators. The ramp generator is used to generate a ramp signal. Each of the multiple comparators includes an input stage, a gain stage, an output stage and a clamping circuit. The input stage is coupled to the ramp generator and one of the multiple input channels, and is used to receive an input signal from the coupled input channel, and receive the ramp signal from the ramp generator, and generate a first output signal. The gain stage is coupled to the input stage, and is used to receive the first output signal and generate a second output signal. The output stage is coupled to the gain stage, and is used to receive the second output signal and generate a third output signal. The clamping circuit is coupled to the gain stage and the output stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 1 is a schematic diagram of an image sensing circuit according to an embodiment of the present invention.

[0008] Figure 2 The image sensing circuit is shown receiving image signals from an array of sensing pixels of an image sensor.

[0009] Figure 3 is a schematic diagram of a comparator.

[0010] Figure 4 This is the waveform diagram of the comparator signal.

[0011] Figure 5 FIG. 1 is a schematic diagram of a comparator according to an embodiment of the present invention.

[0012] Figure 6 Shows Figure 5 A detailed implementation of the comparator in .

[0013] Figure 7 This is the waveform diagram of the comparator signal.

[0014] Figure 8 FIG. 1 is a schematic diagram of a comparator according to an embodiment of the present invention.

[0015] Fig. 9 FIG. 4 is a schematic diagram of another comparator according to an embodiment of the present invention.

[0016] Fig.10 FIG. 4 is a schematic diagram of another comparator according to an embodiment of the present invention.

[0017] The reference numerals are described as follows:

[0018] 10 Image sensor circuit

[0019] CH_1~CH_n Input channels

[0020] VPIX_1~VPIX_n, VPIX image signal

[0021] 102 Ramp Generator

[0022] CP_1~CP_n、30、50、80、90、100 Comparator

[0023] CT_1~CT_n counters

[0024] CA_1~CA_n、CB_1~CB_n、CA、CB、C2 capacitor

[0026] VRMP ramp signal 200 Image Sensor 202 Line Decoder VOUT_1~VOUT_n、VOUT1、VOUT2、VOUT3、VOUT4 output signal AVDD, DVDD power supply voltage 302, 502 input stage

[0027] 304, 504 gain stages

[0028] 306, 506 output stage 308, 508 Inverter AZ1, AZ2 control signal I_STG2, I_MN2, I_MN4, I_MP3 current SW1_1, SW1_2, SW2 switches 510 Clamp Circuit MN1_1, MN1_2 Input transistors MP1_1, MP1_2 Current mirror MB1 Bias transistor VB1, VB3 bias voltage MP2 High-Side Transistor

[0029] MN2 low-side transistor

[0030] MB3, MN3, MN5, MN6 transistors

[0031] EN1, EN2 Enable switch

[0032] MP3, MN4, MP4 clamp transistors DETAILED DESCRIPTION

[0033] Figure 1Schematic diagram of an image sensor circuit 10 according to an embodiment of the present invention. The image sensor circuit 10 has a plurality of input channels CH_1-CH_n to receive input image signals VPIX_1-VPIX_n through the input channels CH_1-CH_n respectively. For example, the image sensor circuit 10 can be implemented in a readout circuit to be coupled to an image sensor array, and each input channel CH_1-CH_n can receive the input image signals VPIX_1-VPIX_n from a row or a column of sensing pixels in the image sensor.

[0034] In detail, the image sensor circuit 10 includes a ramp generator 102, a plurality of comparators CP_1-CP_n, a plurality of counters CT_1-CT_n, and a plurality of capacitors CA_1-CA_n and CB_1-CB_n. The ramp generator 102 is used to generate a ramp signal VRMP, and provide the ramp signal VRMP to the comparators CP_1-CP_n for comparison. For each comparator CP_1-CP_n, its positive input terminal is respectively coupled to the corresponding input channel CH_1-CH_n through the capacitor CB_1-CB_n, and is used to receive the corresponding image signal VPIX_1-VPIX_n; its negative input terminal is respectively coupled to the ramp generator 102 through the capacitor CA_1-CA_n, and is used to receive the ramp signal VRMP. The comparators CP_1-CP_n are respectively used to compare the image signals VPIX_1-VPIX_n with the ramp signal VRMP to generate a comparison result. The counters CT_1 ˜CT_n are respectively coupled to the output terminals of the corresponding comparators CP_1 ˜CP_n, and are arranged to output counting results reflecting the image signals VPIX_1 ˜VPIX_n according to the comparison results.

[0035] As described above, the image sensing circuit 10 may be coupled to an image sensor array. Figure 2As shown, an image sensor 200 may include a sensing pixel array, and image signals VPIX_1-VPIX_n of the sensing pixel array may be received by comparators CP_1-CP_n in the image sensor circuit 10 respectively through the control of a row decoder 202. The comparators CP_1-CP_n may compare the image signals VPIX_1-VPIX_n with the ramp signal VRMP of the ramp generator 102 to generate a comparison result. In this example, the ramp signal VRMP is a negative ramp signal with a negative slope, and when the voltage of the ramp signal VRMP passes through the corresponding image signal VPIX_1-VPIX_n, the output signals VOUT_1-VOUT_n of the comparators CP_1-CP_n transition from a low level to a high level. Conventionally, during the transition of the output signals VOUT_1-VOUT_n, a rush current is generated in each of the comparators CP_1-CP_n. If most of the image signals VPIX_1 to VPIX_n are at the same level, the output signals VOUT_1 to VOUT_n will transition at approximately the same time point, so that the surge currents of the comparators CP_1 to CP_n will be generated at approximately the same time point. The surge currents that appear at the same time will draw a large amount of current from the power supply end, thereby generating a large voltage decay (IR-drop) on the power supply voltage AVDD. In addition, the surge current also generates electromagnetic interference (EMI) problems.

[0036] Due to the trend of high frame rate and high resolution of image sensors, the image sensing circuit 10 needs to include more channels to receive image signals (i.e., a larger value n), and the image signals must be received at a higher frequency. As a result, the overall peak current drawn from the power supply end becomes larger, resulting in more serious voltage decay and electromagnetic interference problems. Voltage decay may affect other components or modules under the same voltage domain, that is, components / modules that receive the same power supply voltage for operation. In addition, voltage decay and electromagnetic interference may also interfere with the received image signal, thereby generating line noise in the sensing result.

[0037] If the comparator changes state when the ramp signal VRMP crosses the video signal VPIX, a surge current will be generated in the comparator, and its principle is described in detail as follows.

[0038] Figure 33 is a schematic diagram of a comparator 30. The comparator 30 includes an input stage 302, a gain stage 304, an output stage 306, and an inverter 308. The comparator 30 can receive the input image signal VPIX and the ramp signal VRMP to generate output signals VOUT1, VOUT2, and VOUT3 at the output terminals of the input stage 302, the gain stage 304, and the output stage 306, respectively. The inverter 308 is coupled to the output terminal of the output stage 306 to generate an output signal VOUT4.

[0039] Figure 4 is a waveform diagram of signals of the comparator 30, which shows control signals AZ1 and AZ2, the image signal VPIX, the ramp signal VRMP, the output signals VOUT1 and VOUT2, and the current I_STG2 of the gain stage 304. First, the comparator 30 operates in a reset phase, wherein the control signals AZ1 and AZ2 turn on the corresponding switches SW1_1, SW1_2 and SW2 to perform auto-zeroing, and the auto-zeroing operation can reset the charges stored in the capacitors CA and CB.

[0040] After the reset phase is over, the comparator 30 enters the comparison phase and starts to compare the image signal VPIX with the ramp signal VRMP. In the first steady state, since the image signal VPIX is less than the ramp signal VRMP, the output signal VOUT1 is at a high level and the output signal VOUT2 is at a low level. Then, the ramp signal VRMP drops and crosses the image signal VPIX, at which time the output signal VOUT1 switches from a high potential to a low potential, and the output signal VOUT2 switches from a low potential to a high potential. The comparator 30 then enters another steady state, in which the output signal VOUT1 is at a low level and the output signal VOUT2 is at a high level.

[0041] In the first steady state before the transition, the voltage of the output signal VOUT1 is equal to the power supply voltage AVDD, and the voltage of the output signal VOUT2 is equal to the ground voltage 0V, wherein the transistor MN2 is turned off and the current I_STG2 of the gain stage 304 is equal to 0. In the second steady state after the transition, the voltage of the output signal VOUT1 is equal to the ground voltage 0V, and the voltage of the output signal VOUT2 is equal to the power supply voltage AVDD, wherein the transistor MP2 is turned off and the current I_STG2 of the gain stage 304 is equal to 0. Therefore, during the transition of the output signals VOUT1 and VOUT2, the gain stage 304 generates a large inrush current, that is, the current I_STG2 has a large peak value at this time. As described above, this inrush current may appear in each comparator in the image sensor circuit at the same time, thereby drawing a huge peak current from the power supply end to cause voltage decay and electromagnetic interference, especially when the image sensor circuit includes a large number of comparators.

[0042] To solve this problem, the present invention proposes a novel comparator structure, which utilizes a clamping circuit coupled to the gain stage circuit to clamp the voltage of the output signal VOUT2, thereby avoiding surge current during voltage transition.

[0043] Figure 5 Schematic diagram of a comparator 50 according to an embodiment of the present invention. The comparator 50 includes an input stage 502, a gain stage 504, an output stage 506, and a clamping circuit 510. The input stage 502 is used to receive the input image signal VPIX and the ramp signal VRMP to generate an output signal VOUT1. The gain stage 504 is used to receive the output signal VOUT1 to generate an output signal VOUT2. The output stage 506 is used to receive the output signal VOUT2 to generate an output signal VOUT3. The clamping circuit 510 is coupled to the gain stage 504 and the output stage 506, and can be used to clamp the voltage of the output signal VOUT2 to eliminate or reduce the surge current in the gain stage 504.

[0044] Figure 6 A detailed implementation of the comparator 50 is shown, which shows the transistor hierarchy structure of the comparator 50. The comparator 50 can be used to compare the ramp signal VRMP with the image signal VPIX to generate output signals VOUT1-VOUT4 of each stage. Figure 6 The implementation and operation of the input stage 502, the gain stage 504 and the output stage 506 in FIG. 5 are similar to those of Figure 3 302, gain stage 304 and output stage 306 in the embodiment of the present invention, so signals or components with similar functions are represented by the same symbols. The clamping circuit 510 is coupled to the gain stage 504 and the output stage 506, and is used to clamp the output signal VOUT2 generated by the gain stage 504 to an appropriate level to prevent the generation of surge current in the gain stage 504. The comparator 50 can operate by receiving a power supply voltage AVDD.

[0045] Figure 6 An inverter 508 is also shown, which may be included in the comparator 50 or coupled to the output terminal of the comparator 50, for inverting the output signal VOUT3 to generate the final output signal VOUT4. The inverter 508 may be operated by receiving another power supply voltage DVDD.

[0046] like Figure 6As shown, the input stage 502 includes an input pair MN1_1 and MN1_2, a current mirror MP1_1 and MP1_2, a bias transistor MB1, and two switches SW1_1 and SW1_2. The input pair MN1_1 and MN1_2 are used to receive the ramp signal VRMP and the image signal VPIX, respectively. The bias transistor MB1 can receive a bias voltage VB1. The switches SW1_1 and SW1_2 are coupled to the input pair MN1_1 and MN1_2, respectively, and perform auto-zeroing under the control of the control signal AZ1. The input stage 502 can be used as a differential to single-ended converter to convert the image signal VPIX and the ramp signal VRMP to generate the output signal VOUT1.

[0047] besides, Figure 6 Also shown are two capacitors CA and CB coupled to the input terminal of the comparator 50. The capacitors CA and CB may be considered to be included in the comparator 50 or disposed at the front end of the input terminal of the comparator 50. By disposing the capacitors CA and CB, the ramp signal VRMP may be coupled to the gate terminal of the input transistor MN1_1 through the capacitor CA, and the image signal VPIX may be coupled to the gate terminal of the input transistor MN1_2 through the capacitor CB. In one embodiment, the comparator 50 may be Figure 1 Therefore, the capacitor CA may be any one of the capacitors CA_1 to CA_n, and the capacitor CB may be any one of the capacitors CB_1 to CB_n.

[0048] The gain stage 504 includes a high-side transistor MP2, a low-side transistor MN2, a switch SW2 and a capacitor C2. The switch SW2 can be controlled by a control signal AZ2 to perform auto-zeroing to reset the charge stored in the capacitor C2. The high-side transistor MP2 and the low-side transistor MN2 in the gain stage 504 can form an inverter for inverting the output signal VOUT1 to generate the output signal VOUT2.

[0049] The output stage 506 includes a plurality of transistors MB3, MN3, MN5, and MN6. Transistor MB3 can receive a bias voltage VB3. Transistor MN3 can be used as an inverter to invert the output signal VOUT2 to generate an output signal VOUT3. Transistors MN5 and MN6 are diode-connected to provide a voltage to clamp the level of the output signal VOUT3.

[0050] like Figure 6As shown, the clamp circuit 510 includes two enabling switches EN1 and EN2 and two clamp transistors MP3 and MN4. The enabling switches EN1 and EN2 are used to control the enabling of the clamp transistors MP3 and MN4 respectively. The clamp transistors MP3 and MN4 can be used to clamp the voltage of the output signal VOUT2. The clamp transistor MP3 is coupled between the high-side transistor MP2 and the power supply terminal for providing the power supply voltage AVDD. The clamp transistor MN4 is coupled between the gain stage 504 and the output stage 506. The clamp transistors MN4 and MP3 can form a negative feedback loop with the other transistors MN5, MN6 and MP2 in the comparator 50 to avoid the occurrence of surge current.

[0051] Specifically, the clamp transistor MP3 is a PMOS transistor, wherein the drain terminal of the clamp transistor MP3 is coupled to the source terminal of the transistor MP2, the source terminal of the clamp transistor MP3 is coupled to the power supply terminal, and the gate terminal of the clamp transistor MP3 is coupled to the output terminal of the gain stage 504. The clamp transistor MP3 can clamp the output signal VOUT2 to have an upper limit lower than the power supply voltage AVDD.

[0052] The clamp transistor MN4 is an NMOS transistor, wherein the drain terminal of the clamp transistor MN4 is coupled to the power supply terminal, the source terminal of the clamp transistor MN4 is coupled to the output terminal of the gain stage 504, and the gate terminal of the clamp transistor MN4 is coupled to the output stage 506. The clamp transistor MN4 can clamp the output signal VOUT2 to have a lower limit higher than the ground voltage 0V.

[0053] The enabling switch EN1 is coupled between the drain terminal of the clamping transistor MP3 and the power supply terminal to control the enabling of the clamping transistor MP3. In this example, the clamping transistor MP3 is enabled only when the enabling switch EN1 is turned off. In another embodiment, the enabling switch EN1 can also be omitted so that the clamping function of the clamping transistor MP3 is always turned on.

[0054] The enabling switch EN2 is coupled between the clamping transistor MN4 and the power supply terminal to control the enabling of the clamping transistor MN4. In this example, the clamping transistor MN4 is enabled only when the enabling switch EN2 is turned on. In another embodiment, the enabling switch EN2 may be omitted so that the clamping function of the clamping transistor MN4 is always turned on.

[0055] Figure 7FIG. 5 is a waveform diagram of signals of the comparator 50, which shows the control signals AZ1 and AZ2, the image signal VPIX, the ramp signal VRMP, the output signals VOUT1, VOUT2 and VOUT3, and the current I_MN2 flowing through the transistor MN2. The partial signal waveforms of the comparator 30 are shown in dashed lines. Figure 7 For comparison. Figure 4 The operation of the comparator 30 in FIG. 5 also includes a reset phase and a comparison phase. In the reset phase, the control signals AZ1 and AZ2 turn on the corresponding switches to perform automatic zeroing. In the comparison phase, the image signal VPIX is compared with the ramp signal VRMP to generate a voltage transition, thereby obtaining a comparison result.

[0056] In the reset phase, switches SW1_1 and SW1_2 are turned on by control signal AZ1 and switch SW2 is turned on by control signal AZ2 to generate auto-zero current in input stage 502 and gain stage 504. The auto-zero current in gain stage 504 can generate a voltage across capacitor C2, and its associated charge can be stored in capacitor C2. Since capacitor C2 is coupled between the gate terminal and the source terminal of transistor MN2, the voltage across capacitor C2 is equal to the gate-to-source voltage Vgs of transistor MN2. MN2 .

[0057] Next, the comparator 50 enters the comparison phase. In the first steady state before the voltage transition, the output signal VOUT1 is high and the output signal VOUT2 is low. Although the high-side transistor MP2 is turned off by the output signal VOUT1, the clamp transistor MN4 can still provide a current to flow to the low-side transistor MN2, so that the low-side transistor MN2 remains turned on and operates in the saturation region. Due to the capacitor C2, the gate-to-source voltage Vgs of the transistor MN2 is MN2 Maintain constant, the current I_MN2 through the transistor MN2 can be maintained at a level approximately equal to the auto-zero current in the reset phase, and this current I_MN2 can be provided by the clamp transistor MN4 (i.e., I_MN4). In this case, the output signal VOUT2 does not drop to the ground voltage, but the voltage of the output signal VOUT2 is clamped to a low level, which is equal to VOUT3-Vgs MN4 , that is, the output signal VOUT3 minus the gate-to-source voltage of the clamp transistor MN4.

[0058] It is worth noting that the low level of the output signal VOUT2 is VOUT3-Vgs MN4 It can be determined by controlling the voltage level of the output signal VOUT3. Figure 6As shown, there are two diode-type transistors MN5 and MN6 in the output stage 506, which are coupled between the output terminal of the output stage 506 and the ground terminal to provide twice the gate-to-source voltage (ie, Vgs MN5 +Vgs MN6 ) to output signal VOUT3. It should be noted that the configuration of transistors MN5 and MN6 is only one of many embodiments of the present invention. In another embodiment, transistors MN5 and MN6 may be replaced by P-type metal oxide semiconductor transistors, or may be replaced by one or more diodes and / or resistors. The number of diodes or diode-type transistors or the resistance value of resistors may be set in a suitable manner according to the voltage requirement of output signal VOUT3.

[0059] In the second steady state after the voltage transition, the output signal VOUT1 is low and the output signal VOUT2 is high. At this time, the high-side transistor MP2 can operate in the linear region and act as a switch to provide a current (i.e., I_MP3) to flow to the transistor MN2 as the current I_MN2. Similarly, due to the capacitor C2, the gate-to-source voltage Vgs of the transistor MN2 is MN2 Maintaining constant, the current I_MN2 can be maintained at a level approximately equal to the auto-zero current in the reset phase and the current in the first steady state. In this case, the output signal VOUT2 does not reach the power supply voltage AVDD due to the clamping transistor MP3, but the voltage of the output signal VOUT2 is clamped to a high level, which is equal to AVDD-Vgs MP3 , that is, the power supply voltage AVDD minus the gate-to-source voltage of the clamp transistor MP3.

[0060] Unlike the comparator 30 in which the output signal VOUT2 reaches the power supply voltage AVDD and the high-side transistor MP2 is turned off so that the current of the gain stage 304 reaches 0, the comparator 50 still has a current in the second stable state, and its current value is approximately equal to the automatic zero current in the gain stage 504. In addition, unlike the comparator 30 in which the output signal VOUT2 reaches the ground voltage and the low-side transistor MN2 is turned off so that the current of the gain stage 304 reaches 0, the comparator 50 still has a current in the first stable state, and its current value is approximately equal to the automatic zero current in the gain stage 504. Therefore, no matter whether the output signal VOUT2 is at a high level or a low level, the transistor MN2 is continuously turned on and operates in the saturation region to keep the current unchanged, so that no surge current occurs in the gain stage 504. In this way, the voltage decay and electromagnetic interference problems in the prior art are solved.

[0061] It is worth noting that the purpose of the present invention is to propose a new comparator structure that can be used in image sensor circuits. Those skilled in the art can make modifications or changes based on this, but are not limited to this. For example, Figure 6 The structures of the input stage 502, the gain stage 504 and the output stage 506 are only examples, and they can be modified appropriately according to system requirements. Figure 6 In the embodiment of the present invention, the clamping circuit 510 uses a clamping transistor MP3 to clamp the upper limit of the output signal VOUT2 of the gain stage 504, and uses another clamping transistor MN4 to clamp the lower limit of the output signal VOUT2 of the gain stage 504. In another embodiment, the clamping circuit may also include only a single clamping transistor to clamp one of the upper limit and the lower limit of the output signal. If the output signal is clamped on one side, the inrush current can also be reduced.

[0062] In addition, the comparator structure of the present invention can be implemented in any image sensor circuit, which can be used to process image signals of various types of image sensors. These image sensors can be complementary metal oxide semiconductor (CMOS) image sensors, but are not limited thereto.

[0063] Figure 8 FIG. 8 is a schematic diagram of a comparator 80 according to an embodiment of the present invention. The structure of the comparator 80 is similar to Figure 6 The comparator 50 in FIG. 8 is similar to the comparator 50 in FIG. 8 , so signals or components with similar functions are represented by the same symbols. The difference between the comparator 80 and the comparator 50 is that in the comparator 80, the N-type metal oxide semiconductor transistor MN4 in the clamping circuit 510 is replaced by a P-type metal oxide semiconductor transistor MP4. In other words, in the comparator 80, the clamping transistor used to clamp the lower limit of the output signal VOUT2 is a P-type metal oxide semiconductor transistor. Figure 8 As shown, the source terminal of the clamp transistor MP4 is coupled to the power supply terminal, the drain terminal of the clamp transistor MP4 is coupled to the output terminal of the gain stage 504 , and the gate terminal of the clamp transistor MP4 is coupled to the output stage 506 .

[0064] If a P-type metal oxide semiconductor clamping transistor MP4 is used, the clamping circuit 510 can generate a positive feedback loop to accelerate the voltage transition when the ramp signal VRMP passes through the image signal VPIX. In this case, the transition time of different comparators in the image sensor circuit may be more divergent, so that the inrush current of different comparators also becomes divergent, thereby reducing the overall ripple and voltage decay on the power supply voltage AVDD.

[0065] Fig. 9 FIG. 1 is a schematic diagram of another comparator 90 according to an embodiment of the present invention. The structure of the comparator 90 is similar to Figure 6 The comparator 50 in FIG. 1 is similar to the comparator 50 in FIG. 1 , so signals or components with similar functions are represented by the same symbols. The difference between the comparator 90 and the comparator 50 is that the clamping circuit 510 in the comparator 90 only includes the enabling switch EN2 and the clamping transistor MN4, while the enabling switch EN1 and the clamping transistor MP3 are omitted. Through such an implementation, the output signal VOUT2 is clamped to a lower limit which is higher than the ground voltage 0V, and the low-side transistor MN2 is not turned off before the voltage transition to reduce the inrush current generated during the voltage transition.

[0066] It is worth noting that the structure of the comparator 90 can be further replaced by using a P-type metal oxide semiconductor clamp transistor MP4 to replace the N-type metal oxide semiconductor clamp transistor MN4, or removing the enabling switch EN2, and the related implementations should all fall within the scope of the present invention.

[0067] Fig.10 FIG. 1 is a schematic diagram of another comparator 100 according to an embodiment of the present invention. The structure of the comparator 100 is similar to Figure 6 The comparator 50 in FIG. 1 is similar to the comparator 50 in FIG. 1 , so signals or components with similar functions are represented by the same symbols. The difference between the comparator 100 and the comparator 50 is that the clamping circuit 510 in the comparator 100 only includes the enabling switch EN1 and the clamping transistor MP3, while the enabling switch EN2 and the clamping transistor MN4 are omitted. Through such an implementation, the output signal VOUT2 is clamped to an upper limit that is lower than the power supply voltage AVDD, and the high-side transistor MP2 is not turned off after the voltage transition to reduce the inrush current generated during the voltage transition.

[0068] It is worth noting that the structure of the comparator 100 can be further replaced by removing the enabling switch EN1 , and the related implementations should all fall within the scope of the present invention.

[0069] In summary, the present invention proposes a new comparator structure for an image sensor circuit. The comparator has a clamping circuit, which may include a first clamping transistor for clamping the output signal of the gain stage so that it has an upper limit lower than the power supply voltage; and / or include a second clamping transistor for clamping the output signal of the gain stage so that it has a lower limit higher than the ground voltage. Therefore, the low-side transistor of the gain stage can be continuously turned on and operated in the saturation region during the voltage transition and steady state to maintain the current of the gain stage constant. In this case, no surge current will appear during the voltage transition of the ramp signal passing through the input image signal, thereby solving the voltage decay and electromagnetic interference problems of the image sensor circuit. The clamping circuit of the present invention only needs to add one or two additional transistors in each comparator, and its structure is quite simple and easy to implement.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A comparator, characterized in that: include: An input stage, used for receiving an input signal and a ramp signal, and generating a first output signal; a gain stage, coupled to the input stage, for receiving the first output signal and generating a second output signal; an output stage, coupled to the gain stage, for receiving the second output signal and generating a third output signal; as well as A clamping circuit is coupled to the gain stage and the output stage.

2. The comparator according to claim 1, wherein: The gain stage includes a high-side transistor and a low-side transistor, and the clamp circuit includes: A first clamping transistor is coupled between the high-side transistor and a power supply terminal of the comparator.

3. The comparator according to claim 2, wherein: A drain terminal of the first clamping transistor is coupled to the high-side transistor, a source terminal of the first clamping transistor is coupled to the power supply terminal, and a gate terminal of the first clamping transistor is coupled to an output terminal of the gain stage.

4. The comparator according to claim 2, wherein: The first clamping transistor is a P-type metal oxide semiconductor transistor.

5. The comparator according to claim 2, wherein: The clamping circuit further includes a first enabling switch coupled between the first clamping transistor and the power supply terminal.

6. The comparator according to claim 2, wherein: The first clamping transistor clamps the second output signal to have an upper limit lower than a power supply voltage of the comparator.

7. The comparator according to claim 1, wherein: The clamping circuit includes: A second clamping transistor is coupled between the gain stage and the output stage.

8. The comparator according to claim 7, wherein: A first terminal of the second clamping transistor is coupled to an output terminal of the gain stage, a second terminal of the second clamping transistor is coupled to a power supply terminal of the comparator, and a gate terminal of the second clamping transistor is coupled to the output stage.

9. The comparator according to claim 7, wherein: The second clamping transistor is a P-type metal oxide semiconductor transistor.

10. The comparator according to claim 7, wherein: The second clamping transistor is an N-type metal oxide semiconductor transistor.

11. The comparator according to claim 7, wherein: The clamping circuit further includes a second enabling switch coupled between the second clamping transistor and a power supply terminal of the comparator.

12. The comparator according to claim 7, wherein: The second clamping transistor clamps the second output signal to have a lower limit higher than a ground voltage.

13. The comparator according to claim 1, wherein: The gain stage includes a high-side transistor and a low-side transistor, and the low-side transistor remains turned on when the second output signal is at a high level and the second output signal is at a low level.

14. An image sensing circuit having a plurality of input channels, characterized in that: The image sensing circuit comprises: a ramp generator, used to generate a ramp signal; and A plurality of comparators, each of which comprises: an input stage coupled to the ramp generator and one of the input channels of the plurality of input channels, for receiving an input signal from the coupled input channel and the ramp signal from the ramp generator, and generating a first output signal; a gain stage, coupled to the input stage, for receiving the first output signal and generating a second output signal; an output stage, coupled to the gain stage, for receiving the second output signal and generating a third output signal; and A clamping circuit is coupled to the gain stage and the output stage.

15. The image sensing circuit according to claim 14, wherein: The gain stage includes a high-side transistor and a low-side transistor, and the clamp circuit includes: A first clamping transistor is coupled between the high-side transistor and a power supply terminal of the comparator.

16. The image sensing circuit according to claim 15, characterized in that: A drain terminal of the first clamping transistor is coupled to the high-side transistor, a source terminal of the first clamping transistor is coupled to the power supply terminal, and a gate terminal of the first clamping transistor is coupled to an output terminal of the gain stage.

17. The image sensing circuit according to claim 15, wherein: The first clamping transistor is a P-type metal oxide semiconductor transistor.

18. The image sensing circuit according to claim 15, wherein: The clamping circuit further includes a first enabling switch coupled between the first clamping transistor and the power supply terminal.

19. The image sensing circuit according to claim 15, wherein: The first clamping transistor clamps the second output signal to have an upper limit lower than a power supply voltage of the comparator.

20. The image sensing circuit according to claim 14, wherein: The clamping circuit includes: A second clamping transistor is coupled between the gain stage and the output stage.

21. The image sensing circuit according to claim 20, wherein: A first terminal of the second clamping transistor is coupled to an output terminal of the gain stage, a second terminal of the second clamping transistor is coupled to a power supply terminal of the comparator, and a gate terminal of the second clamping transistor is coupled to the output stage.

22. The image sensing circuit according to claim 20, wherein: The second clamping transistor is a P-type metal oxide semiconductor transistor.

23. The image sensing circuit according to claim 20, wherein: The second clamping transistor is an N-type metal oxide semiconductor transistor.

24. The image sensing circuit according to claim 20, wherein: The clamping circuit further includes a second enabling switch coupled between the second clamping transistor and a power supply terminal of the comparator.

25. The image sensing circuit according to claim 20, wherein: The second clamping transistor clamps the second output signal to have a lower limit higher than a ground voltage.

26. The image sensing circuit according to claim 14, wherein: The gain stage includes a high-side transistor and a low-side transistor, and the low-side transistor remains turned on when the second output signal is at a high level and the second output signal is at a low level.

27. The image sensing circuit according to claim 14, wherein: Also includes: A plurality of counters, each of which is coupled to an output terminal of one of the plurality of comparators.

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