Light intensity self-adaptive high-speed wide dynamic pulse pixel structure, image sensor and electronic equipment

Abstract

The invention discloses a light intensity self-adaptive high-speed wide dynamic pulse pixel structure, an image sensor and electronic equipment. The high-speed wide dynamic pulse pixel structure comprises a photodiode, a plurality of MOS switch transistors, a capacitance trans-impedance amplifier, a CTIA capacitor, a comparator, a plurality of phase inverters, a pulse signal latch and a 3bit counter. The pixel structure provided by the invention can adaptively select the light sensing node gain according to the light intensity, improves the low light intensity sensitivity, expands the dynamic range, can realize the response to a high-speed scene, and solves the problems that a CMOS image sensor needs to read out a plurality of signals due to high dynamic range requirement, capacitance overflow or double gain structures and the like, and the sensitivity is poor. And the reading time is long.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel structure, and in particular to a high-speed wide dynamic pulse pixel structure with adaptive light intensity, an image sensor and electronic equipment. Background Art

[0002] In the field of complementary metal oxide semiconductor (CMOS) image sensors, dynamic range (DR) is a key parameter in applications such as monitoring, security, and drones, which directly affects the quality of image sensors' perception of scenes. Usually, in the process of image sensor design, it is necessary to maximize the dynamic range as much as possible to expand its scope of application.

[0003] Classic active pixel image sensors have limited dynamic range. At a fixed exposure time, the lowest light intensity that can be perceived is limited by quantization and readout noise; and the maximum perceptible light intensity is usually limited by the full well capacity. By increasing the exposure time, lower light intensities can be perceived, but the maximum measurable light intensity will decrease. If the exposure time is reduced, it can respond at higher illumination, but the accuracy will be lost in the lower illumination area. Therefore, the dynamic range of the sensor is limited by the design of the pixel itself and cannot be expanded by globally adjusting the integration time. Usually, the dynamic range of active pixel image sensors is usually below 70dB. For human vision, the dynamic range of perceptible scenes is around 120dB. In comparison, the dynamic range of classic active pixel image sensors cannot meet people's daily needs.

[0004] The quantization of scenes by traditional image sensors is limited by exposure time and the size of capacitor nodes, resulting in a limited dynamic range. To address the limitation of capacitor node size, a pixel structure with a Lateral Overflow Integration Capacitor (LOFIC) or a dual-gain capacitor node (DCG) is usually used in pixel design to expand the response to high light intensity by expanding the charge storage capacity of the capacitor node. However, the working process requires quantized readout of multiple signals, which takes a long time to read out and cannot be used in high-speed scenes. In addition, to address the limitation of exposure time, the dynamic range is usually expanded by capturing multiple exposure images and fusing the image data of different frames. However, this method has high requirements in terms of computing load, hardware, and power consumption.

[0005] In pulse modulation image sensors, quantization is no longer performed in the form of charge, voltage or current encoding. Instead, image data is represented by pulse timing or pulse edge. This method of visual information encoding avoids the limitation of fixed exposure time on pixel sensitivity and achieves improvement in dynamic range and signal-to-noise ratio. In addition, pulse modulation image sensors perform analog-to-digital conversion within pixels, thereby achieving high temporal resolution. The high speed and high dynamic range characteristics of pulse modulation imaging make it have broad application prospects in high-performance machine vision.

[0006] However, due to its unique reset and encoding method, the pulse modulation (PM) image sensor has a large number of transistors in the pixel unit. In order to ensure the pixel fill factor, the pixel photosensitive node capacitance is usually 10 to 100fF, and the photosensitive conversion gain is low. Therefore, the low-light sensitivity of this structure is poor, which limits its application in dark and high-speed scenes.

[0007] In summary, existing technologies usually improve the dynamic range by expanding the charge storage capacity of photosensitive nodes (DGC or LOFIC structure) or multi-frame sampling. However, large dynamic range structures such as DCG require a long readout time, and the use of multi-frame exposure image fusion also prolongs the response time. Both methods cannot be used for high-speed scene problems. Summary of the invention

[0008] The purpose of the present invention is to provide a high-speed wide dynamic pulse pixel structure and image sensor and electronic device with adaptive light intensity, aiming to solve the problem that CMOS image sensors have high dynamic range requirements, use capacitor overflow or dual gain structures, need to read out multiple signals, and have a long readout time; the use of multi-frame exposure image fusion also prolongs the response time, and both methods cannot be used in high-speed scenes. The proposed pixel structure can adaptively select the photosensitive node gain according to the light intensity, improve the low light intensity sensitivity, expand the dynamic range, and can respond to high-speed scenes at the same time.

[0009] The first aspect of the present invention provides a high-speed wide dynamic pulse pixel structure with adaptive light intensity, comprising a photodiode, a plurality of MOS switch transistors, a capacitive transimpedance amplifier, a CTIA capacitor, a comparator, a plurality of inverters, a pulse signal latch, and a 3-bit counter;

[0010] Among them, one end of the first MOS switch transistor is connected to the non-grounded end of the photodiode and the other end is connected to the negative phase input end of the capacitor transimpedance amplifier; one end of the parallel circuit structure of the second MOS switch transistor, the third MOS switch transistor and the CTIA capacitor is connected to the non-grounded end of the photodiode and the other end is connected to the output end of the capacitor transimpedance amplifier; the positive input end of the capacitor transimpedance amplifier is connected to the reset voltage signal Vrst, and the output end is connected to the negative input end of the comparator;

[0011] One end of the fourth MOS switch transistor, the fifth MOS switch transistor, the sixth MOS switch transistor and the seventh MOS switch transistor are commonly connected to the positive input end of the comparator, and the other ends are respectively connected to the pre-judgment working threshold voltage Vth0, the reset voltage signal Vrst, the first working threshold voltage Vth1 of the pixel working under low light intensity conditions, and the second working threshold voltage Vth2 of the pixel working under high light intensity conditions; the output end of the comparator is connected to one end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor and one end of the tenth MOS switch transistor, and the other end of the tenth MOS switch transistor is connected to the first inverter input The other end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor is connected to the output end of the first inverter and the input end of the second inverter. The output of the second inverter is connected to the pulse signal latch input end and the 3-bit counter input end. The output end of the 3-bit counter is connected to the input end of the third inverter and is input with the global clock signal clk; the input end of the pulse signal latch clk is connected to the latch signal latch, the output end of the pulse signal latch Q is connected to the input end of the fourth inverter, and outputs the latch output signal Latchout; the third inverter and the fourth inverter are respectively input with the row selection signal Sel, and the output ends are connected to the column bus.

[0012] Among them, it includes a working mode switching logic control unit, which is used to control the output of multiple working mode switching control signals to correspondingly control the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor to switch the working mode.

[0013] Among them, the S0 signal input end of the working mode switching logic control unit is connected to the pre-judgment logic unit output signal S0 and the latch input signal Latchin, and controls the output of multiple working mode switching control signals according to the pre-judgment logic unit output signal S0 and the latch input signal Latchin.

[0014] Among them, it includes a reset logic control unit, which is used to control the output reset control signal, and correspondingly controls the reset of the third MOS switch transistor, the eighth MOS crystal switch tube and the fifth MOS switch transistor; the input end of the reset logic control unit is connected to the output end of the pulse signal latch, and is also connected to the reset signal Rst.

[0015] Among them, it includes a pre-judgment logic unit, which is used to adaptively switch the photosensitive node gain according to the light intensity. The input end of the pre-judgment logic unit is connected to the pre-judgment signal SN1 and the output signal Latchout of the pulse signal latch, and the output end of the pre-judgment logic unit is connected to the S0 signal input end of the working mode switching logic control unit.

[0016] Among them, in the working mode switching logic unit, the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor are controlled together through the input S0 signal and the Latchin signal to realize the working state control of the CTIA capacitor and the first inverter.

[0017] Among them, when quantizing high light intensity, the second MOS switch transistor and the ninth MOS switch transistor are closed, the capacitive transimpedance amplifier does not work, the CTIA capacitor does not work, the first inverter does not work, and the photodiode in the pixel is connected to the negative input terminal of the comparator; during the exposure process, the voltage of the photodiode node gradually decreases, and is compared with the second working threshold voltage Vth2 of the comparator in real time. When the threshold voltage is reached, the Vpulse node is triggered to flip, and the flip signal is connected to the pulse signal latch in the pixel by the second inverter; when the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row selection signal Sel arrives, and a reset is triggered when the reset signal Rst arrives; after Vpulse flips, the flipping moment is recorded by a 3-bit counter, and the recorded 3-bit data is output outside the chip at the end of the flip frame, and combined with the 1-bit pulse data to quantize the light intensity together.

[0018] Among them, when quantizing low light intensity, the second MOS switch transistor and the ninth MOS switch transistor are turned off, the CTIA capacitor works, the first inverter works, the photodiode is connected to the negative input terminal of the CTIA capacitor, and the photogenerated charge during exposure is amplified by the CTIA capacitor gain, and the amplified result is compared with the first working threshold voltage Vth1 in the comparator. When the threshold voltage is reached, the Vpulse node is triggered to flip, and the flip signal is connected to the pulse signal latch in the pixel by the first inverter and the second inverter. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the selection signal Sel arrives; in this working mode, the 3-bit counter records the Vpulse flipping moment, and outputs the recorded 3-bit data outside the chip at the end of the flipping frame, and is combined with the 1-bit pulse data to quantize the light intensity together.

[0019] Among them, the pre-judgment logic unit enters the pre-judgment processing process after the pixel outputs a 1-bit high-level pulse. In the pre-judgment processing, the photodiode end is connected to the negative input end of the comparator, and is compared with the set pre-judgment working threshold voltage Vth0 in the comparator. According to the comparison result, the logic gate is controlled to select the pixel working mode of the next frame, and then enters the reset stage.

[0020] A second aspect of the present invention provides an image sensor including the adaptive light intensity high-speed wide dynamic pulse pixel structure.

[0021] According to a third aspect of the present invention, an electronic device is provided, comprising the above-mentioned image sensor.

[0022] The pulse pixel structure of the present invention for adaptively adjusting the gain of the photosensitive node introduces a CTIA capacitor at the photosensitive node on the basis of the traditional pulse structure pixel, and introduces a pre-judgment module at the same time, so that the pixel can control the operation of the CTIA capacitor during the pre-judgment timing. Under high light intensity, the pixel pre-judgment stage controls the CTIA capacitor not to work, and the integral signal of the photodiode (PD) node directly enters the subsequent analog-to-digital conversion and readout; under low light intensity, the pixel pre-judgment stage controls the CTIA capacitor to work, and the integral signal of the photodiode (PD) node is amplified by the CTIA capacitor gain, and then enters the subsequent analog-to-digital conversion and readout. The gain selection of the pre-judgment is used to realize the gain amplification of the pixel under low light conditions and the adaptive selection of the pixel gain for different light intensities, thereby improving the dynamic range of the pixel under low light intensity.

[0023] In addition, a 3-bit counter is introduced into the pixel structure to record and read out the comparator flipping moment, which improves the quantization accuracy and quantization capability of high light intensity and expands the dynamic range of high light intensity.

[0024] In summary, the pixel structure proposed in the present invention can adaptively select the gain of the photosensitive node according to the light intensity, thereby improving the low-light sensitivity and expanding the dynamic range. At the same time, it can respond to high-speed scenes, solving the problem that CMOS image sensors have high dynamic range requirements, use capacitor overflow or dual gain structures, need to read out multiple signals, and have a long readout time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of a high-sensitivity wide dynamic pulse pixel with adaptive light intensity according to an embodiment of the present invention.

[0026] Figure 2 It is a timing diagram of pixel operation under high light intensity according to an embodiment of the present invention.

[0027] Figure 3 It is a timing diagram of pixel operation under low light intensity according to an embodiment of the present invention.

[0028] Figure 4 4 is a pixel operation timing diagram of adaptive gain switching according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0030] The pixel structure of the embodiment of the present invention, based on the traditional pulse modulation pixel structure, adds a gain conversion structure of the photosensitive node to improve the low light intensity perception sensitivity of the pixel, and at the same time adds a pixel photosensitive pre-judgment structure, so that the pixel can adaptively adjust the conversion gain according to the light intensity, while ensuring high-speed response and improving the pixel dynamic range. In addition, the pixel structure combines the quantization method of pulse width modulation and pulse frequency modulation, introduces a global clock and counter, records the comparator flipping moment of the analog-to-digital conversion module in the pixel, and expands the dynamic range under high light intensity.

[0031] See also Figure 1As shown, in the embodiment of the present application, the high-speed wide dynamic pulse pixel structure with adaptive light intensity includes a photodiode (PD) 1, multiple MOS switch transistors, a capacitor transimpedance amplifier (CTIA) 6, a CTIA capacitor (CS) 5, a comparator (COMP) 7, multiple inverters, a pulse signal latch 20, and a 3-bit counter 28; the MOS switch transistors include a first MOS switch transistor 2, a second MOS switch transistor 4, a third MOS switch transistor 3, a fourth MOS switch transistor 8, a fifth MOS switch transistor 9, a sixth MOS switch transistor 10, a seventh MOS switch transistor 11, an eighth MOS switch transistor 12, a ninth MOS switch transistor 13, and a tenth MOS switch transistor 14.

[0032] The first MOS switch transistor (SW3_1) 2 is controlled by the output signal SW3_1 of the control unit of the working mode switching logic control unit 16, the third MOS switch transistor (SW1_2) 3 is controlled by the output signal S1_2 of the reset logic control unit 16, the second MOS switch transistor (SW1_1) 4 is controlled by the output signal S1_1 of the working mode switching logic control unit 16, the fourth MOS switch transistor (SW0) 8 is controlled by the output signal S0 of the pre-judgment logic unit 22; the fifth MOS switch transistor (SW2) 9 is controlled by the output signal S2 of the reset logic control unit 23; the sixth MOS switch transistor (SW5) 10 is controlled by the working mode switching logic control unit 1 6 output signal S5; the seventh MOS switch transistor (SW4) 11 is controlled by the output signal S4 of the working mode switching logic control unit 16; the tenth MOS switch transistor (SW3_1) 14 is controlled by the output signal S3_1 of the working mode switching logic control unit; the eighth MOS switch transistor (SW1_2) 12 is controlled by the output signal S1_2 of the reset logic control unit 23, and the ninth MOS switch transistor (SW1_1) 13 is controlled by the output signal S1_1 of the working mode switching logic control unit 16; the input end of the working mode switching logic control unit 16 is connected to the output end of the first inverter (inv1) 15, and is also connected to the output signal S0 of the pre-judgment logic unit.

[0033] Among them, the input end of the second inverter (inv2) 17 is connected to the output end of the first inverter (inv1) 15, the output end of the second inverter (inv2) 17 is connected to the D input end of the pulse signal latch 20, the input end of the 3-bit counter 18 is connected to the output end of the second inverter (inv1) 17, and is also connected to the global clock signal clk, and the output end of the 3-bit counter 18 is connected to the input end of the third inverter 19; the third inverter 19 is connected to the row selection signal Sel, the output end is connected to the column bus, and outputs the num signal; the Q output end of the pulse signal latch 20 is connected to the latch output signal Latchout, the clk end is connected to the latch signal latch, and the Q output end is connected to the input end of the fourth inverter 21, there is a Vpulse node between the first inverter 12 and the tenth switch transistor 13, there is a Vspike node between the second inverter 17 and the pulse signal latch 20, the fourth inverter 21 is connected to the row selection signal Sel, the output end is connected to the column bus, and outputs the Spike signal.

[0034] In the present invention, the pre-judgment signal SN1 is the same as the Sel, latch, clk, and Rst signals, which are all periodic timing signals provided externally. In the present invention, when the light intensity is quantized to high, the second and ninth MOS switch transistors (corresponding to Figure 1 The two marked SW1_1 switches in the figure are closed, the CTIA capacitor (CS) does not work, the first inverter (inv1) does not work, the photosensitive node in the pixel - the photodiode (PD) is connected to the negative input terminal of the comparator (COMP). During the exposure process, the voltage of the photodiode (PD) node gradually decreases and is compared with the positive threshold Vth2 of the comparator (COMP) in real time. When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch in the pixel by the second inverter (inv2) as the input signal Latchin of the pulse signal latch. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row selection signal Sel arrives, and reset is triggered when the reset signal Rst arrives.

[0035] In addition, after the node Vpulse flips, the flipping moment is recorded by a 3-bit counter, and at the end of the flipping frame, the recorded 3-bit data is output outside the chip and combined with the 1-bit pulse data to quantize the light intensity, thereby improving the dynamic range of the pulse pixel and the quantization accuracy under medium and high light intensities.

[0036] like Figure 2 Shown is the pixel operation timing for quantizing high light intensity.

[0037] After the trigger pulse of the previous frame, the Latchout signal is latched to a low level. When the subsequent periodic signal SN1 arrives, the current frame pre-judgment is entered. The pre-judgment logic unit outputs a signal S0 to control the working mode switching logic control unit to select the working mode. Due to the quantized high light intensity, the working mode switching logic control unit controls the second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are closed, and the first and tenth switch transistors (corresponding to Figure 1 The two SW3_1 switches marked in the figure are turned off, the CTIA capacitor does not work, the first inverter (inv1) does not work, and the photosensitive node in the pixel - the photodiode (PD) is connected to the negative input terminal of the comparator (COMP); the seventh MOS switch transistor (SW4) is closed, and the positive terminal of the comparator (COMP) is connected to the working threshold voltage Vth2 when the CTIA capacitor does not work.

[0038] After the pre-judgment phase, the reset phase begins. The reset logic control unit outputs the third and eighth MOS switch transistors (corresponding to Figure 1 The two SW1_2 switches marked in the figure are closed, and the photodiode (PD) is connected to the negative input terminal of the CTIA capacitor; the fifth MOS switch transistor (SW2) is closed, and the negative terminal of the comparator (COMP) is connected to the reset threshold voltage Vrst in the reset phase.

[0039] When the reset is completed, the third and eighth MOS switch transistors (corresponding to Figure 1 The two SW1_2 switches marked in the figure) and the reset threshold voltage Vrst restore the circuit working state after the pre-judgment is completed, and then start exposure.

[0040] During exposure, the voltage of the photodiode (PD) node gradually decreases and is compared with the negative working threshold voltage Vth2 of the comparator (COMP) in real time. If the voltage of the photodiode (PD) does not reach Vth2 in the current frame, the comparator (COMP) output signal Vpulse (periodic pulse signal) does not flip, so the subsequent pre-judgment logic unit, working mode switching logic control unit and reset logic control unit will not be triggered.

[0041] When the latch signal latch arrives, the Vspike signal latched by the intra-pixel pulse signal latch 20 is a high-level signal. When the row selection signal Sel arrives, the high-level signal latched by the latch outputs a low-level 0 to the column bus via the inverter.

[0042] Since the pulse is not triggered, there is no level flip signal in the current frame, so the 3-bit counter does not record the flip position. When the row selection signal Sel arrives, the 3-bit counter outputs a code value of 000 to the column bus. If the photodiode (PD) voltage reaches Vth2 in the current frame, the comparator (COMP) output signal Vpulse flips, and when the latch signal latch arrives, the pulse signal latch in the pixel latches the Vspike signal as a low level. When the row selection signal Sel arrives, the latched low level signal is latched through the inverter and the high level 1 is output to the column bus. At the same time, the 3-bit counter records the Vpulse flip moment, and when the row selection signal Sel arrives, the 3-bit counter outputs a 3-bit code value to the column bus. After the row selection signal Sel ends, the low level signal latched by the pulse signal latch triggers the pre-judgment, mode switching and reset of the next frame.

[0043] When the light intensity is low, the second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are turned off, the CTIA capacitor works, the first inverter (inv1) works, the photodiode (PD) is connected to the negative input terminal of the CTIA capacitor, the photogenerated charge during exposure is amplified by the CTIA capacitor gain, and the amplified result is compared with the set threshold value Vth1 in the comparator (COMP). When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch in the pixel by the first inverter (inv1) and the first inverter (inv2). When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row selection signal Sel arrives. In this working mode, the 3-bit counter can also record the Vpulse flip moment, and output the recorded 3-bit data to the chip at the end of the flip frame, and combine it with the 1-bit pulse data to quantify the light intensity.

[0044] like Figure 3 Shown is the pixel operation timing for quantizing low light intensity.

[0045] After the trigger pulse of the previous frame, the Latchout signal is latched as a low level. When the subsequent periodic signal SN1 arrives, the current frame pre-judgment is entered. The pre-judgment logic unit outputs the signal S0 to control the working mode switching logic control unit to select the working mode. Due to the quantized low light intensity, the working mode switching logic control unit controls the second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are turned off, and the first and tenth switch transistors (corresponding to Figure 1The two switches SW3_1 marked in the figure are closed, the CTIA capacitor is connected to the photodiode (PD) in a negative feedback manner, and the first inverter (inv1) and the first inverter (inv2) work together; the sixth MOS switch transistor (SW5) 10 is closed, and the negative end of the comparator (COMP) is connected to the threshold value Vth1 when the CTIA capacitor works.

[0046] After the pre-judgment phase, the reset phase begins. The reset logic control unit outputs the third and eighth MOS switch transistors (corresponding to Figure 1 The two SW1_2 switches marked in the figure are closed, and the photodiode (PD) is connected to the negative input terminal of the CTIA capacitor; the fifth MOS switch transistor (SW2) 9 is closed, and the negative terminal of the comparator (COMP) is connected to the threshold Vrst of the reset phase.

[0047] When the reset is completed, the third and eighth MOS switch transistors (corresponding to Figure 1 The two SW1_2 switches marked in the figure) and the reset voltage threshold Vrst are used to restore the circuit working state after the pre-judgment is completed, and then exposure begins. During exposure, the photodiode (PD) node is clamped at the reset threshold voltage Vrst, and the photogenerated charge accumulated in the photodiode (PD) is amplified by the CTIA capacitor, causing the voltage at the output end of the CTIA capacitor to rise, which is compared with the negative working threshold voltage Vth1 of the comparator (COMP) in real time.

[0048] If the photodiode (PD) voltage in the current frame does not reach the working threshold voltage Vth1, the comparator (COMP) output signal Vpulse does not flip, so it will not trigger the subsequent pre-judgment logic unit, working mode switching logic control unit and reset logic control unit. When the latch signal latch arrives, the pulse signal latch in the pixel latches the Vspike signal as a high level. When the row selection signal Sel arrives, the latched high level signal is output to the column bus through the inverter.

[0049] Since the pulse is not triggered, there is no level flip signal in the current frame, so the 3-bit counter does not record the flip position. When the row selection signal Sel arrives, the 3-bit counter outputs a code value of 000 to the column bus. If the output voltage of the CTIA capacitor reaches Vth1 in the current frame, the comparator (COMP) output signal Vpulse flips, and when the latch signal latch arrives, the pulse signal latch in the pixel latches the Vspike signal as a low level. When the row selection signal Sel arrives, the latched low level signal is latched through the inverter and the high level 1 is output to the column bus. At the same time, the 3-bit counter records the Vpulse flip moment, and when the row selection signal Sel arrives, the 3-bit counter outputs a 3-bit code value to the column bus. After the row selection signal Sel ends, the low level signal latched by the pulse signal latch triggers the pre-judgment, mode switching and reset of the next frame.

[0050] In order to improve the dynamic range and quantization accuracy of pixel response, the pixel structure is designed with a pre-judgment stage for adaptively switching the gain of the photosensitivity node according to the light intensity. This stage is entered after the pixel outputs a 1-bit high-level pulse. In this stage, the photodiode (PD) end is connected to the negative input end of the comparator (COMP) and compared with the set pre-judgment threshold Vth0 in the comparator (COMP). According to the comparison result, the logic gate is controlled to select the pixel working mode of the next frame (low light intensity quantization mode or high light intensity quantization mode), and then the reset stage is entered.

[0051] Figure 4 This is the working timing diagram of the pixel adaptive gain switching process.

[0052] If the previous frame quantizes low light intensity, the potential of the photodiode (PD) node maintains the clamp reference voltage Vref unchanged during the exposure process, and the CTIA capacitor output reaches the comparator (COMP) set threshold Vth1 and triggers a flip. At this time, the Vspike signal turns from high to low, and is latched by the latch signal at the end of the frame, and the Latchout signal is latched as a low level. Subsequently, when the SN1 signal arrives, SN1 and Latchout jointly control the start of the pre-judgment logic, and output S0 as a high-level signal. This signal is used as the input of the working mode switching logic, and together with the Latchin signal, controls the first, second, sixth, seventh, ninth, and tenth MOS switch transistors. During the control pre-judgment period, the CTIA capacitor does not work, the first inverter 15 does not work, the photodiode (PD) is connected to the negative input terminal of the comparator (COMP), and the potential of the photodiode (PD) is compared with the pre-judgment threshold Vth0. If the comparator (COMP) does not flip during the pre-judgment period, it indicates that the light intensity is low, and the low light intensity quantization mode is still used. The second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are turned off, and the first and tenth MOS switch transistors (corresponding to Figure 1 The two SW3_1 switches marked in the figure are closed, and the photodiode (PD) is connected to the negative terminal of the CTIA capacitor. Figure 3 Working sequence; if the comparator (COMP) flips during the pre-judgment period, it indicates that the light intensity is high, and the high light intensity working mode is switched, the second and ninth MOS switch transistors (SW1_1) are closed, the first and tenth MOS switch transistors (SW3_1) are turned off, and the photodiode (PD) is connected to the negative input terminal of the comparator (COMP), and the light intensity is kept high. Figure 2 In the embodiment of the present application, based on the traditional pulse structure, a CTIA capacitor is added to the photodiode (PD) node, and the voltage signal V converted by the photodiode (PD) sensing the light intensity is PD After being amplified by the CTIA capacitor gain, it enters the comparator (COMP) input and is compared with the set threshold Vth1, thereby increasing the photodiode (PD) node conversion gain. This can improve the perception sensitivity when quantifying low-light intensity scenes and ensure response to high-speed scenes under low light intensity.

[0053] In addition, in the embodiment of the present application, the pixel structure combines the working mode of the pulse width modulation pixel, adds the global clock clk and the 3-bit counter in the pixel, and when the comparator (COMP) triggers the flip, the 3-bit counter records the position of the moment in a frame, and outputs the 3-bit code value to the column bus when the row selection signal sel arrives. Therefore, under the condition of a certain frame rate, the quantization accuracy of the pulse pixel and the dynamic range of the high light intensity response are improved.

[0054] In an embodiment of the present application, the pixel structure introduces a pre-judgment logic unit after the trigger pulse. The pre-judgment logic unit controls the pixel to adaptively judge the current light intensity and select the working gain of the next frame. It can simultaneously achieve high speed and high gain under low light intensity and high precision and large dynamic under high light intensity, effectively improving the dynamic range of the pixel.

[0055] In summary, the adaptive light intensity pulse pixel structure of the embodiment of the present invention adds a gain conversion structure to the light intensity sensing node, which can adaptively adjust the conversion gain of the photosensitive node, and at the same time increase the adaptive light intensity pre-judgment structure in the pixel, thereby improving the sensitivity of the pixel in low light intensity scenes, and enhancing the response to low light intensity and high-speed scenes. At the same time, it combines the working modes of pulse width modulation (PWM) and pulse frequency modulation (PFM), introduces a global clock and counter, expands the dynamic range of high light intensity, and can respond to high-speed scenes.

[0056] According to a second aspect of the embodiments of the present invention, an image sensor is provided, comprising the adaptive light intensity high-speed wide dynamic pulse pixel structure.

[0057] According to a third aspect of the embodiments of the present invention, an electronic device is provided, comprising the image sensor.

[0058] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0059] Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the claims are included in the present invention.

[0060] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. High-speed wide dynamic pulse pixel structure with adaptive light intensity, characterized by: It includes a photodiode, multiple MOS switch transistors, a capacitor transimpedance amplifier, a CTIA capacitor, a comparator, multiple inverters, a pulse signal latch, and a 3-bit counter; one end of the first MOS switch transistor is connected to the non-grounded end of the photodiode and the other end is connected to the negative input end of the capacitor transimpedance amplifier; one end of the second MOS switch transistor, the third MOS switch transistor, and the CTIA capacitor are connected to the non-grounded end of the photodiode, and the other end is connected to the output end of the CTIA capacitor; the positive input end of the capacitor transimpedance amplifier is connected to the reset voltage signal Vrst, and the output end is connected to the negative input end of the comparator; One end of the fourth MOS switch transistor, the fifth MOS switch transistor, the sixth MOS switch transistor and the seventh MOS switch transistor are commonly connected to the positive input end of the comparator, and the other ends are respectively connected to the pre-judgment working threshold voltage Vth0, the reset voltage signal Vrst, the first working threshold voltage Vth1, and the second working threshold voltage Vth2; The comparator output is connected to one end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor and one end of the tenth MOS switch transistor. The other end of the tenth MOS switch transistor is connected to the input of the first inverter. The other end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor is connected to the output of the first inverter and the input of the second inverter. The output of the second inverter is connected to the pulse signal latch input and the 3-bit counter input. The output of the 3-bit counter is connected to the input of the third inverter and is input with the global clock signal clk. The input of the pulse signal latch clk is connected to the latch signal latch. The output of the pulse signal latch Q is connected to the input of the fourth inverter and outputs the latch output signal Latchout. The row selection signal Sel is respectively input to the third inverter and the output is connected to the column bus.

2. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 1, characterized in that: It includes a working mode switching logic control unit, which is used to control the output of multiple working mode switching control signals to correspondingly control the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor to switch the working mode.

3. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 2, characterized in that: The S0 signal input terminal of the working mode switching logic control unit is connected to the output signal S0 of the pre-judgment logic unit and the latch input signal Latchin, and controls the output of multiple working mode switching control signals according to the output signal S0 of the pre-judgment logic unit and the latch input signal Latchin.

4. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 3, characterized in that: It includes a reset logic control unit, which is used to control the output reset control signal and correspondingly control the reset of the third MOS switch transistor, the eighth MOS crystal switch tube and the fifth MOS switch transistor; the input end of the reset logic control unit is connected to the output end of the pulse signal latch and is also connected to the reset signal Rst.

5. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 4, characterized in that: It includes a pre-judgment logic unit, which is used to adaptively switch the photosensitive node gain according to the light intensity. The input end of the pre-judgment logic unit is connected to the pre-judgment signal SN1 and the output signal Latchout of the pulse signal latch.

6. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to any one of claims 1 to 5, characterized in that: When quantizing high light intensity, the second MOS switch transistor and the ninth MOS switch transistor are closed, the capacitive transimpedance amplifier does not work, the CTIA capacitor does not work, the first inverter does not work, and the photodiode in the pixel is connected to the negative input terminal of the comparator; During the exposure process, the voltage of the photodiode node gradually decreases and is compared with the second working threshold voltage Vth2 of the comparator in real time. When the threshold voltage is reached, the Vpulse node is triggered to flip, and the flip signal is connected to the pulse signal latch in the pixel by the second inverter; when the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row selection signal Sel arrives, and reset is triggered when the reset signal Rst arrives; After Vpulse flips, the flipping moment is recorded by a 3-bit counter. When the flipping frame ends, the recorded 3-bit data is output outside the chip and combined with the 1-bit pulse data to quantify the light intensity.

7. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 6, characterized in that: When quantizing low light intensity, the second MOS switch transistor and the ninth MOS switch transistor are turned off, the CTIA capacitor works, the first inverter works, the photodiode is connected to the negative input terminal of the CTIA capacitor, and the photogenerated charge during exposure is amplified by the CTIA capacitor gain, and the amplified result is compared with the first working threshold voltage Vth1 in the comparator. When the threshold voltage is reached, the Vpulse node is triggered to flip, and the flip signal is connected to the pulse signal latch in the pixel by the first inverter and the second inverter. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the selection signal Sel arrives; in this working mode, the 3-bit counter records the Vpulse flipping moment, and outputs the recorded 3-bit data outside the chip at the end of the flipping frame, and is combined with the 1-bit pulse data to quantize the light intensity together.

8. The high-speed wide dynamic pulse pixel structure with adaptive light intensity according to claim 7, characterized in that: The pre-judgment logic unit enters the pre-judgment processing process after the pixel outputs a 1-bit high-level pulse. During the pre-judgment processing, the photodiode end is connected to the negative input end of the comparator, and is compared with the set pre-judgment working threshold voltage Vth0 in the comparator. The logic gate is controlled to select the pixel working mode of the next frame according to the comparison result, and then enters the reset stage.

9. An image sensor, characterized in that A high-speed wide dynamic pulse pixel structure with adaptive light intensity comprising the structure described in any one of claims 1 to 8.

10. An electronic device, characterized in that Comprising the image sensor as claimed in claim 9.

Images