Control circuit, chip and equipment

Abstract

The invention relates to the technical field of automotive electronics, and discloses a control circuit, a chip and equipment, and the control circuit comprises an adjustment module, a driving module, a control module and a detection module. The adjusting module is realized through a charge pressure pump structure, the cost is low, voltage reduction is realized through a capacitor and a switch, and chip heating is reduced; the driving module obtains a driving voltage in a normal working range of the light-emitting element through voltage margin adjustment; the control module carries out self-adaptive adjustment on the adjustment module through power supply voltages of different magnitudes, so that the adjustment module is switched to a 0.5 X charge pump mode or a 1X charge pump mode, and it is ensured that enough driving voltage is provided for a light-emitting element while chip heating is reduced; moreover, when the detection module detects an automobile load throwing event, the charge pump structure performs adjustment to obtain an LDO loop, thereby ensuring that the adjustment module outputs a fixed voltage when the automobile load throwing event occurs, preventing the boost of the automobile load throwing event from affecting the circuit, and achieving a protection effect on the control circuit.

Description

Technical Field

[0001] The present invention relates to the field of automotive electronic technology, and in particular to a control circuit, a chip and a device. Background Art

[0002] In the field of automotive electronics, the anode of the light-emitting diode (LED) in the integrated ambient light chip is usually directly connected to the positive terminal of the battery. However, the operating voltage of the LED light is usually lower than the supply voltage of the battery (BAT), resulting in a large voltage drop in the chip, which causes the chip to heat up. Summary of the invention

[0003] Embodiments of the present invention provide a control circuit, a chip and a device.

[0004] In a first aspect, the present invention provides a control circuit, which is connected to a light-emitting element, wherein the control circuit includes an adjustment module, a control module and a driving module, wherein the adjustment module is used to adjust the power supply voltage of the control circuit according to a first control signal of the control module in a buck mode or a pass-through mode to obtain an output voltage, and output the output voltage to the driving module; the driving module is used to generate a driving voltage according to the output voltage, and drive the light-emitting element to emit light through the driving voltage; the control module is used to divide the power supply voltage to obtain a comparison voltage, generate a first control signal according to a first difference between the comparison voltage and the driving voltage, and a size relationship with a preset first threshold, and send the first control signal to the adjustment module, wherein the comparison voltage is equal to the output voltage in the buck mode; and when the first difference is greater than the first threshold, the first control signal is used to instruct the adjustment module to switch to the buck mode; when the first difference is less than or equal to the first threshold, the first control signal is used to instruct the adjustment module to switch to the pass-through mode.

[0005] In a possible implementation of the first aspect above, the output voltage in the buck mode is half of the supply voltage, and the output voltage in the pass mode is equal to the supply voltage.

[0006] In an embodiment of the present invention, the adjustment module is implemented by a charge pump structure with low cost. The voltage is increased or decreased by charging and discharging capacitors and switches, thereby reducing chip heating. The control module adaptively adjusts the adjustment module through power supply voltages of different sizes, so that the adjustment module switches to 0.5X charge pump mode or 1X charge pump mode, thereby reducing chip heating while ensuring that sufficient driving voltage is provided to the light-emitting element.

[0007] In a possible implementation of the first aspect above, the driving module is further configured to adjust the output voltage according to a preset target voltage difference to generate a driving voltage.

[0008] In the embodiment of the present invention, the driving module adjusts the output voltage of the adjusting module to a driving voltage within the normal working range of the light emitting element based on the configured voltage margin.

[0009] In a possible implementation of the first aspect above, the control module is also used to increase the first threshold according to a preset adjustment value to obtain a second threshold when the second difference between the first difference and the first threshold is less than a preset reference threshold, and compare the size of the first difference through the second threshold.

[0010] In a possible implementation of the first aspect above, the control module is also used to, when at the first moment it is determined that the adjustment module needs to be controlled to switch from the step-down mode or the pass-through mode to the pass-through mode or the step-down mode, not control the adjustment module; and, when at the second moment it is determined that the adjustment module needs to be controlled to switch from the step-down mode or the pass-through mode to the pass-through mode or the step-down mode, control the adjustment module to switch from the step-down mode or the pass-through mode to the pass-through mode or the step-down mode, wherein the second moment is a moment after a preset time length of the first moment.

[0011] In a possible implementation of the first aspect above, the control circuit further includes: a detection module, wherein the detection module is used to control the output voltage of the adjustment module to be the target voltage when it is detected that the power supply voltage is greater than a preset target voltage threshold.

[0012] In an embodiment of the present application, when the detection module detects that a vehicle load dump event has occurred, the charge pump structure in the adjustment module can be adjusted to obtain an LDO loop, thereby ensuring that the adjustment module outputs a fixed voltage when a vehicle load dump event occurs, thereby avoiding the voltage boost caused by the vehicle load dump event from affecting the circuit and protecting the control circuit.

[0013] In a possible implementation of the first aspect above, the adjustment module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a first capacitor and a second capacitor, wherein the drain of the first MOS tube is connected to the output end of the power supply voltage, the gate of the first MOS tube is connected to the output end of the clock pulse generator, and the source of the first MOS tube is connected to the drain of the second MOS tube and the positive plate of the first capacitor; the drain of the second MOS tube is connected to the positive plate of the first capacitor, the gate of the second MOS tube is connected to the output end of the clock pulse generator, and the source of the second MOS tube is connected to the source of the fourth MOS tube, the positive plate of the second capacitor and the input end of the driving module; the drain of the third MOS tube is grounded, the gate of the third MOS tube is connected to the output end of the clock pulse generator, and the source of the third MOS tube is connected to the negative plate of the first capacitor and the drain of the fourth MOS tube; the drain of the fourth MOS tube is connected to the negative plate of the first capacitor, the gate of the fourth MOS tube is connected to the output end of the clock pulse generator, and the source of the fourth MOS tube is connected to the positive plate of the second capacitor and the input end of the driving module.

[0014] In a possible implementation of the first aspect above, when the adjustment module adjusts the power supply voltage in the step-down mode, the first MOS tube and the fourth MOS tube are in a cross-closed and disconnected state with the second MOS tube and the third MOS tube, and the first capacitor and the second capacitor are in a charging state when the first MOS tube and the fourth MOS tube are in a closed state, and the first capacitor and the second capacitor are in a discharging state when the first MOS tube and the fourth MOS tube are in a disconnected state; when the adjustment module adjusts the power supply voltage in the pass-through mode, the first MOS tube and the second MOS tube are in a closed state, and the third MOS tube and the fourth MOS tube are in a disconnected state.

[0015] In a possible implementation of the first aspect above, the driving module includes a fifth MOS tube, a sixth MOS tube and a reference current source, wherein a source of the fifth MOS tube is connected to a source of the sixth MOS tube and an output end of the adjustment module, a gate of the fifth MOS tube is connected to a gate of the sixth MOS tube, a drain of the fifth MOS tube is connected to the reference current source, and the drain of the fifth MOS tube is short-circuited with the gate of the fifth MOS tube; a source of the sixth MOS tube is connected to the output end of the adjustment module, a drain of the sixth MOS tube is connected to an input end of the control module and a light-emitting element, wherein a voltage margin value of the sixth MOS tube is a target voltage difference value.

[0016] In a possible implementation of the first aspect above, a channel width-to-length ratio of the fifth MOS transistor to the sixth MOS transistor is 1:1.

[0017] In a possible implementation of the first aspect above, the control module includes a first comparator, a second comparator, an adjustable current source, a first resistor, a second resistor, a third resistor and a filter, wherein a first end of the first resistor is connected to an output end of a power supply voltage, a second end of the first resistor is connected to a first end of the second resistor and a positive input end of the second comparator; a first end of the second resistor is connected to a positive input end of the second comparator, and a second end of the second resistor is grounded; a negative input end of the second comparator is short-circuited with an output end of the second comparator, and an output end of the second comparator is connected to a first end of the third resistor; a second end of the third resistor is connected to a negative input end of the first comparator and the adjustable current source; a negative input end of the first comparator is connected to a second end of the third resistor and the adjustable current source, a positive input end of the first comparator is connected to a drain of a sixth MOS tube, and an output end of the first comparator is connected to an input end of the filter; an output end of the filter is connected to an input end of a clock pulse generator, and a control end of the filter is connected to the adjustable current source, wherein a first threshold value is a product of the third resistor and the adjustable current source, and a resistance value of the first resistor is equal to that of the second resistor.

[0018] In a possible implementation of the first aspect above, when the first comparator determines a first comparison result that the first difference is greater than a first threshold, the first comparison result is sent to the filter, and the filter sends a first control signal to the clock pulse generator based on the first comparison result to control the first MOS tube and the fourth MOS tube to be in a cross-closed and disconnected state with the second MOS tube and the third MOS tube; when the first comparator determines a second comparison result that the first difference is less than or equal to the first threshold, the second comparison result is sent to the filter, and the filter sends a first control signal to the clock pulse generator based on the second comparison result to control the first MOS tube and the second MOS tube to be in a closed state, and the third MOS tube and the fourth MOS tube to be in a disconnected state.

[0019] In a possible implementation of the first aspect above, the detection module includes an amplifier, a third comparator, a fourth resistor and a fifth resistor, wherein a first end of the fourth resistor is connected to an output end of a power supply voltage, a second end of the fourth resistor is connected to a first end of the fifth resistor and a negative input end of the third comparator; a first end of the fifth resistor is connected to a negative input end of the third comparator, and a second end of the fifth resistor is grounded; the negative input end of the third comparator is connected to a comparison voltage source, and an output end of the third comparator is connected to an input end of a clock pulse generator; a negative input end of the amplifier is connected to a reference voltage, a positive input end of the amplifier is connected to an output end of the adjustment module, and an output end of the amplifier is connected to a gate of the first MOS tube, wherein the target voltage is equal to the reference voltage.

[0020] In a possible implementation of the first aspect above, when the third comparator detects that the voltage at the negative input terminal of the third comparator is not equal to the voltage at the positive input terminal of the third comparator, it determines that the supply voltage is greater than a preset target voltage threshold, and sends a second control signal to the clock pulse generator to control the third MOS tube and the fourth MOS tube to be in a disconnected state, the second MOS tube to be in a closed state, and controls the first MOS tube to be connected to the output terminal of the amplifier; at the same time, the amplifier adjusts the gate voltage of the first MOS tube based on the voltage difference between the output voltage of the adjustment module and the comparison voltage source so that the source voltage of the first MOS tube is adjusted to the target voltage.

[0021] In a second aspect, a chip is provided, in which a circuit as described in any one of the first aspects is formed.

[0022] According to a third aspect, an electronic device is provided. The electronic device includes a chip, in which a circuit as described in any one of the first aspects is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 According to some embodiments of the present invention, a schematic diagram of a module example of a control circuit is shown;

[0024] Figure 2According to some embodiments of the present invention, a schematic diagram of a structure example of a control circuit is shown;

[0025] Figure 3 According to some embodiments of the present invention, an example schematic diagram of a clock signal is shown;

[0026] Figure 4 According to some embodiments of the present invention, another exemplary schematic diagram of a control circuit module is shown;

[0027] Figure 5 According to some embodiments of the present invention, another schematic diagram of a control circuit structure example is shown;

[0028] Figure 6 According to some embodiments of the present invention, an exemplary schematic diagram of an electronic device is shown. DETAILED DESCRIPTION

[0029] Illustrative embodiments of the present invention include, but are not limited to, a control circuit, a chip, and a device.

[0030] The following is combined with Figures 1 to 6 The technical solution of the present invention is introduced.

[0031] In some embodiments, the operating voltage of the LED lamp (hereinafter referred to as lamp voltage) is usually between 0 volts (voltage, V) and 4 V; for example, the lamp voltage of a red LED lamp is usually between 1.8 V and 2.5 V, and the lamp voltage of a blue LED lamp is usually between 3 V and 3.8 V, etc. The supply voltage of the battery (hereinafter referred to as battery voltage) is usually between 6 V and 12 V. It can be understood that the values ​​and ranges of the lamp voltage and battery voltage in the above examples are only examples of some embodiments of the present application. In other embodiments, the lamp voltage and battery voltage can also be other values ​​and ranges, which are not specifically limited.

[0032] For example, in the field of automotive electronics, take the battery voltage VBAT of 12V and the lamp voltage VLED of the blue LED lamp of 3.5V as an example; during the operation of the integrated ambient light chip, the drive circuit directly connected between the LED lamp and the battery will produce a voltage drop of 8.5V, and the chip power consumption will increase, causing the chip to heat up.

[0033] To this end, the present invention proposes a control circuit 001, which is connected to a light-emitting element (such as an LED lamp) to drive the light-emitting element to emit light. Figure 1As shown, the control circuit 001 includes an adjustment module 11, a driving module 12 and a control module 13; the adjustment module 11 is used to adjust the power supply voltage of the control circuit according to the buck mode or the direct-pass mode according to the first control signal of the control module 13 to obtain an output voltage, and output the output voltage to the driving module 12; the driving module 12 is used to generate a driving voltage according to the output voltage, and drive the light-emitting element to emit light through the driving voltage; the control module 13 is used to divide the power supply voltage to obtain a comparison voltage, generate a first control signal according to a first difference between the comparison voltage and the driving voltage, and a magnitude relationship with a preset first threshold, and send the first control signal to the adjustment module 11, wherein the comparison voltage is equal to the output voltage in the buck mode; and when the first difference is greater than the first threshold, the first control signal is used to instruct the adjustment module 11 to switch to the buck mode; when the first difference is less than or equal to the first threshold, the first control signal is used to instruct the adjustment module 11 to switch to the direct-pass mode.

[0034] Exemplarily, the adjustment module 11 is implemented by a charge pump (CP) structure, which has a low cost. The adjustment module 11 realizes the voltage rise and fall through the charging and discharging of the capacitor and the switch in the charge pump, thereby reducing the heat generation of the chip. The driving module 12 configures the voltage headroom through the target voltage difference, and adjusts the output voltage of the adjustment module 11 to the driving voltage within the normal working range of the light-emitting element based on the voltage headroom, thereby avoiding the excessively high or low driving voltage from affecting the working efficiency of the light-emitting element. When the power supply voltage is large, the control module 13 controls the adjustment module 11 to adjust the power supply voltage through the buck mode (such as 0.5X charge pump) so that the output voltage is reduced by half relative to the power supply voltage, thereby reducing the voltage drop between the output voltage and the light-emitting element, thereby reducing the heat generation of the chip; and when the power supply voltage is small, the control module 13 controls the adjustment module 11 to adjust the power supply voltage through the pass-through mode (such as 1X charge pump) so that the output voltage is equal to the power supply voltage, thereby ensuring that sufficient driving voltage is provided to the light-emitting element. In this way, the control module 13 can adaptively adjust the adjustment module 11 through different power supply voltages to switch different modes, thereby improving the circuit efficiency.

[0035] The following is an example of the connection relationship between the components in each module.

[0036] In some embodiments, in combination Figure 1 ,like Figure 2As shown, the adjustment module 11 includes a P-channel metal oxide semiconductor field effect transistor (positive channel metal oxide semiconductor, PMOS, hereinafter referred to as PMOS tube) MP1 (corresponding to an example of the first MOS tube), a PMOS tube MP2 (corresponding to an example of the second MOS tube), a PMOS tube MP3 (corresponding to an example of the third MOS tube), a PMOS tube MP4 (corresponding to an example of the fourth MOS tube), a capacitor C1 (corresponding to an example of the first capacitor) and a capacitor C0 (corresponding to an example of the second capacitor); the driving module 12 includes a PMOS tube MP5 (corresponding to an example of the fifth MOS tube), a PMOS tube MP6 (corresponding to an example of the sixth MOS tube) and a reference current source; the control module 13 includes a first comparator 10, a second comparator 20, an adjustable current source 30, a resistor R1 (corresponding to an example of the first resistor), a resistor R2 (corresponding to an example of the second resistor), a resistor R3 (corresponding to an example of the third resistor) and a filter.

[0037] Exemplarily, in the adjustment module 11:

[0038] The connection relationship of the PMOS tube MP1 is as follows: the drain of the PMOS tube MP1 is connected to the output end of the power supply voltage VBAT and the first end of the resistor R1, the gate of the PMOS tube MP1 is connected to the output end of the clock pulse generator (not shown in the figure), and the source of the PMOS tube MP1 is connected to the drain of the PMOS tube MP2 and the positive plate of the capacitor C1.

[0039] The connection relationship of the PMOS tube MP2 is as follows: the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP1 and the positive plate of the capacitor C1, the gate of the PMOS tube MP2 is connected to the output end of the clock pulse generator, the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP4, the positive plate of the capacitor C0, the source of the PMOS tube MP5, and the source of the PMOS tube MP6 (the source of the PMOS tube MP5 and the source of the PMOS tube MP6 are used as the input end of the driving module 12, which can be understood as the source of the PMOS tube MP2 is connected to the input end of the driving module 12).

[0040] The connection relationship of the PMOS tube MP3 is as follows: the drain of the PMOS tube MP3 is grounded, the gate of the PMOS tube MP3 is connected to the output end of the clock pulse generator, and the source of the PMOS tube MP3 is connected to the negative plate of the capacitor C1 and the drain of the PMOS tube MP4.

[0041] The connection relationship of the PMOS tube MP4 is as follows: the drain of the PMOS tube MP4 is connected to the negative plate of the capacitor C1 and the source of the PMOS tube MP3, the gate of the PMOS tube MP4 is connected to the output end of the clock pulse generator, and the source of the PMOS tube MP4 is connected to the source of the PMOS tube MP2, the positive plate of the capacitor C0, the source of the PMOS tube MP5, and the source of the PMOS tube MP6 (the source of the PMOS tube MP5 and the source of the PMOS tube MP6 are used as the input end of the driving module 12, which can be understood as the source of the PMOS tube MP4 is connected to the input end of the driving module 12).

[0042] The connection relationship of the capacitor C1 is as follows: the positive plate of the capacitor C1 is connected to the source of the PMOS tube MP1 and the drain of the PMOS tube MP2, and the negative plate of the capacitor C1 is connected to the source of the PMOS tube MP3 and the drain of the PMOS tube MP4.

[0043] The connection relationship of the capacitor C0 is as follows: the positive plate of the capacitor C0 is connected to the source of the PMOS tube MP2, the source of the PMOS tube MP4, the source of the PMOS tube MP5, and the source of the PMOS tube MP6, and the negative plate of the capacitor C0 is grounded.

[0044] For example, in the driving module 12:

[0045] The connection relationship of the PMOS tube MP5 is as follows: the source of the PMOS tube MP5 is connected to the source of the PMOS tube MP2, the source of the PMOS tube MP4, the source of the PMOS tube MP6, and the positive plate of the capacitor C0 (the source of the PMOS tube MP2, the source of the PMOS tube MP4, and the positive plate of the capacitor C0 are used as the output end of the adjustment module 11, that is, it can be understood that the source of the PMOS tube MP5 is connected to the output end of the adjustment module 11), the gate of the PMOS tube MP5 is connected to the gate of the PMOS tube MP6, the drain of the PMOS tube MP5 is connected to the reference current source IREF, and the drain of the PMOS tube MP5 is short-circuited with the gate of the PMOS tube MP5.

[0046] The connection relationship of the PMOS tube MP6 is as follows: the source of the PMOS tube MP6 is connected to the source of the PMOS tube MP2, the source of the PMOS tube MP4, the source of the PMOS tube MP5, and the positive plate of the capacitor C0 (the source of the PMOS tube MP2, the source of the PMOS tube MP4, and the positive plate of the capacitor C0 are used as the output end of the adjustment module 11, that is, it can be understood that the source of the PMOS tube MP6 is connected to the output end of the adjustment module 11), the gate of the PMOS tube MP6 is connected to the gate of the PMOS tube MP5, and the drain of the PMOS tube MP6 is connected to the positive input end of the first comparator 10 and the light-emitting element LED (the positive input end of the first comparator 10 is used as the input end of the control module 13, that is, it can be understood that the drain of the PMOS tube MP6 is connected to the input end of the control module 13).

[0047] For example, in the control module 13:

[0048] The connection relationship of the resistor R1 is as follows: the first end of the resistor R1 is connected to the output end of the power supply voltage VBAT and the drain of the PMOS tube MP1 , and the second end of the resistor R1 is connected to the first end of the resistor R2 and the positive input end of the second comparator 20 .

[0049] The connection relationship of the resistor R2 is as follows: the first end of the resistor R2 is connected to the second end of the resistor R1 and the positive input end of the second comparator 20 , and the second end of the resistor R2 is grounded.

[0050] The connection relationship of the second comparator 20 is as follows: the positive input terminal of the second comparator 20 is connected to the second end of the resistor R1 and the first end of the resistor R2, the negative input terminal of the second comparator 20 is short-circuited with the output terminal of the second comparator 20, and the output terminal of the second comparator 20 is connected to the first end of the resistor R3.

[0051] The connection relationship of the resistor R3 is as follows: a first end of the resistor R3 is connected to the output end of the second comparator 20 , and a second end of the resistor R3 is connected to the negative input end of the first comparator 10 and the adjustable current source 30 .

[0052] The connection relationship of the first comparator 10 is as follows: the negative input terminal of the first comparator 10 is connected to the second end of the resistor R3 and the adjustable current source 30, the positive input terminal of the first comparator 10 is connected to the drain of the PMOS tube MP6, and the output terminal of the first comparator 10 is connected to the input terminal of the filter.

[0053] The connection relationship of the filter is as follows: the input end of the filter is connected to the output end of the first comparator 10 , the output end of the filter is connected to the input end of the clock pulse generator, and the control end of the filter is connected to the adjustable current source 30 .

[0054] In some embodiments, the above-mentioned PMOS transistors MP1 to MP6 may also be configured as NMOS transistors MN1 to MN6 , and the specific connection relationship is adjusted accordingly according to the configuration of the NMOS transistors, and is not specifically limited.

[0055] The following is an example to illustrate the working principle of the adjustment module.

[0056] In some embodiments, the input end of the adjustment module 11 is connected to the power supply voltage VBAT, and the output end of the adjustment module 11 is connected to the input end of the driving module. The adjustment module 11 is used to adjust the power supply voltage VBAT and output the adjusted output voltage to the driving module 12, so that the driving module 12 can drive the light-emitting element LED to emit light.

[0057] In some embodiments, the adjustment module 11 implements a 0.5X or 1X charge pump structure through PMOS tube MP1, PMOS tube MP2, PMOS tube MP3, PMOS tube MP4, capacitor C1 and capacitor C0. Exemplarily, the adjustment module 11 controls the closing and opening of PMOS tubes MP1 to PMOS tubes MP4 through a clock pulse generator, and controls the charging and discharging of capacitors C1 and capacitor C0 through the closing and opening of PMOS tubes MP1 to MP4. Among them, capacitor C1 and capacitor C0 are capacitors of the same specifications.

[0058] In some embodiments, when the power supply voltage VBAT is high, the adjustment module 11 can realize a 0.5X charge pump structure (hereinafter referred to as the 0.5X mode, an example corresponding to the buck mode) by turning off the switch and charging and discharging the capacitor, thereby reducing the voltage by half and reducing chip heating; in other embodiments, when the power supply voltage VBAT is low, the adjustment module 11 can realize a 1X charge pump structure (hereinafter referred to as the 1X mode, an example corresponding to the pass-through mode) by turning off the switch to ensure that the adjustment module 11 can output sufficient output voltage to the driving module 12.

[0059] The following is an example of the 0.5X mode.

[0060] Figure 3 According to an embodiment of the present application, a schematic diagram of a clock signal is shown.

[0061] In some embodiments, Figure 3 As shown, Phase1 and Phase2 are clock signals output by the clock pulse generator, Phase1 is used to control the PMOS tube MP2 and the PMOS tube MP3, and Phase2 is used to control the PMOS tube MP1 and the PMOS tube MP4.

[0062] Exemplarily, a high potential signal represents a disconnection signal, and a low potential signal represents a closing signal. It can be seen that when the PMOS tube MP1 and the PMOS tube MP4 are closed, the PMOS tube MP2 and the PMOS tube MP3 are disconnected; when the PMOS tube MP1 and the PMOS tube MP4 are disconnected, the PMOS tube MP2 and the PMOS tube MP3 are closed.

[0063] Furthermore, combined with Figure 2 and Figure 3 As shown, when the PMOS tube MP1 and the PMOS tube MP4 are closed and the PMOS tube MP2 and the PMOS tube MP3 are disconnected, the capacitors C1 and C0 are in a charging state, and the charge of the capacitor C1 can be expressed by formula (1) as follows:

[0064] QC11 = (VBAT - VOUT_CP)* C1 (1)

[0065] In formula (1), QC11 represents the charge of the capacitor C1 when it is in a charging state, VBAT represents the power supply voltage, VOUT_CP represents the output voltage of the adjustment module 11, and C1 represents the capacitance of the capacitor C1.

[0066] When the PMOS transistors MP1 and MP4 are disconnected and the PMOS transistors MP2 and MP3 are closed, the capacitors C1 and C0 are in a discharging state, and the charge of the capacitor C1 can be expressed by formula (2) as follows:

[0067] QC12 = VOUT_CP * C1 (2)

[0068] In formula (2), QC12 represents the charge of capacitor C1 when it is in a discharged state.

[0069] It can be understood that since the voltage of the capacitor cannot usually change suddenly, that is, when the capacitor switches between the charging state and the discharging state, the voltage of the capacitor is usually the same, that is, the amount of electricity is the same. Therefore, it can be seen that formula (1) and formula (2) are equal, and VOUT_CP can be obtained to be half of VBAT, that is, VOUT_CP = 0.5VBAT. In this way, the adjustment module 11 controls the PMOS tubes MP1, MP4 and the PMOS tubes MP2, MP3 to be closed and opened in a cross-type manner to control the capacitor C1 to switch between charging and discharging, and can achieve a 0.5X mode, so that the output voltage VOUT_CP of the adjustment module 11 is half of the power supply voltage VBAT. Based on this, the adjustment module 11 achieves a 0.5X mode by turning off the switch and charging and discharging the capacitor so that the voltage can be reduced by half, thereby reducing chip heating.

[0070] The following is an example of the 1X mode.

[0071] In some embodiments, the adjustment module 11 can adjust the clock signal through a clock pulse generator so that the PMOS tube MP1 and the PMOS tube MP2 are closed, and the PMOS tube MP3 and the PMOS tube MP4 are disconnected, so that the 1X mode can be realized, so that the output voltage VOUT_CP of the adjustment module 11 is equal to the power supply voltage VBAT, ensuring that the adjustment module 11 can output sufficient output voltage to the driving module.

[0072] The working principle of the driving module 12 is described below by way of example.

[0073] In some embodiments, the input end of the driving module 12 is connected to the output end of the adjustment module 11, and the output end of the driving module 12 is connected to the light-emitting element LED. The driving module 12 outputs a driving voltage to the light-emitting element LED by adjusting the output voltage of the module 11 to drive the light-emitting element LED to emit light.

[0074] In some embodiments, the PMOS tube MP5 and the PMOS tube MP6 form a current mirror structure, and the PMOS tube MP5 can copy the current of the reference current source IREF to the PMOS tube MP6 through the current mirror structure to provide a stable current for the light-emitting element LED connected to the PMOS tube MP6. The channel width-to-length ratio of the PMOS tube MP5 and the PMOS tube MP6 is 1:1, that is, the PMOS tube MP5 copies the current of the reference current source IREF to the PMOS tube MP6 through a current copy ratio of 1:1.

[0075] Furthermore, to ensure the normal operation of the light-emitting element LED, the driving module 12 can set a corresponding voltage margin Vh (an example corresponding to the target voltage difference) through the PMOS tube MP6, and adjust the output voltage VOUT_CP output by the adjustment module 11 through the voltage margin Vh to obtain a driving voltage that meets the normal operating range of the light-emitting element LED.

[0076] Exemplarily, the voltage margin Vh can be set to different voltage margins according to different specifications of the light-emitting element LED or different applications of the control circuit, such as 100mv or 200mv or any value between 100mv and 200mv or other values, without specific limitation.

[0077] The working principle of the control module 13 is described below by way of example.

[0078] In some embodiments, the control module 13 is used to collect the power supply voltage VBAT and the operating voltage (hereinafter referred to as lamp voltage) VLED of the light-emitting element LED, and obtain a comparison result by comparing the power supply voltage VBAT and the lamp voltage VLED, and output a control signal A (corresponding to an example of the first control signal) to the adjustment module 11 based on the comparison result, thereby controlling the adjustment module 11 to switch from 1X mode to 0.5X mode or from 0.5X mode to 1X mode.

[0079] In some embodiments, resistors R1 and R2 are used to divide the power supply voltage VBAT collected by the control module 13 in 0.5X mode, so that the comparison voltage obtained by the voltage division is equal to the output voltage VOUT_CP of the adjustment module 11 in 0.5X mode. Exemplarily, the comparison voltage is identified by 0.5VBAT below.

[0080] Furthermore, the voltage at the positive input terminal of the second comparator 20 is the comparison voltage 0.5VBAT, and since the negative input terminal of the second comparator 20 and the output terminal of the second comparator 20 are short-circuited to form a virtual short and a virtual break, the voltage at the output terminal of the second comparator 20 is equal to the voltage at the positive input terminal of the second comparator 20, that is, the comparison voltage 0.5VBAT.

[0081] In some embodiments, the resistance value of the resistor R3 is R, the current value of the adjustable current source 30 is I, that is, the voltage at the negative input terminal of the first comparator 10 is the comparison voltage 0.5VBAT-IR; and the voltage at the positive input terminal of the first comparator 10 is the lamp voltage VLED.

[0082] Exemplarily, the resistance value R of the resistor R3 is usually a fixed value, and the initial value of the current value I of the adjustable current source 30 can be set according to the voltage margin Vh, so that IR is equal to the voltage margin Vh. Exemplarily, the control module 13 uses IR as a comparison threshold IR when comparing the comparison voltage 0.5VBAT with the lamp voltage VLED.

[0083] In some embodiments, when the first comparator 10 determines that the difference between the comparison voltage 0.5VBAT and the lamp voltage VLED (corresponding to an example of the first difference) is greater than the comparison threshold IR (corresponding to an example of the first threshold) (corresponding to an example of the first comparison result), it means that when the adjustment module 11 is in the 0.5X mode, the driving module 12 has enough voltage margin Vh, that is, the driving module 12 can provide enough driving voltage to the light-emitting element LED. At this time, the control module 13 controls the adjustment module 11 to enter the 0.5X mode, that is, controls the PMOS tubes MP1, MP4 and the PMOS tubes MP2, MP3 to be closed and opened in a cross-type.

[0084] In other embodiments, when the first comparator 10 determines that the difference between the comparison voltage 0.5VBAT and the lamp voltage VLED is less than or equal to the comparison threshold IR (corresponding to the example of the second comparison result), it means that when the adjustment module 11 is in the 0.5X mode, the driving module 12 does not have enough voltage margin Vh, that is, the driving module 12 cannot provide enough driving voltage to the light-emitting element LED. At this time, the control module 13 controls the adjustment module 11 to enter the 1X mode, that is, controls the PMOS tube MP1 and the PMOS tube MP2 to be closed, and the PMOS tube MP3 and the PMOS tube MP4 to be disconnected.

[0085] In some embodiments, in order to prevent the adjustment module 11 from switching between the 1X mode and the 0.5X mode at high frequency due to errors such as offset voltage in the control circuit, the control module 13 may adjust the comparison threshold IR.

[0086] For example, the embodiment of the present application is explained by taking the example that the voltage margin Vh is 0.2V and the initial comparison threshold IR is 0.2V.

[0087] In some embodiments, when the power supply voltage VBAT is 8V and the lamp voltage VLED is 3.5V, since 8 / 2-3.5 is greater than 0.2, the adjustment module 11 enters the 0.5X mode. Further, when the power supply voltage VBAT becomes 7.4V, since 7.4 / 2-3.5 is equal to 0.2, the adjustment module 11 enters the 1X mode.

[0088] However, since there may be errors such as offset voltage in the control circuit, the power supply voltage VBAT may change back and forth around 7.4V, for example, the power supply voltage VBAT changes back and forth between 7.41V, 7.39V, 7.401V, and 7.391V, which may cause the adjustment module 11 to switch between the 1X mode and the 0.5X mode at a high frequency, affecting the circuit working efficiency. In this way, the control module 13 can adjust the comparison threshold IR to avoid the adjustment module 11 from switching between the 1X mode and the 0.5X mode at a high frequency.

[0089] In some embodiments, when the difference between the comparison voltage 0.5VBAT and the lamp voltage VLED and the difference between the current comparison threshold IR (corresponding to the example of the second difference) is less than the preset reference threshold, it means that the difference between the comparison voltage 0.5VBAT and the lamp voltage VLED may be affected by the offset voltage, etc., and switch between being greater than the current comparison threshold IR and being less than or equal to the current comparison threshold IR. In this way, the control module 13 can perform hysteresis voltage control through the filter to increase the current comparison threshold IR, so that the power supply voltage VBAT needs a greater degree of change to switch the mode. Exemplarily, the reference threshold can be 0.1 or 0.05, etc., without specific limitation.

[0090] For example, when the power supply voltage VBAT changes to 7.4V and the adjustment module 11 enters the 1X mode, the control module increases the current comparison threshold IR from 0.2V (corresponding to the example of the first threshold) by 0.1V (corresponding to the example of the adjustment value) to 0.3V (corresponding to the example of the second threshold). At this time, the power supply voltage VBAT needs to change from 7.4V to a voltage value greater than 7.6V before the adjustment module 11 can re-enter the 0.5X mode. At this time, the hysteresis voltage is 7.6-7.4=0.2V. Exemplarily, the control module can also increase the comparison threshold IR from 0.2V to 0.2V, 0.25V or 0.3V, etc. to 0.4V, 0.45V or 0.5V, etc., without specific limitation.

[0091] In some embodiments, in order to further avoid high-frequency switching between the 1X mode and the 0.5X mode of the adjustment module 11, the control module 13 can also perform delayed comparison control through the filter. For example, if the comparison result T1 obtained by the filter at the current moment is used to control the adjustment module 11 to switch from the 0.5X mode to the 1X mode, the filter can retain the comparison result T1 and compare the comparison result T1 with the comparison result T2 of the next moment after the preset time length T of the current moment; if the comparison result T1 is the same as the comparison result T2 and both control the adjustment module 11 to switch from the 0.5X mode to the 1X mode, the filter sends a control signal to the control module 11 to control the adjustment module 11 to switch from the 0.5X mode to the 1X mode; if the comparison result T1 is different from the comparison result T2, such as the comparison result T2 is used to control the adjustment module 11 to switch from the 0.5X mode to the 1X mode. If block 11 continues to execute the 0.5X mode, the filter does not execute the comparison result T1 and the comparison result T2, and continues to obtain the comparison result T3 after the preset time length T. If the comparison result T2 and the comparison result T3 are the same, both of which control the adjustment module 11 to switch from the 0.5X mode to the 1X mode, the filter sends a control signal to the control module 11 to control the adjustment module 11 to switch from the 0.5X mode to the 1X mode; if the comparison result T2 and the comparison result T3 are different, such as the comparison result T3 is used to control the adjustment module 11 to continue to execute the 0.5X mode, the filter does not execute the comparison result T2 and the comparison result T3, and so on. The control module 11 compares the comparison results of the previous moment (corresponding to the example of the first moment) and the next moment (corresponding to the example of the second moment) of the preset time length T through the filter, executes control when the two comparison results are the same, and continues to compare when the two comparison results are different, so as to avoid the control adjustment module 11 from switching modes at high frequency within the preset time length T, and ensure the stability of the control circuit. Exemplarily, the preset duration T may be 1 ms, 2 ms, or any other duration, without specific limitation.

[0092] In some embodiments, in the field of automotive electronics, a load dump event may occur when the car is charging, that is, when the car is charging, the power supply voltage VBAT may suddenly rise to a higher value, such as 40V. At this time, the power supply voltage VBAT can only be reduced to, for example, 20V by adjusting the module 0.5X mode, which is quite different from the working voltage of the light-emitting element LED, and may damage the light-emitting element LED. In this way, for example Figure 4 As shown, the present application configures a detection module 14 in the control circuit 001, detects a vehicle load dump event through the detection module 14, and controls the adjustment module 11 to output a preset fixed voltage when a vehicle load dump event occurs through the detection module 14.

[0093] In some embodiments, in combination Figure 4 ,like Figure 5 As shown, the detection module 14 includes an amplifier 01, a third comparator 30, a resistor R4 and a resistor R5. Exemplarily, in the detection module 14:

[0094] The connection relationship of the amplifier 01 is as follows: the negative input terminal of the amplifier 01 is connected to the reference voltage VREF, the positive input terminal of the amplifier 01 is connected to the source of the PMOS tube MP2, the source of the PMOS tube MP4, the positive plate of the capacitor C0, the source of the PMOS tube MP5, and the source of the PMOS tube MP6 (the source of the PMOS tube MP2, the source of the PMOS tube MP4 and the positive plate of the capacitor C0 are used as the output terminal of the adjustment module 11, that is, it can be understood that the positive input terminal of the amplifier 01 is connected to the output terminal of the adjustment module 11), and the output terminal of the amplifier 01 is connected to the gate of the PMOS tube MP1.

[0095] The connection relationship of the resistor R4 is as follows: the first end of the resistor R4 is connected to the output end of the power supply voltage VBAT, the first end of the resistor R1, and the drain of the PMOS tube MP1; the second end of the resistor R4 is connected to the first end of the resistor R5 and the negative input end of the third comparator 30.

[0096] The connection relationship of the resistor R5 is as follows: the first end of the resistor R5 is connected to the second end of the resistor R4 and the negative input end of the third comparator 30 , and the second end of the resistor R5 is grounded.

[0097] The connection relationship of the third comparator 30 is as follows: the positive input terminal of the third comparator 30 is connected to the second end of the resistor R4 and the first end of the resistor R5, the negative input terminal of the third comparator 30 is connected to the comparison voltage source Vx, and the output terminal of the third comparator 30 is connected to the input terminal of the clock pulse generator (not shown in the figure).

[0098] In some embodiments, resistors R4 and R5 are used to divide the power supply voltage VBAT of the input detection module 14 to obtain the detection voltage. That is, the negative input voltage of the third comparator 30 is the detection voltage, and the third comparator 30 compares the detection voltage with the voltage of the comparison voltage source Vx.

[0099] Exemplarily, the comparison voltage source Vx is used to represent the voltage division value when the power supply voltage VBAT is in a normal range (such as 6V to 12V). For example, when the voltage division value of the power supply voltage VBAT is in a normal range, 1.2V, the voltage of the comparison voltage source Vx is 1.2V. When the detection voltage is the voltage of the comparison voltage source Vx, it indicates that the power supply voltage VBAT is normal, and the third comparator 30 outputs a control signal B of 0 (corresponding to an example of the second control signal) to the adjustment module 11, and does not control the adjustment module 11; when the detection voltage is not the voltage of the comparison voltage source Vx, it indicates that the power supply voltage VBAT is abnormal (such as the power supply voltage VBAT is greater than a preset target voltage threshold), and the third comparator 30 outputs a control signal B of 1 to the adjustment module 11 to control the adjustment module 11. Exemplarily, the target voltage threshold can be 12V, 20V or 24V, etc., without specific limitation.

[0100] Further, when the power supply voltage VBAT is abnormal, the detection module 14 controls the adjustment module 11 to turn off the PMOS tubes MP3 and MP4, turn on the PMOS tube MP2, and connect the gate of the PMOS tube MP1 to the output end of the amplifier 01 and control the conduction state of the PMOS tube MP1 according to the output of the amplifier 01. At this time, a low dropout regulator (LDO) loop is formed between the amplifier 01 and the PMOS tubes MP1 and MP2.

[0101] In the LDO loop, the voltage at the positive input terminal of the amplifier 01 is the output voltage VOUT_CP of the adjustment module 11 (e.g., in 1X mode, the output voltage VOUT_CP is VBAT; in 0.5X mode, the output voltage VOUT_CP is 0.5VBAT), and the voltage at the positive input terminal of the amplifier 01 is the reference voltage VREF, such as 5V; the amplifier 01 amplifies the voltage difference between the output voltage VOUT_CP at the positive input terminal and the reference voltage VREF at the negative input terminal and generates a control signal, and adjusts the gate voltage of the PMOS tube MP1 through the control signal, thereby changing the on-resistance of the PMOS tube MP1, and further adjusting the output voltage of the adjustment module 11. For example, when the output voltage VOUT_CP increases, the voltage difference between the output voltage VOUT_CP and the reference voltage VREF increases, resulting in an increase in the gate voltage of the PMOS tube MP1, which increases the on-resistance of the PMOS tube MP1, resulting in a decrease in the current and voltage flowing through the PMOS tube MP1, until the output voltage VOUT_CP is equal to the voltage of the reference voltage VREF, so that the adjustment module 11 can output a stable voltage, such as an output fixed voltage of 5V (corresponding to an example of a target voltage).

[0102] In this way, the present application can adjust the control circuit 001 to the LDO mode by performing circuit adjustment on the charge pump structure, and no additional circuit is required to enter the LDO mode. The LDO loop in the LDO mode can ensure that the adjustment module 11 outputs a fixed voltage when a car load dump event occurs, thereby avoiding the boost of the car load dump event affecting the circuit and protecting the control circuit.

[0103] It can be understood that the above control circuit 001 can be deployed in any electronic device deployed with a rechargeable battery and a light-emitting element, such as a car, a mobile phone, a computer, etc., without specific limitation.

[0104] Figure 6 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Figure 6As shown, the electronic device 100 includes: a processor 101, a communication interface 103 and a memory 102. Among them, the processor 101, the communication interface 103 and the memory 102 can be connected to each other through an internal bus 104, and can also communicate through other means such as wireless transmission. In the embodiment of the present application, the connection through the bus 104 is taken as an example. The bus 104 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 104 can be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 104 can also include a power bus, a control bus, and a status signal bus. For the sake of clarity, various buses are marked as bus 104 in the figure.

[0105] The processor 101 may be composed of at least one general-purpose processor, such as a central processing unit (CPU), or a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 101 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 102, which enables the electronic device 100 to provide a variety of services.

[0106] The memory 102 may include a volatile memory, such as a random access memory (RAM); the memory 102 may also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD); the memory 102 may also include a combination of the above types.

[0107] The communication interface 103 can be a wired interface (such as an Ethernet interface), an internal interface (such as a PCIe bus interface), a wired interface (such as an Ethernet interface) or a wireless interface (such as a cellular network interface or a wireless LAN interface) for communicating with other devices or modules.

[0108] Need to explain, Figure 6 This is only one possible implementation of the embodiment of the present application. In actual applications, the electronic device 100 may also include more or fewer components, which will not be elaborated here.

[0109] The present application also provides a chip, which can be deployed in the electronic device 100, and the chip forms a circuit as described in any of the above embodiments. The chip can be an analog-to-digital conversion chip, an interface chip, or a power management chip.

[0110] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0111] It should be noted that the units / modules mentioned in the various device embodiments of the present invention are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present invention. In addition, in order to highlight the innovative part of the present invention, the above-mentioned device embodiments of the present invention do not introduce units / modules that are not closely related to solving the technical problems proposed by the present invention, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0112] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0113] While the present invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention.

Claims

1. A control circuit, characterized in that: The control circuit is connected to the light emitting element, wherein the control circuit includes an adjustment module, a control module and a driving module, wherein: The adjustment module is used to adjust the power supply voltage of the control circuit according to the first control signal of the control module in a buck mode or a pass-through mode to obtain an output voltage, and output the output voltage to the driving module; The driving module is used to generate a driving voltage according to the output voltage, and drive the light-emitting element to emit light through the driving voltage; The control module is used to divide the supply voltage to obtain a comparison voltage, generate the first control signal according to a first difference between the comparison voltage and the drive voltage and a magnitude relationship with a preset first threshold, and send the first control signal to the adjustment module, wherein the comparison voltage is equal to the output voltage in the buck mode; and when the first difference is greater than the first threshold, the first control signal is used to instruct the adjustment module to switch to the buck mode; when the first difference is less than or equal to the first threshold, the first control signal is used to instruct the adjustment module to switch to the pass-through mode.

2. The circuit according to claim 1, characterized in that The output voltage in the buck mode is half of the supply voltage, and the output voltage in the pass mode is equal to the supply voltage.

3. The circuit according to claim 1, characterized in that The driving module is further used to adjust the output voltage according to a preset target voltage difference to generate the driving voltage.

4. The circuit according to claim 1, characterized in that The control module is also used to increase the first threshold by a preset adjustment value to obtain a second threshold when a second difference between the first difference and the first threshold is smaller than a preset reference threshold, and compare the size of the first difference with the second threshold.

5. The circuit according to claim 1, characterized in that The control module is further configured to not control the adjustment module when it is determined at the first moment that the adjustment module needs to be controlled to switch from the buck mode or the direct-through mode to the direct-through mode or the buck mode; and When it is determined at the second moment that the adjustment module needs to be controlled to switch from the step-down mode or the direct-through mode to the direct-through mode or the step-down mode, the adjustment module is controlled to switch from the step-down mode or the direct-through mode to the direct-through mode or the step-down mode, wherein the second moment is a moment after a preset time length of the first moment.

6. The circuit according to any one of claims 1 to 5, characterized in that: The control circuit further includes: a detection module, wherein the detection module is used to control the output voltage of the adjustment module to be a target voltage when it is detected that the supply voltage is greater than a preset target voltage threshold.

7. The circuit according to claim 6, characterized in that The adjustment module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first capacitor and a second capacitor, wherein: The drain of the first MOS tube is connected to the output end of the power supply voltage, the gate of the first MOS tube is connected to the output end of the clock pulse generator, and the source of the first MOS tube is connected to the drain of the second MOS tube and the positive plate of the first capacitor; the drain of the second MOS tube is connected to the positive plate of the first capacitor, the gate of the second MOS tube is connected to the output end of the clock pulse generator, and the source of the second MOS tube is connected to the source of the fourth MOS tube, the positive plate of the second capacitor and the input end of the driving module; the drain of the third MOS tube is grounded, the gate of the third MOS tube is connected to the output end of the clock pulse generator, and the source of the third MOS tube is connected to the negative plate of the first capacitor and the drain of the fourth MOS tube; the drain of the fourth MOS tube is connected to the negative plate of the first capacitor, the gate of the fourth MOS tube is connected to the output end of the clock pulse generator, and the source of the fourth MOS tube is connected to the positive plate of the second capacitor and the input end of the driving module.

8. The circuit according to claim 7, characterized in that When the adjustment module adjusts the supply voltage according to the step-down mode, the first MOS transistor and the fourth MOS transistor are in a cross-closed and disconnected state with the second MOS transistor and the third MOS transistor, and the first capacitor and the second capacitor are in a charging state when the first MOS transistor and the fourth MOS transistor are in a closed state, and the first capacitor and the second capacitor are in a discharging state when the first MOS transistor and the fourth MOS transistor are in a disconnected state; When the adjustment module adjusts the power supply voltage according to the through mode, the first MOS transistor and the second MOS transistor are in a closed state, and the third MOS transistor and the fourth MOS transistor are in a disconnected state.

9. The circuit according to claim 7, characterized in that The driving module includes a fifth MOS transistor, a sixth MOS transistor and a reference current source, wherein: The source of the fifth MOS tube is connected to the source of the sixth MOS tube and the output end of the adjustment module, the gate of the fifth MOS tube is connected to the gate of the sixth MOS tube, the drain of the fifth MOS tube is connected to the reference current source, and the drain of the fifth MOS tube is short-circuited with the gate of the fifth MOS tube; the source of the sixth MOS tube is connected to the output end of the adjustment module, and the drain of the sixth MOS tube is connected to the input end of the control module and the light-emitting element, wherein the voltage margin value of the sixth MOS tube is the target voltage difference value.

10. The circuit according to claim 9, characterized in that The channel width-to-length ratio of the fifth MOS transistor and the sixth MOS transistor is 1:

1.

11. The circuit according to claim 9, characterized in that The control module includes a first comparator, a second comparator, an adjustable current source, a first resistor, a second resistor, a third resistor and a filter, wherein: The first end of the first resistor is connected to the output end of the power supply voltage, and the second end of the first resistor is connected to the first end of the second resistor and the positive input end of the second comparator; the first end of the second resistor is connected to the positive input end of the second comparator, and the second end of the second resistor is grounded; the negative input end of the second comparator is short-circuited with the output end of the second comparator, and the output end of the second comparator is connected to the first end of the third resistor; the second end of the third resistor is connected to the negative input end of the first comparator and the adjustable current source; the negative input end of the first comparator is connected to the second end of the third resistor and the adjustable current source, the positive input end of the first comparator is connected to the drain of the sixth MOS tube, and the output end of the first comparator is connected to the input end of the filter; the output end of the filter is connected to the input end of the clock pulse generator, and the control end of the filter is connected to the adjustable current source, wherein the first threshold is the product of the third resistor and the adjustable current source, and the resistance values ​​of the first resistor and the second resistor are equal.

12. The circuit according to claim 11, characterized in that When the first comparator determines that the first difference is greater than the first threshold value, the first comparison result is sent to the filter, and the filter sends the first control signal to the clock pulse generator based on the first comparison result to control the first MOS transistor and the fourth MOS transistor to be in a cross-closed and disconnected state with the second MOS transistor and the third MOS transistor; When the first comparator determines a second comparison result that the first difference is less than or equal to the first threshold, the second comparison result is sent to the filter, and the filter sends the first control signal to the clock pulse generator based on the second comparison result to control the first MOS tube and the second MOS tube to be in a closed state, and the third MOS tube and the fourth MOS tube to be in a disconnected state.

13. The circuit according to claim 11, characterized in that The detection module includes an amplifier, a third comparator, a fourth resistor and a fifth resistor, wherein: The first end of the fourth resistor is connected to the output end of the power supply voltage, and the second end of the fourth resistor is connected to the first end of the fifth resistor and the negative input end of the third comparator; the first end of the fifth resistor is connected to the negative input end of the third comparator, and the second end of the fifth resistor is grounded; the negative input end of the third comparator is connected to a comparison voltage source, and the output end of the third comparator is connected to the input end of the clock pulse generator; the negative input end of the amplifier is connected to a reference voltage, the positive input end of the amplifier is connected to the output end of the adjustment module, and the output end of the amplifier is connected to the gate of the first MOS tube, wherein the target voltage is equal to the reference voltage.

14. The circuit according to claim 13, characterized in that When the third comparator detects that the voltage at the negative input terminal of the third comparator is not equal to the voltage at the positive input terminal of the third comparator, it determines that the supply voltage is greater than the preset target voltage threshold, and sends a second control signal to the clock pulse generator to control the third MOS tube and the fourth MOS tube to be in an open state, the second MOS tube to be in a closed state, and controls the first MOS tube to be connected to the output terminal of the amplifier; at the same time, The amplifier adjusts the gate voltage of the first MOS transistor based on the voltage difference between the output voltage of the adjustment module and the comparison voltage source so that the source voltage of the first MOS transistor is adjusted to the target voltage.

15. A chip, characterized in that: The chip has the circuit according to any one of claims 1 to 14 formed therein.

16. An electronic device, characterized in that: The electronic device comprises a chip in which the circuit according to any one of claims 1 to 14 is formed.

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