A parallel LED system, control method and LED module

Abstract

The present application belongs to the field of LED technology, and discloses a parallel LED system, a control method and an LED module. The parallel LED system includes a main control module, a carrier modulation module, a power carrier bus and at least one LED module; the main control module is used to generate an LED control signal according to the driving data of the LED module and the corresponding preset address; the carrier modulation module is used to modulate the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and send the differential signal to the LED module through the power carrier bus; the LED module is used to filter and decode the differential signal after receiving the differential signal through the power carrier bus, and control the lighting of the lamp beads according to the driving data obtained by decoding. The present application can greatly reduce the signal distortion that is easy to occur when data transmission is carried out in the case of a long light string, and at the same time improve the applicability and flexibility of the present application.

Description

Technical Field

[0001] The present application relates to the field of LED technology, and in particular to a parallel LED system, a control method and an LED module. Background Art

[0002] Power carrier communication refers to the technology of using existing power lines to transmit analog or digital signals at high speed through carrier waves. It does not require the laying of additional communication lines and directly uses existing power line resources for data transmission, thereby greatly reducing communication costs. Compared with other communication methods, it has great advantages and therefore has many applications in the LED field.

[0003] However, when using power carrier technology to transmit digital signals, the parasitic capacitance in the power line will affect the square wave in the digital signal. Especially when there are a large number of LED lamp beads and a long power line, the square wave distortion of the digital signal can easily lead to decoding errors of the LED lamp beads, resulting in display errors of the lamp beads at the back end of the light string. Summary of the invention

[0004] The present application provides a parallel LED system, a control method and an LED module, which can greatly reduce the signal distortion that is easy to occur during data transmission when the light string is long, and at the same time improve the applicability and flexibility of the present application.

[0005] In a first aspect, an embodiment of the present application provides a parallel LED system, comprising:

[0006] A main control module, a carrier modulation module, a power carrier bus and at least one LED module;

[0007] The main control module is used to generate LED control signals according to the driving data of the LED module and the corresponding preset address;

[0008] The carrier modulation module is used to modulate the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and send the differential signal to the LED module through the power carrier bus;

[0009] The LED module is used to filter and decode the differential signal after receiving it through the power carrier bus, and control the lighting of the lamp beads according to the driving data obtained by decoding.

[0010] Furthermore, the LED module is specifically used to delay the differential signal by one symbol period to obtain a delayed signal; multiply the differential signal by the delayed signal to obtain an original signal; perform low-pass filtering on the original signal to obtain a digital signal; and use a counter and a reference clock to record the number of continuous clocks of each high level in the digital signal;

[0011] Determine a decoding threshold according to each continuous clock quantity; decode each continuous clock quantity according to the decoding threshold to obtain an initial relative code; perform XOR processing on the initial relative code to obtain driving data.

[0012] Furthermore, the LED module is also used to use a timer to obtain the low-level duration of the digital signal, and take 1 / n of the low-level duration as the period of the reference clock; wherein n is a positive integer and is greater than 2.

[0013] Furthermore, the LED module is specifically used to calculate the probability density distribution of the number of continuous clocks of each high level;

[0014] Obtain the first continuous clock number and the second continuous clock number with the greatest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean value and the second continuous clock number as the second mean value; otherwise, take the first continuous clock number as the second mean value and the second continuous clock number as the first mean value;

[0015] Calculate the average of the first mean and the second mean as the third mean;

[0016] The first mean is multiplied by 2 and then subtracted from the third mean to obtain a first decoding threshold; the third mean is used as a second decoding threshold; the second mean is multiplied by 2 and then subtracted from the third mean to obtain a third decoding threshold;

[0017] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

[0018] Further, the LED module is further used to calculate the variance of each continuous clock number less than the third mean value after obtaining the third mean value to obtain a first variance; calculate the variance of each continuous clock number greater than the third mean value to obtain a second variance;

[0019] Subtract the first variance from the first mean to obtain the first decoding threshold; use the third mean as the second decoding threshold; and add the second variance to the second mean to obtain the third decoding threshold.

[0020] Furthermore, the LED module is also used to obtain the differential signal and then use a Schmitt trigger to shape the differential signal.

[0021] Furthermore, the system also includes a plurality of decoupling capacitors;

[0022] One end of the decoupling capacitor is connected to the power carrier bus, and the other end is grounded.

[0023] In a second aspect, an embodiment of the present application provides an LED module, including:

[0024] Signal decoding unit, digital control unit and output driving unit;

[0025] The signal decoding unit is used to read the differential signal in the power carrier bus according to the preset address and reference voltage; filter and decode the differential signal to obtain the driving data and send it to the digital control unit;

[0026] The digital control unit is used to generate a PWM signal according to the driving data and send it to the output driving unit;

[0027] The output drive unit is used to control the lamp beads to light up according to the PWM signal when the power signal is at a high level.

[0028] Furthermore, the LED module also includes a power stabilizing unit; the power stabilizing unit is used to receive the power signal in the power carrier bus, generate an internal voltage based on the power signal, and output the internal voltage to the signal decoding unit and the digital control unit.

[0029] Further, the LED module also includes an internal clock unit;

[0030] The signal decoding unit is specifically used to delay the differential signal by one symbol period to obtain a delayed signal; multiply the differential signal by the delayed signal to obtain the original signal; perform low-pass filtering on the original signal to obtain a digital signal and send it to the internal clock unit; and receive the reference clock of the internal clock unit, use the counter and the reference clock to record the number of continuous clocks of each high level in the digital signal; determine a decoding threshold according to each continuous clock number; decode each continuous clock number according to the decoding threshold to obtain an initial relative code; perform XOR processing on the initial relative code to obtain driving data;

[0031] The internal clock unit is used to generate a reference clock according to the digital signal and send it to the signal decoding unit.

[0032] Furthermore, the internal clock unit is specifically used to use a timer to obtain the low level duration of the digital signal when the power signal is at a high level; 1 / n of the low level duration is taken as the period of the reference clock; wherein n is a positive integer and is greater than 2.

[0033] Furthermore, the signal decoding unit is specifically used to calculate the probability density distribution of the number of continuous clocks of each high level;

[0034] Obtain the first continuous clock number and the second continuous clock number with the greatest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean value and the second continuous clock number as the second mean value; otherwise, take the first continuous clock number as the second mean value and the second continuous clock number as the first mean value;

[0035] Calculate the average of the first mean and the second mean as a third mean;

[0036] The first mean is multiplied by 2 and then subtracted from the third mean to obtain a first decoding threshold; the third mean is used as a second decoding threshold; the second mean is multiplied by 2 and then subtracted from the third mean to obtain a third decoding threshold;

[0037] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

[0038] Furthermore, the signal decoding unit is also used to use a Schmitt trigger to shape the differential signal after obtaining the differential signal.

[0039] In a third aspect, an embodiment of the present application provides a parallel LED control method, comprising:

[0040] The main control module generates an LED control signal according to the driving data of the LED module and the corresponding preset address;

[0041] The carrier modulation module modulates the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and sends the differential signal to the LED module through the power carrier bus;

[0042] After receiving the differential signal through the power carrier bus, the LED module filters and decodes the differential signal, and controls the lighting of the lamp beads according to the driving data obtained by decoding.

[0043] Furthermore, after receiving the differential signal through the power carrier bus, the LED module filters and decodes the differential signal, including:

[0044] Delay the differential signal by one symbol period to obtain a delayed signal;

[0045] Multiply the differential signal by the delayed signal to obtain the original signal;

[0046] Perform low-pass filtering on the original signal to obtain a digital signal;

[0047] Record the number of continuous clocks of each high level in the digital signal according to the reference clock;

[0048] Determine a decoding threshold according to the number of each continuous clock;

[0049] Decode each continuous clock quantity according to a decoding threshold to obtain an initial relative code;

[0050] The initial relative code is XOR-ed to obtain the driving data.

[0051] Furthermore, the method also includes:

[0052] Get the duration of low level of digital signal;

[0053] Take 1 / n of the duration of the low level as the period of the reference clock; where n is a positive integer greater than 2.

[0054] Furthermore, the above-mentioned determining the decoding threshold according to the number of each continuous clock includes:

[0055] Calculate the probability density distribution of the number of continuous clocks at each high level;

[0056] Obtain the first continuous clock quantity and the second continuous clock quantity with the greatest occurrence probability;

[0057] Determining whether the first continuous clock quantity is less than the second continuous clock quantity;

[0058] If yes, the first continuous clock quantity is taken as the first mean value, and the second continuous clock quantity is taken as the second mean value;

[0059] If not, the first continuous clock quantity is taken as the second mean value, and the second continuous clock quantity is taken as the first mean value;

[0060] Calculate the average of the first mean and the second mean as the third mean;

[0061] Multiply the first mean by 2 and then subtract the third mean to obtain a first decoding threshold;

[0062] using the third mean as a second decoding threshold;

[0063] The second mean is multiplied by 2 and then subtracted from the third mean to obtain a third decoding threshold.

[0064] Furthermore, the above decoding of each continuous clock quantity according to the decoding threshold to obtain the initial relative code includes:

[0065] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code;

[0066] If the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is code 1;

[0067] If the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is the Reset code.

[0068] Furthermore, the method also includes:

[0069] After obtaining the differential signal, the LED module uses a Schmitt trigger to shape the differential signal.

[0070] In a fourth aspect, an embodiment of the present application provides an LED package, including:

[0071] Package body, internal base conductor, power line pin, ground line pin, control chip and LED lamp bead;

[0072] The package body is in a cubic shape, and a circular window is provided on the first surface, and the circular window is covered with a transparent material;

[0073] The internal base conductor is arranged inside the package body, on a second surface corresponding to the first surface;

[0074] The power line pin is embedded in the third surface of the package body, and the ground line pin is embedded in the fourth surface of the package body;

[0075] The third surface and the fourth surface correspond to each other;

[0076] The power line pin and the ground line pin are connected through a metal wire and an internal base conductor;

[0077] The control chip and LED lamp beads are arranged on the internal base conductor;

[0078] The control chip, LED lamp beads and internal base conductors are connected through packaging wires.

[0079] In summary, compared with the prior art, the technical solution provided in the embodiment of the present application has at least the following beneficial effects:

[0080] A parallel LED system is provided in an embodiment of the present application. In the parallel LED system, a main control module generates an LED control signal according to a preset address and driving data of the LED module, and a carrier modulation module modulates the LED control signal into a differential signal based on a reference voltage, and sends the signal to a power carrier bus. Correspondingly, in the LED module, a single-ended signal is converted into a differential signal based on a reference voltage, thereby reducing errors in the signal including noise, distortion, offset, and offset offset, and effectively improving the accuracy and noise performance of the signal, especially in the control of long light strings. At the same time, since the conversion of the differential signal is controlled by the reference voltage, the driving signal can operate within a wider voltage range, that is, the present application is applicable to different power supply voltages and signal levels on the power carrier bus, greatly improving the applicability and flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 A structural diagram of a parallel LED system provided as an exemplary embodiment of the present application.

[0082] Figure 2 A schematic diagram of the level and initial relative code of a digital signal provided for an exemplary embodiment of the present application.

[0083] Figure 3 A structural diagram of a parallel LED system provided for yet another exemplary embodiment of the present application.

[0084] Figure 4 An internal structure diagram of an LED module provided as an exemplary embodiment of the present application.

[0085] Figure 5 A flowchart of a parallel LED control method provided by an exemplary embodiment of the present application.

[0086] Figure 6 A top view of an LED package provided according to an exemplary embodiment of the present application.

[0087] Figure 7 A side view of an LED package provided according to an exemplary embodiment of the present application.

[0088] Figure 8 A top view of an LED package provided according to yet another exemplary embodiment of the present application.

[0089] Fig. 9 A three-dimensional diagram of an LED package provided according to an exemplary embodiment of the present application.

[0090] Fig.10 A schematic diagram of a through-hole LED package provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0091] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0092] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0093] See also Figure 1 , an embodiment of the present application provides a parallel LED system, comprising:

[0094] A main control module, a carrier modulation module, a power carrier bus and at least one LED module.

[0095] Specifically, the main control module is connected to the carrier modulation module; when there are multiple LED modules, the LED modules are connected in parallel through the power carrier bus, and the input end of the power carrier bus is connected to the output end of the carrier modulation module.

[0096] The main control module is used to generate an LED control signal according to the driving data of the LED module and the corresponding preset address.

[0097] The carrier modulation module is used to modulate the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and send the differential signal to the LED module through the power carrier bus.

[0098] Specifically, the carrier modulation module first needs to differentially encode the LED control signal, and then combine the encoded difference and the reference voltage and send them to the power carrier bus, so that after the LED module reads its own target signal in the power carrier bus according to the preset address, it can obtain a differential signal by subtracting the target signal from the reference voltage.

[0099] The LED module is used to filter and decode the differential signal after receiving it through the power carrier bus, and control the lighting of the lamp beads according to the driving data obtained by decoding.

[0100] The reference voltage may be a ground voltage of each LED module.

[0101] In theory, digital differential signals usually require two wires for transmission, one wire in each pair of wires is used to transmit a positive voltage level, and the other wire is used to transmit a negative voltage level, and the voltage difference is used to represent the logical state of the signal. However, the parallel LED system of the present application is a power carrier transmission, that is, there is only one power carrier bus, and it is impossible to directly use the existing differential signal transmission method to improve the anti-interference ability of the signal; for this reason, the present application adds a differential driver to the LED module to convert the single-ended signal into a differential signal, but this still requires a reference voltage to convert the single-ended signal into a differential signal relative to the reference voltage. At this time, it is easy to think of using the voltage of the power signal in the power carrier bus as a reference voltage, but in actual work, if there is a line resistance in the power carrier bus, then the voltage of the power signal will tend to weaken with distance; therefore, the present application preferably uses a stable ground voltage as a reference voltage. Although the differential signal of the present application is not a true differential signal, it still has a certain anti-interference ability compared to directly using a single-ended signal for data transmission.

[0102] At the same time, since the differential signal is obtained by processing the reference voltage, this means that the voltage range that can be used by the power carrier bus is wider, because only the reference voltage needs to be adjusted to ensure that the amplitude of the differential signal remains unchanged. Therefore, the single-ended to differential operation of the present application can also indirectly broaden the operating voltage range of the power carrier bus and improve flexibility.

[0103] The above-mentioned embodiment provides a parallel LED system, in which the main control module generates an LED control signal according to the preset address and driving data of the LED module, and the carrier modulation module modulates the LED control signal into a differential signal based on the reference voltage, and sends it to the power carrier bus; correspondingly, in the LED module, the operation of converting a single-ended signal to a differential signal is implemented based on the reference voltage, thereby reducing errors in the signal including noise, distortion, offset and offset offset, especially in the control of long light strings, effectively improving the accuracy and noise performance of the signal; at the same time, since the conversion of the differential signal is controlled by the reference voltage, the driving signal can operate within a wider voltage range, that is, the present application is applicable to different power supply voltages and signal levels on the power carrier bus, which greatly improves the applicability and flexibility.

[0104] In some embodiments, the LED module is specifically used to delay the differential signal by one symbol period to obtain a delayed signal; multiply the differential signal by the delayed signal to obtain the original signal; perform low-pass filtering on the original signal to obtain a digital signal; use a counter and a reference clock to record the number of continuous clocks of each high level in the digital signal; determine a decoding threshold according to each continuous clock number; decode each continuous clock number according to the decoding threshold to obtain an initial relative code; perform XOR processing on the initial relative code to obtain driving data. Wherein, the symbol period is the duration of a low level or a high level.

[0105] Specifically, the present application multiplies the differential signal and the delayed signal point by point, utilizing the characteristics of differential coding, that is, the differential relationship between the current code element and the previous code element to obtain the original signal; however, since the result after multiplication usually contains high-frequency components, it is necessary to filter out these high-frequency components through a low-pass filter, and the digital signal obtained after filtering is the LED control signal of the LED module output by the main control module, so the driving data can be obtained by decoding the digital signal.

[0106] See also Figure 2 When decoding a digital signal, the different durations of the high level in the digital signal represent code 0, code 1, and reset code, respectively. Therefore, it is necessary to decode by identifying the duration of the high level.

[0107] Please see the table below. The current conventional decoding method is to use analog OSC to generate a reference clock, use the reference clock to sample the digital signal, and use the counter and sampling value to obtain the number of continuous clocks for each low level and the number of continuous clocks for the high level. The counter is reset every time a low level is detected to last for A clocks; the low level is maintained for a short time (such as 10us), which only plays a filtering role to prevent misjudgment due to fluctuations. When the high level lasts for more than X clocks and less than Y clocks, it is judged as 0 code; when the high level lasts for more than Y clocks and less than Z clocks, it is judged as 1 code; when the high level lasts for more than Z clocks, it is judged as a reset code. The above reference clock, A, X, Y and Z are all set manually.

[0108]

[0109] However, this decoding method also limits the encoding method of the driving data by the main control module, that is, when encoding the driving data, the main control module must also encode according to the settings of the parameters such as A and X in each LED module, which greatly reduces the flexibility; and when the manually set A, X, Y, and Z cannot adapt to the interference changes that the digital signal may receive, for example, if the duration of the high level is uniformly increased due to interference, then it may cause the 1 code to be mistakenly judged as a reset code, and the 0 code to be mistakenly judged as a 1 code.

[0110] Therefore, the present application calculates the decoding threshold according to the number of continuous clocks of each high level obtained by sampling, which can not only avoid the inapplicability of the artificially preset threshold caused by signal interference, but also greatly improve the coding flexibility of the main control module.

[0111] After decoding to obtain the initial relative code, it is necessary to perform XOR processing on each initial relative code in pairs to obtain the absolute code.

[0112] For example, if the previous code element of the current initial relative code is 0 and the current initial relative code is 1, the corresponding absolute code is also 1; if the previous code element of the current initial relative code is 1 and the current initial relative code is 1, the corresponding absolute code is 0, thereby obtaining driving data composed of various absolute codes; wherein the number of absolute codes in the driving data is half of the initial relative code.

[0113] In some embodiments, the LED module is also used to use a timer to obtain the low level duration of the digital signal, and take 1 / n of the low level duration as the period of the reference clock; where n is a positive integer and greater than 2.

[0114] In the digital signal of the present application, the low level is used to reset the number of continuous clocks of the high level recorded by the counter, so the width of the low level must be smaller than the minimum high level width; and based on the Nyquist sampling theorem, the sampling frequency should be at least twice the highest frequency component of the signal. Therefore, the present application sets n to be a positive integer greater than 2, which can ensure that the number of continuous clocks of the low level must be greater than 2, that is, when the number of low level clocks is greater than n, the counter resets the clock count of the high level.

[0115] Similarly, since the duration of the high level is greater than that of the low level, the number of high-level continuous clocks must be greater than n, indicating that the number of high-level continuous clocks of different codes can have obvious differences, which facilitates threshold judgment.

[0116] The above embodiment generates a reference clock based on the duration of the low level, realizes adaptive decoding of the power carrier, and enables the main control module to freely change the duration rule for encoding the drive data.

[0117] For example, during this encoding, the high-level duration of code 0 is 15us, and the high-level duration of code 1 is 25us. During the next encoding, the high-level durations of code 0 and code 1 can be uniformly increased by 10us. When the encoding duration rule of the main control module changes, there is no need to manually modify the decoding threshold used for decoding in each LED module, which greatly improves the flexibility. At the same time, it can also avoid changes in the duration of the high level in the digital signal caused by interference, which helps to improve the decoding accuracy.

[0118] In some embodiments, the LED module is specifically used to calculate the probability density distribution of the number of continuous clocks of each high level; obtain the first continuous clock number and the second continuous clock number with the highest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean and the second continuous clock number as the second mean; otherwise, take the first continuous clock number as the second mean and the second continuous clock number as the first mean; calculate the average of the first mean and the second mean as the third mean; multiply the first mean by 2 and then subtract the third mean to obtain the first decoding threshold; use the third mean as the second decoding threshold; multiply the second mean by 2 and then subtract the third mean to obtain the third decoding threshold.

[0119] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

[0120] Specifically, the reason why the present application sorts the number of continuous clocks is based on the difference in the number of 0 codes, 1 codes and reset codes in the digital signal, that is, no matter what the content of the driving data is, the encoded reset code is always much less than the number of 0 codes and 1 codes, so through the analysis of the probability of occurrence, it can be determined that the number of continuous clocks with the top two occurrence probabilities must correspond to 0 codes and 1 codes; next, according to the judgment criteria of the above table, it can be seen that the number of continuous clocks of 0 code is less than 1 code, so among the two continuous clock numbers with the top two occurrence probabilities, the smaller number of continuous clocks corresponds to 0 code, and its value must be between X and Y, which is referred to as the first mean in the present application, and the larger number of continuous clocks corresponds to 1 code, and its value must be between Y and Z, which is referred to as the second mean in the present application. At this time, the average of the first mean and the second mean, that is, the third mean, can be regarded as the overlapping part of the two intervals, the second decoding threshold Y.

[0121] Then, after determining the second decoding threshold Y, the first mean is used as the median of the first decoding threshold X and the second decoding threshold Y to obtain the first decoding threshold X; similarly, the second mean is used as the median of the second decoding threshold Y and the third decoding threshold Z to obtain the third decoding threshold Z; finally, the initial relative code is decoded according to the obtained X, Y, and Z.

[0122] The above embodiment calculates the decoding threshold based on the number of different continuous clocks of high level, realizes adaptive decoding of power carrier transmission, greatly reduces the manpower burden, and improves the flexibility and anti-interference performance of the present application.

[0123] Furthermore, in addition to the above-mentioned method of calculating the three decoding thresholds, the LED module can also be used to calculate the variance of each continuous clock number less than the third mean after obtaining the third mean to obtain a first variance; calculate the variance of each continuous clock number greater than the third mean to obtain a second variance; subtract the first variance from the first mean to obtain a first decoding threshold; use the third mean as the second decoding threshold; add the second variance to the second mean to obtain a third decoding threshold.

[0124] Specifically, if the first mean and the second mean are directly used as the median to calculate the upper and lower limits of the threshold range, the accuracy may be relatively poor, because the first mean and the second mean are actually the mode rather than the median of the number of continuous clocks corresponding to 0 code and 1 code. Therefore, although the calculation method of treating it as the median can also roughly determine the range of the decoding threshold, the accuracy is not very good.

[0125] In this embodiment, the present application determines the span range of the number of continuous clocks of code 0 and the span range of the number of continuous clocks of code 1 by variance calculation, so that the determination of the first decoding threshold and the third decoding threshold is more accurate.

[0126] Furthermore, the LED module is also used to obtain the differential signal and then use a Schmitt trigger to shape the differential signal.

[0127] Since the delayed signal needs to be obtained based on the code element period of the differential signal, it is necessary to ensure that the wavelength of the differential signal is stable and clear as much as possible. Therefore, after obtaining the differential signal, the present application shapes the differential signal based on the Schmitt trigger to ensure the accuracy of the code element period and the delayed signal, thereby providing a good foundation for subsequent digital signal decoding.

[0128] See also Figure 3 In some embodiments, the system further includes a plurality of decoupling capacitors.

[0129] One end of the decoupling capacitor is connected to the power carrier bus, and the other end is grounded.

[0130] Specifically, the decoupling capacitor does not necessarily have to be set between two LED modules. A decoupling capacitor can be set every certain number of LED modules. Or, taking into account that the parasitic capacitance will gradually increase with the length of the light string, the number of LED modules between the decoupling capacitors can be gradually reduced. For example, the number of LED modules between the first decoupling capacitor and the second decoupling capacitor is 10, the number of LED modules between the second decoupling capacitor and the third decoupling capacitor is 9, and so on. When the number of LED modules between the two decoupling capacitors is reduced to 3 or 5, the reduction can be stopped.

[0131] See also Figure 4 Another embodiment of the present application provides an LED module, comprising:

[0132] Signal decoding unit, digital control unit and output driving unit.

[0133] The signal decoding unit is used to read the differential signal in the power carrier bus according to the preset address and reference voltage; filter and decode the differential signal, obtain the driving data and send it to the digital control unit.

[0134] The signal decoding unit is provided with a differential driver, which converts the target signal read according to the preset address into a differential signal based on the reference voltage, and then sends it to the decoding circuit to obtain driving data.

[0135] The digital control unit is used to generate a PWM signal according to the driving data and send it to the output driving unit.

[0136] Among them, 0 and 1 in the driving data constitute the low level and high level of the PWM signal.

[0137] The output drive unit is used to control the lamp beads to light up according to the PWM signal when the power signal is at a high level.

[0138] The output drive unit is directly powered by the power signal in the power carrier bus. When the power signal is at a high level (for example, greater than 3V), the output drive unit controls the lamp beads to light up, otherwise the lamp beads of the LED module will not light up.

[0139] In some embodiments, the LED module further includes a power stabilizing unit.

[0140] The power supply voltage stabilizing unit is used to receive the power signal in the power carrier bus, generate an internal voltage based on the power signal, and output the internal voltage to the signal decoding unit and the digital control unit.

[0141] Specifically, the power supply voltage stabilization unit is used to receive the power signal in the power carrier bus, and keep the internal voltage at a high value for a period of time when the VDD power supply is pulled low, mainly used to maintain the state of the signal decoding unit and the digital control unit, and the output is marked as DVDD. When the power supply is high (for example, greater than 3V), the signal decoding unit works normally and the LED lights up normally; when the power supply is low (for example, less than 1.5V), the signal decoding unit stops working and the LED does not light up.

[0142] In some embodiments, the LED module further comprises an internal clock unit.

[0143] The signal decoding unit is specifically used to delay the differential signal by one code element period after obtaining the differential signal to obtain a delayed signal; multiply the differential signal by the delayed signal to obtain the original signal; perform low-pass filtering on the original signal to obtain a digital signal and send it to the internal clock unit; and receive the reference clock of the internal clock unit, use the counter and the reference clock to record the number of continuous clocks of each high level in the digital signal; determine the decoding threshold according to each continuous clock number; decode each continuous clock number according to the decoding threshold to obtain an initial relative code; perform XOR processing on the initial relative code to obtain driving data.

[0144] The internal clock unit is used to generate a reference clock according to the digital signal and send it to the signal decoding unit.

[0145] Among them, the internal clock unit is specifically used to use a timer to obtain the low level duration of the digital signal when the power signal is at a high level; 1 / n of the low level duration is taken as the period of the reference clock; wherein n is a positive integer and is greater than 2.

[0146] The internal clock unit is powered directly by the power signal in the power carrier bus. When the power signal is high, the reference clock CLK is output for the signal decoding unit to decode the driving data. When the power signal is low, the reference clock is stopped from being output.

[0147] In some embodiments, the signal decoding unit is specifically used to calculate the probability density distribution of the number of continuous clocks of each high level; obtain the first continuous clock number and the second continuous clock number with the highest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean and the second continuous clock number as the second mean; otherwise, take the first continuous clock number as the second mean and the second continuous clock number as the first mean; calculate the average of the first mean and the second mean as the third mean; multiply the first mean by 2 and then subtract the third mean to obtain the first decoding threshold; use the third mean as the second decoding threshold; multiply the second mean by 2 and then subtract the third mean to obtain the third decoding threshold.

[0148] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

[0149] The above embodiment enables the signal decoding unit to calculate the decoding threshold based on the number of different continuous clocks of the high level, thereby realizing adaptive decoding of power carrier transmission, greatly reducing the manpower burden, and improving the flexibility and anti-interference performance of the present application.

[0150] In some embodiments, the signal decoding unit is further configured to use a Schmitt trigger to shape the differential signal after obtaining the differential signal. Specifically, a Schmitt trigger is provided between the differential driver and the decoding circuit of the signal decoding unit, and the differential signal is shaped based on the Schmitt trigger to ensure the accuracy of the symbol period and the delayed signal.

[0151] See also Figure 5 , the embodiment of the present application provides a parallel LED control method, comprising:

[0152] Step S1, the main control module generates an LED control signal according to the driving data of the LED module and the corresponding preset address.

[0153] Step S2: the carrier modulation module modulates the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and sends the differential signal to the LED module through the power carrier bus.

[0154] Step S3, after receiving the differential signal through the power carrier bus, the LED module filters and decodes the differential signal, and controls the lamp beads to light up according to the driving data obtained by decoding.

[0155] In some embodiments, after receiving the differential signal through the power carrier bus, the LED module filters and decodes the differential signal, specifically including the following steps:

[0156] Step S31, delaying the differential signal by one symbol period to obtain a delayed signal.

[0157] Step S32, multiplying the differential signal and the delayed signal to obtain the original signal.

[0158] Step S33, low-pass filtering the original signal to obtain a digital signal.

[0159] Step S34, recording the number of continuous clocks of each high level in the digital signal according to the reference clock.

[0160] Specifically, a reference clock is used to sample a digital signal, and when a certain number of low levels are sampled, the number of continuous clocks of the high level is reset, and the counting starts again when a high level is sampled next time.

[0161] Step S35, determining a decoding threshold according to the number of each continuous clock.

[0162] Step S36, decoding each continuous clock quantity according to the decoding threshold to obtain an initial relative code.

[0163] Step S37, performing XOR processing on the initial relative code to obtain driving data.

[0164] Specifically, the XOR processing is to perform XOR logic operations on the initial relative codes in pairs, and the obtained absolute codes constitute the driving data.

[0165] The above embodiment calculates the decoding threshold according to the number of continuous clocks of each high level obtained by sampling, which can not only avoid the inapplicability of the artificially preset threshold caused by signal interference, but also greatly improve the encoding flexibility of the main control module.

[0166] In some embodiments, the method further comprises:

[0167] Step S341, obtaining the duration of the low level of the digital signal.

[0168] Step S342, taking 1 / n of the duration of the low level as the period of the reference clock; wherein n is a positive integer greater than 2.

[0169] The above embodiment generates a reference clock based on the duration of the low level, realizes adaptive decoding of the power carrier, and enables the main control module to freely change the duration rule for encoding the drive data.

[0170] In some embodiments, determining the decoding threshold according to the number of continuous clocks includes:

[0171] Step S351, calculating the probability density distribution of the number of continuous clocks at each high level.

[0172] Step S352, obtaining the first continuous clock quantity and the second continuous clock quantity with the greatest occurrence probability.

[0173] Step S353, determine whether the first continuous clock number is less than the second continuous clock number; if so, take the first continuous clock number as the first mean value and the second continuous clock number as the second mean value; if not, take the first continuous clock number as the second mean value and the second continuous clock number as the first mean value.

[0174] Specifically, since the encoded reset code is always much less than the number of 0 codes and 1 codes, it can be determined through the analysis of the occurrence probability that the two continuous clock numbers with the top two occurrence probabilities must correspond to 0 codes and 1 codes; it is known that the continuous clock number of 0 code is less than 1 code, so among the two continuous clock numbers with the top two occurrence probabilities, the smaller continuous clock number corresponds to 0 code, and its value must be between X and Y, which is referred to as the first mean in this application, and the larger continuous clock number corresponds to 1 code, and its value must be between Y and Z, which is referred to as the second mean in this application.

[0175] Step S354, calculating the average of the first mean and the second mean as the third mean.

[0176] Step S355: multiply the first mean by 2 and then subtract the third mean to obtain a first decoding threshold.

[0177] Step S356: Use the third mean as the second decoding threshold.

[0178] Step S357, multiply the second mean by 2 and then subtract the third mean to obtain a third decoding threshold.

[0179] Furthermore, the above decoding of each continuous clock quantity according to the decoding threshold to obtain the initial relative code includes:

[0180] If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code.

[0181] If the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code.

[0182] If the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is the Reset code.

[0183] Among them, the Reset code is a reset code, and the reset code does not participate in the XOR calculation. When performing the XOR operation, if the reset code is encountered, the next 0 or 1 code is directly skipped and the reset code is directly retained in the drive data.

[0184] The above embodiment calculates the decoding threshold based on the number of different continuous clocks of high level, realizes adaptive decoding of power carrier transmission, greatly reduces the manpower burden, and improves the flexibility and anti-interference performance of the present application.

[0185] Furthermore, the method also includes:

[0186] After obtaining the differential signal, the LED module uses a Schmitt trigger to shape the differential signal.

[0187] See also Figure 6 , Figure 7 , Figure 8 and Fig. 9 The embodiment of the present application also provides an LED package, including a package body 10, an internal base conductor 17, a power line pin 12, a ground line pin 13, a control chip 01 and an LED lamp bead 11.

[0188] The package body 10 is in a cubic shape, and a circular window 14 is provided on a first surface thereof. The circular window 14 is covered with a transparent material.

[0189] The internal base conductor 17 is disposed inside the package body, on a second surface corresponding to the first surface.

[0190] The power line pins 12 are embedded in the third surface of the package body, and the ground line pins 13 are embedded in the fourth surface of the package body.

[0191] The third surface and the fourth surface correspond to each other.

[0192] Specifically, Fig. 9 As shown, the height of the package body 10 is much smaller than the length and width, the first surface and the second surface are opposite to each other consisting of the long side and the wide side, and the third surface and the fourth surface are opposite to each other consisting of the long side and the high side.

[0193] The power line pin 12 may include one or two VDD pins for connecting to the power carrier bus; the ground line pin 13 may include one or two GND pins (VSS pins) for grounding. Fig.10 As shown, when the power line pin 12 and the ground line pin 13 are both one, the power line pin 12 is longer than the ground line pin 13 to facilitate identification during networking.

[0194] The power line pin 12 and the ground line pin 13 are connected through a metal wire 16 and an internal base conductor 17 .

[0195] The control chip 01 and the LED lamp bead 11 are arranged on the internal base conductor 17 .

[0196] The control chip 01 , the LED lamp bead 11 and the internal base conductor 17 are connected through the packaging wire 15 .

[0197] The LED lamp beads 11 include lamp beads of three colors: red, green and blue.

[0198] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0199] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A parallel LED system, characterized in that: include: A main control module, a carrier modulation module, a power carrier bus and at least one LED module; The main control module is used to generate an LED control signal according to the driving data of the LED module and the corresponding preset address; The carrier modulation module is used to modulate the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and send the differential signal to the LED module through the power carrier bus; The LED module is used to filter and decode the differential signal after receiving it through the power carrier bus, and control the lighting of the lamp beads according to the driving data obtained by decoding; the LED module is specifically used to delay the differential signal by one code element period to obtain a delayed signal; multiply the differential signal by the delayed signal to obtain the original signal; low-pass filter the original signal to obtain a digital signal; use a counter and a reference clock to record the number of continuous clocks of each high level in the digital signal; determine a decoding threshold according to each continuous clock number; decode each continuous clock number according to the decoding threshold to obtain an initial relative code; perform XOR processing on the initial relative code to obtain the driving data.

2. The parallel LED system according to claim 1, characterized in that: The LED module is also used to use a timer to obtain the low level duration of the digital signal, and take 1 / n of the low level duration as the period of the reference clock; wherein n is a positive integer and is greater than 2.

3. The parallel LED system according to claim 1, characterized in that: The LED module is specifically used to calculate the probability density distribution of the number of continuous clocks of each high level; obtain the first continuous clock number and the second continuous clock number with the highest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean and the second continuous clock number as the second mean; otherwise, take the first continuous clock number as the second mean and the second continuous clock number as the first mean; Calculate the average of the first mean and the second mean as a third mean; The first mean value is multiplied by 2 and then subtracted from the third mean value to obtain a first decoding threshold value; the third mean value is used as a second decoding threshold value; the second mean value is multiplied by 2 and then subtracted from the third mean value to obtain a third decoding threshold value; If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

4. The parallel LED system according to claim 3, characterized in that: The LED module is further used to calculate the variance of each continuous clock number less than the third mean value after obtaining the third mean value to obtain a first variance; calculate the variance of each continuous clock number greater than the third mean value to obtain a second variance; Subtracting the first variance from the first mean to obtain a first decoding threshold; using the third mean as a second decoding threshold; Add the second mean value to the second variance to obtain a third decoding threshold.

5. The parallel LED system according to claim 1, characterized in that: The LED module is also used to shape the differential signal using a Schmitt trigger after obtaining the differential signal.

6. The parallel LED system according to claim 1, characterized in that: It also includes a plurality of decoupling capacitors; one end of the decoupling capacitor is connected to the power carrier bus, and the other end is grounded.

7. An LED module, characterized in that: It includes a signal decoding unit, a digital control unit, an internal clock unit and an output driving unit; the signal decoding unit is used to read the differential signal in the power carrier bus according to the preset address and the reference voltage; filter and decode the differential signal to obtain the driving data and send it to the digital control unit; the signal decoding unit is specifically used to delay the differential signal by one symbol period to obtain the delayed signal; multiply the differential signal by the delayed signal to obtain the original signal; low-pass filter the original signal to obtain the digital signal and send it to the internal clock unit; and receive the reference clock of the internal clock unit, use the counter and the reference clock to record the number of continuous clocks of each high level in the digital signal; determine the decoding threshold according to each continuous clock number; decode each continuous clock number according to the decoding threshold to obtain the initial relative code; perform XOR processing on the initial relative code to obtain the driving data; The digital control unit is used to generate a PWM signal according to the driving data and send it to the output driving unit; The output drive unit is used to control the lamp beads to light up according to the PWM signal when the power signal is at a high level.

8. The LED module according to claim 7, characterized in that: Also includes a power supply voltage stabilization unit; The power supply voltage stabilizing unit is used to receive a power signal in a power carrier bus, generate an internal voltage based on the power signal, and output the internal voltage to the signal decoding unit and the digital control unit.

9. The LED module according to claim 8, characterized in that: The internal clock unit is specifically used to use a timer to obtain the low level duration of the digital signal when the power signal is at a high level; take 1 / n of the low level duration as the period of the reference clock; wherein n is a positive integer and is greater than 2.

10. The LED module according to claim 8, characterized in that: The signal decoding unit is specifically used to calculate the probability density distribution of the number of continuous clocks at each high level; Obtain the first continuous clock number and the second continuous clock number with the greatest probability of occurrence; if the first continuous clock number is less than the second continuous clock number, take the first continuous clock number as the first mean value and the second continuous clock number as the second mean value; otherwise, take the first continuous clock number as the second mean value and the second continuous clock number as the first mean value; Calculate the average of the first mean and the second mean as a third mean; The first mean value is multiplied by 2 and then subtracted from the third mean value to obtain a first decoding threshold value; the third mean value is used as a second decoding threshold value; the second mean value is multiplied by 2 and then subtracted from the third mean value to obtain a third decoding threshold value; If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; if the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is 1 code; if the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is Reset code.

11. The LED module according to claim 7, characterized in that: The signal decoding unit is further configured to use a Schmitt trigger to shape the differential signal after obtaining the differential signal.

12. A parallel LED control method, characterized in that: include: The main control module generates an LED control signal according to the driving data of the LED module and the corresponding preset address; The carrier modulation module modulates the LED control signal generated by the main control module according to the reference voltage to obtain a differential signal, and sends the differential signal to the LED module through the power carrier bus; After receiving the differential signal through the power carrier bus, the LED module filters and decodes the differential signal, and controls the lighting of the lamp beads according to the driving data obtained by decoding; specifically, the LED module delays the differential signal by one code element period to obtain a delayed signal; multiplies the differential signal by the delayed signal to obtain the original signal; low-pass filters the original signal to obtain a digital signal; records the number of continuous clocks of each high level in the digital signal according to the reference clock; determines a decoding threshold according to each continuous clock number; decodes each continuous clock number according to the decoding threshold to obtain an initial relative code; and performs XOR processing on the initial relative code to obtain the driving data.

13. The parallel LED control method according to claim 12, characterized in that: Also includes: Obtaining the duration of the low level of the digital signal; Take 1 / n of the duration of the low level as the period of the reference clock; where n is a positive integer and is greater than 2.

14. The parallel LED control method according to claim 12, characterized in that: The step of determining a decoding threshold according to each of the continuous clock quantities comprises: Calculate the probability density distribution of the number of continuous clocks at each high level; Obtain the first continuous clock quantity and the second continuous clock quantity with the greatest occurrence probability; Determining whether the first continuous clock quantity is less than the second continuous clock quantity; If yes, the first continuous clock quantity is taken as the first mean value, and the second continuous clock quantity is taken as the second mean value; If not, the first continuous clock quantity is taken as the second mean value, and the second continuous clock quantity is taken as the first mean value; Calculate the average of the first mean and the second mean as a third mean; Multiply the first mean by 2 and then subtract the third mean to obtain a first decoding threshold; Using the third mean as a second decoding threshold; The second mean is multiplied by 2 and then subtracted from the third mean to obtain a third decoding threshold.

15. The parallel LED control method according to claim 14, characterized in that: The step of decoding each continuous clock quantity according to the decoding threshold to obtain an initial relative code includes: If the number of continuous clocks is greater than the first decoding threshold and less than the second decoding threshold, the corresponding initial relative code is 0 code; If the number of continuous clocks is greater than the second decoding threshold and less than the third decoding threshold, the corresponding initial relative code is code 1; If the number of continuous clocks is greater than the third decoding threshold, the corresponding initial relative code is the Reset code.

16. The parallel LED control method according to claim 12, characterized in that: Also includes: After obtaining the differential signal, the LED module uses a Schmitt trigger to shape the differential signal.

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