Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate; the word lines penetrate through the different layers and extend in the direction perpendicular to the substrate; the first insulating layers and the first conducting layers are sequentially and alternately distributed from bottom to top in the direction perpendicular to the substrate; the through hole penetrates through each first insulating layer and each first conducting layer, the word line is arranged in the through hole, and the orthographic projection of a second sub-hole, located on the first conducting layer, of the through hole on the substrate is located in the orthographic projection of a first sub-hole, located on the first insulating layer, of the through hole on the substrate; the transistor comprises a semiconductor layer surrounding the side wall of the word line; the plurality of semiconductor layers of the plurality of transistors are arranged at intervals. According to the scheme provided by the embodiment of the invention, the interlayer semiconductor layer is removed, a parasitic transistor is eliminated, and leakage current is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which eliminate parasitic transistors.

[0007] The present disclosure provides a semiconductor device, including:

[0008] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0009] A word line, extending through the different layers in a direction perpendicular to the substrate;

[0010] A first insulating layer and a first conductive layer are alternately distributed from bottom to top in a direction perpendicular to the substrate; a through hole penetrating each of the first insulating layers and each of the first conductive layers, the word line is arranged in the through hole, and the orthographic projection of the second sub-hole of the through hole located in the first conductive layer on the substrate falls within the orthographic projection of the first sub-hole of the through hole located in the first insulating layer on the substrate;

[0011] The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the first electrode and the second electrode are arranged on the first conductive layer;

[0012] The plurality of semiconductor layers of the plurality of transistors are arranged at intervals, and the plurality of semiconductor layers are distributed in different regions of the sidewall of the word line.

[0013] In some embodiments, the through hole is sequentially distributed from inside to outside with the word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers extending in a direction perpendicular to the substrate at different regions surrounding the sidewall of the gate insulating layer;

[0014] The sidewalls of the through hole include a first sidewall located in the first sub-hole and a second sidewall located in the second sub-hole connected to the first sidewall, the first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending in a direction perpendicular to the substrate, the semiconductor layer extends continuously on the second sidewall and extends continuously from the second sidewall to the sub-sidewall of the groove extending in a direction perpendicular to the substrate, and is not distributed on the sub-sidewall so that the multiple semiconductor layers are disconnected at the sub-sidewall.

[0015] In some embodiments, the semiconductor layer is connected to the sidewalls of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode.

[0016] In some embodiments, the first insulating layer only exposes the sidewall in the through hole, and the first conductive layer exposes the sidewall and partial areas of the upper and lower surfaces in the through hole;

[0017] The semiconductor layer is at least distributed on the side wall of the first conductive layer.

[0018] In some embodiments, the semiconductor layer is also distributed on upper and lower surfaces of the first conductive layer exposed in the through hole and is not distributed on a side wall of the first insulating layer.

[0019] In some embodiments, the semiconductor layer includes a first sidewall and a second sidewall disposed opposite to each other along a first direction, wherein the first direction is perpendicular to an extension direction of the substrate and the first electrode;

[0020] The through hole further includes a barrier layer disposed on a side of the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line.

[0021] In some embodiments, the barrier layers on surfaces of different semiconductor layers are spaced apart from each other.

[0022] In some embodiments, the barrier layer is not distributed on the sidewall of the first insulating layer exposed in the through hole, and is not distributed on the sidewall, the upper surface, and the lower surface of the first conductive layer exposed in the through hole.

[0023] In some embodiments, gate insulation layers of multiple transistors at different layers are connected to form an integrated structure.

[0024] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0025] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor includes a first electrode and a second electrode, and the method for manufacturing the semiconductor device includes:

[0026] Providing a substrate, on which a first insulating film and a first conductive film are alternately deposited in sequence, and patterned to form a plurality of stacked structures; each of the stacked structures comprises a stack of first insulating layers and first conductive layers that are alternately arranged, wherein the first conductive layer comprises a preset electrode pattern, wherein the preset electrode pattern comprises a first conductive portion extending along a second direction, wherein the first conductive portion comprises a first electrode and a second electrode of the transistor to be formed;

[0027] Etching the first conductive layer laterally along a first direction so that the orthographic projection of the first conductive portion on the substrate in the first direction falls within the orthographic projection of the first insulating layer on the substrate;

[0028] forming a barrier layer covering a side wall of the first conductive portion and a side wall of the first insulating layer;

[0029] Etching the stacked structure to form a first through hole penetrating each first conductive layer and each first insulating layer of the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the first through hole exposes each first insulating layer, and the first insulating layer is laterally etched by wet etching without etching the barrier layer, so that on a plane parallel to the substrate, the orthographic projection of the first through hole located in the first conductive layer falls within the orthographic projection of the first through hole located in the first insulating layer, and the first through hole disconnects the first electrode and the second electrode in the preset electrode pattern;

[0030] Depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole in sequence to form a semiconductor layer, a gate insulating layer and a word line of the transistor in multiple layers, wherein the word line fills the through hole;

[0031] Etching the stack structure to form a second through hole penetrating the stack structure in a direction perpendicular to the substrate, wherein the second through hole exposes a side wall of the semiconductor layer extending in parallel to the second direction in the first through hole of the first insulating layer;

[0032] The semiconductor layer entirely located in the first through hole of the first insulating layer is removed by etching through the second through hole.

[0033] In some embodiments, the second through hole further exposes a portion of a sidewall of the semiconductor layer located in the first through hole of the first insulating layer and extending parallel to the first direction.

[0034] In some embodiments, before sequentially depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole, the method further includes: the barrier layer is silicon nitride, and the barrier layer in the first through hole is removed by etching.

[0035] In some embodiments, after the semiconductor layer in the first through hole of the first insulating layer is removed by etching the second through hole, the method further includes: depositing an insulating film to fill the second through hole.

[0036] The embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to the substrate; a word line penetrating the different layers and extending along a direction perpendicular to the substrate; a first insulating layer and a first conductive layer alternately distributed from bottom to top along a direction perpendicular to the substrate; a through hole penetrating each of the first insulating layer and each of the first conductive layer, wherein the word line is arranged in the through hole, wherein the second sub-hole of the through hole is located in the first conductive layer and the orthographic projection of the substrate is located, wherein the first sub-hole of the through hole is located in the first insulating layer and the orthographic projection of the substrate is located; the transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the side wall of the word line; the first electrode and the second electrode are arranged in the first conductive layer; the plurality of semiconductor layers of the plurality of transistors are arranged at intervals, and the plurality of semiconductor layers are distributed in different areas of the side wall of the word line. In the semiconductor device provided by the present embodiment, the semiconductor layers of transistors in different layers are arranged at intervals, which can eliminate parasitic transistors between layers, reduce leakage current, and improve device stability; and the first through holes have aperture differences in different layers. When manufacturing the semiconductor device, the aperture difference can be used to stagger the semiconductor layer of the first conductive layer and the semiconductor layer in the first insulating layer. The structure of the semiconductor device in the embodiment of the present application is conducive to achieving the following structural and process advantages: the structure of the semiconductor device can use holes outside the through holes where the word lines are located to remove parasitic transistors, thereby effectively removing the semiconductor layers between layers without affecting the effective channel area of ​​the transistor (the semiconductor layer of the first conductive layer), ensuring the removal of parasitic transistors without affecting the channel while achieving a relatively simple process.

[0037] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0038] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

[0040] Figure 1A A top view of a semiconductor device provided for an exemplary embodiment;

[0041] Figure 1B For along Figure 1A Cross-section view along the AA direction;

[0042] Figure 1C For along Figure 1A Cross-section along the BB direction;

[0043] Figure 1D A cross-sectional view of a semiconductor device along the AA direction provided for another exemplary embodiment;

[0044] Figure 1E A cross-sectional view of a semiconductor device along direction BB provided for another exemplary embodiment;

[0045] Figure 2 A three-dimensional schematic diagram of a stacked structure provided for an exemplary implementation;

[0046] Figure 3A A three-dimensional schematic diagram after a preset pattern is formed provided by an exemplary embodiment;

[0047] Figure 3B A cross-sectional view of the first conductive layer 12 along a direction parallel to the substrate provided for an exemplary embodiment;

[0048] Figure 3C A cross-sectional view along the AA direction after a preset pattern is formed provided by an exemplary embodiment;

[0049] Figure 3D A cross-sectional view along the BB direction after a preset pattern is formed provided by an exemplary embodiment;

[0050] Figure 4A A three-dimensional schematic diagram of an exemplary embodiment after reducing the width of the first conductive portion along the AA direction;

[0051] Figure 4B A cross-sectional view along the AA direction after the width of the first conductive portion along the AA direction is reduced provided by an exemplary embodiment;

[0052] Figure 4C A cross-sectional view along the BB direction after the width of the first conductive portion 121 along the AA direction is reduced, provided by an exemplary embodiment;

[0053] Figure 5A A three-dimensional schematic diagram after forming a barrier layer provided by an exemplary embodiment;

[0054] Figure 5B A cross-sectional view along the AA direction after forming a barrier layer provided by an exemplary embodiment;

[0055] Figure 5C A cross-sectional view along the BB direction after forming a barrier layer provided by an exemplary embodiment;

[0056] Fig. 6A A three-dimensional schematic diagram after forming a second insulating layer provided by an exemplary embodiment;

[0057] Figure 6B A cross-sectional view along the AA direction after forming the second insulating layer provided by an exemplary embodiment;

[0058] Figure 6C A cross-sectional view along the BB direction after forming the second insulating layer provided by an exemplary embodiment;

[0059] Fig. 7A A three-dimensional schematic diagram after forming a first through hole provided by an exemplary embodiment;

[0060] Figure 7B A top view after forming a first through hole is provided for an exemplary embodiment;

[0061] Figure 7C A cross-sectional view along the AA direction after forming a first through hole provided by an exemplary embodiment;

[0062] Fig.7D A cross-sectional view along the BB direction after forming a first through hole provided by an exemplary embodiment;

[0063] Fig. 8A A cross-sectional view along the AA direction after the first sub-hole is enlarged provided by an exemplary embodiment;

[0064] Figure 8B A cross-sectional view along the BB direction after the first sub-hole is enlarged provided by an exemplary embodiment;

[0065] Fig. 9A A three-dimensional schematic diagram after etching the stop layer provided by an exemplary embodiment;

[0066] Fig. 9B A top view after etching the stop layer is provided for an exemplary embodiment;

[0067] Fig. 9C A cross-sectional view along the AA direction after etching the stop layer provided by an exemplary embodiment;

[0068] Fig.9D A cross-sectional view along the BB direction after etching the stop layer provided by an exemplary embodiment;

[0069] Fig. 10A A three-dimensional schematic diagram after forming a semiconductor layer, a gate insulating layer and a word line provided by an exemplary embodiment;

[0070] Fig. 10B A top view after forming a semiconductor layer, a gate insulating layer and a word line is provided for an exemplary embodiment;

[0071] Fig. 10C A cross-sectional view along the AA direction after forming a semiconductor layer, a gate insulating layer and a word line provided for an exemplary embodiment;

[0072] Fig. 10D A cross-sectional view along the BB direction after forming a semiconductor layer, a gate insulating layer and a word line provided for an exemplary embodiment;

[0073] Fig.11A A three-dimensional schematic diagram after forming a second through hole provided by an exemplary embodiment;

[0074] Fig. 11B A top view after forming a second through hole provided for an exemplary embodiment;

[0075] Figure 11B' A top view after forming a second through hole is provided for another exemplary embodiment;

[0076] Fig. 11C A cross-sectional view along the AA direction after forming a second through hole provided by an exemplary embodiment;

[0077] Fig.11D A cross-sectional view along the BB direction after forming the second through hole provided by an exemplary embodiment;

[0078] Fig. 12A A three-dimensional schematic diagram of an exemplary embodiment after etching a semiconductor layer located in a first insulating layer;

[0079] Fig. 12B A top view after etching a semiconductor layer located in a first insulating layer is provided for an exemplary embodiment;

[0080] Fig. 12CA cross-sectional view along the AA direction after etching the semiconductor layer located in the first insulating layer provided for an exemplary embodiment;

[0081] Fig.12D A cross-sectional view along the BB direction after etching the semiconductor layer located in the first insulating layer provided for an exemplary embodiment;

[0082] Fig.13A is a top view after forming the third insulating layer;

[0083] Fig. 13B is a cross-sectional view along the AA direction after the third insulating layer is formed;

[0084] Fig. 13C is a cross-sectional view along the BB direction after the third insulating layer is formed;

[0085] Fig.14 A cross-sectional view along the AA direction after forming a semiconductor layer, a gate insulating layer and a word line provided for another exemplary embodiment;

[0086] Fig.15 A cross-sectional view along the AA direction after forming a second through hole provided for another exemplary embodiment;

[0087] Fig.16 A cross-sectional view along the AA direction after etching the semiconductor layer located in the first insulating layer provided for another exemplary embodiment;

[0088] Fig.17 A cross-sectional view along the AA direction after forming the second insulating layer is provided for another exemplary embodiment. DETAILED DESCRIPTION

[0089] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0090] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0091] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0092] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0093] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0094] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0095] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0096] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0097] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0098] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0099] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0100] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

[0101] The embodiment of the present application is a storage cell structure based on a series of mutually isolated transistors stacked vertically and the semiconductor layers of each transistor are simultaneously formed in a through hole through a single process. The semiconductor layers of each transistor of this type of structure are interconnected, and there are parasitic transistors (referred to as parasitic MOS) between adjacent transistors. In the process, while removing the parasitic MOS, the channel area is affected as little as possible to ensure the stability of the transistor communication performance. Based on the above status quo, the embodiment of the present application proposes a structural improvement and a corresponding process implementation process to achieve the effect of removing the parasitic MOS without affecting the channel area as much as possible.

[0102] Figure 1A A top view of a semiconductor device is provided for an exemplary embodiment. Figure 1B For along Figure 1A Cross-sectional view along the AA direction, Figure 1C For along Figure 1A The semiconductor device may be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

[0103] like Figure 1A , Figure 1B and Figure 1C As shown, the semiconductor device provided in this embodiment may include:

[0104] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

[0105] A word line 40, penetrating through the different layers and extending in a direction perpendicular to the substrate 1;

[0106] The first insulating layer 10 and the first conductive layer 12 are alternately distributed from bottom to top in a direction perpendicular to the substrate 1; a first through hole K1 penetrating each of the first insulating layer 10 and each of the first conductive layer 12, the word line 40 is arranged in the first through hole K1, and the orthographic projection of the second sub-hole of the first through hole K1 located in the first conductive layer 12 on the substrate 1 falls within the orthographic projection of the first sub-hole of the first through hole K1 located in the first insulating layer 10 on the substrate 1;

[0107] The transistor includes a first electrode 51, a second electrode 52 and a semiconductor layer 23 surrounding the sidewall of the word line 40; the first electrode 51 and the second electrode 52 are disposed in the first conductive layer 12;

[0108] The semiconductor layers 23 of the transistors are arranged at intervals, and the semiconductor layers 23 are distributed in different regions of the sidewall of the word line 40 .

[0109] In the semiconductor device provided in this embodiment, the semiconductor layers of transistors in different layers are arranged at intervals, which can eliminate parasitic transistors between layers, reduce leakage current, and improve device stability. The orthographic projection of the first through hole of the first conductive layer 12 is located within the orthographic projection of the first through hole of the first insulating layer 10, that is, there is a difference in aperture between the first through holes in different layers. When manufacturing the semiconductor device, the aperture difference can be used to stagger the semiconductor layer of the first conductive layer 12 and the semiconductor layer in the first insulating layer 10, thereby removing the semiconductor layer between the layers without affecting the semiconductor layer of the first conductive layer 12 (that is, without affecting the effective channel area), which can improve device performance and simplify the process.

[0110] In some embodiments, the transistor may further include a gate insulating layer 24 surrounding the word line 40 .

[0111] In some embodiments, the semiconductor layer 23 may be a fully surrounding type, fully surrounding the sidewall of the word line 40, that is, the cross section of the semiconductor layer 23 along the direction parallel to the substrate 1 is a closed loop. Exemplarily, the semiconductor layer 23 is annular, and the annular shape is adapted to the outer contour of the cross section of the word line 40. Exemplarily, the cross section of the word line 40 is, for example, a circular, elliptical, square, or other structure.

[0112] In some embodiments, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer along a direction perpendicular to the substrate 1. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate.

[0113] In some embodiments, the semiconductor layers 23 disposed at intervals are disconnected from each other, and the gate insulating layer 24 is exposed.

[0114] In some embodiments, the transistor further includes a gate electrode 26, and the gate electrode 26 of transistors of different layers may be a part of the word line 40. It is understandable that before and after the word line is formed, there is no need to separately make a gate electrode, and after the word line is made, a part of the word line acts as a gate electrode. The local morphology of the word line is not limited here, and the word line as a whole extends in a direction perpendicular to the substrate. Locally, corresponding to each transistor, the gate electrode of this area may extend in the horizontal direction and the vertical direction, but the semiconductor layer is formed on the side wall of the word line, and the area wrapped with the semiconductor layer in the side wall of the word line may be the main surface of the film layer including an extension in a direction perpendicular to the substrate, or in addition to the area extending vertically, it also includes an area extending in the horizontal direction.

[0115] In some embodiments, the semiconductor device may be a memory cell array, wherein the memory cell array includes a plurality of memory cells, and the memory cells include transistors. Figure 1A As shown, the transistors in the same layer form a memory cell array distributed along the first direction X and the second direction Y respectively. Each layer may also include: a bit line 30 connected to the second electrode 52 of the transistors in the same column in one layer. Figure 1A , each layer includes three rows and two columns, but the embodiments of the present disclosure are not limited thereto, and each layer may include storage units of other numbers of rows and columns, for example, may include only one storage unit. The AA direction may be parallel to the first direction X, and the BB direction may be parallel to the second direction Y.

[0116] In some embodiments, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30 .

[0117] In some embodiments, the second electrode 52 of the transistor may be a portion of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular.

[0118] The branches may be a plurality of branches on one side wall of the bit line, or a plurality of branches on both side walls at the same time, and each branch may form a transistor or a memory cell accordingly.

[0119] In some embodiments, the bit lines 30 may extend along a first direction X.

[0120] In some embodiments, the first electrode 51 may extend along the second direction Y.

[0121] In some embodiments, the first through hole K1 is sequentially distributed with the word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 extending in a direction perpendicular to the substrate at different regions surrounding the sidewall of the gate insulating layer 24 from inside to outside;

[0122] The plurality of semiconductor layers 23 extend in a direction perpendicular to the substrate and are disconnected at the sidewall of the first insulating layer 10 .

[0123] In some embodiments, the sidewall of the first through hole K1 includes a first sidewall located at the first sub-hole and a second sidewall located at the second sub-hole connected to the first sidewall, the first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending in a direction perpendicular to the substrate 1, the semiconductor layer 23 extends continuously on the second sidewall and extends continuously from the second sidewall to the sub-sidewall of the groove extending in a direction perpendicular to the substrate 1, and is not distributed on the sub-sidewall so that the multiple semiconductor layers 23 are disconnected at the sub-sidewall. That is, the cross-section of the semiconductor layer 23 in the direction perpendicular to the substrate 1 can be two U-shaped shapes distributed on both sides of the word line 40, and the U-shaped opening direction is away from the word line 40.

[0124] In some embodiments, the semiconductor layer 23 is connected to the side walls of the first electrode 51 and the second electrode 52, and is connected to at least one of the upper surface and the lower surface of the first electrode 51 and the second electrode 52. The upper surface of the first electrode 51 and the second electrode 52 is the surface away from the substrate side, the lower surface of the first electrode 51 and the second electrode 52 is the surface facing the substrate side, and the side walls of the first electrode 51 and the second electrode 52 are the surfaces connecting the upper surface and the lower surface. In the solution provided in this embodiment, the semiconductor layer 23 contacts at least one of the side walls and the upper and lower surfaces of the first electrode 51 and the second electrode 52. Compared with the solution in which the semiconductor layer 23 contacts only the side walls, the contact area can be increased, and the contact resistance between the first electrode 51, the second electrode 52 and the semiconductor layer 23 is reduced.

[0125] In some embodiments, the first insulating layer 10 only exposes the sidewall in the first through hole K1, and the first conductive layer 12 exposes the sidewall and partial areas of the upper and lower surfaces in the first through hole K1;

[0126] The semiconductor layer 23 is at least distributed on the sidewall of the first conductive layer 12 , that is, distributed on the sidewall of the first conductive layer 12 exposed in the first through hole K1 .

[0127] In some embodiments, the semiconductor layer 23 may also be distributed on the upper and lower surfaces of the first conductive layer 12 exposed in the first through hole K1 and not distributed on the sidewall of the first insulating layer 10 .

[0128] In some embodiments, the semiconductor device may further include a third insulating layer 15 , wherein the third insulating layer 15 includes a vertical portion extending in a direction perpendicular to the substrate and a surrounding portion surrounding the semiconductor layer 23 located in the first region of the first through hole.

[0129] Figure 1D A cross-sectional view of a semiconductor device along the AA direction provided for another exemplary embodiment, Figure 1E FIG. 1 is a cross-sectional view of a semiconductor device along the BB direction provided for another exemplary embodiment. In this embodiment, a barrier layer is provided on the outer sidewall of the semiconductor layer 23 (the semiconductor layer 23 may include an inner sidewall and an outer sidewall, and the inner sidewall is in contact with the gate insulating layer 24). In some embodiments, as Figure 1D , Figure 1E As shown, the semiconductor layer 23 may include a first side wall and a second side wall that are oppositely arranged along a first direction X, and the first direction X is perpendicular to the extension direction of the substrate and the first electrode 51 (ie, the second direction Y);

[0130] The first through hole K1 may further include a barrier layer 13 disposed on the first sidewall and the second sidewall of the plurality of semiconductor layers 23 away from the word line. The barrier layer 13 is used to limit the size of the first through hole K1 when forming the first through hole K1, so as to achieve precise control of the first through hole K1.

[0131] In some embodiments, the barrier layers 13 on surfaces of different layers of the semiconductor layer 23 are spaced apart from each other.

[0132] In some embodiments, the barrier layer 13 is not distributed on the sidewall of the first insulating layer 10 exposed in the first through hole K1, and is not distributed on the sidewall, upper surface and lower surface of the first conductive layer 12 exposed in the first through hole K1. Figure 1E As shown, there is no barrier layer 13 in the BB direction.

[0133] In some embodiments, the gate insulating layers 24 of multiple transistors at different layers may be connected to form an integrated structure, but the embodiments of the present disclosure are not limited thereto, and the gate insulating layers 24 of multiple transistors at different layers may be disconnected.

[0134] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0135] In one embodiment, the manufacturing process of the semiconductor device may include:

[0136] 101) A first insulating film and a first conductive film are sequentially deposited on a substrate 1 to form a stacked structure including first insulating layers 10 and first conductive layers 12 alternately arranged, such as Figure 2 As shown, Figure 2 The three-dimensional schematic diagram of a stacked structure after forming is provided for an exemplary implementation. A hard mask layer 8 is disposed on the topmost first conductive layer 12 .

[0137] The orthographic projections of the first insulating layer 10 and the first conductive layer 12 in a direction parallel to the substrate overlap.

[0138] In some embodiments, the first insulating film may be an insulating material, including but not limited to silicon oxide, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), and the like.

[0139] In some embodiments, the first conductive film may be a conductive material as follows:

[0140] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0141] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0142] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0143] In some embodiments, the hard mask layer 8 includes but is not limited to at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0144] Figure 2 The stacked structure shown in FIG. 1 includes three first insulating layers 10 and three first conductive layers 12 , which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0145] 102) patterning the stacked structure so that the stacked structure forms a preset pattern;

[0146] The patterning of the stacked structure may include:

[0147] The stacked structure is etched from the top layer to the bottom layer (excluding the substrate) by dry etching to form a plurality of first grooves, wherein the plurality of first grooves enable the first conductive layer 12 to form a preset pattern, and the preset pattern may include a first conductive portion 121 and a second conductive portion 122, wherein the first conductive portion 121 may extend along the second direction Y, and the second conductive portion 122 may extend along the first direction X, such as Figure 3A , Figure 3B , Figure 3C , Figure 3D As shown, Figure 3A To form a three-dimensional schematic diagram after the preset graphics, Figure 3B is a cross-sectional view of the first conductive layer 12 along a direction parallel to the substrate, Figure 3C To form a cross-sectional view along the AA direction after forming a preset pattern, Figure 3D It is a cross-sectional view along the BB direction after the preset pattern is formed. The preset pattern and the pattern of the plurality of first grooves are complementary, that is, the pattern of the preset pattern and the pattern of the first grooves are combined to form the shape of the first conductive layer 12 in step 1). The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0148] The first conductive portion 121 may subsequently form a first electrode 51 of a transistor, and the second conductive portion 122 may form a second electrode 52 of a transistor, and further, form a bit line 30 .

[0149] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive portion 122 may form the bit line 30 .

[0150] Figure 3B The preset shapes shown are only examples, and the preset shapes may be other shapes.

[0151] In this step, the size of the first conductive portion 121 along the AA direction may be larger than the size of the finally formed first electrode 51 along the AA direction.

[0152] When the word line is subsequently formed, a first through hole K1 is formed, and the apertures of the first through hole K1 in the first insulating layer 10 and the first conductive layer 12 are different, wherein the aperture of the first through hole K1 in the first insulating layer 10 is a first aperture d1, and the aperture of the first conductive layer 12 is a second aperture d2. In this step, the dimension d of the first conductive portion 121 along the AA direction may be the first aperture d1. In some embodiments, the difference between d1 and d2 may be 10 nanometers to 50 nanometers.

[0153] 103) reducing the width of the first conductive portion 121 along the AA direction;

[0154] The reducing the width of the first conductive portion along the AA direction may include: introducing an etching solution into the first groove to selectively etch the first conductive layer 12 and the first insulating layer 10 by wet etching, that is, etching the first conductive layer 12 and substantially not etching the first insulating layer 10, so that the size of the first conductive portion 121 along the AA direction is reduced, so that the orthographic projection of the first conductive portion 121 in the AA direction falls within the orthographic projection of the first insulating layer 10, such as Figure 4A , Figure 4B , Figure 4C As shown, Figure 4A This is a three-dimensional schematic diagram after the width of the first conductive portion 121 along the AA direction is reduced. Figure 4B The cross-sectional view along the AA direction after the width of the first conductive portion 121 along the AA direction is reduced, Figure 4C This is a cross-sectional view along the BB direction after the width of the first conductive portion 121 along the AA direction is reduced. In the AA direction, the orthographic projection of the cross section of the first conductive layer 12 on the substrate 1 falls within the orthographic projection of the cross section of the first insulating layer 10 on the substrate. In this step, the size of the first conductive portion 121 along the AA direction can be the aperture of the first through hole K1 formed subsequently in the first conductive layer 12, that is, the second aperture d2.

[0155] 104) forming a barrier layer 13;

[0156] The forming of the barrier layer 13 may include: depositing a barrier layer film on the substrate 1 having the aforementioned structure to form the barrier layer 13, such as Figure 5A , Figure 5B , Figure 5C As shown, Figure 5A is a three-dimensional schematic diagram after the barrier layer 13 is formed, Figure 5B It is a cross-sectional view along the AA direction after the barrier layer 13 is formed. Figure 5C The figure is a cross-sectional view along the BB direction after the barrier layer 13 is formed. The barrier layer 13 covers the upper surface of the hard mask layer 8 and the sidewall and lower surface exposed in the first trench, and covers the sidewall of the first conductive layer 12 exposed in the first trench, and covers the sidewall, upper surface and lower surface of the first insulating layer 10 exposed in the first trench. The barrier layer 13 can protect the insulating film on the same layer as the first conductive layer 12, that is, the second insulating layer 14 formed later on the same layer as the first conductive layer 12, when the first insulating layer 10 is subsequently etched.

[0157] In some embodiments, the barrier layer film is a material having a high etching selectivity ratio with the first insulating film, so as to protect the first conductive layer 12 when the first insulating layer 10 is subsequently etched.

[0158] In some embodiments, the barrier layer 13 can be a single layer or multiple layers.

[0159] In some embodiments, the barrier layer film may include but is not limited to at least one of the following: silicon nitride (Si3N4), aluminum oxide (Al2O3), and the like.

[0160] 105) forming a second insulating layer 14;

[0161] The forming of the second insulating layer 14 may include: depositing a second insulating film on the substrate 1 having the aforementioned structure to form the second insulating layer 14 filling the first trench;

[0162] The hard mask layer 8 and the upper surface of the hard mask layer 8 are removed by grinding so that the second insulating layer 14 is flush with the upper surface of the topmost first conductive layer 12. Fig. 6A , Figure 6B and Figure 6C As shown, Fig. 6A is a three-dimensional schematic diagram after the second insulating layer 14 is formed, Figure 6B is a cross-sectional view along the AA direction after the second insulating layer 14 is formed. Figure 6C It is a cross-sectional view along the BB direction after forming the second insulating layer 14. The second insulating layer 14 fills the first trench.

[0163] In some embodiments, the planarization may be performed by chemical mechanical polishing (CMP).

[0164] In some embodiments, the second insulating film can be made of the same material as or different from the first insulating film.

[0165] In some embodiments, the second insulating film may be an insulating material, including but not limited to silicon oxide, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), and the like.

[0166] 106) forming a first through hole K1;

[0167] The forming of the first through hole K1 may include: etching the stacked structure by dry etching to form a plurality of first through holes K1 penetrating the stacked structure, wherein the sidewalls of the first through holes K1 expose each of the first conductive layer 12 and the first insulating layer 10, and the aperture sizes of the first through holes K1 in different layers are substantially consistent, that is, the aperture of the first through hole K1 in the first insulating layer 10 is consistent with the aperture of the first through hole K1 in the first conductive layer 12, and the first through hole K1 disconnects the first conductive layer 12 to form the first electrode 51 and the second electrode 52 disconnected from each other, such as Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, Fig. 7A is a three-dimensional schematic diagram after the first through hole K1 is formed, Figure 7B This is a top view after the first through hole K1 is formed. Figure 7C It is a cross-sectional view along the AA direction after the first through hole K1 is formed. Fig.7D It is a cross-sectional view along the BB direction after the first through hole K1 is formed.

[0168] The first through hole K1 may include a first sub-hole K11 located in the first insulating layer 10 and a second sub-hole K12 located in the first conductive layer 12. In this step, the aperture of the second sub-hole K12 may be equal to the aperture of the first sub-hole 11.

[0169] In some embodiments, the first through hole K1 may extend in a direction perpendicular to the substrate 1 .

[0170] In some embodiments, the orthographic projection of the first through hole K1 on a plane parallel to the substrate 1 may be a square, but is not limited thereto, and may be other shapes, such as a circle, a hexagon, an ellipse, and the like.

[0171] 107) Enlarging the aperture of the first sub-hole K11;

[0172] The step of enlarging the aperture of the first sub-hole K11 may include: introducing an etching solution into the first through hole K1, and laterally etching the first insulating layer 10 by wet etching to enlarge the aperture of the first sub-hole K11, so that the orthographic projection of the second sub-hole K12 on the substrate 1 falls within the orthographic projection of the first sub-hole K11 on the substrate 1, as shown in FIG. Fig. 8A , Figure 8B As shown, Fig. 8A The cross-sectional view along the AA direction after enlarging the first sub-hole K11 is shown in FIG. Figure 8B The cross-sectional view along the BB direction after the first sub-hole K11 is enlarged. It can be seen that in the AA direction, the orthographic projection of the second sub-hole K12 on the substrate 1 falls within the orthographic projection of the first sub-hole K11 on the substrate 1; in the BB direction, the orthographic projection of the second sub-hole K12 on the substrate 1 falls within the orthographic projection of the first sub-hole K11 on the substrate 1. After the etching solution is passed into the first through hole K1, the second insulating layer 14 on the same layer as the first conductive layer 12 is protected by the barrier layer 13 to avoid being etched by the etching solution. Fig. 8A As shown, in the AA direction, the sidewall of the second sub-hole K12 is provided with a barrier layer 13 to prevent etching of the second insulating layer 14, and the sidewall of the first sub-hole K11 is provided with a barrier layer 13 to limit the aperture of the first sub-hole K11 after expansion. The solution provided in this embodiment can accurately control the hole expansion size through the barrier layer 13, thereby ensuring the controllability and accuracy of the process.

[0173] After the semiconductor layer is subsequently deposited in the first through hole K1, in the direction perpendicular to the substrate 1, since the aperture of the first through hole K1 located in the first insulating layer 10 is different from the aperture of the first conductive layer 12, the semiconductor layer located in the first insulating layer 10 and the semiconductor layer located in the first conductive layer 12 are staggered with each other, which facilitates the removal of the semiconductor layer located in the first insulating layer 10. In some embodiments, the difference between the aperture of the first through hole K1 located in the first insulating layer 10 and the aperture of the first conductive layer 12 can be 10nm to 50nm, so that the distance between the semiconductor layer located in the first insulating layer 10 and the semiconductor layer located in the first conductive layer 12 can be 5nm to 25nm. However, the embodiments of the present disclosure are not limited thereto and can be set to other values ​​as needed.

[0174] 108) etching and removing the barrier layer 13 distributed on the side wall of the first through hole K1;

[0175] The etching and removing of the barrier layer 13 distributed on the side wall of the first through hole K1 may include: introducing an etching solution into the first through hole K1, and removing the barrier layer 13 located on the side wall of the first through hole K1 by wet etching, such as Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D As shown, Fig. 9A is a three-dimensional schematic diagram after etching the barrier layer 13, Fig. 9B is a top view after etching the stop layer 13, Fig. 9C is a cross-sectional view along the AA direction after etching the stop layer 13, Fig.9D It is a cross-sectional view along the BB direction after etching the barrier layer 13. In this step, only the barrier layer 13 is etched away, and the first insulating layer 10 and the second insulating layer 14 are not etched.

[0176] 109) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0177] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0178] On the substrate 1 having the above structure, a semiconductor film, a gate insulating film and a gate electrode film are sequentially deposited and polished to form a semiconductor layer 23, a gate insulating layer 24 and a word line 40; Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D As shown, Fig. 10A is a three-dimensional schematic diagram after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed. Fig. 10B FIG. 4 is a top view after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40. Fig. 10C It is a cross-sectional view along the AA direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed. Fig. 10D It is a cross-sectional view along the BB direction after the semiconductor layer 23 , the gate insulating layer 24 and the word line 40 are formed. The gate electrode 26 of each layer of transistors is a part of the word line 40 .

[0179] After being polished, the surfaces of the semiconductor layer 23 , the gate insulating layer 24 and the word line 40 away from the substrate 1 are flush with the surface of the topmost first conductive layer 12 away from the substrate 1 .

[0180] The semiconductor layer 23 may cover the bottom wall and side walls of the first through hole K1 , the word line 40 fills the first through hole K1 , and the gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 from the word line 40 .

[0181] In some embodiments, the semiconductor film, the gate insulating film, and the gate electrode film may be deposited by ALD.

[0182] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 2 eV.

[0183] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0184] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0185] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0186] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0187] In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0188] In some embodiments, the gate electrode film may be one or more of the following different types of materials:

[0189] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0190] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0191] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0192] 110) forming a second through hole K2;

[0193] The forming of the second through holes K2 may include: etching the stacked structure from the top layer to the bottom layer (excluding the substrate 1) by dry etching to form a plurality of second through holes K2, wherein the second through holes K2 expose the semiconductor layer 23 in the first insulating layer 10 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the BB direction, such as Fig.11A , Fig. 11B , Fig. 11C and Fig.11D As shown, Fig.11A is a three-dimensional schematic diagram after the second through hole K2 is formed. Fig. 11B This is a top view after the second through hole K2 is formed. Fig. 11C It is a cross-sectional view along the AA direction after the second through hole K2 is formed. Fig.11D It is a cross-sectional view along the BB direction after the second through hole K2 is formed. In this step, the second insulating layer 14 is etched away to form the second through hole K2.

[0194] In some embodiments, the orthographic projection of the second through hole K2 on the substrate 1 is located outside the orthographic projection of the first conductive layer 12 .

[0195] like Fig. 11C As shown, the semiconductor layer 23 located in the first insulating layer 10 in the AA direction is completely exposed, and the semiconductor layer 23 located in the first conductive layer 12 in the AA direction is protected by the second insulating layer 14, that is, the two side surfaces of the semiconductor layer 23 located in the first insulating layer 10 arranged along the AA direction are exposed by two second through holes K2, so as to facilitate the subsequent etching of the semiconductor layer 23 by passing an etching solution into the second through holes K2.

[0196] Fig. 11B The size of the second through hole K2 described in the figure is only an example. In another exemplary embodiment, the size of the second through hole along the BB direction can be reduced to expose the semiconductor layer 23 located in the first insulating layer 10 in the AA direction. The larger the size of the second through hole K2 along the BB direction, the more semiconductor layer 23 is exposed, and the subsequent etching speed of the semiconductor layer 23 is faster, which is more conducive to the etching of the semiconductor layer 23.

[0197] In another exemplary embodiment, Figure 11B' As shown, the second through hole K2 may include two sub-through holes: a first sub-through hole K21 and a second sub-through hole K22, wherein the first sub-through hole K21 extends along the BB direction to expose the side wall of the semiconductor layer 23 extending in parallel to the second direction Y in the first through hole K1 of the first insulating layer 10; the second sub-through hole K22 extends along the AA direction to expose part of the side wall of the semiconductor layer 23 extending in parallel to the first direction X in the first through hole K1 of the first insulating layer 10, that is, parts of the two side surfaces of the semiconductor layer 23 arranged in the BB direction in the first insulating layer 10 are exposed by the two second sub-through holes K22, and each second sub-through hole K22 is divided into two parts, which are respectively located on both sides of the electrically conductive portion 121. The solution provided in this embodiment can expose more semiconductor layers 23, so that the semiconductor layers 23 can be etched and removed faster. In the subsequent steps, the second through hole K2 is used as Fig. 11B The shape shown is used as an example for explanation.

[0198] 111) etching the semiconductor layer 23 in the first insulating layer 10;

[0199] The etching of the semiconductor layer 23 in the first insulating layer 10 may include: introducing an etching solution into the second through hole K2 to etch away the semiconductor layer 23 in the first insulating layer 10, and not etching other film layers, such as the second insulating layer 14, the gate insulating layer 24, etc. Fig. 12A , 12B , 12C and 12D, Fig. 12A 2 is a three-dimensional schematic diagram after etching the semiconductor layer 23 located in the first insulating layer 10. Fig. 12B This is a top view after etching the semiconductor layer 23 located in the first insulating layer 10. Fig. 12C It is a cross-sectional view along the AA direction after etching the semiconductor layer 23 located in the first insulating layer 10. Fig.12D It is a cross-sectional view along the BB direction after etching the semiconductor layer 23 located in the first insulating layer 10 .

[0200] When etching the semiconductor layer 23 in the first insulating layer 10, the semiconductor layer 23 in the first insulating layer 10 surrounding the word line 40 is etched away. Fig. 12C and 12D As shown, it can be seen that the semiconductor layer 23 located in the first insulating layer 10 is etched away, and the gate insulating layer 24 is exposed in the second through hole K2.

[0201] In this step, the semiconductor layer 23 in the first insulating layer 10 is etched away, the semiconductor layer 23 between the transistors in adjacent layers is disconnected, and the parasitic transistors are eliminated.

[0202] 112) forming a third insulating layer 15;

[0203] The forming of the third insulating layer 15 may include: depositing a third insulating film filling the second through hole K2 and the area where the etched semiconductor layer 23 is located on the substrate 1 forming the aforementioned structure, so as to form the third insulating layer 15. Fig.13A , Fig. 13B and Fig. 13C As shown, Fig.13A is a top view after the third insulating layer 15 is formed. Fig. 13B is a cross-sectional view along the AA direction after the third insulating layer 15 is formed. Fig. 13C It is a cross-sectional view along the BB direction after the third insulating layer 15 is formed.

[0204] In some embodiments, the third insulating film may be an insulating material, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), and the like.

[0205] In another embodiment, the barrier layer 13 may be formed using a material that has an isolation effect on hydrogen (H) and oxygen (O) and has little effect on the semiconductor layer 23, so that the barrier layer 13 may be retained. The manufacturing process of the semiconductor device may include:

[0206] Steps 201 to 207 are the same as steps 101 to 107;

[0207] 208) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0208] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0209] On the substrate 1 having the above structure, a semiconductor film, a gate insulating film and a gate electrode film are sequentially deposited and polished to form a semiconductor layer 23, a gate insulating layer 24 and a word line 40; Fig.14 As shown, Fig.14It is a cross-sectional view along the AA direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed. The gate electrode 26 of each layer of transistors is a part of the word line 40. In this embodiment, the first through hole K1 is sequentially distributed with the barrier layer 13, the semiconductor layer 23, the gate insulating layer 24 and the word line 40 from the outside to the inside in the AA direction. Fig. 10D , no more details.

[0210] The semiconductor layer 23 may cover the bottom wall and side walls of the first through hole K1 , the word line 40 fills the first through hole K1 , and the gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 from the word line 40 .

[0211] 209) forming a second through hole K2;

[0212] The forming of the second through holes K2 may include: etching the stacked structure from the top layer to the bottom layer (excluding the substrate 1) by dry etching to form a plurality of second through holes K2, wherein the second through holes K2 expose the semiconductor layer 23 in the first insulating layer 10 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the BB direction, such as Fig.15 As shown, Fig.15 This is a cross-sectional view along the AA direction after the second through hole K2 is formed. Fig.11D In another embodiment, the second through hole K2 may be similar to Figure 11B' The shape of the second through hole K2.

[0213] In this embodiment, the second insulating layer 14 and a portion of the blocking layer 13 are removed by etching to form the second through hole K2.

[0214] In some embodiments, the orthographic projection of the second through hole K2 on the substrate 1 is located outside the orthographic projection of the first conductive layer 12 .

[0215] like Fig.15 As shown, the semiconductor layer 23 located in the first insulating layer 10 in the AA direction is completely exposed, and the semiconductor layer 23 located in the first conductive layer 12 in the AA direction is protected by the second insulating layer 14, that is, the semiconductor layer 23 located on two side surfaces distributed along the AA direction in the first insulating layer 10 is exposed by two second through holes K2, so as to facilitate the subsequent etching of the semiconductor layer 23 by passing an etching solution into the second through holes K2.

[0216] 210) etching the semiconductor layer 23 in the first insulating layer 10 to form a third insulating layer 15;

[0217] Referring to steps 111 to 112, the etching of the semiconductor layer 23 in the first insulating layer 10 in the AA direction to form the third insulating layer 15 may include: introducing an etching solution into the plurality of second through holes K2 to etch away the semiconductor layer 23 in the first insulating layer 10, and not etching other film layers, such as the second insulating layer 14, the gate insulating layer 24, etc. Fig.16 As shown, Fig.16 The cross-sectional view along the AA direction after etching the semiconductor layer 23 located in the first insulating layer 10 is shown in FIG. Fig.12D . .

[0218] A third insulating film is deposited to fill the second through hole K2 and the area where the etched semiconductor layer 23 is located to form a third insulating layer 15. Fig.17 As shown, Fig.17 It is a cross-sectional view along the AA direction after the third insulating layer 15 is formed. The cross-sectional view along the BB direction can be referred to Fig. 13C .

[0219] In this embodiment, in the AA direction, the first through hole K1 located in the first conductive layer 12 is sequentially provided with the barrier layer 13 , the semiconductor layer 23 , the gate insulating layer 24 and the word line 40 from the outside to the inside.

[0220] In this embodiment, the barrier layer 13 can be a material such as Al2O3 that has an isolation effect on H and O, and will not react with the semiconductor layer 23 to affect the transistor performance. Therefore, the barrier layer 13 can be retained, thereby reducing one etching process, reducing costs, and avoiding residues caused by etching, etc., which can improve device performance.

[0221] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor includes a first electrode and a second electrode. The method for manufacturing the semiconductor device may include:

[0222] Providing a substrate, on which a first insulating film and a first conductive film are alternately deposited in sequence, and patterned to form a plurality of stacked structures; each of the stacked structures comprises a stack of first insulating layers and first conductive layers that are alternately arranged, wherein the first conductive layer comprises a preset electrode pattern, wherein the preset electrode pattern comprises a first conductive portion extending along a second direction, wherein the first conductive portion comprises a first electrode and a second electrode of the transistor to be formed;

[0223] Etching the first conductive layer laterally along a first direction so that the orthographic projection of the first conductive portion on the substrate in the first direction falls within the orthographic projection of the first insulating layer on the substrate;

[0224] forming a barrier layer covering a side wall of the first conductive portion and a side wall of the first insulating layer;

[0225] Etching the stacked structure to form a first through hole penetrating each first conductive layer and each first insulating layer of the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the first through hole exposes each first insulating layer, and the first insulating layer is laterally etched by wet etching without etching the barrier layer, so that on a plane parallel to the substrate, the orthographic projection of the first through hole located in the first conductive layer falls within the orthographic projection of the first through hole located in the first insulating layer, and the first through hole disconnects the first electrode and the second electrode in the preset electrode pattern;

[0226] Depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole in sequence to form a semiconductor layer, a gate insulating layer and a word line of the transistor in multiple layers, wherein the word line fills the through hole;

[0227] Etching the stack structure to form a second through hole penetrating the stack structure in a direction perpendicular to the substrate, wherein the second through hole exposes a side wall of the semiconductor layer extending in parallel to the second direction in the first through hole of the first insulating layer;

[0228] The semiconductor layer entirely located in the first through hole of the first insulating layer is removed by etching through the second through hole.

[0229] The manufacturing method of the semiconductor device provided by the embodiment of the present disclosure performs hollowing outside the hole of the through hole where the word line is located to remove the parasitic transistor, effectively removing the semiconductor layer between layers without affecting the effective channel area of ​​the transistor (the semiconductor layer of the first conductive layer), ensuring that the parasitic transistor is removed without affecting the channel while achieving a relatively simple process.

[0230] In some embodiments, the second through hole further exposes a portion of a sidewall of the semiconductor layer located in the first through hole of the first insulating layer and extending parallel to the first direction.

[0231] In some embodiments, before sequentially depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole, the method further includes: when the barrier layer is silicon nitride, etching and removing the barrier layer in the first through hole.

[0232] In some embodiments, after the semiconductor layer in the first through hole of the first insulating layer is removed by etching the second through hole, the method further includes: depositing an insulating film to fill the second through hole.

[0233] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0234] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, extending through the different layers in a direction perpendicular to the substrate; A first insulating layer and a first conductive layer are alternately distributed from bottom to top in a direction perpendicular to the substrate; a through hole penetrating each of the first insulating layers and each of the first conductive layers, the word line is arranged in the through hole, and the orthographic projection of the second sub-hole of the through hole located in the first conductive layer on the substrate falls within the orthographic projection of the first sub-hole of the through hole located in the first insulating layer on the substrate; The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the first electrode and the second electrode are arranged on the first conductive layer; The plurality of semiconductor layers of the plurality of transistors are arranged at intervals, and the plurality of semiconductor layers are distributed in different regions of the sidewall of the word line.

2. The semiconductor device according to claim 1, wherein: The word line, the gate insulating layer surrounding the side wall of the word line, and the plurality of semiconductor layers surrounding different regions of the side wall of the gate insulating layer are sequentially distributed in the through hole from inside to outside; The sidewalls of the through hole include a first sidewall located in a first sub-hole and a second sidewall located in a second sub-hole connected to the first sidewall, the first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending in a direction perpendicular to the substrate, the semiconductor layer extends continuously on the second sidewall and extends continuously from the second sidewall to the sub-sidewall of the groove extending in a direction perpendicular to the substrate, and is not distributed on the sub-sidewall so that the multiple semiconductor layers are disconnected at the sub-sidewall.

3. The semiconductor device according to claim 1, wherein: The semiconductor layer is connected to the side walls of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode.

4. The semiconductor device according to claim 1, wherein: The first insulating layer only exposes the side wall in the through hole, and the first conductive layer exposes the side wall and partial areas of the upper and lower surfaces in the through hole; The semiconductor layer is at least distributed on the side wall of the first conductive layer.

5. The semiconductor device according to claim 1, wherein: The semiconductor layer is also distributed on the upper and lower surfaces of the first conductive layer exposed in the through hole and is not distributed on the side wall of the first insulating layer.

6. The semiconductor device according to claim 2, wherein: The semiconductor layer comprises a first side wall and a second side wall arranged opposite to each other along a first direction, wherein the first direction is perpendicular to an extension direction of the substrate and the first electrode; The through hole further includes a barrier layer disposed on a side of the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line.

7. The semiconductor device according to claim 6, characterized in that The barrier layers on surfaces of the semiconductor layers of different layers are spaced apart from each other.

8. The semiconductor device according to claim 6, characterized in that The barrier layer is not distributed on the sidewall of the first insulating layer exposed in the through hole, and is not distributed on the sidewall, the upper surface and the lower surface of the first conductive layer exposed in the through hole.

9. The semiconductor device according to claim 2, characterized in that The gate insulating layers of multiple transistors at different layers are connected to form an integrated structure.

10. An electronic device, characterized in that: Comprising the semiconductor device as claimed in any one of claims 1 to 9.

11. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor comprises a first electrode and a second electrode, and a method for manufacturing the semiconductor device comprises: Providing a substrate, on which a first insulating film and a first conductive film are alternately deposited in sequence, and patterned to form a plurality of stacked structures; each of the stacked structures comprises a stack of first insulating layers and first conductive layers that are alternately arranged, wherein the first conductive layer comprises a preset electrode pattern, wherein the preset electrode pattern comprises a first conductive portion extending along a second direction, wherein the first conductive portion comprises a first electrode and a second electrode of the transistor to be formed; Etching the first conductive layer laterally along a first direction so that the orthographic projection of the first conductive portion on the substrate in the first direction falls within the orthographic projection of the first insulating layer on the substrate; forming a barrier layer covering a side wall of the first conductive portion and a side wall of the first insulating layer; Etching the stacked structure to form a first through hole penetrating each first conductive layer and each first insulating layer of the stacked structure in a direction perpendicular to the substrate, wherein the sidewall of the first through hole exposes each first insulating layer, and the first insulating layer is laterally etched by wet etching without etching the barrier layer, so that on a plane parallel to the substrate, the orthographic projection of the first through hole located in the first conductive layer falls within the orthographic projection of the first through hole located in the first insulating layer, and the first through hole disconnects the first electrode and the second electrode in the preset electrode pattern; Depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole in sequence to form a semiconductor layer, a gate insulating layer and a word line of the transistor in multiple layers, wherein the word line fills the through hole; Etching the stack structure to form a second through hole penetrating the stack structure in a direction perpendicular to the substrate, wherein the second through hole exposes a side wall of the semiconductor layer extending in parallel to the second direction in the first through hole of the first insulating layer; The semiconductor layer entirely located in the first through hole of the first insulating layer is removed by etching through the second through hole.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The second through hole further exposes a portion of a side wall of the semiconductor layer located in the first through hole of the first insulating layer and extending in parallel to the first direction.

13. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that: Before sequentially depositing a semiconductor film, a gate insulating film and a gate electrode film in the first through hole, the method further includes: the barrier layer is silicon nitride, and the barrier layer in the first through hole is removed by etching.

14. The method for manufacturing a semiconductor device according to claim 11 or 12, characterized in that: After the semiconductor layer in the first through hole of the first insulating layer is removed by etching through the second through hole, the method further includes: depositing an insulating film to fill the second through hole.

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