3D memory and manufacturing method thereof, and electronic device

Abstract

A 3D memory and a manufacturing method thereof, and an electronic device. The manufacturing method of the 3D memory comprises: using an atomic deposition process to form a barrier layer on the inner wall of the trench, wherein at least a portion of the barrier layer covers the exposed sidewalls of the multiple branches; forming an insulating dielectric film on the barrier layer, using an oxidation process to form an oxidized insulating dielectric layer from the insulating dielectric film, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer; using an etching process to remove the insulating dielectric layer on a side of the multiple branches away from the bit lines, thereby forming a first groove extending in a direction perpendicular to the substrate; depositing a support material film to fill the first groove; using different patterned etching processes to respectively etch the support material film and the insulating dielectric layer, thereby forming a support structure from the support material film on a side of the multiple branches away from the bit lines; and avoiding etching the support structure to ensure the strength of the support structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, semiconductor technology, and in particular to a 3D memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, conventional DRAM has multiple repetitive "memory cells," each containing a capacitor and transistor. During DRAM manufacturing, because the barrier layer protecting the transistors is made of the same material as the supporting structure, etching away the barrier layer can damage portions of the supporting structure, reducing its strength and impacting the stability of the device. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a method for manufacturing a 3D memory, including:

[0006] forming conductive layers and insulating layers alternately arranged in sequence on a substrate;

[0007] Performing patterned etching to form a plurality of trenches perpendicular to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in a sequential and cyclic manner, each layer of the patterned structure includes a bit line and a plurality of branches connected to the bit line, and the trenches expose sidewalls of the plurality of branches;

[0008] forming a barrier layer on the inner wall of the trench by an atomic deposition process, wherein at least a portion of the barrier layer covers the exposed sidewalls of the plurality of branches;

[0009] forming an insulating dielectric film on the barrier layer, forming an oxidized insulating dielectric layer from the insulating dielectric film by an oxidation process, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer;

[0010] Using an etching process, removing the insulating dielectric layer on a side of the plurality of branches away from the bit line to form a first groove extending in a direction perpendicular to the substrate;

[0011] depositing a thin film of support material filling the first groove;

[0012] Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0013] Performing patterned etching to expose ends of the multiple branches away from the bit line, wherein the exposed ends of the multiple branches form multiple first capacitor electrodes, and the multiple first capacitor electrodes are all connected to the support structure;

[0014] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

[0015] In an exemplary embodiment, the oxidized insulating dielectric layer and the oxidation blocking layer are made of the same material to form an insulating dielectric layer with an integrated structure.

[0016] In an exemplary embodiment, a first etching process is used to etch away a portion of the support material film between a plurality of adjacent branches in the same layer, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0017] Using a second etching process, a portion of the insulating dielectric layer between a plurality of adjacent branches on the same layer is etched away to form a second groove extending in a direction perpendicular to the substrate, wherein the second groove exposes a portion of the sidewall of the insulating layer between the plurality of branches on different layers;

[0018] Patterned etching is used to etch the sidewall of the insulating layer exposed by the second groove in a direction parallel to the substrate to form a hole. The hole and the second groove expose the multiple branches away from one end of the bit line, and the one end of the exposed multiple branches forms multiple first capacitor electrodes.

[0019] In an exemplary embodiment, the support structure and the insulating dielectric layer are made of different materials.

[0020] In an exemplary embodiment, the support structure is silicon nitride, and the insulating dielectric layer is silicon oxide.

[0021] In an exemplary embodiment, the barrier layer has a thickness of 3 nm to 15 nm.

[0022] In one exemplary embodiment, the barrier layer is polysilicon or amorphous silicon.

[0023] An embodiment of the present disclosure further provides a 3D memory, which is manufactured by the above-mentioned manufacturing method of the 3D memory.

[0024] In one exemplary embodiment, the device includes multiple layers of memory cells stacked in a direction perpendicular to a substrate, word lines, and bit lines. The word lines extend in a direction perpendicular to the substrate and penetrate the memory cells in different layers and are connected to the memory cells in different layers. The bit lines extend in a direction parallel to the substrate and are respectively connected to multiple memory cells in the same layer.

[0025] The storage unit includes: a transistor and a capacitor, the capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the first capacitor electrode is connected to the transistor.

[0026] An embodiment of the present disclosure further provides an electronic device, characterized in that it includes the 3D memory according to claim 8 or 9.

[0027] In the manufacturing method of the 3D memory according to the embodiment of the present disclosure, the barrier layer blocks oxygen from oxidizing the multiple branches of the conductive layer, thereby preventing the multiple branches of the conductive layer from being oxidized.

[0028] In the manufacturing method of the 3D memory of the embodiment disclosed herein, the oxidation barrier layer formed after the oxygen in the barrier layer is made of the same oxidation material as the oxidation insulating dielectric layer, so that the oxidation barrier layer serves as a sacrificial layer. The same etching process can be used to etch away the oxidation insulating dielectric layer and the oxidation barrier layer, thereby simplifying the process flow and improving the controllability of the process, which is conducive to improving device performance and enhancing structural stability.

[0029] In the manufacturing method of the 3D memory of the embodiment of the present disclosure, by making the materials of the oxidation barrier layer and the support structure different, etching of the support structure can be avoided during etching of the oxidation barrier layer, thereby ensuring the strength of the support structure.

[0030] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0031] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution.

[0033] Figure 1 A schematic cross-sectional view of a 3D memory device provided by an exemplary embodiment along a direction parallel to a substrate;

[0034] Figure 2a for Figure 1 Schematic diagram in the a-a' direction after forming the insulating layer, conductive layer and barrier layer in the manufacturing process of the 3D memory;

[0035] Figure 2b for Figure 1 Schematic diagram in the b-b' direction after forming the insulating layer, conductive layer and barrier layer in the manufacturing process of the 3D memory;

[0036] Figure 2c for Figure 1 Schematic diagram of the d-d' direction after forming the insulating layer, conductive layer and barrier layer during the manufacturing process of the 3D memory;

[0037] Figure 3a for Figure 1 Schematic diagram in the a-a' direction after forming an oxide insulating dielectric layer during the manufacturing process of a 3D memory;

[0038] Figure 3b for Figure 1 Schematic diagram in the b-b' direction after forming an oxide insulating dielectric layer during the manufacturing process of a 3D memory;

[0039] Figure 3c for Figure 1 Schematic diagram in the d-d' direction after forming an oxide insulating dielectric layer during the manufacturing process of a 3D memory;

[0040] Figure 4a for Figure 1 A schematic diagram of the a-a' direction after forming the first mask layer in the manufacturing process of the 3D memory;

[0041] Figure 4b for Figure 1 A schematic diagram in the bb' direction after forming the first mask layer in the manufacturing process of the 3D memory;

[0042] Figure 5a for Figure 1 Schematic diagram of the a-a' direction after the first groove is formed during the manufacturing process of the 3D memory;

[0043] Figure 5b for Figure 1 A schematic diagram of the bb' direction after the first groove is formed during the manufacturing process of the 3D memory;

[0044] Figure 6a for Figure 1 Schematic diagram in the a-a' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0045] Figure 6b for Figure 1Schematic diagram in the b-b' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0046] Figure 6c for Figure 1 Schematic diagram of the d-d' direction after forming a supporting material film during the manufacturing process of the 3D memory;

[0047] Figure 7a for Figure 1 Schematic diagram of the bb' direction after the second groove is formed during the manufacturing process of the 3D memory;

[0048] Figure 7b for Figure 1 Schematic diagram of the d-d' direction after the second groove is formed during the manufacturing process of the 3D memory;

[0049] Figure 8a for Figure 1 Schematic diagram of the a-a' direction after the hole is formed during the manufacturing process of the 3D memory;

[0050] Figure 8b for Figure 1 Schematic diagram of the bb' direction after the hole is formed during the manufacturing process of the 3D memory;

[0051] Figure 8c for Figure 1 Schematic diagram of the d-d' direction after the formation of holes in the 3D memory manufacturing process. DETAILED DESCRIPTION

[0052] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Unless there is a conflict, the embodiments of the present disclosure and the features therein may be combined with each other in any manner.

[0053] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0054] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0055] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0056] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0057] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0058] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0059] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. The functions of the "source electrode" and "drain electrode" may be reversed when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be reversed.

[0060] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0061] In this disclosure, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.

[0062] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0063] As used herein, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0064] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there are no distinct microstructural boundaries, such as gaps or discontinuities. Generally, a film layer patterned to form a connection is considered integrated. For example, A and B may be formed using the same material into a single film layer and simultaneously formed into a connected structure through the same patterning process.

[0065] The present disclosure provides a method for manufacturing a 3D memory, including:

[0066] forming conductive layers and insulating layers alternately arranged in sequence on a substrate;

[0067] Performing patterned etching to form a plurality of trenches perpendicular to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in a sequential and cyclic manner, each layer of the patterned structure includes a bit line and a plurality of branches connected to the bit line, and the trenches expose sidewalls of the plurality of branches;

[0068] forming a barrier layer on the inner wall of the trench by an atomic deposition process, wherein at least a portion of the barrier layer covers the exposed sidewalls of the plurality of branches;

[0069] forming an insulating dielectric film on the barrier layer, forming an oxidized insulating dielectric layer from the insulating dielectric film by an oxidation process, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer;

[0070] Using an etching process, removing the insulating dielectric layer on a side of the plurality of branches away from the bit line to form a first groove extending in a direction perpendicular to the substrate;

[0071] depositing a thin film of support material filling the first groove;

[0072] Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure;

[0073] Performing patterned etching to expose ends of the multiple branches away from the bit line, wherein the exposed ends of the multiple branches form multiple first capacitor electrodes, and the multiple first capacitor electrodes are all connected to the support structure;

[0074] A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

[0075] The memory disclosed herein is described below by way of some exemplary embodiments.

[0076] Figure 1 A schematic cross-sectional view of a 3D memory device provided in accordance with an exemplary embodiment along a direction parallel to the substrate is shown. In an exemplary embodiment, Figure 1 As shown, the 3D memory provided in this embodiment may include: multiple layers of memory cells stacked in a direction perpendicular to a substrate, word lines, and bit lines 30. The word lines extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers, connecting to the gate electrodes of transistors in the memory cells of different layers; the bit lines 30 extend in a direction parallel to the substrate and are respectively connected to the source electrodes or drain electrodes of the transistors of multiple memory cells in the same layer.

[0077] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0078] In one exemplary embodiment, a memory cell may include a transistor and a capacitor. In one embodiment, a memory cell comprising only a transistor and a capacitor forms a 1T1C structure; the transistor is connected to the bit line and the capacitor, respectively. The capacitor in this application may be understood as a capacitor.

[0079] In an exemplary embodiment, the transistor includes a first electrode 11, a second electrode 12, a gate electrode 14 extending in a direction perpendicular to the substrate, and a semiconductor layer 13 surrounding the gate electrode 14 and insulated from the gate electrode 14, wherein the semiconductor layer 13 extends on the side surface of the gate electrode 14 to form a ring-shaped semiconductor layer extending in a direction perpendicular to the substrate; wherein the channel between the first electrode 11 and the second electrode 12 is a horizontal channel; and the gate electrode 14 is connected to the word line 40.

[0080] A horizontal channel is a channel in which the direction of carrier transmission is in a plane parallel to the substrate, but the direction of carrier transmission is not limited to being in one direction. In practical applications, the direction of carrier transmission extends in one direction as a whole, but locally, it is related to the shape of the semiconductor layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the semiconductor layer is annular, the source contact area and the drain contact area on the annular semiconductor layer are part of the annular ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the direction of carrier transmission in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. This application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0081] In one exemplary embodiment, the gate electrode 14 extends only in a direction perpendicular to the substrate. The gate electrode 14 includes side surfaces and upper and lower end faces. The side surfaces are generally perpendicular to the substrate. In other words, the side surfaces of the gate electrode 14 correspond to the semiconductor layer 13 and function as the gate electrode control region, where the film layer is perpendicular to the substrate. During actual product manufacturing, the side surfaces of the gate electrode 14 may have localized curved regions, which are also included in the aforementioned aspects of this application.

[0082] In an exemplary embodiment, the material of the gate electrode 14 may include but is not limited to at least one of the following: indium tin oxide (ITO), metal tungsten, titanium nitride, titanium aluminum alloy, tantalum nitride, aluminum doped zinc oxide (AZO), indium zinc oxide (IZO).

[0083] In an exemplary embodiment, the semiconductor layer 13 surrounds the gate electrode 14 and is insulated from the gate electrode 14. The semiconductor layer 13 can be understood as a film layer. The semiconductor layer 13 extends along the side surface of the gate electrode 14. The thickness direction of the semiconductor layer 13 is parallel to the substrate. The length of the semiconductor layer 13 extending along the direction perpendicular to the substrate on the side surface of the gate electrode 14 is the height of the semiconductor layer 13.

[0084] In an exemplary embodiment, the semiconductor layer 13 extends on the side surface of the gate electrode 14 to form a ring extending in a direction perpendicular to the substrate. The semiconductor layer 13 extends only in a direction perpendicular to the substrate, or the main part of the semiconductor layer 13 extends in a direction perpendicular to the substrate, and there may be a horizontal part extending in a horizontal direction at the end.

[0085] Here, "surrounding" can be understood as partially or completely surrounding the gate electrode 14. In some embodiments, the surrounding can be completely surrounding, and the cross-section of the semiconductor layer 13 after the surrounding is a closed ring. The cross-section is intercepted along a direction parallel to the substrate. In some embodiments, the surrounding can be partially surrounding, and the cross-section after the surrounding is not closed, but has a ring shape. For example, a ring with an opening.

[0086] In an exemplary embodiment, the semiconductor layer 13 may be a metal oxide, such as indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, or a metal oxide containing In and / or Sn. When the metal oxide material is IGZO, the transistor has a low leakage current (less than or equal to 1E-15A to 1E-10A), where 1E-15A refers to 10 to the negative 15th power amperes and 1E-10A refers to 10 to the negative 10th power amperes, thereby ensuring a low refresh rate for the dynamic memory. It should be noted that the material of the metal oxide can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of the transistor can meet the requirements, the specific adjustment can be made according to the actual situation.

[0087] In an exemplary embodiment, the material composition of different regions of the word line extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process. The same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not restricted.

[0088] In an exemplary embodiment, stacked transistors in different layers may share a word line extending in a direction perpendicular to the substrate.

[0089] In an exemplary embodiment, the gate electrodes 14 of transistors in different layers are integrally connected to the word lines 40. For example, the gate electrodes 14 of transistors in different layers and the word lines 40 are formed using the same material and through the same film manufacturing process, that is, the gate electrodes 14 of transistors in different layers are part of the word lines.

[0090] In an exemplary embodiment, the semiconductor layers 13 corresponding to transistors of different layers may be located on the sidewalls of the word line 40 and respectively located in different regions extending in a direction perpendicular to the substrate.

[0091] In an exemplary embodiment, the transistor may further include a gate insulating layer 15 surrounding the side surface of the gate electrode 14 , wherein the gate insulating layer 15 is disposed between the gate electrode 14 and the semiconductor layer 13 to separate the gate electrode 14 from the semiconductor layer 13 and insulate the gate electrode 14 from the semiconductor layer 13 .

[0092] In an exemplary embodiment, the gate insulating layer 15 may be made of a high-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0093] In one exemplary embodiment, the first electrode 11 and the second electrode 12 of the same transistor can be located in the same conductive film layer. This can be understood as the first electrode 11 and the second electrode 12 being located in the same metal film layer and formed by patterning a single conductive film layer approximately parallel to the upper surface of the substrate. However, the disclosed embodiments are not limited thereto, and the first electrode 11 and the second electrode 12 can be manufactured separately using different patterning processes.

[0094] In an exemplary embodiment, the first electrode 11 or the second electrode 12 of different transistors may be located in different conductive film layers.

[0095] In an exemplary embodiment, the first electrode 11 and the second electrode 12 extend parallel to the substrate and are arranged perpendicular to the word line 2. The first electrode 11 and the second electrode 12 are respectively located on opposite sides of the semiconductor layer 13 in a direction parallel to the substrate, and the first electrode 11 and the second electrode 12 are electrically connected through the semiconductor layer 13.

[0096] In an exemplary embodiment, the first electrode 11 and the second electrode 12 may be made of a metal material with low resistivity, such as titanium nitride (TiN), tungsten, molybdenum, and the like.

[0097] In an exemplary embodiment, the memory cells in the same layer form an array distributed along the first direction D1 and the second direction D2 , respectively, and the bit line 30 is connected to the second electrode 12 of the transistors in the same layer and the same column. Figure 1, each layer includes four rows and two columns of memory cells, but the disclosed embodiments are not limited thereto. Each layer may include memory cells with other numbers of rows and columns, for example, only one memory cell. The first direction D1 and the second direction D2 are both parallel to the substrate, and the first direction D1 and the second direction D2 intersect. In some embodiments, the first direction D1 and the second direction D2 may be perpendicular.

[0098] In an exemplary embodiment, the second electrodes 12 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30. The second electrodes 12 of the transistors in two adjacent columns in the same layer and the bit line 30 may be an integrated structure.

[0099] In an exemplary embodiment, the second electrode 12 of the transistor may be a portion of a bit line 30 to which the second electrode 12 is connected.

[0100] In one exemplary embodiment, the bit lines 30 may extend along the second direction D2.

[0101] In an exemplary embodiment, the first electrode 11 and the second electrode 12 may extend along the first direction D1 and be perpendicular to the bit line 30 .

[0102] In an exemplary embodiment, the 3D memory may further include a data storage element.

[0103] In an exemplary embodiment, the data storage element is a capacitor, forming a 1T1C storage structure. However, the present disclosure is not limited thereto and can be combined with other transistors to form a 2T0C storage structure, etc.

[0104] In an exemplary embodiment, the capacitor may include a first capacitor electrode 41 and a second capacitor electrode, and the first capacitor electrode 41 is connected to the first electrode 11 .

[0105] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 may be an integrated structure.

[0106] In one exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 of the same transistor can be located in the same conductive film layer. This can be understood as the first capacitor electrode 41 and the first electrode 11 being located in the same metal film layer and formed by patterning a single conductive film layer that is approximately parallel to the upper surface of the substrate. However, the disclosed embodiments are not limited thereto, and the first capacitor electrode 41 and the first electrode 11 can be manufactured separately using different patterning processes.

[0107] In an exemplary embodiment, the first capacitor electrode 41 and the first electrode 11 of the same transistor are formed using the same material and through the same film manufacturing process.

[0108] In an exemplary embodiment, the second capacitor electrodes of the capacitors in the same column at different layers may be connected into an integrated structure. The capacitors in the same column at different layers may share the same capacitor electrode as the second capacitor electrode.

[0109] In an exemplary embodiment, the capacitor may further include a capacitor dielectric layer disposed between the first capacitor electrode 41 and the second capacitor electrode. The capacitor dielectric layer serves as a medium between the first capacitor electrode 41 and the second capacitor electrode.

[0110] In an exemplary embodiment, the 3D memory provided in this embodiment may further include: a support structure 20, the support structure 20 including at least a sidewall extending in a direction perpendicular to the substrate, the sidewall of the support structure 20 being located on a side of the capacitors in the same column of different layers away from the bit line 30, and the first capacitor electrodes 41 of the capacitors in the same column of different layers away from the bit line 30 are both connected to the sidewall of the support structure 20 at one end. The support structure 20 is configured to fix the first capacitor electrode 41 during the formation of the second capacitor electrode to prevent deformation of the first capacitor electrode 41.

[0111] In one exemplary embodiment, the support structure 20 may be silicon nitride.

[0112] The technical solution of this embodiment will be further explained below using the manufacturing process of the memory device of this embodiment. The "patterning process" referred to in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, and is a mature manufacturing process in the relevant art. The "photolithography process" referred to in this embodiment includes film coating, mask exposure, and development, and is a mature manufacturing process in the relevant art. Deposition can be achieved using known processes such as sputtering, evaporation, and chemical vapor deposition; coating can use known coating processes; and etching can use known methods, without specific limitations here. In the description of this embodiment, it should be understood that a "thin film" refers to a thin layer of a certain material produced on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" also requires patterning or photolithography during the entire manufacturing process, it is referred to as a "thin film" before patterning and a "layer" after patterning. The "layer" after patterning or photolithography contains at least one "pattern."

[0113] In this embodiment, each layer includes a plurality of storage units, but the embodiments of the present disclosure are not limited thereto, and each layer may include one storage unit.

[0114] In an exemplary embodiment, the 3D memory may be any of the 3D memories described above, and a manufacturing process of the 3D memory may include:

[0115] Step 101, form an insulating layer, a conductive layer, and a barrier layer.

[0116] Forming the insulating layer, the conductive layer, and the barrier layer includes: forming a conductive layer 31 and an insulating layer 32 that are alternately arranged in sequence on a substrate 101, performing patterned etching on the conductive layer 31 and the insulating layer 32 through a mask plate to form trenches extending in a direction perpendicular to the substrate, each insulating layer 32 forms a first patterned structure that is stacked and distributed in sequence in a cyclic manner, each conductive layer 31 forms a second patterned structure that is stacked and distributed in sequence in a cyclic manner, and each second patterned structure includes bit lines and a plurality of branches that extend in a direction perpendicular to the bit lines and are connected to the bit lines; for example, the plurality of branches in the same layer and the bit lines form a "rich" character shape. The side walls of the trenches expose the side walls of the first patterned structure formed by each insulating layer 32 and the second patterned structure formed by the conductive layer 31.

[0117] Subsequently, using an atomic layer deposition method, deposit a barrier layer 33 on the inner walls of the trenches and on the stacked structure formed by the first patterned structure and the second patterned structure. The barrier layer 33 at least covers the side walls of the first patterned structure and the second patterned structure, and at least a part of the barrier layer 33 covers the exposed side walls of the first patterned structure and the second patterned structure, as Figure 2a , Figure 2b and Figure 2c shown.

[0118] In an exemplary embodiment, the barrier layer 33 can be made of polysilicon or amorphous silicon. The barrier layer 33 is configured to block oxygen from oxidizing the conductive layer 31 in a subsequent oxidation process. For example, it blocks oxygen from oxidizing the plurality of branches of the conductive layer 31.

[0119] In an exemplary embodiment, the thickness of the barrier layer 33 can be 3nm - 15nm, which effectively blocks oxygen from entering the conductive layer 31 and can be completely oxidized in a subsequent oxidation process. When the thickness of the barrier layer 33 is greater than 15nm, in a subsequent oxidation process, the barrier layer 33 cannot be completely oxidized, leaving the barrier layer 33 material (polysilicon or amorphous silicon) on the side walls of the conductive layer 31, increasing the risk of short circuits between storage units in different layers; when the thickness of the barrier layer 33 is less than 3nm, it will cause ineffective blocking of oxygen from entering the conductive layer 31.

[0120] In an exemplary embodiment, the insulating layer and the conductive layer can be deposited using a chemical vapor deposition method.

[0121] In an exemplary embodiment, the substrate can be a semiconductor substrate, such as a silicon substrate. Of course, it can be any substrate that provides support, not just the base, and can be a substrate formed by peripheral circuits on the base, etc.

[0122] In an exemplary embodiment, the insulating layer serves to isolate devices and may be a low-K dielectric layer, ie, a dielectric layer with a dielectric constant K≤3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0123] Step 102: forming an oxidized insulating dielectric layer.

[0124] The formation of the oxidized insulating dielectric layer includes: on the basis of the substrate 101 formed with the aforementioned pattern, spin-on dielectrics (SOD) film is coated on the barrier layer 33, and the insulating dielectric film and the barrier layer 33 are oxidized by a high-temperature oxidation process to form an oxidized insulating dielectric layer 34 from the insulating dielectric film, and the barrier layer 33 is oxidized to form an oxidation barrier layer 33-1. The barrier layer 33 can block oxygen from entering the conductive layer 31 during the high-temperature oxidation process, thereby preventing the conductive layer 31 from being oxidized. Figure 3a 、 Figure 3b and Figure 3c shown.

[0125] In one exemplary embodiment, the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1 are made of the same material, forming an integrally structured insulating dielectric layer 35. For example, the barrier layer 33 is made of polycrystalline silicon or amorphous silicon, the oxidation barrier layer 33-1 is made of silicon oxide, and the oxidized insulating dielectric layer 34 is made of silicon oxide. The oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1 are made of the same material, forming an integrally structured insulating dielectric layer 35, which is made of silicon oxide.

[0126] Step 103: forming a first mask layer.

[0127] Forming the first mask layer includes: forming a first mask layer 36 on the side of the insulating dielectric layer 35 away from the substrate 101 on the basis of the substrate 101 on which the aforementioned pattern is formed, wherein the first mask layer 36 overlaps with the orthographic projections of the bit lines and the multiple branches of the conductive layer 31 on the substrate 101, and does not overlap with the orthographic projections of the insulating dielectric layer 35 on the side of the multiple branches away from the bit lines on the substrate 101. The first mask layer 36 exposes the insulating dielectric layer 35 on the side of the multiple branches away from the bit lines, such as Figure 4a and Figure 4b shown.

[0128] In an exemplary embodiment, the first mask layer 36 may include a hard mask layer 36-1, an anti-reflection layer 36-2 and an optical adhesive layer 36-3 stacked in sequence along a direction perpendicular to the substrate 101, wherein the hard mask layer 36-1 may be titanium or titanium nitride, and the anti-reflection layer 36-2 may be silicon oxynitride.

[0129] Step 104: forming a first groove.

[0130] The first groove is formed by etching away the insulating dielectric layer 35 on the side of the exposed multiple branches away from the bit line on the basis of the substrate 101 having the aforementioned pattern, thereby forming a first groove 51 extending in a direction perpendicular to the substrate 101. The first groove 51 is located on the side of the multiple branches away from the bit line, and the first groove 51 is used to accommodate the support structure formed subsequently. Subsequently, the first mask layer 36 is etched away, as shown in FIG. Figure 5a and Figure 5b shown.

[0131] Step 105: forming a supporting material film.

[0132] The forming of the support material film includes: on the basis of the substrate 101 formed with the aforementioned pattern, using an atomic deposition process to deposit a support material film 21 in the first groove 51 and on the stacked structure formed by the first patterned structure and the second patterned structure, so that the support material film 21 fills the first groove 51; then, using a grinding process to flatten the surface of the support material film 21, such as Figure 6a 、 Figure 6b and Figure 6c shown.

[0133] In an exemplary embodiment, the support material film 21 and the insulating dielectric layer 35 are made of different materials. For example, the support material film 21 may be silicon nitride, and the insulating dielectric layer 35 (including the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1) may be silicon oxide.

[0134] Step 106: forming a second groove.

[0135] The second groove is formed by forming a second mask layer on the side of the support material film 21 away from the substrate 101 on the basis of the substrate 101 on which the aforementioned pattern is formed, and etching away a portion of the support material film between the multiple adjacent branches of the same layer using a first etching process; etching away a portion of the insulating dielectric layer 35 between the multiple adjacent branches of the same layer using a second etching process to form a second groove 52 extending in a direction perpendicular to the substrate 101, wherein the second groove 52 exposes a portion of the sidewalls of the insulating layer 32 and a portion of the sidewalls of the insulating dielectric layer 35 between the multiple branches of different layers, so that the support material film located on the side of the multiple branches away from the bit line forms a support structure 20, and the support structure 20 is connected to the end of the multiple branches away from the bit line, such as Figure 7a and Figure 7b shown.

[0136] In an exemplary embodiment, the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1 in the insulating dielectric layer 35 are both made of silicon oxide. The oxidation barrier layer 33-1 can also serve as a sacrificial layer. During the etching of the insulating dielectric layer 35, the same etching process can be used to etch and remove the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1, which simplifies the process flow and improves the controllability of the process, which is beneficial to improving device performance and improving structural stability.

[0137] In an exemplary embodiment, since the material of the insulating dielectric layer 35 is different from that of the supporting material film, etching of the supporting material film can be avoided during etching of the insulating dielectric layer 35 , thereby ensuring the strength of the supporting structure 20 formed by the subsequent supporting material film.

[0138] Step 106: forming holes.

[0139] The hole formation includes: on the basis of the substrate 101 formed with the aforementioned pattern, using patterned etching, etching the sidewalls of the insulating layer 32 exposed by the second groove 52 and the sidewalls of the insulating dielectric layer 35 along a direction parallel to the substrate to form a hole 53, wherein the hole 53 and the second groove 52 expose the ends of the multiple branches away from the bit line, and the exposed multiple branches away from the end of the bit line form multiple first capacitor electrodes 41, and the ends of the multiple first capacitor electrodes 41 away from the bit line are all connected to the support structure 20 and fixed by the support structure 20, such as Figure 8a 、 Figure 8b and Figure 8c As shown;

[0140] Subsequently, a capacitor dielectric layer and a second capacitor electrode are sequentially formed on one end of the exposed multiple branches away from the bit line. The second capacitor electrode is connected to the first capacitor electrode 41 through the capacitor dielectric layer. The first capacitor electrode 41, the capacitor dielectric layer and the second capacitor electrode form the capacitor of the 3D memory.

[0141] In the manufacturing process of the 3D memory according to the embodiment of the present disclosure, the barrier layer 33 blocks oxygen from oxidizing the multiple branches of the conductive layer 31 , thereby preventing the multiple branches of the conductive layer 31 from being oxidized.

[0142] In the manufacturing process of the 3D memory device of the disclosed embodiment, the oxidation barrier layer 33-1 formed after the oxygen is removed from the barrier layer 33 is made of the same oxidizing material as the oxidized insulating dielectric layer 34. The oxidation barrier layer 33-1 serves as a sacrificial layer. The same etching process can be used to etch away the oxidized insulating dielectric layer 34 and the oxidation barrier layer 33-1. This simplifies the process flow and improves the controllability of the process, which is beneficial to improving device performance and enhancing structural stability.

[0143] In the manufacturing process of the 3D memory according to the embodiment of the present disclosure, by making the oxidation blocking layer 33 - 1 and the support structure of different materials, etching of the support structure can be avoided during etching of the oxidation blocking layer 33 - 1 , thereby ensuring the strength of the support structure.

[0144] The present disclosure also provides an electronic device comprising the 3D memory device described in any of the preceding embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power bank. The storage device may include, but is not limited to, computer memory.

[0145] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A method for manufacturing a 3D memory, characterized in that: include: forming conductive layers and insulating layers alternately arranged in sequence on a substrate; Performing patterned etching to form a plurality of trenches perpendicular to the substrate, so that each layer of the conductive layer forms a patterned structure stacked and distributed in a sequential and cyclic manner, each layer of the patterned structure includes a bit line and a plurality of branches connected to the bit line, and the trenches expose sidewalls of the plurality of branches; forming a barrier layer on the inner wall of the trench by an atomic deposition process, wherein at least a portion of the barrier layer covers the exposed sidewalls of the plurality of branches; forming an insulating dielectric film on the barrier layer, forming an oxidized insulating dielectric layer from the insulating dielectric film by an oxidation process, and oxidizing the barrier layer to form an oxidized barrier layer, wherein the oxidized insulating dielectric layer and the oxidized barrier layer form an insulating dielectric layer; Using an etching process, removing the insulating dielectric layer on a side of the plurality of branches away from the bit line to form a first groove extending in a direction perpendicular to the substrate; depositing a thin film of support material filling the first groove; Using different patterned etching processes to etch the support material film and the insulating dielectric layer respectively, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure; Performing patterned etching to expose ends of the multiple branches away from the bit line, wherein the exposed ends of the multiple branches form multiple first capacitor electrodes, and the multiple first capacitor electrodes are all connected to the support structure; A capacitor dielectric layer and a second capacitor electrode are sequentially formed on the first capacitor electrode.

2. The method for manufacturing a 3D memory according to claim 1, wherein: The oxidized insulating dielectric layer and the oxidation barrier layer are made of the same material, forming an integrated insulating dielectric layer.

3. The method for manufacturing a 3D memory according to claim 1, wherein: Using a first etching process, a portion of the support material film between a plurality of adjacent branches in the same layer is etched away, so that the support material film located on a side of the plurality of branches away from the bit line forms a support structure; Using a second etching process, a portion of the insulating dielectric layer between a plurality of adjacent branches on the same layer is etched away to form a second groove extending in a direction perpendicular to the substrate, wherein the second groove exposes a portion of the sidewall of the insulating layer between the plurality of branches on different layers; Patterned etching is used to etch the sidewall of the insulating layer exposed by the second groove in a direction parallel to the substrate to form a hole. The hole and the second groove expose the multiple branches away from one end of the bit line, and the one end of the exposed multiple branches forms multiple first capacitor electrodes.

4. The method for manufacturing a 3D memory according to claim 1, wherein: The supporting structure and the insulating dielectric layer are made of different materials.

5. The method for manufacturing a 3D memory according to claim 4, wherein: The supporting structure is silicon nitride, and the insulating dielectric layer is silicon oxide.

6. The method for manufacturing a 3D memory according to claim 1, wherein: The thickness of the barrier layer is 3nm-15nm.

7. The method for manufacturing a 3D memory according to claim 1, wherein: The barrier layer is polysilicon or amorphous silicon.

8. A 3D memory, characterized in that: The 3D memory is manufactured by the 3D memory manufacturing method according to any one of claims 1 to 7.

9. The 3D memory according to claim 8, characterized in that The memory cell device comprises multiple layers of memory cells stacked in a direction perpendicular to a substrate, word lines, and bit lines. The word lines extend in a direction perpendicular to the substrate and penetrate the memory cells of different layers and are connected to the memory cells of different layers. The bit lines extend in a direction parallel to the substrate and are respectively connected to multiple memory cells in the same layer. The storage unit includes: a transistor and a capacitor, the capacitor includes a first capacitor electrode, a capacitor dielectric layer and a second capacitor electrode, and the first capacitor electrode is connected to the transistor.

10. An electronic device, characterized in that: Comprising the 3D memory according to claim 8 or 9.

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