Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The preparation method of the semiconductor device comprises the following steps: sequentially and alternately depositing a first insulating film and a second insulating film on a substrate to form a laminated structure; etching the laminated structure to form a first through hole penetrating through the laminated structure in the direction perpendicular to the substrate; forming a sacrificial layer filling the first through hole; etching to remove the second insulating film; depositing a first conductive film to form first electrodes and second electrodes of the plurality of transistors, and separating the first electrodes and the second electrodes of the transistors by sacrificial layers; etching a part of the sacrificial layer in the first through hole to form a second through hole penetrating through the sacrificial layer in the direction perpendicular to the substrate; forming semiconductor layers, gate insulation line layers and word lines of a plurality of transistors in the second through hole in sequence; and etching the sacrificial layer at the periphery of the second through hole, exposing at least part of the semiconductor layer in the interlayer region of the adjacent layers, and etching to remove the exposed semiconductor layer, so that the semiconductor layers of the transistors of the adjacent layers are arranged at intervals.

Description

Technical Field

[0001] This article relates to but is not limited to the field of device design and manufacturing of semiconductor technology, especially a semiconductor device and its preparation method, and electronic equipment. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application. Taking DRAM as an example, the traditional known DRAM has multiple repeated storage cells, each of which has a capacitor and a transistor. The capacitor can store 1 bit of data. After charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "0" and "1" respectively. The transistor is a switch that controls the charging and discharging of the capacitor.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device.

[0006] On the one hand, this embodiment provides a method for preparing a semiconductor device. The semiconductor device includes: a plurality of transistors stacked in a direction perpendicular to a substrate and periodically distributed in different layers, and a word line that penetrates the different layers and extends in a direction perpendicular to the substrate; the transistor includes: a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, a semiconductor layer surrounding the sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer disposed between the gate electrode and the semiconductor layer. The method for preparing the semiconductor device includes: providing a substrate, alternately depositing a first insulating film and a second insulating film on the substrate in sequence to form a stacked structure; etching the stacked structure to form a first through hole that penetrates the stacked structure in a direction perpendicular to the substrate; forming a sacrificial layer that fills the first through hole; etching and removing the second insulating film; depositing a first conductive film to form a first conductive layer, the first conductive layer at least including: the first and second electrodes of the plurality of transistors, the first and second electrodes of the transistors being separated by the sacrificial layer; etching a portion of the sacrificial layer in the first through hole to form a second through hole that penetrates the sacrificial layer in a direction perpendicular to the substrate, the sidewalls of the second through hole exposing the first and second electrodes of the transistor, and in adjacent The side wall of the second through hole in the interlayer area of ​​the layer exposes the sacrificial layer; a semiconductor film, a gate insulating film and a third conductive film are deposited in sequence in the second through hole to form the semiconductor layer, the gate insulating layer and the third conductive layer of the multiple transistors, the third conductive layer includes: the word line and the gate electrodes of the multiple transistors, the multiple transistors arranged in a direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each transistor in the multiple transistors is a part of the word line; the semiconductor layer of the transistor is in contact with the first electrode and the second electrode of the transistor; the sacrificial layer around the second through hole is etched to expose at least part of the semiconductor layer located in the interlayer area of ​​the adjacent layer, and the exposed semiconductor layer is etched to remove the exposed semiconductor layer, so that the semiconductor layers of the transistors in the adjacent layers are arranged at intervals.

[0007] In some exemplary embodiments, etching the stacked structure to form a first through hole penetrating the stacked structure in a direction perpendicular to the substrate includes: forming a hard mask layer on a side of the stacked structure away from the substrate; using the hard mask layer, etching the first insulating film and the second insulating film of the stacked structure to form a first initial via hole in the first insulating film and a second via hole in the second insulating film, wherein the first initial via hole and the second via hole are aligned and connected in a direction perpendicular to the substrate; wet etching the first insulating film to expand the first initial via hole to become a first via hole; the first via hole and the second via hole are connected to form the first through hole, and the orthographic projection of the second via hole on the substrate is within the orthographic projection range of the first via hole on the substrate.

[0008] In some exemplary embodiments, the depositing of the first conductive film to form the first conductive layer includes: depositing the first conductive film, and dry-etching the first conductive film so that the edge of the etched first conductive film is flush with the edge of the first insulating film; and wet-etching the first conductive film so that the edge of the first conductive film is retracted toward the inside of the edge of the first insulating film, and the first conductive films located on both sides of the sacrificial layer are disconnected to form the first electrode and the second electrode of the transistor.

[0009] In some exemplary embodiments, the thickness of the wet etching for the first insulating film is the same as the thickness of the wet etching for the first conductive film. In some exemplary embodiments, the semiconductor device further includes: a plurality of capacitors, the capacitors including a first electrode plate and a second electrode plate, the second electrode of the transistor and the first electrode plate of the connected capacitor are an integrated structure connected to each other; after forming the first conductive layer and before etching a portion of the sacrificial layer in the first through hole, the preparation method further includes: depositing a first insulating film to cover the first conductive layer; etching a portion of the first insulating film to expose a portion of the surface of the first electrode and the second electrode of the plurality of transistors and a portion of the surface of the sacrificial layer facing the first electrode; depositing a third insulating film and a second conductive film in sequence in the area where the first insulating film is removed to form a third insulating layer and a second conductive layer, the second conductive layer including: the second electrode plate of the capacitor, the third insulating layer being located between the first electrode plate and the second electrode plate of the capacitor.

[0010] In some exemplary embodiments, after etching a portion of the sacrificial layer within the first through hole to form a second through hole that penetrates the sacrificial layer in a direction perpendicular to the substrate, the preparation method further includes: etching the sacrificial layer within the second through hole to enlarge the second through hole and thinning the sacrificial layer outside the second through hole.

[0011] In some exemplary embodiments, the etching of the sacrificial layer around the second through hole exposes at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers, and etching away the exposed semiconductor layer so that the semiconductor layers of the transistors in the adjacent layers are spaced apart, comprising: etching the first insulating film in sequence by dry etching and wet etching to expose the sacrificial layer located in the interlayer region of the adjacent layers, and etching the sacrificial layer to expose at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers; and wet etching the exposed semiconductor layer so that the semiconductor layers of the transistors in different layers are spaced apart.

[0012] In some exemplary embodiments, the sacrificial layer is made of a material having a selectivity ratio with respect to the semiconductor layer by wet etching.

[0013] In some exemplary embodiments, the material of the sacrificial layer includes aluminum oxide.

[0014] On the other hand, the present embodiment provides a semiconductor device, comprising: a word line and a plurality of transistors. The plurality of transistors are stacked along a direction perpendicular to the substrate and periodically distributed in different layers; the word line runs through the different layers and extends along a direction perpendicular to the substrate. The transistor comprises: a gate electrode extending along a direction perpendicular to the substrate, a semiconductor layer surrounding the side wall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer; a plurality of transistors arranged along a direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each of the plurality of transistors is a part of the word line; the semiconductor layers of the plurality of transistors are arranged at intervals. The word line in the interlayer region of adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in the interlayer region of adjacent layers is surrounded by the first insulating layer.

[0015] In some exemplary embodiments, at least a portion of the gate insulating layer in the interlayer region of adjacent layers contacts an independent semiconductor layer, and the semiconductor layer in the interlayer region of adjacent layers contacts a sacrificial layer; the semiconductor layer in the interlayer region of adjacent layers is disconnected from the semiconductor layer of the transistor.

[0016] In some exemplary embodiments, the material of the sacrificial layer includes: aluminum oxide.

[0017] In some exemplary embodiments, the word line includes: a first main portion and a second main portion extending in a direction perpendicular to the substrate and alternately connected, the first main portion serving as a gate electrode of the transistor, and the second main portion being located in an interlayer region of an adjacent layer; an orthographic projection of the first main portion on the substrate is located within the range of an orthographic projection of the second main portion on the substrate.

[0018] In some exemplary embodiments, the gate insulating layer includes: a first insulating portion and a second insulating portion extending in a direction perpendicular to the substrate and alternately connected, the first insulating portion is located between the semiconductor layer and the gate electrode of the transistor, the second insulating portion is located in the interlayer region of adjacent layers, and the second insulating portion forms a step on a surface of the first insulating portion protruding from the plane of the substrate parallel to the substrate; the semiconductor layer of the transistor is distributed on the side walls of the first insulating portion and the step.

[0019] On the other hand, this embodiment provides an electronic device, including the semiconductor device as described above.

[0020] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0022] Figure 1 is a three-dimensional schematic diagram of a semiconductor device according to at least one embodiment of the present disclosure;

[0023] Figure 2 for Figure 1 A schematic top view of a semiconductor device shown;

[0024] Figure 3 for Figure 1 The cross-sectional view along the AA' direction;

[0025] Figure 4 for Figure 1 A three-dimensional schematic diagram of a semiconductor device after omitting the first insulating layer;

[0026] Figure 5 for Figure 4 A partial enlarged schematic diagram of the middle dotted line area;

[0027] Fig. 6A is a three-dimensional schematic diagram of a stacked structure according to at least one embodiment of the present disclosure;

[0028] Figure 6B for Fig. 6A The cross-sectional schematic diagram of the stacked structure shown in the planes where the first direction and the third direction are located;

[0029] Fig. 7A It is a three-dimensional schematic diagram of a stacked structure after a first through hole is formed in at least one embodiment of the present disclosure;

[0030] Figure 7B is a cross-sectional view of the stacked structure along the AA' direction after one etching;

[0031] Figure 7C is a cross-sectional view of the stacked structure along the AA' direction after the first through hole is formed;

[0032] Fig.7D is a cross-sectional view of the stacked structure along the BB' direction after the first through hole is formed;

[0033] Fig. 7E A cross-sectional view of the second insulating film parallel to the plane where the substrate is located after the first through hole is formed;

[0034] Figure 7F A cross-sectional view of the first insulating film parallel to the plane where the substrate is located after the first through hole is formed;

[0035] Fig. 8AA three-dimensional schematic diagram of a stacked structure after a sacrificial layer is formed according to at least one embodiment of the present disclosure;

[0036] Figure 8B for Fig. 8A The cross-sectional view along the AA' direction;

[0037] Figure 8C for Fig. 8A A cross-sectional view of the first insulating film in a plane parallel to the substrate;

[0038] Fig.9A A three-dimensional schematic diagram of a stacked structure after grooves are formed in at least one embodiment of the present disclosure;

[0039] Fig. 9B for Fig.9A The cross-sectional view along the AA' direction;

[0040] Fig. 10A A three-dimensional schematic diagram of a stacked structure after a support layer is formed according to at least one embodiment of the present disclosure;

[0041] Fig. 10B for Fig. 10A The cross-sectional view along the AA' direction;

[0042] Fig. 10C for Fig. 10A A schematic top view of the laminated structure;

[0043] Fig.11A A three-dimensional schematic diagram of a stacked structure after a first hollow portion and a second hollow portion are formed in at least one embodiment of the present disclosure;

[0044] Fig. 11B for Fig.11A The cross-sectional view along the BB' direction;

[0045] Fig. 11C for Fig.11A A schematic top view of the laminated structure;

[0046] Fig. 12A It is a three-dimensional schematic diagram of the stacked structure after the second insulating film is removed according to at least one embodiment of the present disclosure;

[0047] Fig. 12B for Fig. 12A The cross-sectional view along the AA' direction;

[0048] Fig. 12C for Fig. 12A The cross-sectional view along the BB' direction;

[0049] Fig.13A It is a three-dimensional schematic diagram of a stacked structure after the first conductive film is deposited in at least one embodiment of the present disclosure;

[0050] Fig. 13B for Fig.13A A cross-sectional view of the first insulating film in a plane parallel to the substrate;

[0051] Fig.14A is a three-dimensional schematic diagram of a stacked structure after the first conductive film is etched once in at least one embodiment of the present disclosure;

[0052] Fig. 14B for Fig.14A The cross-sectional view along the BB' direction;

[0053] Fig. 14C for Fig.14A A schematic top view of the laminated structure;

[0054] Fig.15A is a three-dimensional schematic diagram of a stacked structure after the first conductive film is etched twice in at least one embodiment of the present disclosure;

[0055] Fig. 15B for Fig.15A The cross-sectional view along the AA' direction;

[0056] Fig. 15C for Fig.15A The cross-sectional view along the BB' direction;

[0057] Fig.16A It is a three-dimensional schematic diagram of a stacked structure after the first insulating film is deposited again according to at least one embodiment of the present disclosure;

[0058] Fig. 16B for Fig.16A A schematic top view of the laminated structure;

[0059] Fig.17A A three-dimensional schematic diagram of a stacked structure after a sixth hollow portion and a seventh hollow portion are formed in at least one embodiment of the present disclosure;

[0060] Fig. 17B for Fig.17A The cross-sectional view along the AA' direction;

[0061] Fig. 17C for Fig.17A A schematic top view of the laminated structure;

[0062] Fig.18A A three-dimensional schematic diagram of a stacked structure after forming a second electrode plate of a capacitor according to at least one embodiment of the present disclosure;

[0063] Fig.18B for Fig.18A The cross-sectional view along the AA' direction;

[0064] Fig.18C for Fig.18AA schematic top view of the laminated structure in FIG.

[0065] Fig.19A A three-dimensional schematic diagram of a stacked structure after etching a sacrificial layer according to at least one embodiment of the present disclosure;

[0066] Fig.19B for Fig.19A The cross-sectional view along the AA' direction;

[0067] Fig.19C for Fig.9A A schematic top view of the laminated structure;

[0068] Fig. 20A A cross-sectional view of the stacked structure along the AA' direction after the second through hole is widened according to at least one embodiment of the present disclosure;

[0069] Fig. 20B A schematic top view of the stacked structure after the second through hole is widened in at least one embodiment of the present disclosure;

[0070] Fig.21A A three-dimensional schematic diagram of a stacked structure after a semiconductor layer, a gate insulating layer and a third conductive layer are formed according to at least one embodiment of the present disclosure;

[0071] Fig. 21B for Fig.21A The cross-sectional view along the AA' direction;

[0072] Fig. 21C for Fig.21A A schematic top view of a stacked structure;

[0073] Fig.22A is a three-dimensional schematic diagram of a stacked structure after etching the first insulating film in at least one embodiment of the present disclosure;

[0074] Fig. 22B for Fig.22A A schematic top view of a stacked structure;

[0075] Fig.23A is a three-dimensional schematic diagram of a stacked structure after etching a sacrificial layer in at least one embodiment of the present disclosure;

[0076] Fig. 23B for Fig.23A The cross-sectional view along the AA' direction;

[0077] Fig.23C for Fig.23A A schematic top view of a stacked structure;

[0078] Fig.24A It is a three-dimensional schematic diagram of a stacked structure after etching and exposing a semiconductor layer in at least one embodiment of the present disclosure;

[0079] Fig. 24B for Fig.24A The cross-sectional view along the AA' direction;

[0080] Fig.24C for Fig.24A A schematic top view of a laminated structure;

[0081] Fig.25 FIG. 4 is a schematic cross-sectional view of another semiconductor device along the AA′ direction according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0083] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0084] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0085] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0086] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a physical connection or a signal connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0087] In this specification, "connection" or "electrical connection" may include the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0088] In this specification, a transistor may include a gate (also referred to as a gate electrode), a channel, a first electrode, and a second electrode. Among them, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. The source electrode may also be referred to as a source electrode terminal, a source region, or a source electrode, and the drain electrode may also be referred to as a drain electrode terminal, a drain region, or a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0089] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0090] The "A and B are arranged in the same layer" mentioned in the present disclosure includes film layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes. A and B arranged in the same layer may be located on the same horizontal plane but not necessarily on the same film layer, or located in different regions of the same film layer but not necessarily on the same horizontal plane.

[0091] In the embodiment of the present disclosure, "A and B are interconnected integral structures" may include a film layer patterned to form a connection as an integral structure. For example, A and B are structures formed in a film layer using the same material and formed simultaneously with a connection relationship through the same patterning process.

[0092] In the embodiments of the present disclosure, "substrate" means and includes a base material or structure on which a material such as a vertical field effect transistor is formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0093] The present embodiment provides a semiconductor device and a method for manufacturing the same, and an electronic device, which can effectively reduce or eliminate parasitic MOS tubes (parasitic MOS for short) while ensuring the size of the semiconductor device.

[0094] This embodiment provides a semiconductor device, including: a word line (WL) and a plurality of transistors. The plurality of transistors are stacked along a direction perpendicular to the substrate and periodically distributed in different layers; the word line runs through the different layers and extends along a direction perpendicular to the substrate. The transistor includes: a gate electrode extending along a direction perpendicular to the substrate, a semiconductor layer surrounding the side wall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer. The plurality of transistors arranged along a direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each of the plurality of transistors is a part of the word line; the semiconductor layers of the plurality of transistors are arranged at intervals; the word line in the interlayer region of adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in the interlayer region of adjacent layers is surrounded by the first insulating layer.

[0095] The semiconductor device of this embodiment can effectively reduce or eliminate the parasitic MOS in at least part of the interlayer region by spacing the semiconductor layers of the multiple transistors, thereby improving the stability of the device.

[0096] In some exemplary embodiments, the channel between the first electrode and the second electrode of the transistor is a horizontal channel. A horizontal channel is a channel in which the carrier transmission direction is generally in a plane parallel to the substrate.

[0097] In some exemplary embodiments, at least part of the gate insulating layer in the interlayer region of adjacent layers contacts the independent semiconductor layer, and the semiconductor layer in the interlayer region of adjacent layers contacts the sacrificial layer; the semiconductor layer in the interlayer region of adjacent layers is disconnected from the semiconductor layer of the transistor. In some examples, the material of the sacrificial layer includes: aluminum oxide. In some examples, during the preparation of the semiconductor device, the semiconductor layer in the interlayer region is removed by sequentially exposing the sacrificial layer and the semiconductor layer in the interlayer region. Limited by the process conditions, when there is residue in the sacrificial layer, the semiconductor layer protected by the sacrificial layer may partially remain, thereby leaving a semiconductor layer disconnected from the semiconductor layer of the transistor outside the gate insulating layer in the interlayer region. In this example, the parasitic MOS in the interlayer region is reduced by etching away the small range of semiconductor layer exposed by the sacrificial layer.

[0098] In some exemplary embodiments, a word line may include: a first main body and a second main body extending in a direction perpendicular to the substrate and alternately connected, the first main body may serve as a gate electrode of a transistor, and the second main body may be located in an interlayer region of an adjacent layer; an orthographic projection of the first main body on the substrate may be located within the orthographic projection of the second main body on the substrate. In this example, the cross-sectional sizes of the word line at different positions in the extension direction may be different. For example, the cross-sectional size of the first main body of the word line serving as the gate electrode of the transistor may be smaller than the cross-sectional size of the second main body of the word line located in the interlayer region. However, this embodiment is not limited to this. In other examples, the cross-sectional sizes of the word line at different positions in the extension direction may be the same.

[0099] In some exemplary embodiments, the gate insulating layer may include: a first insulating portion and a second insulating portion extending in a direction perpendicular to the substrate and alternately connected, the first insulating portion may be located between the semiconductor layer and the gate electrode of the transistor, the second insulating portion may be located in the interlayer region of the adjacent layers, the second insulating portion forms a step on the surface of the first insulating portion protruding parallel to the plane where the substrate is located; the semiconductor layer of the transistor is distributed on the sidewall of the first insulating portion and the step. This example utilizes the morphology of the word line to form a step on the gate insulating layer, and the step can prevent the semiconductor layer damaged in the interlayer region from extending to the layer where the transistor is located, thereby ensuring the performance of the transistor.

[0100] The solution of this embodiment is described below by means of some examples.

[0101] Figure 1 The figure is a three-dimensional schematic diagram of a semiconductor device according to at least one embodiment of the present disclosure. Figure 2 for Figure 1 A schematic top view of a semiconductor device is shown. Figure 3 for Figure 1 Cross-sectional view along AA' direction. Figure 4 for Figure 1A three-dimensional schematic diagram of a semiconductor device after the first insulating layer is omitted. Figure 5 for Figure 4 A partial enlarged schematic diagram of the dotted line area. In this example, three layers of memory cells stacked in a direction perpendicular to the substrate are used as an example for illustration, and each layer of memory cells may include a plurality of memory cells arranged in an array along a first direction D1 and a second direction D2, for example, six memory cells arranged in a 2×3 array.

[0102] In some examples, the plane where the first direction D1 and the second direction D2 are located may be parallel to the plane where the substrate 100 is located, and the third direction D3 may be perpendicular to the plane where the substrate 100 is located. The first direction D1 and the second direction D2 may intersect, for example, the first direction D1 may be perpendicular to the second direction D2. In a plane parallel to the substrate, a plurality of memory cells arranged along the first direction D1 may be referred to as a row of memory cells, and a plurality of memory cells arranged along the second direction D2 may be referred to as a column of memory cells. In this example, in each layer, two columns of memory cells may be arranged along the first direction D1, and three rows of memory cells may be arranged along the second direction D2.

[0103] In some examples, such as Figures 1 to 3 As shown, the semiconductor device may include: layer regions 300 and interlayer regions 400 alternately arranged along a third direction D3. The layer region 300 may include a plurality of memory cells arranged in an array. The memory cell may include: a transistor and a capacitor. The transistor may include: a first electrode 31, a second electrode 32, a gate electrode 33, and a semiconductor layer 34. The capacitor may include: a first plate 41 and a second plate 42. The first electrode 31 of the transistor of the memory cell is connected to the first plate 41 of the capacitor, for example, the first electrode 31 of the transistor and the first plate 41 of the connected capacitor may be an integrated structure connected to each other. A plurality of memory cells (for example, six memory cells) located in the same layer may be electrically connected to the same bit line 22. For example, the bit line 22 may extend along the second direction D2. The second electrodes 32 of the transistors of two adjacent columns of memory cells may be connected to the same bit line 22, for example, the second electrodes 32 of the transistors of two adjacent columns of the same layer may be an integrated structure connected to each other.

[0104] In some examples, such as Figures 1 to 3As shown, the gate electrodes 33 of the transistors of the multiple memory cells arranged along the third direction D3 can be connected to the same word line 21, and the gate electrodes 33 of the multiple transistors and the word line 21 can be an integrated structure connected to each other. The gate electrode 33 of the transistor can be insulated from the semiconductor layer 34. The semiconductor layer 34 extends on the side wall of the gate electrode 33 to form a ring structure extending along the third direction D3. The semiconductor layer 34 can completely surround the gate electrode 33. For example, the semiconductor layer 34 surrounding the gate electrode 33 can be a closed ring in a cross section parallel to the plane where the substrate is located. In other examples, the semiconductor layer 34 can partially surround the gate electrode 33, and the semiconductor layer 34 surrounding the gate electrode 33 can not be closed in a cross section parallel to the plane where the substrate is located, but has an open ring.

[0105] In some examples, such as Figure 1 and Figure 3 As shown, a gate insulating layer 35 may be provided around the sidewall of the word line 21, and the gate insulating layer 35 is in direct contact with the word line 21, and extends on the sidewall of the word line 21 to form a ring structure extending along the third direction D3. The gate insulating layer 35 may include: a first insulating portion 351 located in the layer region 300 and a second insulating portion 352 located in the interlayer region 400. The first insulating portion 351 and the second insulating portion 352 may be an integral structure connected to each other. The first insulating portion 351 is located between the semiconductor layer 34 and the gate electrode 33 of the transistor, and is in direct contact with the semiconductor layer 34 and the gate electrode 33 to ensure that the semiconductor layer 34 and the gate electrode 33 are insulated. The interlayer region 400 may not be provided with a semiconductor layer, so that the semiconductor layers 34 of the adjacent layer regions 300 may be disconnected and spaced. The second insulating portion 352 of the gate insulating layer 35 of the interlayer region 400 may be in direct contact with the first insulating layer 51. The first insulating layer 51 may surround the second insulating portion 352, and the second insulating portion 352 may surround the word line 21.

[0106] In some examples, such as Figure 3 As shown, the word line 21 may include a first main body 211 and a second main body 212 extending along a third direction D3 and alternately connected. The first main body 211 may be located in the layer region 300, the first main body 211 may serve as a gate electrode 33 of a transistor, and the second main body 212 may be located in the interlayer region 400. The first main body 211 and the second main body 212 are an integral structure connected to each other. The orthographic projection of the first main body 211 on the substrate 100 may be located within the orthographic projection range of the second main body 212 on the substrate 100. Taking the example that the cross-sectional shapes of the first main body 211 and the second main body 212 of the word line 21 are both square in parallel to the substrate, the side length of the first main body 211 may be smaller than the side length of the second main body 212.

[0107] In some examples, such as Figures 3 to 5As shown, due to the different sizes of the first main body 211 and the second main body 212 of the word line 21, a step 200 can be formed between the first insulating portion 351 and the second insulating portion 352 of the gate insulating layer 35. The second insulating portion 352 can form a step 200 on the surface of the first insulating portion 351 that is parallel to the plane where the substrate is located. The semiconductor layer 34 of the transistor can be distributed on the sidewall of the first insulating portion 351 and the step 200. By forming the step 200, the semiconductor layer damaged in the interlayer region can be prevented from extending to the layer region 300, and the performance of the transistor can be guaranteed.

[0108] In some examples, such as Figure 3 As shown, the first electrode 31 of the transistor and the first plate 41 of the capacitor can be an integrated structure connected to each other. The integrated structure of the first electrode 31 and the first plate 41 can extend in a plane parallel to the substrate. The first electrode 31 and the second electrode 32 of the transistor can be in direct contact with the semiconductor layer 34. The second plate 42 of the capacitor can be located on a side of the first plate 31 away from the gate electrode. Figure 1 and Figure 3 As shown, for two columns of memory cells arranged along the first direction D1, the second plate of the capacitor of the first column of memory cells can be located on the side of the connected word line 21 in the opposite direction of the first direction D1, and the second plate of the capacitor of the second column of memory cells can be located on the side of the connected word line 21 in the first direction D1. The second plates of the capacitors of the plurality of memory cells can be an integrated structure connected to each other. A third insulating layer 52 can be provided between the second plate 42 of the capacitor and the first plate 41.

[0109] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.

[0110] In some examples, the manufacturing process of the semiconductor device may include the following steps. In this example, the cross-sectional view along the AA' direction refers to a cross-sectional view passing through the AA' direction and perpendicular to the plane where the substrate is located, and the cross-sectional view along the BB' direction refers to a cross-sectional view passing through the BB' direction and perpendicular to the plane where the substrate is located.

[0111] (1) A first insulating film 11 and a second insulating film 12 are alternately deposited on a substrate 100 to form a stacked structure 10. Fig. 6AIt is a three-dimensional schematic diagram of a stacked structure according to at least one embodiment of the present disclosure. Figure 6B for Fig. 6A The cross-sectional schematic diagram of the stacked structure shown is a plane where the first direction and the third direction are located.

[0112] In some examples, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. The material of the first insulating film 11 may include an oxide, such as silicon dioxide (SiO2). The material of the second insulating film 12 may include a nitride. Nitride refers to a class of compound materials composed of nitrogen and metal elements (such as aluminum, gallium, titanium, etc.).

[0113] In some examples, the stacked structure 10 may include: four first insulating films 11 and three second insulating films 12 that are alternately stacked. This embodiment does not limit the number of first insulating films 11 and second insulating films 12 included in the stacked structure. In some examples, the thickness of the first insulating film 11 closest to the substrate 100 and the first insulating film 11 farthest from the substrate 100 may be substantially the same, and may be greater than the thickness of the first insulating film 11 sandwiched by two second insulating films 12.

[0114] In some examples, the first insulating film 11 and the second insulating film 12 may cover the substrate 100. The orthographic projection of the first insulating film 11 on the substrate 100 may coincide with the orthographic projection of the second insulating film 12 on the substrate 100, for example, the orthographic projection shape may be a rectangle, and the orthographic projection of the first insulating film 11 on the substrate 100 may coincide with the substrate 100.

[0115] (2) A hard mask layer (HM) 13 is formed on the stacked structure by a patterning process, and the stacked structure is etched twice using the hard mask layer 13 to form a plurality of first through holes K1 penetrating the stacked structure in the third direction D3.

[0116] Fig. 7A It is a three-dimensional schematic diagram of the stacked structure after the first through hole is formed according to at least one embodiment of the present disclosure. Figure 7B It is a cross-sectional view of the stacked structure along the AA' direction after one etching. Figure 7C It is a cross-sectional view of the stacked structure along the AA' direction after the first through hole is formed. Fig.7D It is a cross-sectional view of the stacked structure along the BB' direction after the first through hole is formed. Fig. 7E It is a cross-sectional view of the second insulating film after the first through hole is formed, parallel to the plane where the substrate is located. Figure 7F It is a cross-sectional view of the first insulating film after the first through hole is formed, parallel to the plane where the substrate is located.

[0117] In some examples, a hard mask film is coated on the surface of the first insulating film 11 farthest from the substrate 100, and a hard mask layer 13 having a mask pattern is formed by an ATH lithography process. The hard mask layer 13 can be made of materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), titanium nitride (TiN), and amorphous carbon (ACHM), and is mainly used in multiple exposure processes, etc.

[0118] Subsequently, the stacked structure is etched twice. In this step, the stacked structure can be etched once using the hard mask layer 13 to form a plurality of first initial via holes K11a in the first insulating film 11 and a plurality of second via holes K12 in the second insulating film 12. The first initial via holes K11a and the second via holes K12 are aligned and connected in the third direction D3, as shown in FIG. Figure 7B As shown. The orthographic projections of the first initial via K11a and the second via K12 on the substrate 100 may overlap, for example, the orthographic projection shapes may both be rectangular. Subsequently, the first insulating film 11 is further etched for a second time, so that the first initial via K11a expands outward to form the first via K11. For example, the first insulating film 11 is etched for a second time by wet etching (for example, oxide wet etching). In the wet etching, an acid solution with a relatively high etching selectivity for the first insulating film 11 and the second insulating film 12 may be selected, and the first insulating film 11 is laterally etched in the first initial via K11a in a direction away from the center of the first initial via K11a by a certain thickness (for example, the thickness of the wet etching is L3), so that part of the first insulating film 11 surrounding the first initial via K1a is etched away, exposing part of the surface of the second insulating film 12 parallel to the plane of the substrate, and forming the first via K11, as shown in FIG. Figure 7F In this example, by selecting a solution with a high etching selectivity ratio for etching, the second etching can be performed only on the first insulating film 11, and the second insulating film 12 is almost not etched, so that the size of the second via hole K12 can be maintained.

[0119] In some examples, such as Figure 7C As shown, the first through hole K1 of the stacked structure may include: a first through hole K11 and a second through hole K12 that penetrate and are alternately connected along the third direction D3. Figure 7F As shown, the orthographic projection of the first via hole K11 on the substrate 100 may be substantially a rectangle with rounded or chamfered corners. Fig. 7EAs shown, the orthographic projection of the second via K12 on the substrate 100 may be roughly rectangular. The orthographic projection of the first via K11 on the substrate 100 may cover the orthographic projection of the second via K12 on the substrate 100. The orthographic projections of the center positions of the first via K11 and the second via K12 on the substrate 100 may overlap. The sidewall of the second via K12 exposes the second insulating film 12, and the sidewall of the first via K11 exposes the first insulating film 11 and the second insulating film 12 away from or close to the surface of the substrate.

[0120] In some examples, such as Figure 7C As shown, taking the first through hole K11 and the second through hole K12 of the first through hole K1 as squares in the cross section parallel to the substrate, the side length of the first through hole K11 located in the first insulating film 11 is L1, and the side length of the second through hole K12 located in the second insulating film 12 is L2, then L1 = L2 + 2 × L3. For example, the etching thickness L3 can be 15 nanometers (nm) to 30nm, such as about 25nm or 30nm.

[0121] In this example, the first through hole formed by two etchings has different sizes in the first insulating film and the second insulating film, which is beneficial to controlling the morphology of the word line in the subsequent preparation process.

[0122] (3) Depositing a sacrificial film on the substrate 100 to form a sacrificial layer 15 that fills the plurality of first through holes, so that the surface of the stacked structure away from the substrate 100 is flush. In some examples, after depositing the sacrificial film in the first through holes of the stacked structure, chemical mechanical polishing (CMP) can be performed to achieve surface flatness on the side of the stacked structure away from the substrate 100.

[0123] Fig. 8A The diagram is a three-dimensional schematic diagram of a stacked structure after a sacrificial layer is formed according to at least one embodiment of the present disclosure. Figure 8B for Fig. 8A Cross-sectional view along AA' direction. Figure 8C for Fig. 8A A cross-sectional view of the first insulating film in a plane parallel to the substrate.

[0124] In some examples, such as FIG. 8A to FIG. 8C As shown, the sacrificial layer 15 may include a plurality of filling pillars 151 extending along the third direction D3, and one filling pillar 151 may fill a corresponding first through hole K1. The plurality of filling pillars 151 may be arranged in two columns along the first direction D1 and in three rows along the second direction D2.

[0125] In some examples, the sacrificial layer 15 may be made of a material having a selectivity ratio with respect to the wet etching of the semiconductor layer. For example, the material of the sacrificial layer 15 may include aluminum oxide (Al 2 O 3 ).

[0126] The sacrificial layer in this example can protect the semiconductor layer of the transistor in subsequent processes, and can etch the semiconductor layer in the interlayer region by selectively removing the sacrificial layer in a small range, so as to reduce or eliminate parasitic MOS while ensuring the stability of the mechanical structure.

[0127] (3) The first insulating film 11 and the second insulating film 12 forming the stacked structure of the aforementioned pattern are etched to form grooves Q1 arranged opposite to each other in the first direction D1, and a supporting material is deposited in the grooves Q1 to form a supporting layer 16.

[0128] Fig.9A It is a three-dimensional schematic diagram of a stacked structure after grooves are formed according to at least one embodiment of the present disclosure. Fig. 9B for Fig.9A Cross-sectional view along AA' direction. Fig. 10A It is a three-dimensional schematic diagram of a stacked structure after a support layer is formed according to at least one embodiment of the present disclosure. Fig. 10B for Fig. 10A Cross-sectional view along AA' direction. Fig. 10C for Fig. 10A Schematic top view of the laminated structure.

[0129] In some examples, such as Fig.9A and Fig. 9B As shown, the stacked structure is etched to remove the two side edges of the first insulating film 11 and the second insulating film 12 along the first direction D1, forming two grooves Q1, which can expose the two side ends of the first insulating film 11 and the second insulating film 12 in the first direction D1, and a portion of the surface of the substrate 100 close to the first insulating film 11. FIG. 10A to FIG. 10C As shown, a support material is deposited in the two grooves Q1 to form a support layer 16. The support layer 16 can cover the end surfaces of the first insulating film 11 and the second insulating film 12 on both sides in the first direction D1 and a part of the surface of the substrate 100 close to the first insulating film 11. The edge of the support layer 16 can be flush with the edge of the substrate 100 by CMP. The orthographic projection of the support layer 16 on the substrate 100 can be located within the range of the substrate 100.

[0130] In some examples, the support layer 16 may be made of silicon oxynitride (SiON) or other insulating materials. The support layer 16 may be made of insulating materials to avoid generating capacitance with the second plate of the capacitor formed subsequently, thereby ensuring the performance of the semiconductor device.

[0131] (4) Etch the first insulating film 11 and the second insulating film 12 of the stacked structure forming the foregoing pattern to form a plurality of first hollow portions 171 and a plurality of second hollow portions 172.

[0132] Fig.11A This is a three-dimensional schematic diagram of the stacked structure after forming the first hollow portion and the second hollow portion in at least one embodiment of the present disclosure. Fig. 11B is Fig.11A The cross-sectional view along the BB' direction in Fig. 11C is Fig.11A The top view schematic diagram of the stacked structure in

[0133] In some examples, as FIG. 11A to FIG. 11C shown, a photolithography process can be used to etch the stacked structure to form a plurality of first hollow portions 171 and a plurality of second hollow portions 172. In a plane parallel to the substrate, the first hollow portion 171 can be located between adjacent filling columns of the sacrificial layer 15 in the second direction D2, and the second hollow portion 172 can be adjacent to one filling column in the second direction D2. The orthographic projections of the first hollow portion 171 and the second hollow portion 172 on the substrate 100 can be generally rectangular. The orthographic projection of the etched stacked structure on the substrate 100 can be generally in the shape of the Chinese character "丰" (abundant). The sides of the first hollow portion 171 and the second hollow portion 172 can expose the first insulating film 11 and the second insulating film 12. In the first direction D1, adjacent first hollow portions 171 are separated by the first insulating film 11 and the second insulating film 12, and in the second direction D2, adjacent first hollow portions 171 are separated by the first insulating film 11, the second insulating film 12, and the sacrificial layer 15. In the first direction D1, adjacent second hollow portions 172 are separated by the first insulating film 11 and the second insulating film 12, and in the second direction D2, adjacent first hollow portions 171 and second hollow portions 172 are separated by the first insulating film 11, the second insulating film 12, and the sacrificial layer 15.

[0134] (5) Etch the second insulating film of the stacked structure forming the foregoing pattern to completely remove the second insulating film and form a plurality of third hollow portions 173 that connect the first hollow portion 171 and the second hollow portion 172. Subsequently, deposit a first conductive film on the stacked structure and perform two etchings on the first conductive film to form a first conductive layer. The first conductive layer includes: the first electrodes and the second electrodes of a plurality of transistors, and bit lines. The first conductive film in this example can fill the area where the removed second insulating film is located.

[0135] Fig. 12A This is a three-dimensional schematic diagram of the stacked structure after removing the second insulating film in at least one embodiment of the present disclosure. Fig. 12B is Fig. 12A The cross-sectional view along the AA' direction in Fig. 12C is Fig. 12ACross-sectional view along BB' direction.

[0136] In some examples, such as FIG. 12A to FIG. 12C As shown, the second insulating film 12 in the stacked structure can be etched cleanly by dry etching to expose a portion of the surface of the filling column 151 of the sacrificial layer 15. In the third direction D3, the third hollow portion 173 can be located between adjacent first insulating films 11, and the third hollow portion 173 can connect the first hollow portion 171 and the second hollow portion 172. The first insulating film of this example can ensure the structural stability parallel to the plane where the substrate is located, and the sacrificial layer can ensure the structural stability perpendicular to the plane where the substrate is located. This example can ensure the stability of the mechanical structure during the preparation process.

[0137] Fig.13A It is a three-dimensional schematic diagram of a stacked structure after depositing a first conductive film in at least one embodiment of the present disclosure. Fig. 13B for Fig.13A A cross-sectional view of the first insulating film in a plane parallel to the substrate.

[0138] In some examples, such as Fig.13A and Fig. 13B As shown, after the first conductive film 180 is deposited on the stacked structure, the first conductive film 180 can be filled in the first hollow portion 171, the second hollow portion 172 and the third hollow portion 173. The edges of both sides of the first conductive film 180 along the first direction D1 can be flush with the edges of the substrate 100. The surface of the first conductive film 180 away from the substrate 100 can be kept flat with the plane where the substrate 100 is located. The stacked structure after the first conductive film 180 is deposited can be roughly in the shape of a cuboid.

[0139] In some examples, the first conductive film may be made of metal material.

[0140] Fig.14A It is a three-dimensional schematic diagram of the stacked structure after the first conductive film is etched once in at least one embodiment of the present disclosure. Fig. 14B for Fig.14A Cross-sectional view along BB' direction. Fig. 14C for Fig.14A Schematic top view of the laminated structure.

[0141] In some examples, such as FIG. 14A to FIG. 14CAs shown, a dry etching process may be used to etch the first conductive thin film 180 to form a plurality of fourth hollow portions 174 and a plurality of fifth hollow portions 175. The orthographic projection of the dry-etched first conductive thin film 180 on the substrate 100 may be within the orthographic projection range of the first insulating thin film 11 on the substrate 100. The edges of the dry-etched first conductive thin film 180 and the first insulating thin film 11 may be flush. In a plane parallel to the substrate 100, the fourth hollow portions 174 may be located between adjacent filling columns 151 of the sacrificial layer 15 in the second direction D2, and the fifth hollow portions 175 may be adjacent to one filling column 151 in the second direction D2. The orthographic projections of the fourth hollow portions 174 and the fifth hollow portions 175 on the substrate 100 may be generally rectangular. The orthographic projection of the stacked structure after etching on the substrate 100 may be generally in the shape of the Chinese character "丰".

[0142] Fig.15A This is a three-dimensional schematic diagram of a stacked structure after secondary etching of the first conductive thin film in at least one embodiment of the present disclosure. Fig. 15B is Fig.15A a cross-sectional view along the AA' direction in Fig. 15C is Fig.15A a cross-sectional view along the BB' direction in

[0143] In some examples, as FIG. 15A to FIG. 15C shown, a wet etching process is used to etch the first conductive thin film 180 to form the first conductive layer 18. In the wet etching of the first conductive thin film, a certain thickness may be etched transversely on the first conductive thin film, so that the edges of the wet-etched first conductive thin film 180 in the second direction D2 may be indented inwardly from the edges of the first insulating thin film 11, and the first conductive thin film 180 on both sides of the filling column 151 of the sacrificial layer may be disconnected, thereby forming the first electrode 31 and the second electrode 32 of the transistor. The first conductive layer 18 may include: the first electrodes 31 and the second electrodes 32 of a plurality of transistors, and bit lines 22. The second electrodes 32 of transistors located in the same layer and adjacent in the first direction D1 may be an integrally connected structure. The second electrodes 32 of two adjacent columns of transistors located in the same layer may be electrically connected to the same bit line 22. The bit lines 22 may extend along the second direction D2. The first electrodes 31 and the second electrodes 32 of the transistors may be located on both sides of the filling column 151 of the sacrificial layer 15 in the first direction D1. Two side surfaces of the filling column 151 in the second direction D2 may be exposed and not covered by the first insulating thin film 11.

[0144] In some examples, the thickness of the wet etching for the first conductive film can be substantially the same as the thickness of the wet etching for the first insulating film in the aforementioned step. For example, the wet etching thickness for the first conductive film can be 15 nm to 30 nm, such as about 25 nm or 30 nm. In this example, by setting the same wet etching thickness, it is possible to ensure that the sacrificial layer is exposed in the wet etching process of the first conductive film to form the first electrode and the second electrode of the first transistor.

[0145] In this example, the first through hole is expanded by etching the first insulating film twice, and the first conductive film is retracted by etching the first conductive film twice. The two processes can form an uneven size difference between the first conductive layer and the first insulating film, which is beneficial to controlling the morphology of the transistor.

[0146] Fig.16A It is a three-dimensional schematic diagram of a stacked structure after the first insulating film is deposited again according to at least one embodiment of the present disclosure. Fig. 16B for Fig.16A Schematic top view of the laminated structure.

[0147] In some examples, such as Fig.16A and Fig. 16B As shown, after forming the first conductive layer, the first insulating film 11 is deposited again, and the first insulating film 11 can fill the fourth hollow portion 174 and the fifth hollow portion 175. Through CMP, the two sides of the first insulating film 11 in the second direction D2 can be flush with the side of the substrate 100, and the surface of the first insulating film 11 away from the substrate 100 can be kept flat.

[0148] (6) Etching the first insulating film of the stacked structure forming the aforementioned pattern to form a sixth hollow portion and a seventh hollow portion to expose a portion of the surface of the first electrode and the second electrode of the plurality of transistors and a portion of the side surface of the filling column of the sacrificial layer. Subsequently, a third insulating film and a second conductive film are sequentially deposited on the sixth hollow portion and the seventh hollow portion to form a third insulating layer and a second conductive layer.

[0149] Fig.17A It is a three-dimensional schematic diagram of the stacked structure after the sixth hollow portion and the seventh hollow portion are formed according to at least one embodiment of the present disclosure. Fig. 17B for Fig.17A Cross-sectional view along AA' direction. Fig. 17C for Fig.17A Schematic top view of the laminated structure.

[0150] In some examples, such as FIG. 17A to FIG. 17CAs shown, the first insulating film 11 may be etched by a photolithography process to form a sixth hollow portion 176 and a seventh hollow portion 177. The sixth hollow portion 176 and the seventh hollow portion 177 may be located on both sides of the plurality of filling pillars 151 along the first direction D1. The first insulating film in the sixth hollow portion 176 and the seventh hollow portion 177 is removed, exposing the side of the support layer 16 facing the first electrode 31 of the transistor, partial surfaces of the first electrodes 31 of the plurality of transistors, and partial side surfaces of the filling pillars 151 facing the support layer 16 and the first electrode 31.

[0151] Fig.18A It is a three-dimensional schematic diagram of a stacked structure after forming a second electrode plate of a capacitor according to at least one embodiment of the present disclosure. Fig.18B for Fig.18A Cross-sectional view along AA' direction. Fig.18C for Fig.18A Schematic diagram of the top view of the stacked structure.

[0152] In some examples, such as 18A to 18C As shown, a third insulating film and a second conductive film are sequentially deposited in the sixth hollow portion 176 and the seventh hollow portion 177 to form a third insulating layer 52 and a second conductive layer. The third insulating layer 52 can cover the first electrodes of the multiple transistors exposed by the sixth hollow portion 176 and the seventh hollow portion 177 and the side of the sacrificial layer. The third insulating layer 52 can be located between the second conductive layer and the first conductive layer, so that the first conductive layer and the second conductive layer are insulated. The third insulating layer 52 can serve as a dielectric layer between the two plates of the capacitor. The second conductive layer may include: a second plate 42 of the capacitor. The second plates 42 of the capacitors of the multiple storage units may be an integrated structure connected to each other.

[0153] In some examples, the third insulating film and the second conductive film may be deposited by atomic layer deposition (ALD).

[0154] In some examples, the third insulating layer may be made of a high dielectric constant (High-K) dielectric material, such as a dielectric material with a dielectric constant K≥3.9. The High-K dielectric material may include, but is not limited to, at least one of the following: silicon oxide, hafnium oxide.

[0155] In some examples, the second conductive film may be made of metal material.

[0156] (7) The sacrificial layer of the stacked structure forming the aforementioned pattern is etched to form a plurality of second through holes K2 penetrating the sacrificial layer 15 in the third direction D3.

[0157] Fig.19A The diagram is a three-dimensional schematic diagram of a stacked structure after etching the sacrificial layer according to at least one embodiment of the present disclosure. Fig.19B for Fig.19A Cross-sectional view along AA' direction. Fig.19C for Fig.9A Schematic top view of the laminated structure.

[0158] In some examples, such as FIG. 19A to FIG. 19B As shown, the sacrificial layer 15 in the first through hole can be etched by photolithography to form a second through hole K2. Each filling column 151 can form a corresponding second through hole K2. The second through hole K2 can penetrate the sacrificial layer 15 along the third direction D3. The orthographic projection of the second through hole K2 on the substrate 100 can be roughly rectangular, and the orthographic projection of the second through hole K2 on the substrate is located within the orthographic projection range of the first through hole K1 on the substrate. Since the size of the first through hole K1 in the first insulating film and the first conductive layer is different, by setting a second through hole K2 with a size smaller than the first through hole K1, the sacrificial layer 15 between the first electrode 31 and the second electrode 32 of the transistor can be removed, so that the second through hole K2 can expose part of the surface of the first electrode 31 and the second electrode 32 of the transistor, and the side wall of the second through hole K2 located in the interlayer region of the adjacent layers exposes the sacrificial layer 15. In the interlayer region of the adjacent layers, the sacrificial layer 15 located between the side wall of the first through hole K1 and the side wall of the second through hole K2 can be retained, for example, the sacrificial layer after etching can surround the second through hole K2.

[0159] In some examples, the sacrificial layer 15 may continue to be etched in the second through hole K2 to increase the size of the second through hole K2 and to thin the sacrificial layer 15 around the second through hole K2 .

[0160] Fig. 20A It is a cross-sectional view of the stacked structure along the AA′ direction after the second through hole is widened according to at least one embodiment of the present disclosure. Fig. 20B The diagram is a top view of the stacked structure after the second through hole is widened according to at least one embodiment of the present disclosure.

[0161] In some examples, such as Fig. 20A and Fig. 20B As shown, the remaining sacrificial layer 15 can be laterally etched in the second through hole K2, and the sacrificial layer 15 around the second through hole K2 can be thinned, so that the size of the second through hole K2 in the interlayer region of the adjacent layers can be larger than the size between the first electrode and the second electrode. The second through hole K2 in the interlayer region can expose the sacrificial layer 15 and the partial surface of the first electrode and the second electrode of the transistor parallel to the plane where the substrate is located.

[0162] In this example, by etching the sacrificial layer 15 twice, the sizes of the second through hole K2 in the layer region and the interlayer region can be different, which is beneficial to controlling the morphology of the word line and the gate insulation layer in the subsequent process.

[0163] (8) A semiconductor film, a gate insulating film and a third conductive film are sequentially deposited in the second through hole K2 of the stacked structure forming the aforementioned pattern to form a semiconductor layer, a gate insulating layer and a third conductive layer of multiple transistors. The third conductive layer includes: a word line and gate electrodes of multiple transistors.

[0164] Fig.21A The diagram is a three-dimensional schematic diagram of a stacked structure after a semiconductor layer, a gate insulating layer and a third conductive layer are formed according to at least one embodiment of the present disclosure. Fig. 21B for Fig.21A Cross-sectional view along AA' direction. Fig. 21C for Fig.21A Schematic diagram of the top view of the stacked structure.

[0165] In some examples, such as FIG. 21A to FIG. 21C As shown, a semiconductor film, a gate insulating film and a third conductive film can be sequentially deposited in the second through hole K2 by ALD to form a semiconductor layer 34, a gate insulating layer 35 and a third conductive layer. For example, in the second through hole K2, a semiconductor film, a gate insulating film and a third conductive film are sequentially deposited along the edge to the center. The third conductive layer may include: a word line 21 and gate electrodes of multiple transistors. The word line 21 located in the layer area can be used as the gate electrode of the transistor. Since the size of the second through hole K2 in the layer area 300 and the interlayer area 400 is different, the size of the word line 21 in the layer area 300 and the interlayer area 400 may be different. The gate insulating layer 35 can be arranged around the side wall of the word line 21, and the semiconductor layer 34 can be arranged around the side wall of the gate insulating layer 35. In the layer area 300, the semiconductor layer 34 can be directly in contact with the first electrode 31 and the second electrode 32 of the transistor. In the interlayer area 400, the semiconductor layer 34 is in contact with the remaining sacrificial layer 15.

[0166] In some examples, the semiconductor layer 34 may be made of metal oxide material, for example, the metal oxide material may include: Indium Gallium Zinc Oxide (IGZO). When the material of the semiconductor layer is IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15A), thereby ensuring a low refresh rate of the dynamic memory. However, this embodiment is not limited to this. In other examples, the material of the metal oxide may include: ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO and other materials, as long as the leakage current of the transistor can meet the requirements, it can be adjusted according to the actual situation.

[0167] In some examples, the gate insulating layer 35 may be made of a High-K dielectric material, such as a dielectric material with a dielectric constant K≥3.9. For example, the High-K dielectric material may include at least one of the following: silicon oxide, hafnium oxide.

[0168] In some examples, the material of the third conductive layer may include at least one of the following: indium tin oxide (ITO), TiN / W, aluminum doped zinc oxide (AZO), and indium zinc oxide (IZO).

[0169] (9) Etching the stacked structure forming the aforementioned pattern to expose the sacrificial layer outside the second through hole, and etching the exposed sacrificial layer to expose at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers, and etching away the exposed semiconductor layer so that the semiconductor layers of the transistors in the adjacent layers are spaced apart.

[0170] In some examples, the first insulating film of the stacked structure may be etched twice to expose the sacrificial layer 15 around the second through hole K2 .

[0171] Fig.22A It is a three-dimensional schematic diagram of the stacked structure after etching the first insulating film in at least one embodiment of the present disclosure. Fig. 22B for Fig.22A Schematic diagram of the top view of the stacked structure.

[0172] In some examples, such as Fig.22A and Fig. 22BAs shown, the first insulating film 11 can be etched by dry etching to form the eighth hollow portion 178 and the ninth hollow portion 179. The first insulating film 11 in the eighth hollow portion 178 and the ninth hollow portion 179 can be removed. In a plane parallel to the substrate, the eighth hollow portion 178 can be located between adjacent word lines 21 in the second direction D2, and the ninth hollow portion 179 can be adjacent to a word line 21 in the second direction D2. The orthographic projections of the eighth hollow portion 178 and the ninth hollow portion 179 on the substrate 100 can both be roughly rectangular. The sides of the eighth hollow portion 178 and the ninth hollow portion 179 can be surrounded by the first insulating film 11 and the third insulating layer 52. In this example, the eighth hollow portion 178 and the ninth hollow portion 179 may not expose the surface of the sacrificial layer 15. This embodiment is not limited to this. In other examples, the sides of the eighth hollow portion and the ninth hollow portion may expose part of the surface of the sacrificial layer 15.

[0173] In some examples, after the first insulating film 11 is dry-etched, the first insulating film 11 may be wet-etched to expose the sacrificial layer 15 located at the periphery of the second through hole.

[0174] Fig.23A It is a three-dimensional schematic diagram of the stacked structure after etching the sacrificial layer in at least one embodiment of the present disclosure. Fig. 23B for Fig.23A Cross-sectional view along AA' direction. Fig.23C for Fig.23A Schematic diagram of the top view of the stacked structure.

[0175] In some examples, such as FIG. 23A to FIG. 23C As shown, after the sacrificial layer 15 is exposed by etching the first insulating film 11, the exposed sacrificial layer 15 can be etched to expose the semiconductor layer 34. Since the exposed sacrificial layer 15 is located in the interlayer region 400, the semiconductor layer 34 in the interlayer region 400 can be exposed after the sacrificial layer 15 is etched. In this step, the remaining portion of the sacrificial layer 15 can be completely etched away. In some examples, due to the influence of process conditions, the sacrificial layer 15 may remain.

[0176] Fig.24A It is a three-dimensional schematic diagram of the stacked structure after etching the exposed semiconductor layer in at least one embodiment of the present disclosure. Fig. 24B for Fig.24A Cross-sectional view along AA' direction. Fig.24C for Fig.24A Schematic diagram of the top view of the stacked structure.

[0177] In some examples, such as FIG. 24A to FIG. 24CAs shown, the semiconductor layer 34 in the interlayer region 400 exposed by wet etching can be etched away to disconnect the semiconductor layers of transistors in adjacent layers. In this example, by removing the semiconductor layer in the interlayer region 400, parasitic MOS can be effectively reduced or removed without affecting the effective channel length of the transistor, thereby enhancing device stability.

[0178] In some examples, after etching the semiconductor layer in the interlayer region 400, a first insulating film may be deposited again, and the edge of the first insulating film may be flush with the edge of the substrate by CMP, and the surface of the first insulating film away from the substrate may be kept flat, thereby forming a first insulating layer 51. The semiconductor device prepared in this example may be Figure 1 shown.

[0179] The method for preparing a semiconductor device provided in this example can form a first through hole in the stacked structure, deposit a sacrificial layer in the first through hole, form a second through hole in the sacrificial layer, and deposit a semiconductor layer, a gate insulating layer, and a gate electrode of a transistor in the second through hole. During the preparation process, the sacrificial layer can be arranged around the semiconductor layer in the interlayer region, and the sacrificial layer and the semiconductor layer in the interlayer region are sequentially etched by exposing the sacrificial layer, which can effectively reduce or remove parasitic MOS while ensuring the size of the device. The preparation method of this example sequentially exposes and etches the sacrificial layer and the local semiconductor layer, and selectively removes the sacrificial layer and the local semiconductor layer in a small range, without exposing the complete semiconductor layer to cause the structure to be suspended. This example can ensure the stability of the mechanical structure and is conducive to the miniaturization of the device.

[0180] Moreover, in this example, the first through hole is expanded by etching the first insulating film twice, and the first conductive film is retracted by etching the first conductive film twice. The two processes can form a uneven size difference between the first conductive layer and the first insulating film, which is beneficial to control the morphology of the transistor. The word line morphology of this example can form a step at the junction of the layer region and the interlayer region of the gate insulating layer. The step can prevent the damaged semiconductor layer in the interlayer region from extending to the layer region, thereby ensuring the performance of the transistor.

[0181] Fig.25 FIG. 1 is a schematic cross-sectional view of another semiconductor device along the AA′ direction according to at least one embodiment of the present disclosure. Fig.25As shown, the word line 21 can be a strip structure extending along the third direction D3. The cross-sectional sizes of the word line 21 at different positions in the extension direction can be the same. The size of the word line 21 in the layer area 300 and the interlayer area 400 can be the same. In the preparation method of this example, after the sacrificial layer is etched to form the second through hole, further etching may not be performed in the second through hole, so that the size of the second through hole in the layer area and the interlayer area can be the same. The preparation method of the semiconductor device of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0182] This embodiment also provides a method for preparing a semiconductor device, the semiconductor device comprising: a plurality of transistors stacked in a direction perpendicular to the substrate and periodically distributed in different layers, a word line penetrating the different layers and extending in a direction perpendicular to the substrate; the transistor comprising: a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, a semiconductor layer surrounding the sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer disposed between the gate electrode and the semiconductor layer. The method for preparing the semiconductor device comprises: providing a substrate, alternately depositing a first insulating film and a second insulating film on the substrate in sequence to form a stacked structure; etching the stacked structure to form a first through hole penetrating the stacked structure in a direction perpendicular to the substrate; forming a sacrificial layer filling the first through hole; etching and removing the second insulating film; depositing a first conductive film to form a first conductive layer, the first conductive layer comprising at least: the first and second electrodes of the plurality of transistors, the first and second electrodes of the transistors being separated by the sacrificial layer; etching a portion of the sacrificial layer in the first through hole to form a second through hole penetrating the sacrificial layer in a direction perpendicular to the substrate, the sidewall of the second through hole exposing the first and second electrodes of the transistor, and in adjacent The side wall of the second through hole in the interlayer area of ​​the layer exposes the sacrificial layer; a semiconductor film, a gate insulating film and a third conductive film are deposited in sequence in the second through hole to form the semiconductor layer, the gate insulating layer and the third conductive layer of the multiple transistors, the third conductive layer includes: the word line and the gate electrodes of the multiple transistors, the multiple transistors arranged in a direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each transistor in the multiple transistors is a part of the word line; the semiconductor layer of the transistor is in contact with the first electrode and the second electrode of the transistor; the sacrificial layer around the second through hole is etched to expose at least part of the semiconductor layer located in the interlayer area of ​​the adjacent layer, and the exposed semiconductor layer is etched to remove the exposed semiconductor layer, so that the semiconductor layers of the transistors in the adjacent layers are arranged at intervals.

[0183] In some exemplary embodiments, etching the stacked structure to form a first through hole penetrating the stacked structure in a direction perpendicular to the substrate includes: forming a hard mask layer on a side of the stacked structure away from the substrate; using the hard mask layer, etching the first insulating film and the second insulating film of the stacked structure to form a first initial via hole in the first insulating film and a second via hole in the second insulating film, wherein the first initial via hole and the second via hole are aligned and connected in a direction perpendicular to the substrate; wet etching the first insulating film to expand the first initial via hole to become a first via hole; the first via hole and the second via hole are connected to form the first through hole, and the orthographic projection of the second via hole on the substrate is within the orthographic projection range of the first via hole on the substrate.

[0184] In some exemplary embodiments, the depositing of the first conductive film to form the first conductive layer includes: depositing the first conductive film, and dry-etching the first conductive film so that the edge of the etched first conductive film is flush with the edge of the first insulating film; and wet-etching the first conductive film so that the edge of the first conductive film is retracted toward the inside of the edge of the first insulating film, and the first conductive films located on both sides of the sacrificial layer are disconnected to form the first electrode and the second electrode of the transistor.

[0185] In some exemplary embodiments, a thickness of the wet etching for the first insulating film is the same as a thickness of the wet etching for the first conductive film.

[0186] In some exemplary embodiments, the semiconductor device further includes: a plurality of capacitors, the capacitors including a first plate and a second plate, the second electrode of the transistor and the first plate of the connected capacitor are an integrated structure connected to each other. After forming the first conductive layer and before etching a portion of the sacrificial layer in the first through hole, the preparation method further includes: depositing a first insulating film to cover the first conductive layer; etching a portion of the first insulating film to expose a portion of the surface of the first electrode and the second electrode of the plurality of transistors and a portion of the surface of the sacrificial layer facing the first electrode; depositing a third insulating film and a second conductive film in sequence in the area where the first insulating film is removed to form a third insulating layer and a second conductive layer, the second conductive layer including: the second plate of the capacitor, the third insulating layer being located between the first plate and the second plate of the capacitor.

[0187] In some exemplary embodiments, after etching a portion of the sacrificial layer within the first through hole to form a second through hole that penetrates the sacrificial layer in a direction perpendicular to the substrate, the preparation method further includes: etching the sacrificial layer within the second through hole to enlarge the second through hole and thinning the sacrificial layer outside the second through hole.

[0188] In some exemplary embodiments, the etching of the sacrificial layer around the second through hole exposes at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers, and etching away the exposed semiconductor layer so that the semiconductor layers of the transistors in the adjacent layers are spaced apart, comprising: etching the first insulating film in sequence by dry etching and wet etching to expose the sacrificial layer located in the interlayer region of the adjacent layers, and etching the sacrificial layer to expose at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers; and wet etching the exposed semiconductor layer so that the semiconductor layers of the transistors in different layers are spaced apart.

[0189] In some exemplary embodiments, the sacrificial layer is made of a material having a selectivity ratio with respect to the semiconductor layer by wet etching.

[0190] In some exemplary embodiments, the material of the sacrificial layer includes aluminum oxide.

[0191] The description of the method for preparing the semiconductor device of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0192] This embodiment further provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may include: a storage device, a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device, a mobile power supply, or a smart mobile terminal. The storage device may include a memory in a computer, etc., which is not limited in this embodiment.

[0193] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can refer to the usual design. In the absence of conflict, the embodiments of the present disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A method for preparing a semiconductor device, characterized in that: The semiconductor device comprises: a plurality of transistors stacked in a direction perpendicular to a substrate and periodically distributed in different layers, and a word line running through the different layers and extending in a direction perpendicular to the substrate; the transistor comprises: a first electrode, a second electrode, a gate electrode extending in a direction perpendicular to the substrate, a semiconductor layer surrounding a side wall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer; The method for preparing the semiconductor device comprises: Providing a substrate, and alternately depositing a first insulating film and a second insulating film on the substrate in sequence to form a stacked structure; Etching the stacked structure to form a first through hole penetrating the stacked structure in a direction perpendicular to the substrate; forming a sacrificial layer filling the first through hole; Etching and removing the second insulating film; Depositing a first conductive film to form a first conductive layer, wherein the first conductive layer at least includes: first electrodes and second electrodes of the plurality of transistors, wherein the first electrodes and second electrodes of the transistors are separated by the sacrificial layer; Etching a portion of the sacrificial layer in the first through hole to form a second through hole penetrating the sacrificial layer in a direction perpendicular to the substrate, wherein the sidewall of the second through hole exposes the first electrode and the second electrode of the transistor, and the sidewall of the second through hole in the interlayer region of adjacent layers exposes the sacrificial layer; A semiconductor film, a gate insulating film and a third conductive film are sequentially deposited in the second through hole to form a semiconductor layer, a gate insulating layer and a third conductive layer of the plurality of transistors, wherein the third conductive layer includes: the word line and the gate electrodes of the plurality of transistors, the plurality of transistors arranged in a direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each transistor in the plurality of transistors is a part of the word line; the semiconductor layer of the transistor is in contact with the first electrode and the second electrode of the transistor; The sacrificial layer around the second through hole is etched to expose at least part of the semiconductor layer located in the interlayer region of the adjacent layers, and the exposed semiconductor layer is removed by etching, so that the semiconductor layers of the transistors in the adjacent layers are arranged at intervals.

2. The method for preparing a semiconductor device according to claim 1, wherein: The etching of the stacked structure to form a first through hole penetrating the stacked structure in a direction perpendicular to the substrate includes: forming a hard mask layer on a side of the stacked structure away from the substrate; Using the hard mask layer, etching the first insulating film and the second insulating film of the stacked structure, forming a first initial via hole in the first insulating film, and forming a second via hole in the second insulating film, wherein the first initial via hole and the second via hole are aligned and connected in a direction perpendicular to the substrate; The first insulating film is wet-etched to expand the first initial via hole into a first via hole; the first via hole and the second via hole are connected to form the first through hole, and the orthographic projection of the second via hole on the substrate is within the orthographic projection range of the first via hole on the substrate.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The step of depositing a first conductive film to form a first conductive layer comprises: Depositing a first conductive film, and dry-etching the first conductive film so that an edge of the etched first conductive film is flush with an edge of the first insulating film; The first conductive film is wet-etched so that the edge of the first conductive film is retracted toward the inner side of the edge of the first insulating film, and the first conductive films on both sides of the sacrificial layer are disconnected to form the first electrode and the second electrode of the transistor.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The thickness of the wet etching for the first insulating film is the same as the thickness of the wet etching for the first conductive film.

5. The method for preparing a semiconductor device according to claim 1, characterized in that: The semiconductor device further comprises: a plurality of capacitors, wherein the capacitors comprise a first electrode plate and a second electrode plate, and the second electrode of the transistor and the first electrode plate of the connected capacitor are an integrated structure connected to each other; After forming the first conductive layer and before etching a portion of the sacrificial layer in the first through hole, the preparation method further includes: Depositing a first insulating film to cover the first conductive layer; Etching a portion of the first insulating film to expose a portion of the surfaces of the first electrodes and the second electrodes of the plurality of transistors and a portion of the surface of the sacrificial layer facing the first electrode; A third insulating film and a second conductive film are sequentially deposited in the area where the first insulating film is removed to form a third insulating layer and a second conductive layer, wherein the second conductive layer includes: a second plate of the capacitor, and the third insulating layer is located between the first plate and the second plate of the capacitor.

6. The method for preparing a semiconductor device according to claim 1, wherein: After etching a portion of the sacrificial layer in the first through hole to form a second through hole penetrating the sacrificial layer in a direction perpendicular to the substrate, the preparation method further includes: The sacrificial layer is etched in the second through hole to enlarge the second through hole and thin the sacrificial layer around the second through hole.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: The step of etching the sacrificial layer around the second through hole to expose at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers, and etching away the exposed semiconductor layer so that the semiconductor layers of the transistors in the adjacent layers are arranged at intervals, comprises: Sequentially etching the first insulating film by dry etching and wet etching to expose the sacrificial layer located in the interlayer region of the adjacent layers, and etching the sacrificial layer to expose at least a portion of the semiconductor layer located in the interlayer region of the adjacent layers; The semiconductor layers are exposed by wet etching, so that the semiconductor layers of transistors in different layers are arranged at intervals.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The sacrificial layer is made of a material having a selectivity ratio with the semiconductor layer by wet etching.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The material of the sacrificial layer includes aluminum oxide.

10. A semiconductor device, characterized in that: include: Multiple transistors are stacked in a direction perpendicular to the substrate and periodically distributed in different layers; A word line, penetrating the different layers and extending in a direction perpendicular to the substrate; The transistor comprises: a gate electrode extending in a direction perpendicular to the substrate, a semiconductor layer surrounding the sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer; A plurality of transistors arranged along a direction perpendicular to a substrate are connected to a same word line, and a gate electrode of each of the plurality of transistors is a part of the word line; semiconductor layers of the plurality of transistors are arranged at intervals; the word line in an interlayer region between adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in an interlayer region between adjacent layers is surrounded by a first insulating layer.

11. The semiconductor device according to claim 10, characterized in that At least part of the gate insulating layer in the interlayer region of adjacent layers contacts the independent semiconductor layer, and the semiconductor layer in the interlayer region of adjacent layers contacts the sacrificial layer; the semiconductor layer in the interlayer region of adjacent layers is disconnected from the semiconductor layer of the transistor.

12. The semiconductor device according to claim 11, characterized in that The material of the sacrificial layer includes: aluminum oxide.

13. The semiconductor device according to claim 10, characterized in that The word line includes: a first main body and a second main body extending in a direction perpendicular to the substrate and alternately connected, the first main body serving as the gate electrode of the transistor, and the second main body located in an interlayer region of an adjacent layer; an orthographic projection of the first main body on the substrate is located within the range of an orthographic projection of the second main body on the substrate.

14. The semiconductor device according to claim 13, characterized in that The gate insulating layer includes: a first insulating part and a second insulating part extending in a direction perpendicular to the substrate and alternately connected, the first insulating part is located between the semiconductor layer and the gate electrode of the transistor, the second insulating part is located in the interlayer region of adjacent layers, and the second insulating part forms a step on the surface of the first insulating part protruding from the plane where the substrate is located; the semiconductor layer of the transistor is distributed on the side walls of the first insulating part and the step.

15. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device as claimed in any one of claims 10 to 14.

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