Display substrate, display device and load compensation method applied to display substrate

Abstract

The invention provides a display substrate, a display device and a load compensation method applied to the display substrate. The display substrate comprises a plurality of scanning signal lines arranged on a substrate body and used for providing scanning signals for a plurality of rows of pixel units respectively; and the plurality of load compensation units are arranged on the substrate base plate, are positioned in the frame area and are electrically connected with at least some of the plurality of scanning signal lines respectively. The at least one load compensation unit comprises at least one of a compensation capacitor and a compensation resistor. The display substrate comprises N rows of pixel units, the number of sub-pixels included in n rows of pixel units in the N rows of pixel units is different, N is a positive integer larger than or equal to 2, and n is a positive integer larger than or equal to 2 and smaller than or equal to N. For the n rows of pixel units, the scanning signal line of each row of pixel units is electrically connected with the respective load compensation unit, the load compensation value of the load compensation unit of each row of pixel units is in negative correlation with the number of sub-pixels included in the row of pixel units, and the load compensation value comprises at least one of a capacitance compensation value and a resistance compensation value.

Description

Display substrate, display device, and load compensation method applied to display substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate, a display device, and a load compensation method applied to the display substrate. Background Art

[0002] With the continuous advancement of technology, there is an increasing demand for customized designs of special-shaped display screens. In special-shaped display screens, the display panel has a special-shaped display area. The number of sub-pixels in each row of pixel cells in the special-shaped display area is significantly different from the number of sub-pixels in each row of pixel cells in the normal display area. This large difference in the number of sub-pixels in each row of pixel cells can lead to significant load differences between the normal display area and the special-shaped display area, as well as large load differences between adjacent rows of pixel cells, which may cause display problems.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arranged in an array along row and column directions on the base substrate, each row of pixel units comprising a plurality of sub-pixels; a plurality of scanning signal lines provided on the base substrate, the plurality of scanning signal lines being used to respectively provide scanning signals to the plurality of rows of pixel units; a plurality of load compensation units provided on the base substrate and located in the frame area, the plurality of load compensation units being respectively connected to the plurality of sub-pixels in the plurality of scanning signal lines. At least some of the scanning signal lines are electrically connected; and a common electrode is arranged on the base substrate, at least a portion of the common electrode is located in the display area, and the common electrode is connected to a common voltage signal, wherein at least one of the load compensation units includes at least one of a compensation capacitor and a compensation resistor; the display substrate includes N rows of pixel units, and the numbers of sub-pixels included in n rows of pixel units in the N rows of pixel units are inconsistent with each other, wherein N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 2 and less than or equal to N; and for the n rows of pixel units, the scanning signal lines of each row of pixel units are respectively electrically connected to their own load compensation units, and the load compensation value of the load compensation unit of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.

[0006] According to some exemplary embodiments, the compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is electrically connected to the scanning signal line, the second compensation capacitor electrode is connected to the common voltage signal, and the orthographic projection of the first compensation capacitor electrode on the substrate and the orthographic projection of the second compensation capacitor electrode on the substrate at least partially overlap.

[0007] According to some exemplary embodiments, for the n rows of pixel units, the multiple scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation capacitors, and the overlapping area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units.

[0008] According to some exemplary embodiments, for the at least n rows of pixel units, a size in the row direction of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units.

[0009] According to some exemplary embodiments, the compensation resistor includes a compensation conductive trace; and for the n rows of pixel units, a plurality of scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation conductive traces, and the resistance value of the compensation conductive trace of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units.

[0010] According to some exemplary embodiments, for the at least n rows of pixel units, the length of the compensation conductive trace of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and / or the wire diameter of the compensation conductive trace of each row of pixel units is positively correlated with the number of sub-pixels included in the row of pixel units.

[0011] According to some exemplary embodiments, the display substrate further includes: a gate driving circuit arranged on the base substrate and located in the border area, the gate driving circuit being used to output a scanning signal; and a plurality of scanning signal leads arranged on the base substrate and located in the border area, the plurality of scanning signal leads being electrically connected to the plurality of scanning signal lines, respectively, wherein the display substrate includes: a first conductive layer located on the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; and a third conductive layer located on a side of the second conductive layer away from the base substrate, wherein, for the same row of pixel units, the first compensation capacitor electrode and the scanning signal lead are connected to each other, and the first compensation capacitor electrode and the scanning signal lead are both located on a same conductive layer selected from the first conductive layer and the second conductive layer.

[0012] According to some exemplary embodiments, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer; or, wherein the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer.

[0013] According to some exemplary embodiments, the compensation capacitor includes a first sub-compensation capacitor and a second sub-compensation capacitor, the second compensation capacitor electrode includes a first sub-compensation capacitor electrode and a second sub-compensation capacitor electrode, and the first sub-compensation capacitor electrode and the second sub-compensation capacitor electrode are both connected to the common voltage signal; the first compensation capacitor electrode is located in the second conductive layer, the first sub-compensation capacitor electrode is located in the first conductive layer, and the second sub-compensation capacitor electrode is located in the third conductive layer; the orthographic projection of the first compensation capacitor electrode on the base substrate and the orthographic projection of the first sub-compensation capacitor electrode on the base substrate at least partially overlap to form the first sub-compensation capacitor electrode; the orthographic projection of the first compensation capacitor electrode on the base substrate and the orthographic projection of the second sub-compensation capacitor electrode on the base substrate at least partially overlap to form the second sub-compensation capacitor electrode.

[0014] According to some exemplary embodiments, the display substrate further includes: a driving chip arranged on the base substrate and located in the border area, the driving chip being used to output a scanning signal; and a plurality of scanning signal leads arranged on the base substrate and located in the border area, the plurality of scanning signal leads being electrically connected to the plurality of scanning signal lines respectively, wherein the display substrate includes: a first conductive layer located on the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; and a third conductive layer located on a side of the second conductive layer away from the base substrate, wherein, for the same row of pixel units, the first compensation capacitor electrode and the scanning signal lead are connected to each other, and the first compensation capacitor electrode and the scanning signal lead are both located on a same conductive layer selected from the first conductive layer and the second conductive layer.

[0015] According to some exemplary embodiments, for odd-numbered rows of pixel cells, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer; for even-numbered rows of pixel cells, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer; for all n rows of pixel cells, the second compensation capacitor electrode is both located in the third conductive layer; or, wherein, for odd-numbered rows of pixel cells, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer; for even-numbered rows of pixel cells, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer; for all n rows of pixel cells, the second compensation capacitor electrode is both located in the third conductive layer.

[0016] According to some exemplary embodiments, for the pixel cells in odd rows, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer; and for the pixel cells in even rows, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer; or, wherein, for the pixel cells in odd rows, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer; and for the pixel cells in even rows, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer.

[0017] According to some exemplary embodiments, the first compensation capacitor electrode and the scan signal lead connected to each other are a continuously extending integral structure.

[0018] According to some exemplary embodiments, the first compensation capacitor electrode includes a plurality of curved routing sections extending from the scan signal lead; or, the first compensation capacitor electrode includes a first conductive portion extending from the scan signal lead, and the first conductive portion has a hollow structure.

[0019] According to some exemplary embodiments, the scanning signal leads of the pixel units in two adjacent rows extend along the row direction, and the first compensation capacitor electrode is located between the scanning signal leads of the pixel units in the two adjacent rows in the column direction.

[0020] According to some exemplary embodiments, the display substrate includes an electrostatic protection ring connected to a common voltage signal; and the second compensation capacitor electrode includes a second conductive portion extending from the electrostatic protection ring.

[0021] According to some exemplary embodiments, for the n rows of pixel units, the second conductive portion of the compensation capacitor of the n rows of pixel units is a continuously extended integrated structure; or, for the n rows of pixel units, the second conductive portion of the compensation capacitor of the n rows of pixel units extends from the electrostatic protection ring toward the display area respectively.

[0022] According to some exemplary embodiments, the display substrate further includes an electrostatic protection circuit, one end of the electrostatic protection circuit being electrically connected to both the scan signal lead and the scan signal line, and the other end of the electrostatic protection circuit being electrically connected to the electrostatic protection ring, for releasing static electricity on the scan signal lead and the scan signal line to the electrostatic protection ring.

[0023] According to some exemplary embodiments, the display substrate further includes a first conductive transition portion located in the third conductive layer; an end of the scanning signal lead close to the display area is electrically connected to a first portion of the first conductive transition portion through a first via, an end of the scanning signal line away from the display area is electrically connected to a second portion of the first conductive transition portion through a second via, and a third portion of the first conductive transition portion is electrically connected to one end of the electrostatic protection circuit through a third via.

[0024] According to some exemplary embodiments, the display substrate further includes a second conductive transition portion located in the third conductive layer; a portion of the scan signal lead is electrically connected to a portion of the second conductive transition portion through a fourth via, and another portion of the second conductive transition portion is electrically connected to one end of the first compensation capacitor electrode through a fifth via; and / or, the display substrate further includes a third conductive transition portion located in the third conductive layer; another portion of the scan signal lead is electrically connected to a portion of the third conductive transition portion through a sixth via, and another portion of the third conductive transition portion is electrically connected to the other end of the first compensation capacitor electrode through a seventh via.

[0025] According to some exemplary embodiments, a portion of the scan signal lead line forms the compensation resistor.

[0026] According to some exemplary embodiments, at least a portion of the scan signal leads providing scan signals to at least one row of pixel units includes multiple sections of meandering lines, and the compensation resistor includes the multiple sections of meandering lines.

[0027] According to some exemplary embodiments, a difference in total loads on the scanning signal lines of pixel units in any two adjacent rows is within a specified threshold, wherein the total load includes a product of a capacitive load and a resistive load on the scanning signal lines.

[0028] According to some exemplary embodiments, the display substrate includes a common voltage signal bus that provides the common voltage signal; and for the load compensation unit of at least one row of pixel units, the compensation capacitor is located on a side of the common voltage signal bus close to the display area in the row direction, the compensation resistor is located on a side of the compensation capacitor close to the display area in the row direction, and the electrostatic protection circuit is located on a side of the compensation resistor close to the display area.

[0029] In another aspect, a display device is provided, comprising the display substrate as described above.

[0030] On the other hand, a load compensation method for a display substrate is provided, wherein the display substrate comprises: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arranged in an array on the base substrate along row and column directions, each row of pixel units comprising a plurality of sub-pixels; a plurality of scanning signal lines provided on the base substrate, the plurality of scanning signal lines being used to provide scanning signals to the plurality of rows of pixel units respectively; a plurality of load compensation units provided on the base substrate and located in the frame area, the plurality of load compensation units being electrically connected to at least some of the plurality of scanning signal lines respectively; and a common electrode provided on the base substrate, at least a portion of the common electrode being located in the display area, the common electrode being connected to a common voltage signal, wherein the display substrate comprises N rows of pixel units, wherein N is a positive integer greater than or equal to 2, and the method comprises: driving the display substrate to display a white screen; obtaining a charging voltage of the p-th row of pixel units and the q-th row of pixel units, wherein the p-th row of pixel units is the charging voltage of the p-th row of pixel units; The method further comprises: determining a row of pixel units having the least number of sub-pixels among the N rows of pixel units, wherein the qth row of pixel units is a row of pixel units having the greatest number of sub-pixels among the N rows of pixel units; calculating a difference in charging voltages between the pth row of pixel units and the qth row of pixel units; comparing the difference in charging voltages with a predetermined voltage threshold; determining that load compensation is required in response to the difference in charging voltages being greater than the predetermined voltage threshold; determining n rows of pixel units requiring load compensation in response to the load compensation, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein a difference between the charging voltage of each row of pixel units in the n rows of pixel units and the charging voltage of the qth row of pixel units is greater than the predetermined threshold; and determining a load compensation value of a load compensation unit based on the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units, wherein a plurality of scan signal lines providing scan signals to the n rows of pixel units are respectively electrically connected to respective load compensation units, the load compensation value of the n rows of pixel units being negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value comprising at least one of a capacitance compensation value and a resistance compensation value.

[0031] On the other hand, a load compensation method for a display substrate is provided, wherein the display substrate comprises: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arranged in an array on the base substrate along row and column directions, each row of pixel units comprising a plurality of sub-pixels; a plurality of scanning signal lines provided on the base substrate, the plurality of scanning signal lines being used to respectively provide scanning signals to a plurality of rows of pixel units; a plurality of load compensation units provided on the base substrate and located in the frame area, the plurality of load compensation units being respectively electrically connected to at least some of the plurality of scanning signal lines; and a common electrode provided on the base substrate, at least a portion of the common electrode being located in the display area, the common electrode being connected to a common voltage signal, wherein the display substrate comprises N rows of pixel units, wherein N is a positive integer greater than or equal to 2, and the method The method comprises: calculating the load difference between any two adjacent rows of pixel units; comparing the load difference with a prescribed load difference threshold; in response to the load difference being greater than the prescribed load difference threshold, determining n rows of pixel units that require load compensation, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein the load difference between each row of pixel units in the n rows of pixel units and the pixel units in its adjacent row is greater than the prescribed load difference threshold; determining a load compensation value of a load compensation unit according to the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units, wherein the qth row of pixel units is a row of pixel units with the largest number of sub-pixels in the N rows of pixel units, and a plurality of scanning signal lines providing scanning signals to the n rows of pixel units are electrically connected to respective load compensation units, and the load compensation value of the n rows of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0033] FIG. 1A is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure.

[0034] 1B to 1D schematically illustrate examples of several unusual shapes of display substrates.

[0035] FIG. 2A is a diagram schematically illustrating a pixel layout of the display device shown in FIG. 1A .

[0036] FIG. 2B is a partially enlarged view of portion I shown in FIG. 1A .

[0037] FIG. 2C is a partial enlarged view of portion II shown in FIG. 1A .

[0038] FIG. 3A is a schematic diagram schematically illustrating the structure of a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure.

[0039] FIG3B schematically shows a cross-sectional view of a thin film transistor in an embodiment of the present disclosure.

[0040] FIG. 4A is a schematic diagram of a fan-out region of a display substrate according to some exemplary embodiments of the present disclosure.

[0041] 4B to 4D are partial enlarged views of region III, region IV, and region V in FIG. 4A , respectively.

[0042] FIG. 5 is a diagram showing a load difference ratio of signal scan lines between two adjacent rows of pixel units in the display substrate shown in FIG. 1A before load compensation.

[0043] FIG. 6 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating load compensation units of a portion of rows of pixel units.

[0044] FIG. 7 is a partial enlarged view of the display substrate shown in FIG. 6 , schematically illustrating a load compensation unit of the pixel unit in the i-th row.

[0045] FIG8 is a partial enlarged view of the display substrate shown in FIG6 , schematically illustrating a load compensation unit of the pixel unit in the (i+1)th row.

[0046] FIG9 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of compensation capacitors and electrostatic protection circuits of two rows of pixel units.

[0047] 10 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of compensation capacitors, electrostatic protection circuits, and electrostatic protection structures of a certain row of pixel units.

[0048] FIG11 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, which schematically shows a plan view of compensation capacitors and compensation resistors of pixel units in certain rows.

[0049] 12A to 12D are schematic cross-sectional views respectively schematically illustrating compensation capacitors of a display substrate according to some exemplary embodiments of the present disclosure.

[0050] FIG. 13A is a partially enlarged view of a display substrate at region VI in FIG. 10 according to some exemplary embodiments of the present disclosure.

[0051] FIG13B is a cross-sectional view taken along line BB′ in FIG13A .

[0052] FIG. 14A is a partial enlarged view of a display substrate at region VI in FIG. 10 according to some other exemplary embodiments of the present disclosure.

[0053] FIG14B is a cross-sectional view taken along line CC′ in FIG14A .

[0054] FIG. 15A is a partially enlarged view of a display substrate at region VI in FIG. 10 according to some exemplary embodiments of the present disclosure.

[0055] FIG15B is a cross-sectional view taken along line DD′ in FIG15A .

[0056] FIG. 16 is a cross-sectional view of a display substrate taken along line AA′ in FIG. 3A according to some exemplary embodiments of the present disclosure.

[0057] FIG. 17A is a flowchart of a load compensation method applied to a display substrate according to some exemplary embodiments of the present disclosure.

[0058] FIG. 17B is a flowchart of a load compensation method applied to a display substrate according to other exemplary embodiments of the present disclosure.

[0059] FIG. 18 is an equivalent circuit diagram of an electrostatic protection circuit according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0060] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0061] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0062] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0063] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0064] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0065] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0066] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0067] Those skilled in the art should understand that, herein, unless otherwise specified, the expressions "continuous extension", "integrated structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same patterning process during the manufacturing process. There are no spaces or breaks between these elements, components, structures and / or parts, but they are continuously extended structures.

[0068] It should be noted that in this article, the term "negative correlation" refers to two quantities changing in opposite directions. For example, when one quantity increases, the other decreases; when one decreases, the other increases. The term "positive correlation" refers to two quantities changing in the same direction. For example, when one quantity increases, the other increases; when one decreases, the other decreases.

[0069] The embodiments of the present disclosure provide at least one display substrate and a display device. The display substrate includes: a base substrate, the base substrate including a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array along the row direction and the column direction on the base substrate, and each row of pixel units includes a plurality of sub-pixels; a plurality of scanning signal lines arranged on the base substrate, the plurality of scanning signal lines are used to provide scanning signals to the plurality of rows of pixel units respectively; a plurality of load compensation units arranged on the base substrate and located in the frame area, the plurality of load compensation units are electrically connected to at least some of the plurality of scanning signal lines respectively; and a common electrode arranged on the base substrate, at least one of the common electrodes A portion is located in the display area, the common electrode is connected to a common voltage signal, wherein at least one of the load compensation units includes at least one of a compensation capacitor and a compensation resistor; the display substrate includes N rows of pixel units, n rows of pixel units in the N rows of pixel units include different numbers of sub-pixels, wherein N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 2 and less than or equal to N; and for the n rows of pixel units, the scanning signal lines of each row of pixel units are electrically connected to a respective load compensation unit, the load compensation value of the load compensation unit of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value. In an embodiment of the present disclosure, load compensation can be performed on each row of pixel units with inconsistent loads. For example, a load compensation unit is electrically connected to the scanning signal line of each row of pixel units requiring load compensation, so that the load on the scanning signal line of each row of pixel units is substantially consistent. In this way, undesirable phenomena such as display unevenness in each sub-display area can be at least improved or even eliminated.

[0070] FIG1A is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure. FIG2A is a schematic diagram schematically illustrating a pixel layout of the display device shown in FIG1A . FIG2B is a partially enlarged view of portion I shown in FIG1A . FIG2C is a partially enlarged view of portion II shown in FIG1A .

[0071] With reference to FIG1A and FIG2A to FIG2C , the display device 1000 may include a display substrate. The display substrate may include a base substrate 100, which may include a display area AA and a frame area NA located on at least one side of the display area. It should be noted that in the embodiment shown in FIG1 , the frame area NA surrounds the display area AA. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the frame area NA may be located on at least one side of the display area AA but may not surround the display area AA.

[0072] The display substrate may include a plurality of pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit for displaying an image. For example, the pixel unit P may include a light emitting device that emits white light and / or colored light.

[0073] The pixel cells P may be provided in a plurality and arranged in a matrix along rows extending in a first direction (e.g., row direction) X and columns extending in a second direction (e.g., column direction) Y. However, the embodiments of the present disclosure do not specifically limit the arrangement of the pixel cells P, and the pixel cells P may be arranged in various forms. For example, the pixel cells P may be arranged such that a direction inclined with respect to the first direction X and the second direction Y becomes a column direction, and a direction intersecting the column direction becomes a row direction.

[0074] A pixel unit P may include multiple sub-pixels. For example, a pixel unit P may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit P may include four sub-pixels, namely, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel.

[0075] In some exemplary embodiments, the display substrate may be a liquid crystal display substrate, such as an array substrate of a liquid crystal display panel. Figure 3A is a schematic diagram illustrating the structure of a sub-pixel of a display substrate according to some exemplary embodiments of the present disclosure. With reference to Figures 1A to 3A, the display substrate may include: a first electrode E1, a second electrode E2, data signal lines DL, and scan signal lines GL, disposed on a base substrate 100. It should be understood that, if the display panel is a liquid crystal display panel, the display panel may include a liquid crystal layer positioned between the array substrate and a color filter substrate. The specific structures of the array substrate, color filter substrate, and liquid crystal layer can refer to those of existing liquid crystal display panels and will not be described in detail here. The first electrode E1 and the second electrode E2 are capable of generating a corresponding liquid crystal electric field under the influence of a drive signal. Liquid crystals in the liquid crystal layer are deflected by the liquid crystal electric field, thereby achieving the corresponding display function. For example, the liquid crystal layer may be disposed between the first electrode E1 and the second electrode E2. One of the first electrode E1 and the second electrode E2 may be a pixel electrode, and the other may be a common electrode. For example, the first electrode E1 may be a common electrode, and the second electrode E2 may be a pixel electrode.

[0076] In some specific embodiments, at least one sub-pixel further includes a thin film transistor T electrically connected to the data signal line DL. In the embodiments of the present disclosure, the thin film transistor T can have either a top-gate structure or a bottom-gate structure, which can be determined based on actual needs and is not limited here. The following describes the thin film transistor T in the embodiments of the present disclosure using a top-gate structure as an example.

[0077] Figure 3B schematically illustrates a cross-sectional view of a thin film transistor according to an embodiment of the present disclosure, and Figure 16 is a cross-sectional view of a display substrate according to some exemplary embodiments of the present disclosure, taken along line AA' in Figure 2B. Referring to Figures 3A, 3B, and 16, the display substrate may include: a semiconductor layer ACT located on a base substrate 100; a first conductive layer 10 located on a side of the semiconductor layer ACT remote from the base substrate 100; a second conductive layer 20 located on a side of the first conductive layer 10 remote from the base substrate 100; and a third conductive layer 30 located on a side of the second conductive layer 20 remote from the base substrate 100. For example, a thin film transistor T may include an active layer CH, a gate GE1, a source electrode SE1, and a drain electrode DE1. The active layer CH of the thin film transistor T may be located in the semiconductor layer ACT, the gate GE1 of the thin film transistor T may be located in the first conductive layer 10, and the source electrode SE1 and drain electrode DE1 of the thin film transistor T may be located in the second conductive layer 20. For example, a first electrode E1 (e.g., a common electrode) may be located in the third conductive layer 30.

[0078] As shown in Figure 3A, the display substrate can adopt a two-image two-domain (2Pixel2Domain, 2P2D) sub-pixel structure design. Each sub-pixel may include a plurality of strip-shaped pixel electrodes E2, and the plurality of strip-shaped pixel electrodes E2 of each sub-pixel are separated by slits. The so-called two-image two-domain means that the extension directions of the pixel electrodes E2 of two adjacent rows of sub-pixels are different, and the pixel electrodes E2 of each two adjacent rows of sub-pixels are roughly symmetrical with respect to the scanning signal line GL. Therefore, in the display substrate, for two adjacent rows of sub-pixels, the pixel electrode E2 and the common electrode E1 of one row of sub-pixels can form a first domain electric field, and the pixel electrode E2 and the common electrode E1 of the other row of sub-pixels can form a second domain electric field. Among them, the directions of the first domain electric field and the second domain electric field are different. In other words, the directions of the electric fields corresponding to each two adjacent rows of sub-pixels form a certain angle between each other, and then, the light emitting directions of each two adjacent rows of sub-pixels can compensate each other, which is beneficial to improving the display effect.

[0079] Referring back to FIG. 1A , the display substrate may have an irregular shape, which may include any irregular shape. For example, FIG. 1B to FIG. 1D schematically illustrate several examples of irregular shapes. It should be understood that the embodiments of the present disclosure do not particularly limit the shape of the display substrate. The embodiments of the present disclosure are described in detail below using the irregular shape shown in FIG. 1A as an example.

[0080] In an embodiment of the present disclosure, the display substrate includes N rows of pixel units, where N is a positive integer greater than or equal to 2. Exemplarily, with reference to FIG1A , the display area AA may include a plurality of sub-display areas AA1, AA2, and AA3. For example, at least one row of pixel units is provided in each sub-display area AA1, AA2, and AA3. In the embodiment shown in FIG1A , the number of sub-pixels included in each row of pixel units decreases irregularly from bottom to top. For example, the number of sub-pixels included in each row of pixel units located in the sub-display area AA3 is greater than the number of sub-pixels included in each row of pixel units located in the sub-display area AA2, and the number of sub-pixels included in each row of pixel units located in the sub-display area AA2 is greater than the number of sub-pixels included in each row of pixel units located in the sub-display area AA1.

[0081] For each row of pixel units, a scan signal line GL is provided to provide scan signals to each sub-pixel in that row of pixel units. In an embodiment of the present disclosure, among the N rows of pixel units, there are n rows of pixel units, and the number of sub-pixels included in these n rows of pixel units is inconsistent, where n is a positive integer greater than or equal to 2 and less than or equal to N. The loads electrically connected to the scan signal lines GL of these n rows of pixel units are inconsistent. For example, the theoretical load of the scan signal lines of each row of pixel units can be calculated based on the design drawing of the display substrate. For the scan signal lines, their loads can include resistive loads and capacitive loads.

[0082] The resistance R on the scanning signal line of the pixel unit in the i-th row of N rows of pixel units can be calculated using the following formula:

[0083] Ri=Rs*L / W, where L is the length of the scan signal line of the i-th row pixel unit, W is the width of the scan signal line of the i-th row pixel unit, and Rs is the square resistance of the metal material used for the scan signal line of the i-th row pixel unit.

[0084] The capacitance Ci on the scanning signal line of the i-th row of pixel units in the N rows of pixel units can be calculated using the following formula:

[0085] Ci=Ni*Cpixel, where Ni is the number of sub-pixels included in the pixel unit of the i-th row, and Cpixel is the capacitance load value of a single sub-pixel, which can be extracted by software or obtained by calculating the flat plate capacitance based on the area.

[0086] The inventors have found through research that for pixel units in different rows with inconsistent loads, the charging voltages achieved within the same charging time are inconsistent, which may lead to undesirable phenomena such as uneven display in each sub-display area during actual display.

[0087] In an embodiment of the present disclosure, load compensation can be performed on each row of pixel units with inconsistent loads. For example, a load compensation unit is electrically connected to the scanning signal line of each row of pixel units that requires load compensation, so that the load on the scanning signal line of each row of pixel units is basically consistent. In this way, undesirable phenomena such as uneven display of each sub-display area can be at least improved or even eliminated.

[0088] 1A to 3B , a display substrate according to some exemplary embodiments of the present disclosure may include: a base substrate 100, the base substrate 100 including a display area AA and a border area NA located on at least one side of the display area; a plurality of pixel units P located in the display area AA, the plurality of pixel units P being arranged in an array along a row direction X and a column direction Y on the base substrate 100, each row of pixel units P including a plurality of sub-pixels; a plurality of scanning signal lines GL provided on the base substrate 100, the plurality of scanning signal lines GL being used to respectively provide scanning signals to a plurality of rows of pixel units P; a plurality of load compensation units 200 provided on the base substrate 100 and located in the border area NA, the plurality of load compensation units 200 being respectively electrically connected to at least some of the plurality of scanning signal lines GL; and a common electrode E1 provided on the base substrate 100, at least a portion of the common electrode E1 being located in the display area AA, the common electrode E1 being connected to a common voltage signal.

[0089] 17A is a flow chart of a load compensation method applied to a display substrate according to some exemplary embodiments of the present disclosure. The load compensation method may include the following steps S1710 to S1770.

[0090] In step S1710, the display substrate is driven to display a white image. For example, for a display substrate such as an ADS type liquid crystal display substrate, the white image requires the highest charging voltage.

[0091] In step S1720, the charging voltages of the p-th row of pixel units and the q-th row of pixel units are obtained, where the p-th row of pixel units is the row of pixel units with the least number of sub-pixels among the N rows of pixel units, and the q-th row of pixel units is the row of pixel units with the greatest number of sub-pixels among the N rows of pixel units. For example, the p-th row of pixel units is a row of pixel units with a lighter load, and the charging voltage on the corresponding scanning signal line is larger, which is recorded as Vmax; the q-th row of pixel units is a row of pixel units with a heavier load, and the charging voltage on the corresponding scanning signal line is smaller, which is recorded as Vmin.

[0092] In step S1730 , the difference between the charging voltages of the pixel units in the p-th row and the pixel units in the q-th row is calculated, for example, δV=Vmax−Vmin, where δV is the difference between the charging voltages.

[0093] In step S1740, the difference in the charging voltage is compared with a specified voltage threshold. For example, the specified voltage threshold is a critical value between an acceptable range and an unacceptable range. The basis for the acceptable range is that the user cannot see the difference in the display of the entire panel, such as uneven display defects. In other words, when the entire panel is displayed at the same grayscale, δV less than one grayscale will not be visible to the naked eye. Therefore, the critical value can be calculated. According to the gamma curve, the minimum voltage difference of the signal determined by 6-bit data (i.e., the specified voltage threshold) is approximately 30mV, and the minimum voltage difference of the signal determined by 8-bit data (i.e., the specified voltage threshold) is approximately 8mV.

[0094] In step S1750, in response to the difference in the charging voltage being greater than a predetermined voltage threshold, it is determined that load compensation is required. For example, when it is determined that the difference between the charging voltage and Vmin of at least one row of pixel units is greater than the predetermined voltage threshold (e.g., 8 mV), it is determined that the display substrate requires load compensation.

[0095] In step S1760, in response to the load compensation, n rows of pixel units that need to be load compensated are determined, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein the difference between the charging voltage of each row of pixel units in the n rows of pixel units and the charging voltage of the qth row of pixel units is greater than a specified threshold.

[0096] For example, the voltage difference between the charging voltage and Vmin of the pixel cells in the remaining rows except the qth row is determined, and all rows of pixel cells whose voltage difference is greater than the specified voltage threshold (e.g., 8 mV) are found. These rows of pixel cells are then identified as the n rows of pixel cells that require load compensation. In this way, the n rows of pixel cells that require load compensation can be accurately determined.

[0097] In step S1770, a load compensation value of a load compensation unit is determined based on the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units. A plurality of scanning signal lines providing scanning signals to the n rows of pixel units are electrically connected to respective load compensation units. The load compensation value of the n rows of pixel units is negatively correlated with the number of sub-pixels in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value. In this manner, based on the precise determination of the n rows of pixel units requiring load compensation, load compensation is performed on the scanning signal lines of the n rows of pixel units, ensuring that the loads on the scanning signal lines of each row of pixel units are substantially consistent. This can at least improve, or even eliminate, undesirable phenomena such as display non-uniformity in each sub-display area.

[0098] FIG5 is a diagram showing the load difference ratio between signal scan lines of two adjacent rows of pixel units in the display substrate shown in FIG1A before load compensation. FIG17B is a flow chart of a load compensation method applied to a display substrate according to other exemplary embodiments of the present disclosure. Referring to FIG5 and FIG17B , the load compensation method may include the following steps S1810 to S1870.

[0099] In step S1810, the load difference between any two adjacent rows of pixel units is calculated. For example, the load difference can be expressed as a load difference percentage Ai between the two adjacent rows of pixel units:

[0100] Ai=[(R i *C i -R i+1 *C i+1 ) / R i+1 *C i+1 ]*100%, where R i and C i Represent the resistance load value and capacitance load value of the pixel unit in row i, R i+1 and C i+1 They represent the resistance load value and capacitance load value of the pixel unit in the i+1th row respectively.

[0101] In step S1820, the load difference is compared with a predetermined load difference threshold. For example, the load difference threshold can be determined based on whether the user can visually see the display difference, and the load difference threshold can be approximately 2% to 5%.

[0102] In step S1830, in response to the load difference being greater than a specified load difference threshold, n rows of pixel units requiring load compensation are determined, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein the load difference between each row of pixel units in the n rows of pixel units and its adjacent row of pixel units is greater than the specified load difference threshold.

[0103] As shown in Figure 5, the load difference ratio diagram on the scanning signal lines of two adjacent rows of pixel units shows that: for the embodiment shown in Figure 1A, the Ai value suddenly changes from row 940 to row 960, so load compensation is performed on the pixel units in rows 940 to 960. In addition, starting from row 950, the Ai value between two adjacent rows begins to exceed the load difference threshold, and compensation is required for the pixel units in rows 950 to 960. The area requiring compensation is the sub-display area AA1 shown in Figure 1A. It should be noted that although the sub-display area AA2 is also a special-shaped display area, there is no sudden change in the Ai value, and the Ai value between two adjacent rows is less than the load difference threshold, so no load compensation is required. In this way, the n rows of pixel units that require load compensation can be accurately determined.

[0104] In step S1840, a load compensation value of a load compensation unit is determined based on the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units. The qth row of pixel units is the row of pixel units with the largest number of sub-pixels in the N rows of pixel units. A plurality of scanning signal lines providing scanning signals to the n rows of pixel units are electrically connected to respective load compensation units. The load compensation value of the n rows of pixel units is negatively correlated with the number of sub-pixels in the row of pixel units. The load compensation value includes at least one of a capacitance compensation value and a resistance compensation value. In this manner, based on the precise determination of the n rows of pixel units requiring load compensation, load compensation is performed on the scanning signal lines of the n rows of pixel units, ensuring that the loads on the scanning signal lines of each row of pixel units are substantially consistent. This can at least improve, or even eliminate, undesirable phenomena such as display non-uniformity in each sub-display area.

[0105] In an embodiment of the present disclosure, at least one of the load compensation units includes at least one of a compensation capacitor and a compensation resistor.

[0106] For example, the compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is electrically connected to the scanning signal line, the second compensation capacitor electrode is connected to the common voltage signal, and the orthographic projection of the first compensation capacitor electrode on the substrate and the orthographic projection of the second compensation capacitor electrode on the substrate at least partially overlap. For the n rows of pixel units, the multiple scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation capacitors, and the overlapping area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units. For the at least n rows of pixel units, the size of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units in the row direction is negatively correlated with the number of sub-pixels included in the row of pixel units.

[0107] For example, the compensation resistor includes a compensation conductive trace. For the n rows of pixel units, a plurality of scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation conductive traces, and the resistance value of the compensation conductive trace of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units. For the at least n rows of pixel units, the length of the compensation conductive trace of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and / or the wire diameter of the compensation conductive trace of each row of pixel units is positively correlated with the number of sub-pixels included in the row of pixel units.

[0108] In the display substrate provided by the embodiments of the present disclosure, the smaller the number of sub-pixels connected to a corresponding scan signal line, the higher the compensation load value of the load compensation unit. By using load compensation units with different compensation load values ​​to compensate for scan signal lines with different numbers of sub-pixels, the load on different scan signal lines is uniform, preventing display variations and ensuring display quality.

[0109] Referring back to FIG. 1 , a display substrate according to some exemplary embodiments of the present disclosure may include: a driver chip 110 disposed on the base substrate 100 and located in the frame area NA, the driver chip 110 being used to output a scan signal; and a plurality of scan signal leads GLY disposed on the base substrate 100 and located in the frame area NA, the plurality of scan signal leads GLY being electrically connected to the plurality of scan signal lines GL, respectively. For example, the driver chip 110 may be a gate driver chip for providing a gate scan signal, and accordingly, the scan signal line GL is a gate line, and the scan signal lead GLY is a gate lead. In this embodiment, the scan signal lead GLY is electrically connected between the driver chip 110 and the scan signal line GL, and is used to provide the scan signal generated by the driver chip 110 to the scan signal line GL. The scan signal line GL then transmits the scan signal to each sub-pixel of a row of pixel units electrically connected thereto. In this embodiment, the scan signal lead GLY is located in a fan-out area (i.e., a fanout area), i.e., the scan signal lead GLY is a fan-out area routing line.

[0110] FIG4A is a schematic diagram of a fan-out area of ​​a display substrate according to some exemplary embodiments of the present disclosure. FIG4B to FIG4D are partial enlarged views of Region III, Region IV, and Region V in FIG4A , respectively. As shown in FIG4A to FIG4D , the fan-out area FA of the display substrate has limited space, and a large number of scan signal leads GLY need to be arranged in the fan-out area FA. In this case, a double-layer wiring method is adopted for the scan signal leads GLY in the fan-out area FA. That is, the scan signal leads GLY of two adjacent rows of pixel units can be located in two different conductive layers, respectively, to facilitate wiring in the fan-out area FA.

[0111] For example, for pixel cells in odd rows, the scan signal lead GLY is located in the first conductive layer 10; for pixel cells in even rows, the scan signal lead GLY is located in the second conductive layer 20. Alternatively, for pixel cells in odd rows, the scan signal lead GLY is located in the second conductive layer 20; for pixel cells in even rows, the scan signal lead GLY is located in the first conductive layer 10.

[0112] It should be noted that in other embodiments of the present disclosure, for example, if there is sufficient space in the fan-out area FA, the scan signal leads GLY can be arranged in a single layer in the fan-out area FA. For example, for N rows of pixel cells, all scan signal leads GLY are located in the first conductive layer 10. Alternatively, for N rows of pixel cells, all scan signal leads GLY are located in the second conductive layer 20.

[0113] Figure 6 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating the load compensation units of some rows of pixel units. Figure 7 is a partial enlarged diagram of the display substrate shown in Figure 6, schematically illustrating the load compensation units of the pixel units in the i-th row. Figure 8 is a partial enlarged diagram of the display substrate shown in Figure 6, schematically illustrating the load compensation units of the pixel units in the i+1-th row. Figure 9 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a plan view of the compensation capacitors and electrostatic protection circuits of two rows of pixel units. Figure 10 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a plan view of the compensation capacitors, electrostatic protection circuits, and electrostatic protection structures of a certain row of pixel units. Figure 11 is a partial schematic diagram of a display substrate according to some exemplary embodiments of the present disclosure, schematically illustrating a plan view of the compensation capacitors and compensation resistors of certain rows of pixel units. Figures 12A to 12D respectively schematically illustrate schematic cross-sectional views of the compensation capacitors of the display substrate according to some exemplary embodiments of the present disclosure. FIG13A is a partially enlarged view of a display substrate at region VI in FIG10 according to some exemplary embodiments of the present disclosure. FIG13B is a cross-sectional view taken along line BB′ in FIG13A. FIG14A is a partially enlarged view of a display substrate at region VI in FIG10 according to other exemplary embodiments of the present disclosure. FIG14B is a cross-sectional view taken along line CC′ in FIG14A. FIG15A is a partially enlarged view of a display substrate at region VI in FIG10 according to some exemplary embodiments of the present disclosure. FIG15B is a cross-sectional view taken along line DD′ in FIG15A.

[0114] In the embodiments of the present disclosure, as described above, the scan signal leads GLY can be arranged in a double-layer configuration. As shown in FIG7 , the scan signal leads GLY for the pixel units in the i-th row are located in the second conductive layer 20 ; as shown in FIG8 , the scan signal leads GLY for the pixel units in the i+1-th row are located in the first conductive layer 10 .

[0115] In an embodiment of the present disclosure, the compensation capacitor 200 may include a first compensation capacitor electrode 210 and a second compensation capacitor electrode 220. The first compensation capacitor electrode 210 may be connected to a scan signal, such as a gate scan signal; and the second compensation capacitor electrode 220 may be connected to a common voltage signal.

[0116] For example, the first compensation capacitor electrode 210 may be connected to the gate scan lead GLY. For another example, as shown in Figures 7 to 9, the first compensation capacitor electrode 210 and the scan signal lead GLY connected to each other may be a continuously extending integral structure.

[0117] For example, the first compensation capacitor electrode 210 includes a plurality of curved lines extending from the scanning signal lead GLY. Optionally, the first compensation capacitor electrode 210 includes a first conductive portion extending from the scanning signal lead GLY, and the first conductive portion has a hollow structure. In the embodiment of the present disclosure, by setting the first compensation capacitor electrode to be connected to the scanning signal lead, that is, the first compensation capacitor electrode and the scanning signal lead are set on the same layer, it is beneficial to form the first compensation capacitor electrode. The first compensation capacitor electrode is formed as a plurality of curved lines or a conductive portion with a hollow structure, which can avoid static electricity accumulation on the first compensation capacitor electrode while ensuring that it has a large conductive area, which is beneficial to electrostatic protection.

[0118] As shown in FIG7 , the display substrate may further include an electrostatic protection ring 310 for receiving a common voltage signal. The second compensation capacitor electrode 220 may be connected to the electrostatic protection ring 310 to receive the common voltage signal. For example, the second compensation capacitor electrode 220 may include a second conductive portion 320 extending from the electrostatic protection ring 310.

[0119] 9 , for the n rows of pixel units, the second conductive portion 320 of the compensation capacitor of the n rows of pixel units is a continuously extending integral structure.

[0120] 10 , for the n rows of pixel units, the second conductive portions 320 of the compensation capacitors of the n rows of pixel units extend from the electrostatic protection ring 310 toward the display area AA.

[0121] For any row of pixel units among the n rows of pixel units that require load compensation, the compensation capacitor is connected to the scanning signal lead GLY of the pixel unit in this row, and the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor are respectively located in different conductive layers, and the orthographic projections of the first compensation capacitor electrode and the second compensation capacitor electrode on the base substrate 100 at least partially overlap, and at least one insulating layer is arranged between the first compensation capacitor electrode and the second compensation capacitor electrode to form a capacitor structure.

[0122] For example, for odd-numbered rows of pixel cells, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A. For even-numbered rows of pixel cells, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and 12B. For all n rows of pixel cells, the second compensation capacitor electrode 220 is located in the third conductive layer 30, as shown in Figures 7-10, 12A, and 12B.

[0123] Optionally, for pixel cells in odd rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and 12B. For pixel cells in even rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A. For all n rows of pixel cells, the second compensation capacitor electrode 220 is located in the third conductive layer 30, as shown in Figures 7-10, 12A, and 12B.

[0124] Optionally, for pixel cells in odd rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A; the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in Figure 12C) or the third conductive layer 30. For pixel cells in even rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and 12B; the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in Figure 12C) or the third conductive layer 30.

[0125] Optionally, for pixel cells in odd rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20, as shown in Figures 7, 9, 10, and 12B; the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in Figure 12C) or the third conductive layer 30. For pixel cells in even rows, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10, as shown in Figures 8, 9, and 12A; the second compensation capacitor electrode 220 is located in the second conductive layer 20 (as shown in Figure 12C) or the third conductive layer 30.

[0126] Optionally, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10 , and the second compensation capacitor electrode 220 is located in the second conductive layer 20 or the third conductive layer 30 .

[0127] Optionally, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20 , and the second compensation capacitor electrode 220 is located in the first conductive layer 10 or the third conductive layer 30 .

[0128] That is to say, for the same row of pixel units, the first compensation capacitor electrode 210 and the scanning signal lead GLY are connected to each other, and the first compensation capacitor electrode 210 and the scanning signal lead GLY are both located in the same conductive layer selected from the first conductive layer 10 and the second conductive layer 20; the second compensation capacitor electrode 220 is located in another conductive layer different from the first compensation capacitor electrode 210.

[0129] According to other exemplary embodiments of the present disclosure, the display substrate may adopt GOA technology, i.e., Gate Driver on Array (GDA). In GOA technology, the driving circuit is directly arranged on the array substrate or display substrate to replace the external driver chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a scan signal line. The shift registers at each level output the turn-on voltage in sequence to achieve row-by-row scanning of pixels. In some embodiments, each level of shift register can also be connected to multiple scan signal lines. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrates.

[0130] 11 , the display substrate may include: a gate drive circuit 120 disposed on the base substrate 100 and located in the frame area NA, the gate drive circuit 120 being used to output a scan signal; and a plurality of scan signal leads GLY disposed on the base substrate 100 and located in the frame area NA, the plurality of scan signal leads GLY being electrically connected to the plurality of scan signal lines GL, respectively. In this embodiment, the scan signal lead GLY is electrically connected between the gate drive circuit 120 and the scan signal line GL, and is used to provide the scan signal generated by the gate drive circuit 120 to the scan signal line GL. The scan signal line GL then transmits the scan signal to each sub-pixel of a row of pixel units electrically connected thereto. In this embodiment, the scan signal lead GLY does not need to be disposed in the fan-out area (i.e., the fanout area). In this case, the scan signal lead GLY can be arranged in a single-layer wiring manner.

[0131] For example, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the first conductive layer 10 , and the second compensation capacitor electrode 220 is located in the second conductive layer 20 or the third conductive layer 30 .

[0132] Optionally, the first compensation capacitor electrode 210 and the scan signal lead GLY are both located in the second conductive layer 20 , and the second compensation capacitor electrode 220 is located in the first conductive layer 10 or the third conductive layer 30 .

[0133] Referring to Figure 12D, in some exemplary embodiments of the present disclosure, the compensation capacitor 200 may include a first sub-compensation capacitor 200A and a second sub-compensation capacitor 200B, the second compensation capacitor electrode 220 includes a first sub-compensation capacitor electrode 221 and a second sub-compensation capacitor electrode 222, and the first sub-compensation capacitor electrode 221 and the second sub-compensation capacitor electrode 222 are both connected to the common voltage signal.

[0134] For example, the first compensation capacitor electrode 210 is located in the second conductive layer 20 , the first sub-compensation capacitor electrode 221 is located in the first conductive layer 10 , and the second sub-compensation capacitor electrode 222 is located in the third conductive layer 30 .

[0135] The orthographic projection of the first compensation capacitor electrode 210 on the base substrate and the orthographic projection of the first sub-compensation capacitor electrode 221 on the base substrate at least partially overlap to form the first sub-compensation capacitor electrode 200A.

[0136] The orthographic projection of the first compensation capacitor electrode 210 on the base substrate and the orthographic projection of the second sub-compensation capacitor electrode 222 on the base substrate at least partially overlap to form the second sub-compensation capacitor electrode 200B.

[0137] In this embodiment, the compensation capacitor includes two capacitors connected in parallel. This helps increase the overlap area between the first compensation capacitor electrode and the second compensation capacitor electrode, thereby increasing the capacitance value of the compensation capacitor. In this way, the compensation capacitor can maintain the same capacitance value while reducing the width of the frame area occupied by the compensation capacitor, thereby facilitating the realization of a narrow-frame display device.

[0138] In an embodiment of the present disclosure, the load compensation unit may include at least one of a compensation capacitor and a compensation resistor. For example, the load compensation unit may only include the above-mentioned compensation capacitor, the load compensation unit may only include a compensation resistor, or the load compensation unit may include both a compensation capacitor and a compensation resistor.

[0139] 10 and 11 , a portion of the scan signal lead line GLY forms the compensation resistor 400 .

[0140] For example, at least a portion of the scan signal lead GLY, which provides scan signals to at least one row of pixel units, includes multiple curved segments, and the compensation resistor 400 includes these multiple curved segments. This curved routing arrangement increases the length of the scan signal lead GLY, thereby increasing its resistance. In this manner, resistance compensation is performed on the scan signal lead.

[0141] Optionally, the wire diameter of the scanning signal lead GLY may be changed to perform resistance compensation on the scanning signal lead.

[0142] Referring back to FIG. 11 , the scanning signal leads GLY of the pixel units in two adjacent rows extend along the row direction X, and the first compensation capacitor electrode 210 is located between the scanning signal leads GLY of the pixel units in two adjacent rows in the column direction Y.

[0143] 7 to 11 , the display substrate further includes an electrostatic protection circuit 300 , one end of which is electrically connected to both the scan signal lead GLY and the scan signal line GL, and the other end of which is electrically connected to the electrostatic protection ring 310 , for discharging static electricity on the scan signal lead GLY and the scan signal line GL to the electrostatic protection ring 310 .

[0144] FIG18 is an equivalent circuit diagram of an electrostatic protection circuit according to some exemplary embodiments of the present disclosure. Referring to FIG18 in conjunction with FIG7 to FIG11 , the electrostatic protection circuit may include four thin-film transistors. For example, the thin-film transistors of the electrostatic protection circuit may be formed simultaneously with the thin-film transistors of the pixel driving circuit. The gate electrode G1 of thin-film transistor T1 and the source electrode S1 of thin-film transistor T1 are electrically connected together, forming the first external lead of the electrostatic protection circuit. For example, this external lead may be electrically connected to both the scan signal lead GLY and the scan signal line GL. The drain electrode D2 of thin-film transistor T2 may be electrically connected to the source electrode S1 of thin-film transistor T1. Similarly, the gate electrode G2 of thin-film transistor T2 and the source electrode S2 of thin-film transistor T2 are electrically connected together. The drain electrode D1 of thin-film transistor T1 is electrically connected to the source electrode S2 of thin-film transistor T2. The gate electrode G3 of thin-film transistor T3 and the source electrode S3 of thin-film transistor T3 are electrically connected together, and are also electrically connected to the drain electrode D1 of thin-film transistor T1 and the gate electrode G2 of thin-film transistor T2. The drain electrode D4 of the thin film transistor T4 is electrically connected to the source electrode S3 of the thin film transistor T3. Similar to the above, the gate electrode G4 of the thin film transistor T4 and the source electrode S4 of the thin film transistor T4 are electrically connected together to form a second external lead of the electrostatic protection circuit. For example, this external lead can be electrically connected to the electrostatic protection ring 310. The drain electrode D3 of the thin film transistor T3 is electrically connected to the source electrode S4 of the thin film transistor T4.

[0145] In the embodiment of the present disclosure, when high-voltage static electricity is generated on a scan signal lead GLY or scan signal line GL, this high-voltage static electricity is dissipated through the static electricity protection circuit 300 to the static electricity protection ring 310. Then, through the static electricity protection ring 310, it is dissipated to the common voltage signal bus, thereby dissipating the high-voltage static electricity across the entire display substrate. In this way, damage to a scan signal lead GLY or scan signal line GL by the high-voltage static electricity can be prevented.

[0146] As shown in FIG9 , the display substrate further includes a first conductive transition portion 330 located in the third conductive layer 30. An end of the scan signal lead GLY near the display area AA is electrically connected to a first portion of the first conductive transition portion 330 via a first via hole VH1. An end of the scan signal line GL away from the display area AA is electrically connected to a second portion of the first conductive transition portion 330 via a second via hole VH2. A third portion of the first conductive transition portion 330 is electrically connected to one end of the electrostatic protection circuit 300 via a third via hole VH3.

[0147] Optionally, the display substrate may further include an electrostatic protection structure for the compensation capacitor. Referring to Figure 10 , the display substrate further includes a second conductive transition portion 340 located in the third conductive layer 30. A portion of the scan signal lead GLY is electrically connected to a portion of the second conductive transition portion 340 via a fourth via VH4, while another portion of the second conductive transition portion 340 is electrically connected to one end of the first compensation capacitor electrode 210 via a fifth via VH5.

[0148] The display substrate further includes a third conductive transition portion 350 located in the third conductive layer 30. Another portion of the scan signal lead GLY is electrically connected to a portion of the third conductive transition portion 350 through a sixth via hole VH6, and another portion of the third conductive transition portion 350 is electrically connected to the other end of the first compensation capacitor electrode 210 through a seventh via hole VH7.

[0149] For example, referring to Figures 13A and 13B, the scan signal lead GLY can be located in the first conductive layer 10, the first compensation capacitor electrode 210 can be located in the first conductive layer 10, and the second conductive transition portion 340 can be located in the third conductive layer 30. At least two insulating layers are provided between the first conductive layer 10 and the third conductive layer 30. In this case, the fourth via VH4, the fifth via VH5, the sixth via VH6, and the seventh via VH7 respectively penetrate the at least two insulating layers. The scan signal lead GLY located in the first conductive layer 10 is electrically connected to the second conductive transition portion 340 located in the third conductive layer 30 through the fourth via VH4. The first compensation capacitor electrode 210 located in the first conductive layer 10 is electrically connected to the second conductive transition portion 340 located in the third conductive layer 30 through the fifth via VH5. Through this conductive transition structure, the scan signal lead GLY and the first compensation capacitor electrode 210 are electrically connected. Through such a layer-changing design, the length of continuous extension of the same type of conductive traces can be reduced, thereby preventing electrostatic burns.

[0150] For example, referring to Figures 14A and 14B, the scan signal lead GLY can be located in the first conductive layer 10, the first compensation capacitor electrode 210 can be located in the second conductive layer 20, and the second conductive transition portion 340 can be located in the third conductive layer 30. At least one insulating layer is provided between the first conductive layer 10 and the second conductive layer 20. At least two insulating layers are provided between the first conductive layer 10 and the third conductive layer 30. In this case, the fourth via VH4 and the sixth via VH6 respectively penetrate the at least two insulating layers, and the fifth via VH5 and the seventh via VH7 respectively penetrate the at least one insulating layer. The scan signal lead GLY in the first conductive layer 10 is electrically connected to the second conductive transition portion 340 in the third conductive layer 30 via the fourth via VH4. The first compensation capacitor electrode 210 in the second conductive layer 20 is electrically connected to the second conductive transition portion 340 in the third conductive layer 30 via the fifth via VH5. This conductive transition structure electrically connects the scan signal lead GLY and the first compensation capacitor electrode 210. This layer-switching design reduces the length of continuously extending conductive traces of the same type, thereby preventing electrostatic burns.

[0151] For example, referring to Figures 15A and 15B, the scan signal lead GLY can be located in the second conductive layer 20, the first compensation capacitor electrode 210 can be located in the second conductive layer 20, and the second conductive transition portion 340 can be located in the third conductive layer 30. At least one insulating layer is provided between the second conductive layer 20 and the third conductive layer 30. In this case, the fourth via VH4, the fifth via VH5, the sixth via VH6, and the seventh via VH7 respectively penetrate the at least one insulating layer. The scan signal lead GLY located in the second conductive layer 20 is electrically connected to the second conductive transition portion 340 located in the third conductive layer 30 through the fourth via VH4. The first compensation capacitor electrode 210 located in the second conductive layer 20 is electrically connected to the second conductive transition portion 340 located in the third conductive layer 30 through the fifth via VH5. Through this conductive transition structure, the scan signal lead GLY and the first compensation capacitor electrode 210 are electrically connected. Through such a layer-changing design, the length of continuous extension of the same type of conductive traces can be reduced, thereby preventing electrostatic burns.

[0152] 10 , the display substrate includes a common voltage signal bus 360 for providing the common voltage signal. For the load compensation unit of at least one row of pixel units, the compensation capacitor 200 is located on a side of the common voltage signal bus 360 close to the display area AA in the row direction X, the compensation resistor 400 is located on a side of the compensation capacitor 200 close to the display area AA in the row direction X, and the electrostatic protection circuit 300 is located on a side of the compensation resistor 400 close to the display area AA.

[0153] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above. For example, the display panel may be a liquid crystal display panel.

[0154] At least some embodiments of the present disclosure further provide a display device. The display device may include the display substrate described above. The display device includes a display area AA and a frame area NA, wherein the frame area NA has a relatively small width, thereby realizing a narrow-frame display device.

[0155] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0156] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. Please refer to the above description for details, which will not be repeated here.

[0157] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; A plurality of pixel units located in the display area, wherein the plurality of pixel units are arranged in an array along row and column directions on the base substrate, and each row of pixel units includes a plurality of sub-pixels; A plurality of scanning signal lines provided on the base substrate, the plurality of scanning signal lines being used to provide scanning signals to a plurality of rows of pixel units respectively; a plurality of load compensation units disposed on the base substrate and located in the frame region, the plurality of load compensation units being electrically connected to at least some of the plurality of scan signal lines respectively; and A common electrode is provided on the base substrate, at least a portion of the common electrode is located in the display area, and the common electrode is connected to a common voltage signal. Wherein, at least one of the load compensation units includes at least one of a compensation capacitor and a compensation resistor; The display substrate includes N rows of pixel units, wherein n rows of pixel units in the N rows of pixel units include different numbers of sub-pixels, wherein N is a positive integer greater than or equal to 2, and n is a positive integer greater than or equal to 2 and less than or equal to N; and For the n rows of pixel units, the scanning signal lines of each row of pixel units are electrically connected to their own load compensation units, and the load compensation value of the load compensation unit of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units. The load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.

2. The display substrate according to claim 1, wherein The compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is electrically connected to the scanning signal line, the second compensation capacitor electrode is connected to the common voltage signal, and the orthographic projection of the first compensation capacitor electrode on the base substrate and the orthographic projection of the second compensation capacitor electrode on the base substrate at least partially overlap.

3. The display substrate according to claim 2, wherein: For the n rows of pixel units, the multiple scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation capacitors, and the overlapping area between the first compensation capacitor electrode and the second compensation capacitor electrode of the compensation capacitor of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units.

4. The display substrate according to claim 3, wherein: For the at least n rows of pixel units, a size in the row direction of at least one of the first compensation capacitor electrode and the second compensation capacitor electrode of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units.

5. The display substrate according to any one of claims 1 to 4, wherein: The compensation resistor includes a compensation conductive trace; and For the n rows of pixel units, the multiple scanning signal leads that provide scanning signals to each row of pixel units are electrically connected to their respective compensation conductive traces, and the resistance value of the compensation conductive trace of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units. The display substrate according to claim 5 , wherein: For the at least n rows of pixel units, the length of the compensation conductive traces of each row of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and / or the wire diameter of the compensation conductive traces of each row of pixel units is positively correlated with the number of sub-pixels included in the row of pixel units.

7. The display substrate according to claim 1, wherein: The display substrate further includes: A gate driving circuit is provided on the base substrate and located in the frame area, the gate driving circuit is used to output a scanning signal; and A plurality of scanning signal leads are provided on the base substrate and located in the frame area, and the plurality of scanning signal leads are electrically connected to the plurality of scanning signal lines respectively. The display substrate includes: a first conductive layer located on the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; and a third conductive layer located on a side of the second conductive layer away from the base substrate. For the same row of pixel units, the first compensation capacitor electrode and the scanning signal lead are connected to each other, and the first compensation capacitor electrode and the scanning signal lead are both located in a same conductive layer selected from the first conductive layer and the second conductive layer.

8. The display substrate according to claim 7, wherein: The first compensation capacitor electrode and the scan signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer; or, The first compensation capacitor electrode and the scan signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer.

9. The display substrate according to claim 7, wherein: The compensation capacitor includes a first sub-compensation capacitor and a second sub-compensation capacitor, the second compensation capacitor electrode includes a first sub-compensation capacitor electrode and a second sub-compensation capacitor electrode, and the first sub-compensation capacitor electrode and the second sub-compensation capacitor electrode are both connected to the common voltage signal; The first compensation capacitor electrode is located in the second conductive layer, the first sub-compensation capacitor electrode is located in the first conductive layer, and the second sub-compensation capacitor electrode is located in the third conductive layer; The orthographic projection of the first compensation capacitor electrode on the base substrate and the orthographic projection of the first sub-compensation capacitor electrode on the base substrate at least partially overlap to form the first sub-compensation capacitor electrode; The orthographic projection of the first compensation capacitor electrode on the base substrate and the orthographic projection of the second sub-compensation capacitor electrode on the base substrate at least partially overlap to form the second sub-compensation capacitor electrode.

10. The display substrate according to claim 1, wherein The display substrate further includes: A driving chip is provided on the base substrate and located in the frame area, the driving chip is used to output a scanning signal; and A plurality of scanning signal leads are provided on the base substrate and located in the frame area, and the plurality of scanning signal leads are electrically connected to the plurality of scanning signal lines respectively. The display substrate includes: a first conductive layer located on the base substrate; a second conductive layer located on a side of the first conductive layer away from the base substrate; and a third conductive layer located on a side of the second conductive layer away from the base substrate. For the same row of pixel units, the first compensation capacitor electrode and the scanning signal lead are connected to each other, and the first compensation capacitor electrode and the scanning signal lead are both located in a same conductive layer selected from the first conductive layer and the second conductive layer.

11. The display substrate according to claim 10, wherein: For pixel units in odd rows, the first compensation capacitor electrode and the scan signal lead are both located in the first conductive layer; for pixel units in even rows, the first compensation capacitor electrode and the scan signal lead are both located in the second conductive layer; for pixel units in all n rows, the second compensation capacitor electrode is both located in the third conductive layer; or, Among them, for the pixel units in odd rows, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer; for the pixel units in even rows, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer; for all n rows of pixel units, the second compensation capacitor electrode is all located in the third conductive layer.

12. The display substrate according to claim 10, wherein: For pixel units in odd rows, the first compensation capacitor electrode and the scan signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer; and for pixel units in even rows, the first compensation capacitor electrode and the scan signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer; or, Among them, for the pixel units in odd rows, the first compensation capacitor electrode and the scanning signal lead are both located in the second conductive layer, and the second compensation capacitor electrode is located in the first conductive layer or the third conductive layer; and for the pixel units in even rows, the first compensation capacitor electrode and the scanning signal lead are both located in the first conductive layer, and the second compensation capacitor electrode is located in the second conductive layer or the third conductive layer.

13. The display substrate according to claim 2, wherein: The first compensation capacitor electrode and the scan signal lead connected to each other are a continuously extending integral structure.

14. The display substrate according to claim 13, wherein: The first compensation capacitor electrode includes a plurality of curved lines extending from the scan signal lead; or The first compensation capacitor electrode includes a first conductive portion extending from the scan signal lead, and the first conductive portion has a hollow structure.

15. The display substrate according to claim 2, wherein: The scanning signal leads of the pixel units in two adjacent rows are extended along the row direction, and the first compensation capacitor electrode is located between the scanning signal leads of the pixel units in two adjacent rows in the column direction.

16. The display substrate according to claim 2, wherein: The display substrate includes an electrostatic protection ring connected to a common voltage signal; and The second compensation capacitor electrode includes a second conductive portion extending from the electrostatic protection ring.

17. The display substrate according to claim 16, wherein: For the n rows of pixel units, the second conductive portion of the compensation capacitor of the n rows of pixel units is a continuously extending integral structure; or, For the n rows of pixel units, the second conductive portions of the compensation capacitors of the n rows of pixel units extend from the electrostatic protection ring toward the display area.

18. The display substrate according to claim 2, wherein: The display substrate also includes an electrostatic protection circuit, one end of which is electrically connected to the scan signal lead and the scan signal line, and the other end of the electrostatic protection circuit is electrically connected to the electrostatic protection ring, for releasing static electricity on the scan signal lead and the scan signal line to the electrostatic protection ring.

19. The display substrate according to claim 18, wherein: The display substrate further includes a first conductive transition portion located in the third conductive layer; One end of the scanning signal lead close to the display area is electrically connected to the first part of the first conductive transition portion through a first via hole, and one end of the scanning signal line away from the display area is electrically connected to the second part of the first conductive transition portion through a second via hole, and the third part of the first conductive transition portion is electrically connected to one end of the electrostatic protection circuit through a third via hole.

20. The display substrate according to claim 19, wherein The display substrate further includes a second conductive transition portion located in the third conductive layer; a portion of the scan signal lead is electrically connected to a portion of the second conductive transition portion through a fourth via hole, and another portion of the second conductive transition portion is electrically connected to one end of the first compensation capacitor electrode through a fifth via hole; and / or, The display substrate also includes a third conductive transition portion located in the third conductive layer; another part of the scan signal lead is electrically connected to a part of the third conductive transition portion through a sixth via hole, and another part of the third conductive transition portion is electrically connected to the other end of the first compensation capacitor electrode through a seventh via hole.

21. The display substrate according to claim 5, wherein A portion of the scan signal lead line forms the compensation resistor.

22. The display substrate according to claim 21, wherein At least a portion of the scanning signal lead lines providing scanning signals to at least one row of pixel units includes a plurality of curved lines, and the compensation resistor includes the plurality of curved lines.

23. The display substrate according to claim 5, wherein: A difference in total loads on the scanning signal lines of pixel units in any two adjacent rows is within a specified threshold, wherein the total load includes a product of a capacitive load and a resistive load on the scanning signal lines.

24. The display substrate according to claim 18, wherein The display substrate includes a common voltage signal bus for providing the common voltage signal; and For the load compensation unit of at least one row of pixel units, the compensation capacitor is located on the side of the common voltage signal bus close to the display area in the row direction, the compensation resistor is located on the side of the compensation capacitor close to the display area in the row direction, and the electrostatic protection circuit is located on the side of the compensation resistor close to the display area.

25. A display device comprising the display substrate according to any one of claims 1 to 24.

26. A load compensation method applied to a display substrate, the display substrate comprising: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arranged in an array along row and column directions on the base substrate, each row of pixel units including a plurality of sub-pixels; a plurality of scan signal lines provided on the base substrate, the plurality of scan signal lines being used to respectively provide scan signals to the plurality of rows of pixel units; a plurality of load compensation units provided on the base substrate and located in the frame area, the plurality of load compensation units being respectively electrically connected to at least some of the plurality of scan signal lines; and a common electrode disposed on the base substrate, at least a portion of the common electrode being located in the display area, the common electrode being connected to a common voltage signal, wherein the display substrate includes N rows of pixel units, wherein N is a positive integer greater than or equal to 2, Characterized in that the method comprises: driving the display substrate to display a white screen; Obtaining charging voltages of pixel units in the p-th row and pixel units in the q-th row, wherein the pixel units in the p-th row are pixel units in the N-th row with the least number of sub-pixels, and the pixel units in the q-th row are pixel units in the N-th row with the greatest number of sub-pixels; Calculating a difference in charging voltage between the pixel units in the p-th row and the pixel units in the q-th row; comparing the difference in the charging voltage with a specified voltage threshold; In response to the difference between the charging voltages being greater than a specified voltage threshold, determining that load compensation is required; In response to the load compensation, determining n rows of pixel units that require load compensation, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein a difference between a charging voltage of each row of pixel units in the n rows of pixel units and a charging voltage of the qth row of pixel units is greater than a specified threshold; The load compensation value of the load compensation unit is determined based on the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units, wherein a plurality of scanning signal lines that provide scanning signals to the n rows of pixel units are electrically connected to respective load compensation units, respectively, the load compensation value of the n rows of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.

27. A load compensation method applied to a display substrate, the display substrate comprising: a base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units being arranged in an array along row and column directions on the base substrate, each row of pixel units including a plurality of sub-pixels; a plurality of scan signal lines provided on the base substrate, the plurality of scan signal lines being used to respectively provide scan signals to the plurality of rows of pixel units; a plurality of load compensation units provided on the base substrate and located in the frame area, the plurality of load compensation units being respectively electrically connected to at least some of the plurality of scan signal lines; and a common electrode disposed on the base substrate, at least a portion of the common electrode being located in the display area, the common electrode being connected to a common voltage signal, wherein the display substrate includes N rows of pixel units, wherein N is a positive integer greater than or equal to 2, Characterized in that the method comprises: Calculate the load difference between any two adjacent rows of pixel units; comparing the load difference with a specified load difference threshold; In response to the load difference being greater than a specified load difference threshold, determining n rows of pixel units that require load compensation, where n is a positive integer greater than or equal to 2 and less than or equal to N, wherein a load difference between each row of pixel units in the n rows of pixel units and its adjacent row of pixel units is greater than the specified load difference threshold; The load compensation value of the load compensation unit is determined based on the number of sub-pixels in each row of pixel units in the n rows of pixel units and the number of sub-pixels in the qth row of pixel units, wherein the qth row of pixel units is a row of pixel units with the largest number of sub-pixels in the N rows of pixel units, and a plurality of scanning signal lines that provide scanning signals to the n rows of pixel units are electrically connected to respective load compensation units, respectively, and the load compensation value of the n rows of pixel units is negatively correlated with the number of sub-pixels included in the row of pixel units, and the load compensation value includes at least one of a capacitance compensation value and a resistance compensation value.

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