Scanning circuit, array substrate and display device

Abstract

A scanning circuit is provided. The scanning circuit comprises a plurality of scanning units. Each of the plurality of scan cells includes a plurality of transistors. Each gate of each of the plurality of transistors includes a first portion and a second portion located in different layers. A first portion of each gate of the plurality of transistors in each scan cell is configured to be supplied with a power supply signal. Second portions of the respective gates of the plurality of transistors in the respective scan cells are configured to be supplied with gate scan signals, respectively. And the first parts of the grids of the at least two transistors in each scanning unit are one part of the integral structure.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a scanning circuit, an array substrate and a display device. Background Art

[0002] The image display device includes a driver for controlling the image display in each of a plurality of pixels. The driver is a transistor-based circuit including a gate drive circuit and a data drive circuit. The gate drive circuit is formed by cascading a plurality of shift register units. Each shift register unit outputs a gate drive signal to one of a plurality of gate lines. The gate drive signal from the gate drive circuit scans through the gate lines row by row, thereby controlling each row of transistors to be in an on / off state. The gate drive circuit can be integrated into a gate on array (GOA) circuit, and the GOA circuit can be directly formed in an array substrate of a display panel. Summary of the invention

[0003] In one aspect, the present disclosure provides a scanning circuit, comprising a plurality of scanning units; wherein each of the plurality of scanning units comprises a plurality of transistors; each gate of each of the plurality of transistors comprises a first part and a second part located at different layers; the first part of each gate of the plurality of transistors in each of the scanning units is configured to be provided with a power supply signal; the second part of each gate of the plurality of transistors in each of the scanning units is configured to be respectively provided with a gate scanning signal; and the first part of the gates of at least two transistors in each of the scanning units is part of the overall structure.

[0004] Optionally, the first parts of the gates of the at least two transistors in each scanning unit are connected to the same power signal line.

[0005] Optionally, a first portion of the gates of the plurality of transistors in each scanning unit is part of an integral structure.

[0006] Optionally, first portions of the gates of the plurality of transistors in each scanning unit are connected to the same power signal line.

[0007] Optionally, the first portions of the gates of the plurality of transistors are located at a same layer as at least one capacitor electrode of the one or more capacitors in each of the scanning units.

[0008] Optionally, the plurality of transistors are a plurality of n-type transistors.

[0009] Optionally, the active layers of the multiple transistors in each scanning unit are located in a layer, which is located on a side of the first part away from the substrate; and the second part is located in a layer, which is located on a side of the active layer away from the first part.

[0010] Optionally, one or more power lines are located on a side of the second portion away from the substrate, and the one or more power lines are configured to provide one or more power signals to the first portion.

[0011] Optionally, the scanning circuit also includes multiple power lines; wherein a first power line among the multiple power lines is configured to provide a power signal to a first part of a gate of at least one transistor in each scanning unit; and a second power line among the multiple power lines is configured to provide a power signal to a first part of a gate of a group of transistors in each scanning unit.

[0012] Optionally, a first portion of the gates of the group of transistors in each scanning unit is part of the integral structure.

[0013] Optionally, the scanning circuit also includes a third power line, a fourth power line and a fifth power line; wherein the fourth power line is connected to a first part of the gate of the first transistor in each scanning unit and is configured to provide a power signal to the first part of the gate of the first transistor in each scanning unit; the fifth power line is connected to a first part of the gate of the third transistor in each scanning unit and is configured to provide a power signal to the first part of the gate of the third transistor in each scanning unit; and the third power line is connected to an overall structure and is configured to provide a power signal to the overall structure, wherein the overall structure includes a first part of the gate of the transistor other than the first transistor and the third transistor in each scanning unit.

[0014] In another aspect, the present disclosure provides an array substrate, comprising a plurality of scanning circuits; wherein the plurality of scanning circuits include the scanning circuit.

[0015] Optionally, the overall structure includes first portions of gates of at least two transistors in each of a plurality of scanning units in a same level, respectively from the plurality of scanning circuits.

[0016] Optionally, the first portions of the gates of the at least two transistors in each of the plurality of scanning units in the same stage, respectively from the plurality of scanning circuits, are connected to the same power signal line.

[0017] Optionally, the overall structure includes first portions of respective gates of all transistors of a plurality of scan units in a same level, respectively, from the plurality of scan circuits.

[0018] Optionally, first portions of respective gates of all transistors of a plurality of scanning units in a same stage, respectively from the plurality of scanning circuits, are connected to a same power signal line.

[0019] Optionally, the array substrate further includes a third power line, a plurality of fourth power lines and a plurality of fifth power lines; wherein each of the plurality of fourth power lines is connected to a first part of a gate of a first transistor in a corresponding scanning circuit in the plurality of scanning circuits, and is configured to provide a power signal to the first part of the gate of the first transistor; each of the plurality of fifth power lines is connected to a first part of a gate of a third transistor in a corresponding scanning circuit in the plurality of scanning circuits, and is configured to provide a power signal to the first part; and the third power line is connected to an overall structure and is configured to provide a power signal to the overall structure, the overall structure including a first part of a gate of a transistor other than the first transistor and the third transistor in each of a plurality of scanning units in the same level respectively from the plurality of scanning circuits.

[0020] Optionally, the array substrate also includes a plurality of integral structures, which are commonly connected to a single third power line located in a peripheral area of ​​the array substrate; wherein each of the plurality of integral structures includes a first part of each gate of transistors of a plurality of scanning units in the same corresponding level respectively from the plurality of scanning circuits.

[0021] Optionally, the array substrate also includes a plurality of integral structures, which are commonly connected to a single third power line located in a peripheral area of ​​the array substrate; wherein each of the plurality of integral structures includes a first part of the gates of a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor of a plurality of scanning units at the same level respectively from the plurality of scanning circuits.

[0022] In another aspect, the present disclosure provides a display device including the scanning circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0025] Figure 2 It is shown Figure 1 A timing diagram of the operation of the corresponding scanning unit is shown in FIG.

[0026] Figure 3 is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0027] Figure 4 is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0028] Figure 5A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0029] Figure 5B It is shown Figure 5A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG.

[0030] Figure 5C To show Figure 5A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in .

[0031] Figure 5D To show Figure 5A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in .

[0032] Figure 5E It is shown Figure 5A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in .

[0033] Fig. 5F To show Figure 5A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0034] Figure 6 is along Figure 5A Cross-sectional view along line A-A'.

[0035] Figure 7 is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0036] Fig. 8A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0037] Figure 8B It is shown Fig. 8A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG.

[0038] Figure 8C To show Fig. 8A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in .

[0039] Fig.8D It is shown Fig. 8A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in .

[0040] Fig. 8E It is shown Fig. 8A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in .

[0041] Figure 8F To show Fig. 8A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0042] Figure 8G To show Fig. 8A Schematic diagram of the structure of the second signal line layer in the corresponding scanning unit shown in .

[0043] Fig. 9A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0044] Fig. 9B It is shown Fig. 9A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG.

[0045] Fig. 9C To show Fig. 9A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in .

[0046] Fig.9D To show Fig. 9A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in .

[0047] Fig.9E It is shown Fig. 9A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in .

[0048] Fig.9F To show Fig. 9A Schematic diagram of the structure of the third conductive layer in the corresponding scanning unit shown in .

[0049] Figure 9G To show Fig. 9A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0050] Fig.10is a schematic diagram showing the layout of multiple scanning circuits in an array substrate according to some embodiments of the present disclosure.

[0051] Fig.11 is a schematic diagram showing the structure of the overall structure of the first part of each gate of transistors in a plurality of scan circuits in an array substrate according to some embodiments of the present disclosure.

[0052] Fig.12 is a schematic diagram showing the connection between a third power line in an array substrate and a first portion of an overall structure including respective gates of transistors in a plurality of scan circuits according to some embodiments of the present disclosure.

[0053] Fig.13A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure.

[0054] Fig. 13B It is shown Fig.13A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG.

[0055] Fig. 13C To show Fig.13A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in .

[0056] Fig.13D To show Fig.13A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in .

[0057] Fig.13E It is shown Fig.13A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in .

[0058] Fig.13F To show Fig.13A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0059] Fig.14 is a schematic diagram showing the structure of the overall structure of a first part of some gates of some transistors in a plurality of scan circuits in an array substrate according to some embodiments of the present disclosure.

[0060] Fig.15 is a schematic diagram showing the connection between a third power line in an array substrate and a first portion of an overall structure including some gates of some transistors in a plurality of scan circuits according to some embodiments of the present disclosure.

[0061] Fig.16 is a schematic diagram showing a display area and a peripheral area in a display panel according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0062] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0063] The relevant scanning circuit in the relevant display device usually uses polysilicon as the semiconductor material to manufacture the active layer of the transistor. However, polysilicon transistors are prone to leakage current. The inventors of the present disclosure have found that transistors using metal oxide materials as the material for manufacturing the active layer have better performance and have negligible leakage current. In addition, the inventors of the present disclosure have found that, surprisingly and unexpectedly, the substrate bias effect can be used to significantly improve the performance of metal oxide transistors.

[0064] The substrate bias effect refers to the influence of the substrate voltage between the source and the drain on the threshold voltage (Vth) of the transistor. When the substrate voltage is positive, Vth will be caused to shift toward the positive bias; conversely, when the substrate voltage is negative, Vth will be caused to shift toward the negative bias. The inventors of the present disclosure have found that the substrate bias effect can be used to implement a positive bias of Vth in a transistor, thereby ensuring that the transistor can be correctly turned on or off. Specifically, the substrate voltage of the transistor can be set to a positive value, which will cause Vth to shift toward the positive bias. This method ensures that the transistor operates within the correct voltage range and avoids unnecessary errors.

[0065] Therefore, the present disclosure particularly provides a scanning circuit, an array substrate and a display device, which substantially avoid one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes a plurality of scanning units. Optionally, each scanning unit in the plurality of scanning units includes a plurality of transistors. Optionally, each gate of each transistor in the plurality of transistors includes a first portion and a second portion located at different layers. Optionally, the first portion of each gate of the plurality of transistors in each scanning unit is configured to be provided with a power supply signal. Optionally, the second portion of each gate of the plurality of transistors in each scanning unit is configured to be provided with a gate scanning signal, respectively. Optionally, the first portion of the gate of at least two transistors in each scanning unit is part of the overall structure.

[0066] Various suitable scanning circuits may be used in the present disclosure. Figure 1 is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 1In some embodiments, each scanning unit includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, and a third processing subcircuit PSC3. Each scanning unit can be configured to send a control signal to one or more rows of sub-pixels. In one example, each scanning unit is configured to send a control signal to a single row of sub-pixels. In another example, each scanning unit is configured to send a control signal to two or more rows of sub-pixels.

[0067] In some embodiments, the output sub-circuit OSC is configured to provide the voltage of the first power signal VGL or the second power signal VGH to the output terminal TM4 in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0068] The ninth transistor T9 is coupled between the first power supply signal VGL and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which ( Figure 1 The signal (denoted as Outc) may be transmitted to the nth gate line and used as a gate driving signal having a gate-on level.

[0069] The tenth transistor T10 is coupled between the output terminal TM4 and the second power supply signal VGH. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which (at Figure 1 In the figure, Outc) may be provided to the nth gate line and used as a gate drive signal with a gate cut-off level. In an example, when the gate drive signal has a gate cut-off level, it can be understood that the gate drive signal is not provided.

[0070] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0071] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 to the first node N1.

[0072] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0073] The eighth transistor T8 is coupled between the first power signal VGL and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the first power signal VGL can be provided to the fourth node N4.

[0074] The second capacitor C2 is coupled between the first power signal VGL and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0075] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.

[0076] A first end of the first capacitor C1 is coupled to the fifth node N5 , and a second end of the first capacitor C1 is coupled to the third node N3 , which is a common node between the sixth transistor T6 and the seventh transistor T7 .

[0077] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, and thus, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0078] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the second clock signal CB provided to the third input terminal TM3, thereby applying the voltage of the first power signal VGL to the third node N3.

[0079] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5.

[0080] The fifth transistor T5 is coupled between the first power signal VGL and the fourth transistor T4. A gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0081] The fourth transistor T4 is coupled between the fifth transistor T5 and the first node. The gate of the fourth transistor T4 is configured to be provided with a second clock signal CB, which is provided to the third input terminal TM3. The first electrode of the fourth transistor T4 is coupled to the first node N1. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0082] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate of the second transistor T2 is coupled to the first node N1.

[0083] The third transistor T3 is coupled between the second node N2 and the second power signal VGH. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on so that the voltage of the second power signal VGH can be provided to the second node N2.

[0084] The present disclosure can be implemented in a scanning circuit having various types of transistors, including a scanning circuit having a p-type transistor, a scanning circuit having an n-type transistor, and a scanning circuit having one or more p-type transistors and one or more n-type transistors. For a p-type transistor, a valid control signal (e.g., a turn-on control signal) is a low voltage signal, while an invalid control signal (e.g., a cut-off control signal) is a high voltage signal. For an n-type transistor, a valid control signal (e.g., a turn-on control signal) is a high voltage signal, while an invalid control signal (e.g., a cut-off control signal) is a low voltage signal.

[0085] In some embodiments, reference Figure 1 , each of the first to tenth transistors T1 to T10 may be formed of an n-type transistor such as a metal oxide transistor. In some embodiments, the gate-on voltage of the first to tenth transistors T1 to T10 may be set to a high level, and the gate-off voltage may be set to a low level.

[0086] In an alternative embodiment, each of the first to tenth transistors T1 to T10 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to tenth transistors T1 to T10 may be set to a low level, and the gate-off voltage may be set to a high level.

[0087] Figure 2 It is shown Figure 1 The timing diagram of the operation of the corresponding scanning unit is shown in FIG. Figure 2 In some embodiments, the operation of each scanning unit includes a first stage p1, a second stage p2, a third stage p3, a fourth stage p4 and a fifth stage p5.

[0088] In some embodiments, during the first phase p1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. In addition, during the first phase p1, the second clock signal CB is not provided to the third input terminal TM3, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0089] In some embodiments, during the first phase p1, the start signal STV to be provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scanning unit has a high level, and a high voltage (e.g., the voltage of the second power signal VGH) may be applied to the first node N1. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0090] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0091] In some embodiments, when the third transistor T3 is turned on, the voltage of the second power signal VGH is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0092] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the first power signal VGL is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0093] In some embodiments, when the tenth transistor T10 is turned on, the voltage of the second power signal VGH is provided to the output terminal TM4. During the first phase p1, no gate driving signal is provided to the n-th gate line.

[0094] In some embodiments, during the second phase p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the previous phase. Since the first node N1 is maintained in a high voltage state, the second transistor T2, the eighth transistor T8 and the tenth transistor T10 remain turned on. When the eighth transistor T8 remains turned on, the voltage of the first power supply signal VGL is provided to the fourth node N4. Since the fourth node N4 remains in a low voltage state, the ninth transistor T9 remains turned off.

[0095] In some embodiments, during the second phase p2, the second clock signal CB is provided to the third input terminal TM3. The fourth transistor T4 and the seventh transistor T7 are turned on by the second clock signal CB provided to the third input terminal TM3. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a low voltage.

[0096] In some embodiments, during the third phase p3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.

[0097] In some embodiments, during the third phase p3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK is provided to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0098] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a low voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from an output terminal of a previous scanning unit. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0099] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 and the third node N3 are electrically coupled to each other. Since the second clock signal CB is not provided to the third input terminal TM3 during the third phase p3, the third node N3 is maintained at a low voltage. Since the seventh transistor T7 remains turned off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store a voltage corresponding to the turn-on level of the sixth transistor T6.

[0100] In some embodiments, during the fourth phase p4, the second clock signal CB may be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0101] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The high voltage of the second clock signal CB provided to the third input terminal TM3 is provided to the third node N3 and the fourth node N4 via the sixth transistor T6 that remains turned on. When the high voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0102] In some embodiments, when the ninth transistor T9 is turned on, the voltage of the first power signal VGL is provided to the output terminal TM4. The voltage of the first power signal VGL provided to the output terminal TM4 is provided to the n-th gate line as a gate driving signal.

[0103] In some embodiments, during the fifth stage p5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a high voltage through the second capacitor C2. The ninth transistor T9 remains turned on, and the voltage of the first power supply signal VGL is provided to the nth level gate line as a gate drive signal.

[0104] The supply of the second clock signal CB is interrupted during the fifth phase p5 , so the fourth transistor T4 remains turned off, and thus the voltage of the second clock signal CB does not affect the voltage of the first node N1 .

[0105] Various alternative scanning circuits may be used in the present disclosure. Figure 3 is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 3 In some embodiments, each scanning unit includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first voltage stabilizing subcircuit SSC1, and a second voltage stabilizing subcircuit SSC2. Each scanning unit can be configured to send a control signal to one or more rows of sub-pixels. In one example, each scanning unit is configured to send a control signal to a single row of sub-pixels. In another example, each scanning unit is configured to send a control signal to two or more rows of sub-pixels.

[0106] In some embodiments, the output sub-circuit OSC is configured to provide the voltage of the second power signal VGH or the first power signal VGL to the output terminal TM4 in response to the voltage of the fourth node N4. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0107] The ninth transistor T9 is coupled between the second power supply signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, which ( Figure 3 The signal (denoted as Outc) may be transmitted to the nth gate line and used as a gate driving signal having a gate-on level.

[0108] The tenth transistor T10 is coupled between the output terminal TM4 and the first power signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power signal VGL is provided to the output terminal TM4, which (at Figure 3 In the example, when the gate drive signal has the gate cut-off level, it can be understood that the gate drive signal is not provided.

[0109] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0110] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 to the first node N1.

[0111] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0112] The eighth transistor T8 is coupled between the second power signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power signal VGH can be provided to the fourth node N4.

[0113] The second capacitor C2 is coupled between the second power signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge a voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0114] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and is configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7 and a first capacitor C1.

[0115] A first end of the first capacitor C1 is coupled to the fifth node N5 , and a second end of the first capacitor C1 is coupled to the third node N3 , which is a common node between the sixth transistor T6 and the seventh transistor T7 .

[0116] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, and thus, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0117] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the second clock signal CB provided to the third input terminal TM3, thereby applying the voltage of the second power signal VGH to the third node N3.

[0118] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a third capacitor C3.

[0119] The fifth transistor T5 is coupled between the second power signal VGH and the fourth transistor T4. A gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0120] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to be provided with the second clock signal CB provided to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0121] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. A gate of the second transistor T2 is coupled to the first node N1.

[0122] The third transistor T3 is coupled between the second node N2 and the first power signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on so that the voltage of the first power signal VGL can be provided to the second node N2.

[0123] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. A first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the first electrode of the fourth transistor T4. A second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0124] In some embodiments, the first voltage stabilizing subcircuit SSC1 is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first voltage stabilizing subcircuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first voltage stabilizing subcircuit SSC1 includes an eleventh transistor T11.

[0125] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power signal VGL. Since the first power signal VGL has a gate-on level voltage, the eleventh transistor T11 can always remain turned on. Therefore, the second node N2 and the fifth node N5 can be maintained at the same voltage and operate as substantially the same node.

[0126] In some embodiments, the second voltage stabilizing sub-circuit SSC2 is coupled between the first node N1 and the output sub-circuit OSC. Optionally, the second voltage stabilizing sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second voltage stabilizing sub-circuit SSC2 includes a twelfth transistor T12.

[0127] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power signal VGL. Since the first power signal VGL has a gate-on level voltage, the twelfth transistor T12 can always remain turned on. Therefore, the first node N1 and the gate of the tenth transistor T10 can be maintained at the same voltage.

[0128] In some embodiments, reference Figure 3 , each of the first to twelfth transistors T1 to T12 may be formed of an n-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a high level, and the gate-off voltage may be set to a low level.

[0129] In an alternative embodiment, each of the first to twelfth transistors T1 to T12 may be formed of a p-type transistor. In some embodiments, the gate-on voltage of the first to twelfth transistors T1 to T12 may be set to a low level, and the gate-off voltage may be set to a high level.

[0130] Various alternative scanning circuits may be used in the present disclosure. Figure 4is a circuit diagram of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 4 In some embodiments, each scanning unit includes a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GC2. In some embodiments, the gate of the first control transistor GT1 is electrically connected to the first clock signal terminal GCK1, the first electrode of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second electrode of the first control transistor GT1 is electrically connected to the first node G1; the gate of the second control transistor GT2 is electrically connected to the first node G1, the first electrode of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK1, and the second electrode of the second control transistor GT2 is electrically connected to the second node G2; the gate of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK1, the first electrode of the third control transistor GT3 is electrically connected to the first power supply signal VGL, and the second electrode of the third control transistor GT3 is electrically connected to the second node G2; the gate of the fourth control transistor GT4 is electrically connected to the second node G2, the first electrode of the fourth control transistor GT4 is electrically connected to the second power supply signal VGH, and the second electrode of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the gate of the fifth control transistor GT5 is electrically connected to the third node G3, and the first electrode of the fifth control transistor GT5 is electrically connected to the second clock The gate of the sixth control transistor GT6 is electrically connected to the second node G2, the first electrode of the sixth control transistor GT6 is electrically connected to the second power supply signal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7; the gate of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the seventh control transistor GT7 is electrically connected to the first node G1; the gate of the eighth control transistor GT8 is electrically connected to the first power supply signal VGL, the first electrode of the eighth control transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third node G3; the first electrode plate GC11 of the first control capacitor GC1 is electrically connected to the second node G2, and the second electrode plate GC12 of the first control capacitor GC1 is electrically connected to the second power supply signal VGH; the first electrode plate GC21 of the second control capacitor GC2 is electrically connected to the third node G3, and the second electrode plate GC22 of the second control capacitor GC2 is electrically connected to the output terminal GOUT. In an example, the first control transistor GT1 to the eighth control transistor GT8 can be a P-type transistor or can be an N-type transistor. In another example, the second power signal VGH provides a continuous high level signal, and the first power signal VGL provides a continuous low level signal.

[0131] Figure 5Ais a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 5B It is shown Figure 5A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG. Figure 5C To show Figure 5A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in . Figure 5D To show Figure 5A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in . Figure 5E It is shown Figure 5A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in .

[0132] Fig. 5F To show Figure 5A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0133] Figure 6 is along Figure 5A Cross-sectional view along line A-A'. Figure 5A Marked with marks indicating transistors (T1, T2, T3, T4, T5, T6, T7, T8, T9 and T10) and capacitors (C1 and C2) in each scanning unit and signal lines (CB, CK, VGL, VGH, VGL2 and STV).

[0134] Reference FIG. 5A to FIG. 5F as well as Figure 6 In some embodiments, the array substrate includes a base substrate BS, a light-shielding layer LSL located on the base substrate BS, an insulating layer IN located on a side of the light-shielding layer LSL away from the base substrate BS, a first conductive layer Gate1 located on a side of the insulating layer IN away from the base substrate BS, a first gate insulating layer GI1 located on a side of the first conductive layer Gate1 away from the base substrate BS, a semiconductor material layer SML located on a side of the first gate insulating layer GI1 away from the base substrate BS, a second gate insulating layer GI2 located on a side of the semiconductor material layer SML away from the base substrate BS, a second conductive layer Gate2 located on a side of the second gate insulating layer GI2 away from the base substrate BS, a passivation layer PVX located on a side of the semiconductor material layer SML away from the base substrate BS; and a first signal line layer SD1 located on a side of the passivation layer PVX away from the base substrate BS.

[0135] refer to Figure 5A and Figure 5BIn some embodiments, the light shielding layer LSL includes a first capacitor electrode Ce1 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light shielding layer. For example, a metal material can be deposited on a substrate by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable metal materials for manufacturing the light shielding layer include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or stacks containing them.

[0136] refer to Figure 5A and Figure 5C In some embodiments, the first conductive layer Gate1 includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a first portion of each gate of each transistor. In one example, the first conductive layer Gate1 includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, a first portion G1-1 of the gate of the first transistor, a first portion G2-1 of the gate of the second transistor, a first portion G3-1 of the gate of the third transistor, a first portion G4-1 of the gate of the fourth transistor, a first portion G5-1 of the gate of the fifth transistor, a first portion G6-1 of the gate of the sixth transistor, a first portion G7-1 of the gate of the seventh transistor, a first portion G8-1 of the gate of the eighth transistor, a first portion G9-1 of the gate of the ninth transistor, and a first portion G10-1 of the gate of the tenth transistor. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer Gate1. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first conductive layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0137] Reference Figure 5A and Figure 5E In some embodiments, the semiconductor material layer SML includes an active layer of a transistor in each scanning unit. Figure 5EMarked with a mark, it represents the active layer of the transistor in each scanning unit, such as the active layer ACT1 of the first transistor, the active layer ACT2 of the second transistor, the active layer ACT3 of the third transistor, the active layer ACT4 of the fourth transistor, the active layer ACT5 of the fifth transistor, the active layer ACT6 of the sixth transistor, the active layer ACT7 of the seventh transistor, the active layer ACT8 of the eighth transistor, the active layer ACT9 of the ninth transistor, and the active layer ACT10 of the tenth transistor. Various suitable semiconductor materials can be used to manufacture the semiconductor material layer SML. Examples of semiconductor materials used to manufacture the semiconductor material layer SML include: metal oxide-based semiconductor materials (such as indium gallium zinc oxide) and metal nitride oxide-based semiconductor materials (such as zinc oxynitride).

[0138] refer to Figure 5A and Figure 5D In some embodiments, the second conductive layer Gate2 includes the second portion of each gate of each transistor. In one example, the second conductive layer Gate2 includes the second portion G1-2 of the gate of the first transistor, the second portion G2-2 of the gate of the second transistor, the second portion G3-2 of the gate of the third transistor, the second portion G4-2 of the gate of the fourth transistor, the second portion G5-2 of the gate of the fifth transistor, the second portion G6-2 of the gate of the sixth transistor, the second portion G7-2 of the gate of the seventh transistor, the second portion G8-2 of the gate of the eighth transistor, the second portion G9-2 of the gate of the ninth transistor, and the second portion G10-2 of the gate of the tenth transistor. In some embodiments, the second conductive layer Gate2 also includes a first output signal line OUT1, which is configured to transmit an output signal from each scanning unit to the fourth terminal TM4; and a second output signal line OUT2, which is configured to transmit an output signal from each scanning unit to the first terminal in the next level scanning unit.

[0139] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second conductive layer Gate2. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second conductive layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0140] refer to Figure 5A and Fig. 5F In some embodiments, the first signal line layer SD1 includes a start signal line STVL, a first clock signal line CKL, a second clock signal line CBL, a first power line VGLL, a second power line VGHL, and a third power line VGLL2. Fig. 5FMarked with a mark, the mark represents the first electrode and the second electrode of the transistor in each scanning unit. For example, the first transistor includes a first electrode S1 and a second electrode D1, the second transistor includes a first electrode S2 and a second electrode D2, the third transistor includes a first electrode S3 and a second electrode D3, the fourth transistor includes a first electrode S4 and a second electrode D4, the fifth transistor includes a first electrode S5 and a second electrode D5, the sixth transistor includes a first electrode S6 and a second electrode D6, the seventh transistor includes a first electrode S7 and a second electrode D7, the eighth transistor includes a first electrode S8 and a second electrode D8, the ninth transistor includes a first electrode S9 and a second electrode D9, and the tenth transistor includes a first electrode S10 and a second electrode D10. In some embodiments, the first signal line layer SD1 also includes a third output signal line OUT3 connected to the second electrodes of the ninth transistor and the tenth transistor. The third output signal line OUT3 is also connected to the first output signal line OUT1 and to the second output signal line OUT2.

[0141] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer SD1 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer SD1 includes a plurality of sublayers stacked together. In one example, the first signal line layer SD1 includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer SD1 includes a stacked molybdenum / aluminum / molybdenum multilayer structure.

[0142] In some embodiments, the first power line VGLL is configured to provide a first power signal, the second power line VGHL is configured to provide a second power signal, and the third power line VGLL2 is configured to provide a third power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the first power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the third power signal. Optionally, the voltage level of the third power signal is higher than the voltage level of the first power signal.

[0143] Reference FIG. 5A to FIG. 5F as well as Figure 6In some embodiments, each gate of each transistor in each scanning unit includes two parts located at two different layers. For example, the gate of the first transistor includes a first part G1-1 and a second part G1-2; the gate of the second transistor includes a first part G2-1 and a second part G2-2; the gate of the third transistor includes a first part G3-1 and a second part G3-2; the gate of the fourth transistor includes a first part G4-1 and a second part G4-2; the gate of the fifth transistor includes a first part G5-1 and a second part G5-2; the gate of the sixth transistor includes a first part G6-1 and a second part G6-2; the gate of the seventh transistor includes a first part G7-1 and a second part G7-2; the gate of the eighth transistor includes a first part G8-1 and a second part G8-2; the gate of the ninth transistor includes a first part G9-1 and a second part G9-2; the gate of the tenth transistor includes a first part G10-1 and a second part G10-2.

[0144] In one example, a first portion of each gate of each transistor in each scanning unit is located at the first conductive layer Gate1, and a second portion of each gate of each transistor in each scanning unit is located at the second conductive layer Gate2. Various alternative embodiments can be practiced according to the present disclosure. In an alternative example, a first portion of each gate of each transistor in each scanning unit is located at the second conductive layer Gate2, and a second portion of each gate of each transistor in each scanning unit is located at the third conductive layer. In another alternative example, a first portion of each gate of each transistor in each scanning unit is located at the light shielding layer LSL, and a second portion of each gate of each transistor in each scanning unit is located at the second conductive layer Gate2.

[0145] In some embodiments, each active layer of each transistor in each scanning unit is located on a side of the first portion of each gate of each transistor in each scanning unit away from the substrate BS. Optionally, each second portion of each gate of each transistor in each scanning unit is located on a side of the active layer of each transistor in each scanning unit away from the first portion of each gate of each transistor in each scanning unit.

[0146] In an alternative example, the second portion of each transistor of each transistor in each scanning unit is located on a side where the first portion of each gate of each transistor in each scanning unit is away from the substrate BS. Optionally, each active layer of each transistor in each scanning unit is located on a side where the second portion of each gate of each transistor in each scanning unit is away from the first portion of each transistor of each transistor in each scanning unit.

[0147] In an alternative example, the first portion of each transistor of each transistor in each scanning unit is located on a side where the second portion of each gate of each transistor in each scanning unit is away from the substrate BS. Optionally, each active layer of each transistor in each scanning unit is located on a side where the second portion of each gate of each transistor in each scanning unit is away from the substrate BS, and is located on a side where the first portion of each gate of each transistor in each scanning unit is close to the substrate BS.

[0148] In some embodiments, the orthographic projection of the second portion of each gate of each transistor in each scanning unit on the substrate substrate overlaps at least partially with the orthographic projection of the first portion of each gate of each transistor in each scanning unit on the substrate substrate. Optionally, the orthographic projection of the second portion of each gate of each transistor in each scanning unit on the substrate substrate overlaps substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or completely overlaps) with the orthographic projection of the first portion of each gate of each transistor in each scanning unit on the substrate substrate.

[0149] In some embodiments, the orthographic projection of the active layer of each transistor in each scanning unit on the substrate at least partially overlaps with the orthographic projection of the first part of each gate of each transistor in each scanning unit on the substrate, and at least partially overlaps with the orthographic projection of the second part of each gate of each transistor in each scanning unit on the substrate.

[0150] In some embodiments, the first portion of each gate of the transistor in each scanning unit is configured to be provided with the same signal. Optionally, the first portion of each gate of the transistor in each scanning unit is configured to be provided with a power signal (e.g., a third power signal provided by a third power signal line VGLL2).

[0151] In some embodiments, the first portion of each gate of the transistors in each scanning unit is part of the overall structure. For example, the first portion G1-1 of the gate of the first transistor, the first portion G2-1 of the gate of the second transistor, the first portion G3-1 of the gate of the third transistor, the first portion G4-1 of the gate of the fourth transistor, the first portion G5-1 of the gate of the fifth transistor, the first portion G6-1 of the gate of the sixth transistor, the first portion G7-1 of the gate of the seventh transistor, the first portion G8-1 of the gate of the eighth transistor, the first portion G9-1 of the gate of the ninth transistor, and the first portion G10-1 of the gate of the tenth transistor are interconnected and are part of the overall structure. Reference Figure 5A , Figure 5C , Fig. 5F and Figure 6, the overall structure of the first part including each gate of the transistor in each scanning unit is located at a different layer from the third power line VGLL2. In an example, the third power line VGLL2 is connected to the overall structure of the first part including each gate of the transistor in each scanning unit, for example, through a via extending through the passivation layer PVX, the second gate insulating layer GI2 and the first gate insulating layer GI1.

[0152] exist FIG. 5A to FIG. 5F In the example shown, the start signal line STVL separates the third power line VGLL2 from the transistors of each scanning unit. Various alternative embodiments may be practiced according to the present disclosure. Figure 7 is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 7 In some embodiments, the third power line VGLL2 separates the start signal line STVL from the transistors of each scanning unit.

[0153] exist FIG. 5A to FIG. 5F In the example shown, the third power line VGLL2 is located in the same layer as the start signal line STVL, the first clock signal line CKL, the second clock signal line CBL, the first power line VGLL, and the second power line VGHL. As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when the third power line VGLL2 and the first power line VGLL are formed due to one or more steps of the same patterning process performed in the material deposited in the same deposition process, the third power line VGLL2 and the first power line VGLL are located in the same layer. In another example, the third power line VGLL2 and the first power line VGLL can be formed in the same layer by simultaneously performing the step of forming the third power line VGLL2 and the step of forming the first power line VGLL. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0154] In some embodiments, the third power line VGLL2 is located at a different layer from at least one of the start signal line STVL, the first clock signal line CKL, the second clock signal line CBL, the first power line VGLL, or the second power line VGHL. Fig. 8A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Figure 8B It is shown Fig. 8A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG. Figure 8C To show Fig. 8A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in . Fig.8D It is shown Fig. 8ASchematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in . Fig. 8E It is shown Fig. 8A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in . Figure 8F To show Fig. 8A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in . Figure 8G To show Fig. 8A Schematic diagram of the structure of the second signal line layer in the corresponding scanning unit shown in FIG. FIG. 8A to FIG. 8G In some embodiments, the array substrate further includes a second signal line layer located on a side of the first signal line layer away from the base substrate.

[0155] refer to Fig. 8A and Figure 8B In some embodiments, the light shielding layer LSL includes a first capacitor electrode Ce1 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2.

[0156] refer to Fig. 8A and Figure 8C In some embodiments, the first conductive layer Gate1 includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a first portion of each gate of each transistor.

[0157] Reference Fig. 8A and Fig.8D In some embodiments, the semiconductor material layer SML includes an active layer of a transistor in each scanning unit.

[0158] See also Fig. 8A and Fig. 8E In some embodiments, the second conductive layer Gate2 includes a second portion of each gate of each transistor, a first output signal line OUT1 configured to transmit the output signal from each scanning unit to the fourth terminal TM4, and a second output signal line OUT2 configured to transmit the output signal from each scanning unit to the first terminal in the scanning unit in the next level.

[0159] refer to Fig. 8A and Figure 8F In some embodiments, the first signal line layer SD1 includes a start signal line STVL, a first clock signal line CKL, a second clock signal line CBL, a first power line VGLL, a second power line VGHL, and a third output signal line OUT3 connected to the second electrodes of the ninth transistor and the tenth transistor.

[0160] refer to Fig. 8A and Figure 8GIn some embodiments, the second signal line layer SD2 includes a third power line VGLL2. The third power line VGLL2 is connected to the overall structure of the first portion of the first conductive layer including each gate of the transistor in each scanning unit.

[0161] Various alternative embodiments may be practiced in accordance with the present disclosure. Fig. 9A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Fig. 9B It is shown Fig. 9A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG. Fig. 9C To show Fig. 9A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in . Fig.9D To show Fig. 9A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in . Fig.9E It is shown Fig. 9A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in . Fig.9F To show Fig. 9A Schematic diagram of the structure of the third conductive layer in the corresponding scanning unit shown in . Figure 9G To show Fig. 9A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0162] Reference Fig. 9A and Fig. 9B In some embodiments, the light shielding layer LSL does not include any capacitor electrodes of the first capacitor or the second capacitor.

[0163] refer to Fig. 9A and Fig. 9C In some embodiments, the first conductive layer Gate1 includes a first capacitor electrode Ce1 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2.

[0164] refer to Fig. 9A and Fig.9D In some embodiments, the second conductive layer Gate2 includes a second capacitor electrode Ce2 of the first capacitor C1, a fourth capacitor electrode Ce4 of the second capacitor C2, and a first portion of each gate of each transistor.

[0165] Reference Fig. 9A and Fig.9E In some embodiments, the semiconductor material layer SML includes an active layer of a transistor in each scanning unit.

[0166] See also Fig. 9A and Fig.9FIn some embodiments, the third conductive layer Gate3 includes a second portion of each gate of each transistor, a first output signal line OUT1 configured to transmit the output signal from each scanning unit to the fourth end TM4, and a second output signal line OUT2 configured to transmit the output signal from each scanning unit to the first end of the scanning unit in the next level.

[0167] refer to Fig. 9A and Figure 9G In some embodiments, the first signal line layer SD1 includes a start signal line STVL, a first clock signal line CKL, a second clock signal line CBL, a first power line VGLL, a second power line VGHL, a third power line VGLL2, and a third output signal line OUT3 connected to the second electrodes of the ninth transistor and the tenth transistor. The third output signal line OUT3 is also connected to the first output signal line OUT1 and to the second output signal line OUT2.

[0168] Fig.10 is a schematic diagram showing the layout of multiple scanning circuits in an array substrate according to some embodiments of the present disclosure. Fig.10 In some embodiments, the array substrate includes a plurality of scanning circuits, for example, a first scanning circuit SC1, a second scanning circuit SC2, a third scanning circuit SC3, and a fourth scanning circuit SC4. Examples of scanning circuits include a light emitting control signal generating circuit configured to generate a light emitting control signal for a sub-pixel in the array substrate, a reset control signal generating circuit configured to generate a reset control signal for a sub-pixel in the array substrate, and a gate scanning signal generating circuit configured to generate a gate scanning signal for a sub-pixel in the array substrate. In some embodiments, each of the plurality of scanning circuits includes a multi-stage cascade scanning unit. Optionally, the multi-stage cascade scanning unit is configured to provide a plurality of control signals (e.g., gate scanning signals, reset control signals, or light emitting control signals) to a plurality of rows of sub-pixels.

[0169] Fig.11 Schematic diagram showing the overall structure of the first part of each gate of transistors in a plurality of scanning circuits in an array substrate according to some embodiments of the present disclosure. Fig.11 In some embodiments, the array substrate includes a plurality of scanning circuits RSC. In some embodiments, the first portion of each gate of transistors of a plurality of scanning units in the same level (eg, the same row) of the plurality of scanning circuits RSC is part of the integral structure.

[0170] Fig.12Schematic diagram showing the connection between the third power line in the array substrate and the overall structure of the first part including each gate of the transistors in the plurality of scanning circuits according to some embodiments of the present disclosure. Fig.11 and Fig.12 In some embodiments, the overall structure including the first part of each gate of the transistors of the plurality of scanning units in the same level (e.g., the same row) of the plurality of scanning circuits RSC is connected to the third power line VGLL2 located in the peripheral area of ​​the array substrate. Optionally, the plurality of overall structures are commonly connected to a single third power line located in the peripheral area of ​​the array substrate; wherein each of the plurality of overall structures includes the first part of each gate of the transistors of the plurality of scanning units in the same corresponding level (e.g., the same corresponding row) of the plurality of scanning circuits RSC.

[0171] Various alternative embodiments may be practiced in accordance with the present disclosure. Fig.13A is a schematic diagram showing the structure of a corresponding scanning unit of a scanning circuit in some embodiments of the present disclosure. Fig. 13B It is shown Fig.13A Schematic diagram of the structure of the light shielding layer in the corresponding scanning unit shown in FIG. Fig. 13C To show Fig.13A Schematic diagram of the structure of the first conductive layer in the corresponding scanning unit shown in . Fig.13D To show Fig.13A Schematic diagram of the structure of the semiconductor material layer in the corresponding scanning unit shown in . Fig.13E It is shown Fig.13A Schematic diagram of the structure of the second conductive layer in the corresponding scanning unit shown in . Fig.13F To show Fig.13A Schematic diagram of the structure of the first signal line layer in the corresponding scanning unit shown in .

[0172] refer to Fig.13A and Fig. 13B In some embodiments, the light shielding layer LSL includes a first capacitor electrode Ce1 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2.

[0173] refer to Fig.13A and Fig. 13CIn some embodiments, the first conductive layer Gate1 includes the second capacitor electrode Ce2 of the first capacitor C1, the fourth capacitor electrode Ce4 of the second capacitor C2, and the first portion of each gate of each transistor. In one example, the first conductive layer Gate1 includes the second capacitor electrode Ce2 of the first capacitor C1, the fourth capacitor electrode Ce4 of the second capacitor C2, the first portion G1-1 of the gate of the first transistor, the first portion G2-1 of the gate of the second transistor, the first portion G3-1 of the gate of the third transistor, the first portion G4-1 of the gate of the fourth transistor, the first portion G5-1 of the gate of the fifth transistor, the first portion G6-1 of the gate of the sixth transistor, the first portion G7-1 of the gate of the seventh transistor, the first portion G8-1 of the gate of the eighth transistor, the first portion G9-1 of the gate of the ninth transistor, and the first portion G10-1 of the gate of the tenth transistor.

[0174] In some embodiments, the first portion of each gate of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in each scanning unit is part of the overall structure. For example, the first portion G2-1 of the gate of the second transistor, the first portion G4-1 of the gate of the fourth transistor, the first portion G5-1 of the gate of the fifth transistor, the first portion G6-1 of the gate of the sixth transistor, the first portion G7-1 of the gate of the seventh transistor, the first portion G8-1 of the gate of the eighth transistor, the first portion G9-1 of the gate of the ninth transistor, and the first portion G10-1 of the gate of the tenth transistor are interconnected and are part of the overall structure.

[0175] In some embodiments, the first portion G1 - 1 of the gate of the first transistor T1 is spaced apart from the overall structure.

[0176] In some embodiments, the first portion G3 - 1 of the gate of the third transistor T3 is spaced apart from the overall structure.

[0177] In some embodiments, the overall structure also includes a first connecting line CL1 (as part of the overall structure), which connects the first part of each gate of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 to the third power line.

[0178] In some embodiments, each scanning unit further includes a second connection line CL2 connecting the first portion G1-1 of the gate of the first transistor T1 and the fourth power line. Optionally, the second connection line CL2 and the first portion G1-1 of the gate of the first transistor T1 are part of another integral structure.

[0179] In some embodiments, each scanning unit further includes a third connection line CL3 connecting the first portion G3-1 of the gate of the third transistor T3 and the fifth power line. Optionally, the second connection line CL2 and the first portion G3-1 of the gate of the third transistor T3 are part of another integral structure.

[0180] Reference Fig.13A and Fig.13D In some embodiments, the semiconductor material layer SML includes an active layer of a transistor in each scanning unit. Fig.13E Marked with a mark, the mark represents the active layer of the transistor in each scanning unit, for example, the active layer ACT1 of the first transistor, the active layer ACT2 of the second transistor, the active layer ACT3 of the third transistor, the active layer ACT4 of the fourth transistor, the active layer ACT5 of the fifth transistor, the active layer ACT6 of the sixth transistor, the active layer ACT7 of the seventh transistor, the active layer ACT8 of the eighth transistor, the active layer ACT9 of the ninth transistor, and the active layer ACT10 of the tenth transistor. Various suitable semiconductor materials can be used to manufacture the semiconductor material layer SML. Examples of semiconductor materials used to manufacture the semiconductor material layer SML include: metal oxide-based semiconductor materials (such as indium gallium zinc oxide) and metal nitride oxide-based semiconductor materials (such as zinc oxynitride).

[0181] refer to Fig.13A and Fig.13E In some embodiments, the second conductive layer Gate2 includes the second portion of each gate of each transistor. In one example, the second conductive layer Gate2 includes the second portion G1-2 of the gate of the first transistor, the second portion G2-2 of the gate of the second transistor, the second portion G3-2 of the gate of the third transistor, the second portion G4-2 of the gate of the fourth transistor, the second portion G5-2 of the gate of the fifth transistor, the second portion G6-2 of the gate of the sixth transistor, the second portion G7-2 of the gate of the seventh transistor, the second portion G8-2 of the gate of the eighth transistor, the second portion G9-2 of the gate of the ninth transistor, and the second portion G10-2 of the gate of the tenth transistor. In some embodiments, the second conductive layer Gate2 also includes a first output signal line OUT1, which is configured to transmit an output signal from each scanning unit to the fourth terminal TM4; and a second output signal line OUT2, which is configured to transmit an output signal from each scanning unit to the first terminal in the next level scanning unit.

[0182] refer to Fig.13A and Fig.13F In some embodiments, the first signal line layer SD1 includes a start signal line STVL, a first clock signal line CKL, a second clock signal line CBL, a first power line VGLL, a second power line VGHL, a third power line VGLL2, a fourth power line VGLL3 and a fifth power line VGLL4. Fig.13F Marked with a mark, the mark represents the first electrode and the second electrode of the transistor in each scanning unit. For example, the first transistor includes a first electrode S1 and a second electrode D1, the second transistor includes a first electrode S2 and a second electrode D2, the third transistor includes a first electrode S3 and a second electrode D3, the fourth transistor includes a first electrode S4 and a second electrode D4, the fifth transistor includes a first electrode S5 and a second electrode D5, the sixth transistor includes a first electrode S6 and a second electrode D6, the seventh transistor includes a first electrode S7 and a second electrode D7, the eighth transistor includes a first electrode S8 and a second electrode D8, the ninth transistor includes a first electrode S9 and a second electrode D9, and the tenth transistor includes a first electrode S10 and a second electrode D10. In some embodiments, the first signal line layer SD1 also includes a third output signal line OUT3 connected to the second electrodes of the ninth transistor and the tenth transistor. The third output signal line OUT3 is also connected to the first output signal line OUT1 and to the second output signal line OUT2.

[0183] Reference Fig.13A , Fig. 13C and Fig.13F , the third power line VGLL2 is connected to the first connection line CL1. The third power line VGLL2 is configured to provide a third power signal to a first portion of each gate of the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 through the first connection line CL1.

[0184] In some embodiments, the fourth power line VGLL3 is connected to the second connection line CL2 . The fourth power line VGLL3 is configured to provide a fourth power signal to the first portion G1 - 1 of the gate of the first transistor T1 through the fourth power line VGLL3 .

[0185] In some embodiments, the fifth power line VGLL4 is connected to the third connection line CL3. The fifth power line VGLL4 is configured to provide a fifth power signal to the first portion G3-1 of the gate of the third transistor T3 through the fifth power line VGLL4.

[0186] In some embodiments, the first power line VGLL is configured to provide a first power signal, the second power line VGHL is configured to provide a second power signal, the third power line VGLL2 is configured to provide a third power signal, the fourth power line VGLL3 is configured to provide a fourth power signal, and the fifth power line VGLL4 is configured to provide a fifth power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the first power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the third power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the fourth power signal. Optionally, the voltage level of the second power signal is higher than the voltage level of the fifth power signal. Optionally, the voltage level of the third power signal is higher than the voltage level of the first power signal. Optionally, the voltage level of the fourth power signal is higher than the voltage level of the first power signal. Optionally, the voltage level of the fifth power signal is higher than the voltage level of the first power signal.

[0187] Fig.14 1 is a schematic diagram showing the overall structure of the first part of some gates of some transistors in a plurality of scanning circuits in an array substrate according to some embodiments of the present disclosure. Fig.14 In some embodiments, the array substrate includes a plurality of scanning circuits RSC. In some embodiments, a first portion of a gate of a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor of a plurality of scanning units in the same level (e.g., in the same row) respectively from the plurality of scanning circuits RSC is a part of the integral structure.

[0188] Fig.15 Schematic diagram showing the connection between the third power line in the array substrate and the overall structure of the first part including some gates of some transistors in a plurality of scanning circuits according to some embodiments of the present disclosure. Fig.14 and Fig.15In some embodiments, the overall structure including the first part of the gates of the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor of the plurality of scanning units in the same level (for example, the same row) of the plurality of scanning circuits RSC is connected to the third power line VGLL2 located in the peripheral area of ​​the array substrate. Optionally, the plurality of overall structures are commonly connected to a single third power line located in the peripheral area of ​​the array substrate; wherein each of the plurality of overall structures includes the first part of the gates of the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the tenth transistor of the plurality of scanning units in the same level (for example, the same row) of the plurality of scanning circuits RSC.

[0189] In another aspect, the present invention provides a display device, comprising a scanning circuit described herein or manufactured by a method described herein, and a display panel having a plurality of light-emitting elements. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a mini light-emitting diode display device. Optionally, the display device is a quantum dot display device.

[0190] Fig.16 Schematic diagram showing a display area and a peripheral area in a display panel according to some embodiments of the present disclosure. Fig.16 , in some embodiments, the display device includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the display panel that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in a liquid crystal display or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in a liquid crystal display or the area corresponding to the pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels.

[0191] In some embodiments, the scanning circuit is located in the peripheral area. As used herein, the term "peripheral area" refers to an area of ​​the display panel in which various circuits (e.g., scanning circuits) and wires are provided to transmit signals to the display panel. In order to increase the transparency of the display panel, opaque or non-transparent components of the display panel (e.g., batteries, printed circuit boards, metal frames) can be arranged in the peripheral area instead of in the display area.

[0192] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described in order to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A scanning circuit comprising a plurality of scanning units; in, Each of the plurality of scanning units comprises a plurality of transistors; Each gate of each transistor of the plurality of transistors includes a first portion and a second portion located at different layers; A first portion of each gate of each of the plurality of transistors in each of the scanning units is configured to be provided with a power supply signal; The second portions of the respective gates of the plurality of transistors in the respective scanning units are configured to be respectively provided with gate scanning signals; and The first portion of the gates of at least two transistors in each scanning unit is part of the integral structure.

2. The scanning circuit according to claim 1, wherein: The first portions of the gates of the at least two transistors in the respective scanning units are connected to the same power signal line.

3. The scanning circuit according to claim 1, wherein: A first portion of the gates of the plurality of transistors in each of the scanning units is part of an integral structure.

4. The scanning circuit according to claim 1, wherein: First portions of the gates of the plurality of transistors in the respective scanning units are connected to the same power signal line.

5. The scanning circuit according to claim 1, wherein: The first portions of the gates of the plurality of transistors are located at a same layer as at least one capacitor electrode of the one or more capacitors in each of the scanning units.

6. The scanning circuit according to any one of claims 1 to 5, wherein: The plurality of transistors are a plurality of n-type transistors.

7. The scanning circuit according to any one of claims 1 to 6, wherein: The active layers of the plurality of transistors in each scanning unit are located in a layer, and the layer is located on a side of the first part away from the substrate; as well as The second portion is located in a layer located on a side of the active layer away from the first portion.

8. The scanning circuit according to claim 7, wherein: One or more power lines are located on a side of the second portion away from the substrate, and the one or more power lines are configured to provide one or more power signals to the first portion.

9. The scanning circuit according to any one of claims 1 to 8, further comprising a plurality of power supply lines; in, A first power line among the plurality of power lines is configured to provide a power signal to a first portion of a gate of at least one transistor in each of the scanning units; as well as A second power line among the plurality of power lines is configured to provide a power signal to a first portion of gates of a group of transistors in each of the scanning units.

10. The scanning circuit according to claim 9, wherein: A first portion of the gates of the group of transistors in each scanning unit is part of an integral structure.

11. The scanning circuit according to any one of claims 1 to 8, further comprising a third power line, a fourth power line and a fifth power line; in, The fourth power line is connected to a first portion of a gate of a first transistor in each scanning unit and is configured to provide a power signal to the first portion of the gate of the first transistor in each scanning unit; The fifth power line is connected to a first portion of a gate of the third transistor in each of the scanning units and is configured to provide a power signal to the first portion of the gate of the third transistor in each of the scanning units; as well as The third power line is connected to an overall structure including a first portion of a gate of a transistor other than the first transistor and the third transistor in each scanning unit and is configured to provide a power signal to the overall structure.

12. An array substrate comprising a plurality of scanning circuits; in, The plurality of scanning circuits include the scanning circuit according to claim 1 .

13. The array substrate according to claim 12, wherein: The overall structure includes first portions of gates of at least two transistors in each of a plurality of scan units in a same level, respectively, from the plurality of scan circuits.

14. The array substrate according to claim 13, wherein: The first portions of the gates of the at least two transistors in each of a plurality of scanning units in the same stage, respectively from the plurality of scanning circuits, are connected to the same power signal line.

15. The array substrate according to claim 12, wherein: The overall structure includes first portions of respective gates of all transistors of a plurality of scan units in a same stage, respectively, from the plurality of scan circuits.

16. The array substrate according to claim 12, wherein: First portions of respective gates of all transistors of a plurality of scanning units in a same stage, respectively from the plurality of scanning circuits, are connected to a same power supply signal line.

17. The array substrate according to claim 12, further comprising a third power line, a plurality of fourth power lines and a plurality of fifth power lines; in, Each of the plurality of fourth power lines is connected to a first portion of a gate of a first transistor in a corresponding scan circuit of the plurality of scan circuits and is configured to provide a power signal to the first portion of the gate of the first transistor; each of the plurality of fifth power lines is connected to a first portion of a gate of a third transistor in the corresponding scan circuit of the plurality of scan circuits and is configured to provide a power signal to the first portion; as well as The third power line is connected to an overall structure and is configured to provide a power signal to the overall structure, wherein the overall structure includes a first portion of a gate of a transistor other than the first transistor and the third transistor in each of a plurality of scanning units in the same level respectively from the plurality of scanning circuits.

18. The array substrate according to claim 12, further comprising a plurality of integral structures, wherein the plurality of integral structures are commonly connected to a single third power line located in a peripheral area of ​​the array substrate; in, Each of the plurality of integral structures includes a first portion of each of the gates of transistors of a plurality of scan units in the same corresponding stage, respectively, from the plurality of scan circuits.

19. The array substrate according to claim 12, further comprising a plurality of integral structures, wherein the plurality of integral structures are commonly connected to a single third power line located in a peripheral area of ​​the array substrate; in, Each of the multiple integral structures includes a first portion of the gates of a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor respectively from multiple scanning units in the same level of the multiple scanning circuits.

20. A display device comprising the scanning circuit according to any one of claims 1 to 11.

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