Display, photoelectric conversion device, and electronic apparatus

Abstract

To prevent a reduction in display quality in a display that writes signals in a plurality of pixels.SOLUTION: A display has: a display area including a plurality of pixels arranged in a matrix, the pixels each including a writing control transistor, a light emission control transistor, and a driving transistor driving a light emitting device; first selection lines connected to the writing control transistors in the pixels arranged in a row direction; second selection lines connected to the light emission control transistors in the pixels arranged in the row direction; a first scan circuit that sequentially scans the plurality of first selection lines; and a second scan circuit that scans the plurality of second selection lines. Image data is divided into a plurality of regions different in resolution, and the plurality of regions are arranged so that at least two or more regions are included in a column direction. The speed of scanning performed by the first scan circuit is different in each of the regions arranged in the column direction. The speed of scanning performed by the second scan circuit is equal to or more than the minimum speed and less than the maximum speed of scanning performed by the first scan circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device, a photoelectric conversion device, and an electronic device. [Background technology]

[0002] As display devices become more pixel-rich and have higher frame rates, the amount of image data increases. Therefore, a technique is known in which the central part of a display area, where the user's gaze is likely to be directed, is displayed at high resolution, and the other areas, where the user's gaze is less likely to be directed, are displayed at low resolution. Patent Document 1 discloses a technique in which the other areas are displayed at low resolution by writing the same signal to multiple pixels in the display area. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-107582 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the above technology, in a display device in which the same signal is written to multiple pixels, the light-emitting area of ​​the display region may become uneven over time, which may cause the amount of current flowing through the light-emitting element to become uneven over time, resulting in a deterioration in display quality.

[0005] The present invention has been made in view of the above, and has an object to suppress degradation of display quality in a display device in which signals are written to a plurality of pixels. [Means for solving the problem]

[0006] One aspect of the present invention is a display device comprising: a display area including a plurality of pixels arranged in a matrix, each pixel including a light-emitting element, a write control transistor that writes a signal voltage to the light-emitting element, an emission control transistor that causes the light-emitting element to emit light, and a drive transistor that drives the light-emitting element; a first selection line provided for each row of the plurality of pixels and connected to the write control transistor of the pixels arranged in the row direction; a second selection line provided for each row of the plurality of pixels and connected to the emission control transistor of the pixels arranged in the row direction; a first scanning circuit that scans the plurality of first selection lines in sequence; and a second scanning circuit that scans the plurality of second selection lines in sequence; the display area displays image data, the image data being divided into a plurality of regions with different resolutions, and the plurality of regions are arranged so that there are at least two of them in the column direction; the scanning speed by the first scanning circuit differs for each region arranged in the column direction; and the scanning speed by the second scanning circuit is greater than or equal to the minimum speed and less than the maximum speed of the scanning speed by the first scanning circuit. [Effects of the Invention]

[0007] According to the present invention, by making the light-emitting area of ​​the display region uniform over time, it is possible to suppress the imbalance over time in the amount of current flowing through the light-emitting element, and to suppress the deterioration of display quality. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to a first embodiment; [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a pixel driving circuit according to the first embodiment; [Figure 3A] FIG. 1 is a diagram schematically illustrating writing and light emission control in a display device according to a conventional technique. [Figure 3B] FIG. 1 is a diagram schematically illustrating writing and light emission control in a display device according to a conventional technique. [Figure 3C] FIG. 1 is a diagram schematically illustrating writing and light emission control of the display device according to the first embodiment. [Figure 3D]FIG. 10 is a diagram schematically illustrating writing and light emission control of a display device according to a modified example. [Figure 3E] FIG. 1 is a diagram schematically illustrating writing and light emission control in a display device according to a conventional technique. [Figure 3F] FIG. 1 is a diagram schematically illustrating writing and light emission control of the display device according to the first embodiment. [Figure 3G] FIG. 10 is a diagram schematically illustrating writing and light emission control of a display device according to a modified example. [Figure 4] FIG. 1 is a diagram showing an example of the configuration of a vertical scanning circuit according to the first embodiment; [Figure 5] 1 is an operation timing diagram of a vertical scanning circuit according to the first embodiment; [Figure 6] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 7] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 8] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 9] FIG. 1 is a diagram schematically illustrating the relationship between an image signal and a display image in the first embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a vertical scanning circuit according to a modified example; [Figure 11] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 12] FIG. 10 is a diagram showing an example of the configuration of a vertical scanning circuit according to a modified example; [Figure 13] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 14] FIG. 10 is a diagram showing an example of the configuration of a vertical scanning circuit according to a modified example; [Figure 15] FIG. 10 is a diagram showing an example of the configuration of a display device according to a second embodiment. [Figure 16] FIG. 10 is a diagram showing an example of the configuration of a vertical scanning circuit according to a second embodiment. [Figure 17] 10 is an operation timing diagram of a vertical scanning circuit according to the second embodiment. [Figure 18] FIG. 10 is a diagram showing an example of the configuration of a vertical scanning circuit according to a modified example; [Figure 19] FIG. 10 is a diagram showing an example of the configuration of a pixel drive circuit according to a modified example; [Figure 20] FIG. 10 is a diagram showing an example of the configuration of a pixel drive circuit according to a modified example; [Figure 21] 1 is an operation timing diagram of a vertical scanning circuit according to a modified example. [Figure 22] FIG. 10 is a diagram schematically illustrating the relationship between an image signal and a display image in the second embodiment. [Figure 23] FIG. 1 is a cross-sectional view illustrating an example of a portion of a display device according to an embodiment. [Figure 24] 1 is a cross-sectional view illustrating an example of a display device according to an embodiment; [Figure 25] Schematic diagram showing an example of a display component according to a third embodiment. [Figure 26] FIG. 1 is a schematic diagram illustrating an example of an imaging device according to a fourth embodiment and a fifth embodiment. [Figure 27] 10 is a schematic diagram showing an example of an image display device according to a sixth embodiment. [Figure 28] 13 is a schematic diagram showing an application example of the display device according to the seventh embodiment. [Figure 29] 13 is a schematic diagram showing an application example of the display device according to the eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Embodiment 1) A display device according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram illustrating an example of the configuration of a display device 1 according to this embodiment. The display device 1 includes a pixel array 100, a vertical scanning circuit 200, a signal output circuit 300, and a control circuit 400. The pixel array 100 is a display area including a plurality of pixels arranged in a matrix, and includes a plurality of unit pixel drive circuits 101 arranged two-dimensionally across a plurality of rows and columns. Each unit pixel drive circuit 101 includes a light-emitting element, such as an organic EL element, and transistors for controlling the writing of image signals and light emission. In this embodiment, it is assumed that the unit pixel drive circuit 101 corresponds to a pixel. However, to realize the operation of the display device 1 described below, the pixel may include components other than the unit pixel drive circuit 101 as appropriate. Furthermore, in FIG. 1, other unit pixel drive circuits having the same shape as the unit pixel drive circuit 101 are also configured similarly to the unit pixel drive circuit 101. As such, in the display device 1 according to the first embodiment, the sizes of the plurality of pixel drive circuits in the display area are uniform.

[0010] The unit pixel driving circuit 101 is connected to the vertical scanning circuit 200 via a write selection line 102 and an emission selection line 104 that are provided in common for each row. Furthermore, the unit pixel driving circuit 101 is connected to the signal output circuit 300 via an image signal line 103 that is provided in common for each column. The signal output circuit 300 is controlled by the control circuit 400 and outputs individual image signals to the unit pixel drive circuit 101 for each column.

[0011] On the other hand, the vertical scanning circuit 200 is controlled by the control circuit 400, and selects a row (hereinafter referred to as a write row) in the pixel array 100 to which a signal voltage related to an image signal is written, using write control signals WR(1) to WR(N) output via the write selection lines 102. Then, the vertical scanning circuit 200 selects a row in which the light emitting element is to emit light at a luminance corresponding to the written signal voltage, using light emission control signals EM(1) to EM(N) output via the light emission selection lines 104. Here, N is an integer.

[0012] 2 shows an example of the configuration of a unit pixel drive circuit 101 according to this embodiment. The unit pixel drive circuit 101 includes an emission control transistor 111, a write control transistor 112, a drive transistor 113, and an light emitting diode 114. The cathode terminal of the light emitting diode 114 is connected to VSS, which is the ground level, and the anode terminal of the light emitting diode 114 is connected to the source terminal of the drive transistor 113. The drain terminal of the drive transistor 113 is connected to the source terminal of the emission control transistor 111, and the gate terminal of the drive transistor 113 is connected to the source terminal of the write control transistor 112. The drain terminal of the emission control transistor 111 is connected to VDD, which is a power supply, and the gate terminal of the emission control transistor 111 is connected to an emission selection line 104. The drain terminal of the write control transistor 112 is connected to an image signal line 103, and the gate terminal of the write control transistor 112 is connected to the write selection line 102. In this embodiment, the write selection line 102 is a first selection line provided for each row of the plurality of unit pixel drive circuits 101 and connected to the write control transistors of the unit pixel drive circuits 101 arranged in the row direction. The emission selection line 104 is a second selection line provided for each row of the plurality of unit pixel drive circuits 101 and connected to the emission control transistors of the unit pixel drive circuits 101 arranged in the row direction.

[0013] Next, an example of the operation of the unit pixel drive circuit 101 will be described. When the write selection line 102 becomes an ON level (hereinafter referred to as an "H level"), the write control transistor 112 is turned ON. Then, a signal voltage related to the image signal supplied from the image signal line 103 is written to Node_A, to which the gate terminal of the drive transistor 113 is connected. Next, when the write selection line 102 becomes an OFF level (hereinafter referred to as an "L level"), the write control transistor 112 is turned OFF, and the signal voltage is held in the parasitic capacitance of Node_A. In this embodiment, the parasitic capacitance of Node_A may be, for example, an inter-wiring capacitance, a parasitic capacitance between the gate terminal and source terminal of the drive transistor 113, or a parasitic capacitance between the gate terminal and drain terminal. Thereafter, when the emission selection line 104 becomes an H level, the emission control transistor 111 is turned ON. Then, a current corresponding to the signal voltage held at Node_A, to which the gate terminal of the drive transistor 113 is connected, is supplied to the light-emitting diode 114, causing the light-emitting diode 114 to emit light.

[0014] Here, the control of signal voltage writing and light emission in a conventional display device that writes the same image signal to multiple pixels in a display area will be described with reference to Figures 3A and 3B. It is assumed that the layout of the write selection lines, light emission selection lines, and vertical scanning circuit in the conventional display device is the same as that of display device 1 described above. In the following description, it is assumed that the display area of ​​the display device displays image data, that the image data is divided into multiple regions with different resolutions, and that the multiple regions are arranged so that at least two or more are included in the column direction. It is assumed that the scanning speed by the write scanning circuit and the scanning speed by the light emission scanning circuit are each given by "(total spacing of selection lines in a region) / (time required to scan a region)".

[0015] Conventional display devices perform light-emission duty control, in which a certain light-emitting element emits light for only a limited period during one frame period. FIG. 3A is a graph showing the relationship between the write time, light-emission time, and light-emission amount in a pixel array, according to a method for controlling the writing of signal voltages and light emission in a display device disclosed in Patent Document 1. As shown in FIG. 3A, this control method writes signal voltages to all pixel drive circuits in the high-resolution and low-resolution regions that make up the display area, and then causes all pixels to emit light simultaneously (full-area light emission). In FIG. 3A, within the period T1 of one frame, periods T11 and T13 are periods for writing signal voltages to the pixel drive circuits in the low-resolution region, and period T12 is a period for writing signal voltages to the pixel drive circuits in the high-resolution region. With this control method, light emission in the display area is uneven over time within the period T1 of one frame, which also causes the amount of current flowing through the light-emitting elements to be uneven over time, resulting in a deterioration in display quality.

[0016] FIG. 3B is a graph showing the relationship between the write time, the light emission time, and the amount of light emitted in the pixel array using another control method for writing signal voltages and emitting light in a conventional display device. As shown in FIG. 3B, a control method in which light is emitted for a fixed period of time immediately after writing in each pixel drive circuit is also possible. In FIG. 3B, within the period T2 of one frame, periods T21 and T23 are periods during which signal voltages are written to the pixel drive circuit for the low-resolution region, and period T22 is a period during which signal voltages are written to the pixel drive circuit for the high-resolution region. Compared to the control method of FIG. 3A, this control method can suppress temporal imbalances in the amount of current flowing through the light-emitting elements during period T2 of one frame. However, this control method may cause flickering of the displayed image due to differences in the light emission scanning speed between periods T21 and T23 and period T22.

[0017] FIG. 3E is a graph showing the relationship between the write time, the light emission time, and the amount of light emitted in the pixel array when a different control method for signal voltage writing and light emission is used in a conventional display device. In FIG. 3E, within the period T5 of one frame, periods T51 and T55 are periods during which signal voltages are written to the pixel drive circuits in the low-resolution region. Periods T52 and T54 are periods during which signal voltages are written to the pixel drive circuits in the medium-resolution region. Period T53 is a period during which signal voltages are written to the pixel drive circuits in the high-resolution region. In FIG. 3E, the number of pixel drive circuits simultaneously writing signal voltages in the low-resolution region is greater than the number of pixel drive circuits simultaneously writing signal voltages in the low-resolution region in FIGS. 3A and 3B. If the conventional control method is used when the number of pixel drive circuits simultaneously writing signal voltages is increased, the difference in light emission scanning speed between the periods in each resolution region may result in flickering of the displayed image. Furthermore, the amount of light emitted in the low-resolution region is greater than the amount of light emitted in FIG. 3B, resulting in a greater temporal imbalance in the current flowing through the light-emitting element than in FIG. 3B.

[0018] Next, a method for controlling the writing of signal voltages and light emission in the display device 1 according to this embodiment will be described. FIG. 3C is a graph showing the relationship between the writing time, light emission time, and the amount of light emitted in the pixel array according to an example method for controlling the writing of signal voltages and light emission in the display device 1. In FIG. 3C, the scanning speed for writing signal voltages to each pixel drive circuit differs between the low-resolution region and the high-resolution region, as in FIGS. 3A and 3B. Within the frame period T3, periods T31 and T33 are periods for writing signal voltages to the pixel drive circuit for the low-resolution region, and period T32 is a period for writing signal voltages to the pixel drive circuit for the high-resolution region. However, in the display device 1, the scanning speed of the vertical scanning circuit 200 for emitting light from light-emitting elements is constant throughout the frame period T3. This control can reduce temporal bias in the amount of current flowing through the light-emitting elements compared to the case of FIG. 3A. Furthermore, this control can prevent flickering of the display image caused by changes in the light-emission scanning speed compared to the case of FIG. 3B.

[0019] Next, the configuration of the display device 1 for realizing the control method shown in Fig. 3C will be described with reference to Fig. 4 and Fig. 5. Fig. 4 is a diagram showing an example of the configuration of the vertical scanning circuit 200 of the display device 1, and Fig. 5 is a diagram showing an example of the operation timing of the driving waveform of the vertical scanning circuit 200.

[0020] FIG. 4 shows a vertical scanning circuit 200, a signal output circuit 300, and some unit pixel driving circuits 101 in the pixel array 100. The number N in FIG. 1, which represents the number of write selection lines 102 and emission selection lines 104 in FIG. 1, can take any integer value. For example, in the case of the Full HD standard, N=1080. For simplicity's sake, FIG. 4 shows the circuitry within the display device 1 when N=12 as in FIG. 1. As shown in FIG. 4, the vertical scanning circuit 200 is composed of a write scanning circuit 201 and an emission scanning circuit 202. The write scanning circuit 201 and the emission scanning circuit 202 are shift register circuits in which D-flip-flop circuits are cascaded in the column direction of the pixel array 100. Furthermore, in the figure, the unit pixel driving circuits 101 connected to the write selection lines transmitting WR(1) to WR(4) and WR(9) to WR(12) and the emission selection lines transmitting EM(1) to EM(4) and EM(9) to EM(12) belong to the low-resolution region. In addition, the unit pixel drive circuit 101 connected to the write selection lines that transmit WR(5) to WR(8) and the light emission selection lines that transmit EM(5) to EM(8) in the figure belongs to the high resolution region. A write start pulse WR_S and a write clock WR_CLK are supplied to the write scanning circuit 201, and a light emission start pulse EM_S and a write clock EM_CLK are supplied to the light emission scanning circuit 202.

[0021] As shown in FIG. 5, at time t0, V_SYNC goes high, starting one frame. Here, in the low-resolution region, the write scanning circuit 201 writes signal voltages to two unit pixel drive circuits 101 connected to the same image signal line 103. For example, when WR_CLK goes high at time t1, the first-stage D-Flip Flop circuit 201a of the write scanning circuit 201 captures the high level of its input WR_S. Then, the D-Flip Flop circuit 201a outputs high levels to the write selection line for transmitting WR(1) and the write selection line for transmitting WR(2). As a result, the signal voltages related to the image signal A output from the signal output circuit 300 to the image signal line 103 at time t1 are written to the unit pixel drive circuits 101 arranged in two rows.

[0022] Furthermore, in the high-resolution region, the write scanning circuit 201 writes signal voltages to the unit pixel driving circuits 101 row by row. For example, when WR_CLK goes high at time t3, the third-stage D-Flip Flop circuit 201b of the write scanning circuit 201 captures the high levels of the input write selection line for transmitting WR(3) and the write selection line for transmitting WR(4). The D-Flip Flop circuit 201b then outputs a high level to the write selection line for transmitting WR(5). As a result, the signal voltage related to the image signal C output from the signal output circuit 300 to the image signal line 103 at time t3 is written to the unit pixel driving circuit 101 connected to the write selection line for transmitting WR(5). In this way, the write scanning circuit 201 sequentially scans the multiple write selection lines, thereby sequentially writing signal voltages related to the image signal to the unit pixel driving circuits 101 in the low-resolution region and the high-resolution region.

[0023] 9 shows an example of the relationship between the image signal output from the signal output circuit 300 and the display image displayed on the pixel array 100 when the display device 1 writes a signal voltage. When the display device 1 writes a signal voltage, the image signal output from the signal output circuit 300 has a reduced amount of image data in the low-resolution region in the row direction in order to display the display image shown in FIG. 9. As a result, the display device 1 sends the image signal transmitted from the outside directly from the signal output circuit 300 to the pixel array 100 without performing expansion processing on the image signal in the control circuit 400 and the signal output circuit 300, thereby reducing the amount of image data related to image display. This can reduce the latency.

[0024] 5, when EM_CLK goes high at time t2, for example, the first-stage D-Flip Flop circuit 202a of the light-emitting scanning circuit 202 takes in the high level of EM_S, which is its input. The D-Flip Flop circuit 202a then outputs the high level to the light-emitting selection line for EM(1) transmission. When EM_CLK goes high again at time t4, the second-stage D-Flip Flop circuit 202b of the light-emitting scanning circuit 202 takes in the high level of the light-emitting selection line for EM(1) transmission, which is its input, and outputs the high level to the light-emitting selection line for EM(2) transmission.

[0025] As shown in FIG. 3C , the light emission scanning circuit 202 sequentially scans the plurality of light emission selection lines, causing light emission of the light emitting elements to occur sequentially at a constant scanning speed during the light emission period T34 of the pixel array 100, regardless of whether the pixel array 100 is in a low-resolution region or a high-resolution region. This makes it possible to suppress changes in the light emitting area of ​​the pixel array 100 and suppress changes in the amount of current flowing through the light emitting elements. In addition, in this embodiment, the period T3 of one frame is set to the time required for one scan of the write selection lines 102 of all rows by the write scanning circuit 201. In this way, by defining one frame period in accordance with the write time required to write signal voltages by scanning the write scanning circuit 201, it is expected that the display device 1 will be able to write signal voltages to the pixel drive circuit 101 more efficiently.

[0026] Furthermore, in this embodiment, the scanning speed by the light emission scanning circuit 202 in period T34 is equal to or greater than the scanning speed by the write scanning circuit 201 in period T32, but is less than the scanning speed by the write scanning circuit 201 in periods T31 and T33. That is, in the display device 1 according to this embodiment, the light emission scanning speed of an area in which image data with a relatively low resolution is displayed is equal to or greater than the light emission scanning speed of an area in which image data with a relatively high resolution is displayed. In this embodiment, the write scanning speed by the write scanning circuit 201 differs for each of a plurality of areas in the pixel array 100, arranged in the column direction, in which image data with different resolutions are displayed.

[0027] Next, Fig. 3F shows a graph illustrating the relationship between the write scanning time and the light emission scanning time according to the control method of this embodiment and the amount of light emitted in the pixel array when the write scanning circuit 201 writes a signal voltage to the pixel drive circuit for a pixel array having low, medium, and high resolution regions. The medium resolution region can be appropriately provided between the low resolution region and the high resolution region in the configuration shown in Fig. 4.

[0028] In FIG. 3F , period T6 of one frame is the time required for the write scanning circuit 201 to perform one scan of the write selection lines 102 of all rows. Of period T6 of one frame, periods T61 and T65 are periods for writing signal voltages to the pixel drive circuits of the low-resolution region. Periods T62 and T64 are periods for writing signal voltages to the pixel drive circuits of the medium-resolution region. Period T63 is a period for writing signal voltages to the pixel drive circuits of the high-resolution region. The scanning speed of the light-emission scanning circuit 202 in period T66 is equal to or greater than the scanning speed of the write scanning circuit 201 in period T63, but is lower than the scanning speed of the write scanning circuit 201 in periods T61 and T63. By performing scanning in this manner by the light-emission scanning circuit 202, it is expected that the display device 1 can efficiently write signal voltages to light-emitting elements while suppressing changes in the amount of current flowing through the light-emitting elements due to changes in the amount of light emitted.

[0029] (Variation 1) Next, a first modification of the above embodiment will be described. In the following description, the same components as those of the display device 1 according to the above embodiment will be denoted by the same reference numerals. A detailed description of the configuration and operation will be omitted.

[0030] Fig. 6 is a diagram showing an example of the operation timing of the drive waveform of the vertical scanning circuit 200 in this modified example. The operation timing diagram in Fig. 6 corresponds to the graph shown in Fig. 3D. Note that the selection of the write selection line 102 by the write scanning circuit 201 and the selection of the emission selection line 104 by the emission scanning circuit 202 shown in the operation timing diagram in Fig. 6 are the same as those explained above using the operation timing diagram in Fig. 5.

[0031] 3D, in this modification, the period T4 of one frame is set to a time defined so that the light emission scanning speed for the light emission selection lines 104 of all rows by the light emission scanning circuit 202 remains constant when transitioning to the next frame. By defining one frame period in this way in accordance with the light emission time required for light emission by scanning by the light emission scanning circuit 202, the light emission area of ​​the pixel array 100 in the display device 1 can be made uniform at any timing.

[0032] 3D, in this modification, within period T44, periods T41 and T43 are periods for writing signal voltages to the pixel drive circuit for the low-resolution region, and period T42 is a period for writing signal voltages to the pixel drive circuit for the high-resolution region. Furthermore, the scanning speed by the light-emission scanning circuit 202 during period T4 of one frame is equal to or greater than the scanning speed by the write scanning circuit 201 during period T42, but is less than the scanning speed by the write scanning circuit 201 during periods T41 and T43.

[0033] (Variation 2) Next, a second modification of the above embodiment will be described. In the following description, the same components as those of the display device 1 according to the above embodiment will be denoted by the same reference numerals, and detailed descriptions of the components and operations will be omitted.

[0034] FIG. 7 is a diagram showing an example of the operation timing of the vertical scanning circuit 200 in this modified example. The selection of the write selection line 102 in the scan by the write scanning circuit 201 and the selection of the emission selection line 104 in the scan by the emission scanning circuit 202 shown in the operation timing diagram of FIG. 7 are the same as those described above using the operation timing diagram of FIG. 5. However, in FIG. 7, the frequencies of WR_CLK and EM_CLK are different from each other. In this modified example, one frame period is defined as the time required for one scan of the write selection lines 102 of all rows by the write scanning circuit 201. Furthermore, as shown in FIG. 3D, one frame period T4 is defined as the time required for one scan of the emission selection lines 104 of all rows by the emission scanning circuit 202. By defining one frame period in this way according to the light emission time required for light emission by the scan by the emission scanning circuit 202, the light-emitting area of ​​the pixel array 100 in the display device 1 can be made uniform at any timing. The drive frequencies of the write scanning circuit 201 and the emission scanning circuit 202 are set to satisfy the above conditions.

[0035] Furthermore, the scanning speed by the light emission scanning circuit 202 during one frame period is equal to or greater than the scanning speed for the high resolution region by the write scanning circuit 201, and is less than the scanning speed for the low resolution region by the write scanning circuit 201. Therefore, in the display device 1 according to this modification, it is possible to end one frame and move on to the next frame immediately after writing is completed, while making the light emitting area in the pixel array 100 uniform at any timing.

[0036] (Variation 3) Next, a third modification of the above embodiment will be described. The same components as those of the display device 1 according to the embodiment are denoted by the same reference numerals, and detailed descriptions of the components and operations will be omitted.

[0037] Fig. 8 is a diagram showing an example of the operation timing of the drive waveform of the vertical scanning circuit 200 in this modified example. The operation timing diagram in Fig. 8 corresponds to the graph shown in Fig. 3G. Note that the selection of the write selection line 102 in scanning by the write scanning circuit 201 and the selection of the emission selection line 104 in scanning by the emission scanning circuit 202 shown in the operation timing diagram in Fig. 8 are the same as those described above using the operation timing diagram in Fig. 5. However, in Fig. 8, the frequencies of WR_CLK and EM_CLK are different from each other.

[0038] 3G, in this modification, periods T71 and T73 of period T74 are periods for writing signal voltages to the pixel drive circuit for the low-resolution region, and period T72 is a period for writing signal voltages to the pixel drive circuit for the high-resolution region. Period T75 is a light-emitting period for the pixel array 100. In this modification, one frame period is defined as the time required for one scan of the write selection lines 102 of all rows by the write scanning circuit 201. The scanning speed by the write scanning circuit 201 during one frame period is equal to or greater than the scanning speed by the write scanning circuit 201 for the high-resolution region, but is less than the scanning speed by the write scanning circuit 201 for the low-resolution region.

[0039] 3G, in the display device 1 according to this modification, light emission begins a certain time after the writing start time. Even if the writing start time and the light emission start time do not coincide in this way, the display device 1 can end one frame and move on to the next frame immediately after writing is completed, while making the light-emitting area of ​​the pixel array 100 uniform.

[0040] (Variation 4) Next, a fourth modification of the above embodiment will be described. In the following description, the same components as those of the display device 1 according to the above embodiment will be denoted by the same reference numerals, and detailed descriptions of the components and operations will be omitted.

[0041] FIG. 10 is a diagram showing an example of the configuration of the vertical scanning circuit 200 of the display device 1 according to this modification. FIG. 11 is a diagram showing an example of the operation timing of the driving waveform of the vertical scanning circuit 200 according to this modification. In the vertical scanning circuit 200 shown in FIG. 10, the configuration of the write scanning circuit 201 is the same as that of the write scanning circuit 201 shown in FIG. 4, but the configuration of the light emission scanning circuit 202 is different from that of the light emission scanning circuit 202 shown in FIG. 4. Specifically, for example, two light emission selection lines (a selection line for transmitting EM(1) and a selection line for transmitting EM(2)) are connected to one D-Flip Flop circuit 202a. The D-Flip Flop circuit 202b and the subsequent D-Flip Flop circuit are also configured in the same way. As a result, as shown in the operation timing diagram of FIG. 11, the display device 1 according to this modification causes the unit pixel driving circuits 101 arranged in two rows to emit light collectively and sequentially at a constant scanning speed. The light emission scanning circuit 202 may be configured to collectively cause the unit pixel driving circuits 101 arranged in three or more rows to emit light.

[0042] Therefore, even when the display device 1 collectively emits light from the unit pixel drive circuits 101 arranged in multiple rows, the scanning speed by the write scanning circuit 201 is not uniform for each of the multiple regions in the pixel array 100 where image data with different resolutions is displayed. Also, the scanning speed by the light emission scanning circuit 202 across the multiple regions is equal to or greater than the minimum speed and less than the maximum speed of the scanning speed by the write scanning circuit 201. In this way, by controlling the scanning speed by the write scanning circuit 201 and the scanning speed by the light emission scanning circuit 202, the light emission area is made uniform, and the efficiency of writing signal voltages to the unit pixel drive circuits 101 is improved. It can be expected that this will happen.

[0043] (Variation 5) Next, a fifth modification of the above embodiment will be described. In the following description, the same components as those of the display device 1 according to the above embodiment will be denoted by the same reference numerals, and detailed descriptions of the components and operations will be omitted.

[0044] Fig. 12 is a diagram showing an example of the configuration of the vertical scanning circuit 200 of the display device 1 according to this modification. Fig. 13 is a diagram showing operation timing, which is an example of the drive waveform of the vertical scanning circuit 200 according to this modification. In the vertical scanning circuit 200 shown in Fig. 12, the configurations of the write scanning circuit 201 and the light emission scanning circuit 202 are different from the configurations of the write scanning circuit 201 and the light emission scanning circuit 202 shown in Fig. 4.

[0045] Specifically, as shown in FIG. 12, for example, the pixel array 100 is divided into a low-resolution region, a medium-resolution region, and a high-resolution region. In the write scanning circuit 201, four write selection lines (selection lines for transmitting WR(1) to WR(4)) are connected to one D-Flip Flop circuit 201c for the low-resolution region. Two write selection lines (selection lines for transmitting WR(5) and WR(6)) are connected to one D-Flip Flop circuit 201d for the medium-resolution region. One write selection line (selection line for transmitting WR(7)) is connected to one D-Flip Flop circuit 201e for the high-resolution region. Other D-Flip Flop circuits are configured similarly in each resolution region. Note that the number of write selection lines connected to a D-Flip Flop circuit in each resolution region is not limited to these. In this way, the number of write selection lines connected to one D-Flip Flop circuit differs for each of a plurality of regions in which image data with different resolutions is displayed.

[0046] 13, the display device 1 of this modification causes the unit pixel drive circuits 101 to emit light row by row in any resolution range. The display device 1 also causes the entire pixel array 100 to emit light sequentially at a constant scanning speed.

[0047] The operation of the display device 1 according to this modification will now be described. As shown in the operation timing diagram of FIG. 13, at time t0, V_SYNC goes high, starting one frame. Here, in the low-resolution region, the write scanning circuit 201 writes signal voltages to four unit pixel drive circuits 101 connected to the same image signal line 103. For example, when WR_CLK goes high at time t1, the first-stage D-flip-flop circuit 201c of the write scanning circuit 201 captures the high level of its input, WR_S. The D-flip-flop circuit 201c then outputs a high level to the write selection lines WR(1), WR(2), WR(3), and WR(4). As a result, the image signal A output from the signal output circuit 300 to the image signal line 103 at time t1 is written to the unit pixel drive circuits 101 arranged in four rows.

[0048] Furthermore, in the medium resolution region, the write scanning circuit 201 writes signal voltages to two unit pixel driving circuits 101. For example, when WR_CLK goes high at time t2, the second-stage D-flip flop circuit 201d of the write scanning circuit 201 takes in the high levels of the input write selection lines for transmitting WR(1), WR(2), WR(3), and WR(4). The D-flip flop circuit 201d then outputs the high level to the write selection lines for transmitting WR(5) and WR(6). As a result, the image signal B output from the signal output circuit 300 to the image signal line 103 at time t2 is written to the unit pixel driving circuits 101 arranged in two rows.

[0049] In addition, in the high resolution region, the write scanning circuit 201 writes a signal voltage to one unit pixel driving circuit 101. For example, when WR_CLK goes high at time t4, the third-stage D-Flip Flop circuit 201e of the write scanning circuit 201 takes in the high level of the input write selection lines for transmitting WR(5) and WR(6), and outputs the high level to the write selection line for transmitting WR(7).

[0050] By scanning in this manner, data is written sequentially to the pixel drive circuits of the low-resolution area, the medium-resolution area, and the high-resolution area, thereby enabling the display device 1 to reduce latency related to image display in the same manner as the circuit configuration of FIG.

[0051] Regarding scanning by the light emission scanning circuit 202, for example, when EM_CLK goes high at time t3, the first-stage D-flip flop circuit 202a of the light emission scanning circuit 202 receives the high level of EM_S as its input. The D-flip flop circuit 202a then outputs the high level to the light emission selection line for EM(1) transmission. When EM_CLK goes high again at time t4, the second-stage D-flip flop circuit 202b of the light emission scanning circuit 202 receives the high level of the light emission selection line for EM(1) transmission as its input and outputs the high level to the light emission selection line for EM(2) transmission. By performing scanning in this manner by the light emission scanning circuit 202, light emission of light emitting elements is sequentially performed at a constant scanning speed during the light emission period of the pixel array 100, regardless of whether the region is a low-resolution region, a medium-resolution region, or a high-resolution region. This allows the display device 1 to achieve a uniform light-emitting area in the pixel array 100.

[0052] (Variation 6) Next, a sixth modification of the above embodiment will be described. In the following description, the same components as those of the display device 1 according to the above embodiment will be denoted by the same reference numerals, and detailed descriptions of the components and operations will be omitted.

[0053] The operation of the vertical scanning circuit 200 in the above embodiment is an example, and the light emission control signal EM(N) and the write control signal WR(N) in FIG. 4 may be logically operated with other control signals in an arbitrary logic gate circuit, and the obtained result may be output as a control signal to the unit pixel driving circuit 101. FIG. 14A shows an example of the configuration of the vertical scanning circuit 200 according to this modification. In this modification, for example, the vertical scanning circuit 200 includes a write scanning circuit 201, a light emission scanning circuit 202, and an output control logic gate circuit 204 connected to the unit pixel driving circuit 101.

[0054] 14B shows an example of the configuration of the output control logic gate circuit 204. The output control logic gate circuit 204 outputs the logical product of the control signals SIG_A and SIG_B, which are input to the unit pixel drive circuit 101, and the write control signal WR(N), as the write control signal WR_A(N) and the control signal WR_B(N). In this way, the output control logic gate circuit 204 is connected to the outputs of the write scanning circuit 201 and the light emission scanning circuit 202, and outputs the result of the logical operation to the unit pixel drive circuit 101.

[0055] Furthermore, the write control signal and the light emission control signal do not have to be of one type. Furthermore, by adding circuits such as switches, D-Flip Flops, and decoders to the write scanning circuit 201, it may be possible to dynamically change the positions of, for example, low-resolution and high-resolution regions in the pixel array 100. Furthermore, when writing and emitting light in each row, the write control signal and the light emission control signal do not need to be fixed at the H level, and there may be a period when they are at the L level. Furthermore, the above-mentioned circuits do not need to operate with positive logic, and some or all of the circuits may be configured to operate with negative logic.

[0056] (Embodiment 2) A display device according to a second embodiment of the present invention will be described. The same components as those of the display device 1 according to the first embodiment are denoted by the same reference numerals, and detailed descriptions of the components and operations thereof will be omitted.

[0057] 15 is a schematic diagram showing an example of the configuration of a display device 2 according to this embodiment. The display device 2 includes a pixel array 100, a vertical scanning circuit 200, a signal output circuit 300, and a control circuit 400. In this embodiment, the pixel array 100 of the display device 2 includes, in addition to a unit pixel drive circuit 101, pixel drive circuits 502 and 503 having a light-emitting area twice that of the unit pixel drive circuit 101, and a pixel drive circuit 504 having a light-emitting area four times that of the unit pixel drive circuit 101. Note that in FIG. 15, the other pixel drive circuits having the same shape as the pixel drive circuits 101, 502, 503, and 504 are also configured in the same manner as the corresponding pixel drive circuits 101, 502, 503, and 504.

[0058] In the display device 2, for example, compared to the unit pixel drive circuit 101 of FIG. 2, the channel width of the drive transistor 113 and the area of ​​the light-emitting diode 114 are doubled in the pixel drive circuits 502 and 503, and quadrupled in the pixel drive circuit 504. This allows the light-emitting area of ​​the pixel drive circuits 502 and 503 to be doubled or quadrupled. The pixel drive circuit 502 has twice the vertical area of ​​the unit pixel drive circuit 101, and the pixel drive circuit 503 has twice the horizontal area of ​​the unit pixel drive circuit 101. The pixel drive circuit 504 has twice the vertical and horizontal areas of the unit pixel drive circuit 101. In this embodiment, the area formed by the pixel drive circuit 504 corresponds to the low-resolution area. The area formed by the pixel drive circuits 502 and 503 corresponds to the medium-resolution area. The area formed by the unit pixel drive circuit 101 corresponds to the high-resolution area. In this way, in the display device 2 according to this embodiment, the size of the pixel drive circuit differs for each resolution region in the pixel array.

[0059] Fig. 16 shows an example of the configuration of the vertical scanning circuit 200 in this embodiment, and Fig. 17 shows an operation timing diagram that is an example of the drive waveforms of the vertical scanning circuit 200 in this embodiment. As shown in Fig. 16, the vertical scanning circuit 200 is made up of a write scanning circuit 201 and an emission scanning circuit 202, and the write scanning circuit 201 and the emission scanning circuit 202 are shift register circuits in which D-flip flop circuits are cascaded in the column direction of the pixel array. A write start pulse WR_S and a write clock WR_CLK are supplied to the write scanning circuit 201, and an emission start pulse EM_S and a write clock EM_CLK are supplied to the emission scanning circuit 202.

[0060] 16, two types of image signal lines are provided: image signal line 103a to which pixel drive circuit 503 and pixel drive circuit 504 are connected, and image signal line 103b to which unit pixel drive circuit 101 and pixel drive circuit 502 are connected. However, the scanning method described below is performed in the same way for both image signal lines.

[0061] As shown in FIG. 17, at time t0, V_SYNC goes high, starting one frame. Here, the write scanning circuit 201 writes a signal voltage to the pixel driving circuit 504 in the low-resolution region and to the pixel driving circuit 502 in the medium-resolution region. For example, when WR_CLK goes high at time t1, the first-stage D-Flip Flop circuit 201f of the write scanning circuit 201 receives the high level of its input WR_S and outputs a high level to the write selection line for transmitting WR(1). As a result, the image signal A1 output from the signal output circuit 300 to the image signal line 103a at time t1 is written to the pixel driving circuit 504, and the image signals A2 and A3 output to the image signal line 103b are written to the pixel driving circuit 502. The write scanning circuit 201 also writes a signal voltage to the pixel driving circuit 503 in the medium-resolution region and to the unit pixel driving circuit 101 in the high-resolution region. For example, when WR_CLK goes high at time t3, the third stage of the write scanning circuit 201 The second D-Flip Flop circuit 201g takes in the H level of the input write selection line for WR(2) transmission and outputs an H level to the write selection line for WR(3) transmission. As a result, at time t3, the image signal C1 output from the signal output circuit 300 to the image signal line 103a is written to the pixel drive circuit 503, and the image signals C2 and C3 output to the image signal line 103b are written to the unit pixel drive circuit 101. By scanning in this manner, data is sequentially written to the pixel drive circuit 503 for the low resolution region, the pixel drive circuits 502 and 504 for the medium resolution region, and the unit pixel drive circuit 101 for the high resolution region.

[0062] 22 shows an example of the relationship between an image signal 1001 output from the signal output circuit 300 and a display image 1002 displayed on the pixel array 100 when the display device 2 writes a signal voltage. According to the signal voltage writing of the display device 2, in order to display the display image 1002 shown in FIG. 22, the image signal 1001 output from the signal output circuit 300 has a reduced amount of image data in the low-resolution region and medium-resolution region in the row direction. As a result, the display device 2 can reduce latency related to image display by sending an externally transmitted image signal directly from the signal output circuit 300 to the pixel array 100 without decompressing it in the control circuit 400 and the signal output circuit 300.

[0063] In the scanning by the light emission scanning circuit 202 shown in the operation timing diagram of FIG. 17, when EM_CLK becomes H level at time t2, for example, the first stage D-Flip The D-Flip Flop circuit 202c takes in the H level of EM_S, which is its input. Then, the D-Flip Flop circuit 202c outputs an H level to the light emission selection line for EM(1) transmission. When EM_CLK goes high again at time t4, the third-stage D-Flip Flop circuit 202e of the light emission scanning circuit 202 takes in the H level of the second-stage D-Flip Flop circuit 202d, which is its input, and outputs an H level to the light emission selection line for EM(2) transmission. When EM_CLK goes high again at time t5, the fifth-stage D-Flip Flop circuit 202g of the light emission scanning circuit 202 takes in the H level of the fourth-stage D-Flip Flop circuit 202f of the light emission scanning circuit 202, which is its input. Then, the D-Flip Flop circuit 202g outputs an H level to the light emission selection line for EM(3) transmission and the light emission selection line for EM(4) transmission. By performing scanning in this manner by the light emission scanning circuit 202, in the display device 2, during the light emission period of the pixel array 100, light is emitted sequentially from the light emitting elements at a constant scanning speed regardless of whether it is a low resolution area, a medium resolution area, or a high resolution area.

[0064] Therefore, in the display device 2 according to this embodiment, in the column direction of pixel array 100 (the scanning direction of vertical scanning circuit 200), the length of the light-emitting area of ​​the high-resolution region during light emission is the same as the length of the light-emitting area of ​​pixel drive circuit 502 of the medium-resolution region and the pixel drive circuit 504 of the low-resolution region during light emission. This makes it possible to make the light-emitting area uniform across pixel array 100, regardless of the region, even if the pixel area differs between regions with different resolutions in display device 2.

[0065] Furthermore, in this embodiment, as in embodiment 1, the scanning speed by the light emission scanning circuit 202 is equal to or greater than the scanning speed by the write scanning circuit 201 for high-resolution regions, and is less than the scanning speed by the write scanning circuit 201 for low-resolution regions. That is, in this embodiment, the scanning speed by the write scanning circuit 201 is not uniform for each of the multiple regions in the pixel array 100 where image data with different resolutions are displayed. Furthermore, the scanning speed by the light emission scanning circuit 202 across the multiple regions is equal to or greater than the minimum speed and less than the maximum speed of the scanning speed by the write scanning circuit 201.

[0066] (Variation 7) Next, Modification 7, which is a modification of Embodiment 2, will be described. Here, the same components as those of the display device 2 according to the above embodiment are denoted by the same reference numerals, and detailed description of the components and operations will be omitted.

[0067] 18 shows an example of the configuration of a vertical scanning circuit 200 and a pixel array 100 according to this modification. As shown in FIG. 18, the vertical scanning circuit 200 is configured with a write scanning circuit 201 and an emission scanning circuit 202. The write scanning circuit 201 and the emission scanning circuit 202 are configured by a D-Flip It is a shift register circuit in which flop circuits are cascaded in the column direction of the pixel array. A write start pulse WR_S and a write clock WR_CLK are supplied to the write scanning circuit 201, and a light emission start pulse EM_S and a write clock EM_CLK are supplied to the light emission scanning circuit 202. Note that in Figure 18, the other pixel driving circuits having the same shape as the respective pixel driving circuits 101, 602, 603, and 604 are also configured in the same way as the corresponding pixel driving circuits 101, 602, 603, and 604.

[0068] 18, pixel driving circuits 602, 603, and 604 correspond to pixel driving circuits 502, 503, and 504 in embodiment 2. The configurations of pixel driving circuits 602, 603, and 604 will be described in detail later. Two types of image signal lines are provided: image signal line 103a to which pixel driving circuit 603 and pixel driving circuit 604 are connected, and image signal line 103b to which unit pixel driving circuit 101 and pixel driving circuit 602 are connected. However, the scanning method described below is performed in the same way for both image signal lines.

[0069] 19 shows an example of the configuration of a pixel drive circuit 602. The pixel drive circuit 602 includes one write control transistor 112a, two light-emitting control transistors 111a and 111b, two drive transistors 113a and 113b, and two light-emitting diodes 114a and 114b. The cathode terminals of the light-emitting diodes 114a and 114b are connected to VSS, which is the ground level, and the anode terminals of the light-emitting diodes 114a and 114b are connected to the source terminals of the drive transistors 113a and 113b, respectively. The drain terminals of the drive transistors 113a and 113b are connected to the source terminals of the light-emitting control transistors 111a and 111b, respectively, and the gate terminals of the drive transistors 113a and 113b are connected to the source terminal of the write control transistor 112. The drain terminals of the light emission control transistors 111a and 111b are connected to the power supply VDD, and the gate terminals of the light emission control transistors 111a and 111b are connected to the light emission selection lines 104a and 104b, respectively. The drain terminal of the write control transistor 112 is connected to the image signal line 103b, and the gate terminal of the write control transistor 112 is connected to the write selection line 102.

[0070] The operation of the pixel drive circuit 602 is the same as that of Fig. 2, and therefore a detailed description thereof will be omitted here. According to the pixel drive circuit 602 of Fig. 19, since it is provided with two light emission selection lines 104a, 104b, it is possible to control the number of light emitting diodes to emit light (to one or two) by causing only one or both of the light emitting diodes 114a, 114b to emit light.

[0071] 20 shows an example of the configuration of the pixel drive circuit 604. The pixel drive circuit 604 includes one write control transistor 112c and four light-emitting control transistors 111c, 111d, 111e, and 111f. The pixel drive circuit 604 also includes four drive transistors 113c, 113d, 113e, and 113f and four light-emitting diodes 114c, 114d, 114e, and 114f. The cathode terminals of the light-emitting diodes 114c, 114d, 114e, and 114f are connected to VSS, which is the ground level. The anode terminals of the light-emitting diodes 114c, 114d, 114e, and 114f are connected to the source terminals of the drive transistors 113c, 113d, 113e, and 113f, respectively. The drive transistors 1 The drain terminals of the light-emitting control transistors 111c, 111d, 111e, and 111f are connected to the source terminals of the light-emitting control transistors 111c, 111d, 111e, and 111f, respectively. The gate terminals of the drive transistors 113c, 113d, 113e, and 113f are connected to the source terminal of the write control transistor 112c. The drain terminals of the light-emitting control transistors 111c, 111d, 111e, and 111f are connected to the power supply VDD. The gate terminals of the light-emitting control transistors 111c and 111d are connected to the light-emitting selection line 104a, and the gate terminals of the light-emitting control transistors 111e and 111f are connected to the light-emitting selection line 104b. The drain terminal of the write control transistor 112c is connected to the image signal line 103a, and the gate terminal of the write control transistor 112c is connected to the write selection line 102.

[0072] The operation of the pixel drive circuit 604 is the same as that described in Fig. 2, and therefore a detailed description thereof will be omitted here. The pixel drive circuit 604 in Fig. 20 is provided with two emission selection lines 104a and 104b, and therefore it is possible to cause either one of the pair of light-emitting diodes 114c and 114d and the pair of light-emitting diodes 114e and 114f to emit light, or both of them to emit light. This allows the pixel drive circuit 604 to control the number of light-emitting diodes to emit light (two or four).

[0073] FIG. 21 shows an operation timing diagram illustrating an example of a drive waveform of the vertical scanning circuit 200 in this embodiment. In scanning by the light emission scanning circuit 202 shown in the operation timing diagram of FIG. 21, when EM_CLK goes high at time t1, for example, the first-stage D-flip flop circuit 202c of the light emission scanning circuit 202 captures the high level of EM_S as its input. The D-flip flop circuit 202c then outputs the high level to the light emission selection line for EM(1) transmission. Furthermore, when EM_CLK goes high again at time t2, the second-stage D-flip flop circuit 202d of the light emission scanning circuit 202 captures the high level of the input light emission selection line for EM(1) transmission and outputs the high level to the light emission selection line for EM(2) transmission. By performing scanning in this manner by the light emission scanning circuit 202, in the display device 2, light emission of light emitting elements is sequentially performed at a constant scanning speed during the light emission period of the pixel array 100, regardless of whether the region is a low-resolution region, a medium-resolution region, or a high-resolution region. This allows the light-emitting area of ​​the pixel array 100 in the display device 2 to be uniform.

[0074] Therefore, in the display device 2 according to this modification, scanning is performed by the light emission scanning circuit 202 so that the amount of light emission of the pixel drive circuit in a relatively low resolution region is determined according to the size of the pixel drive circuit in a relatively high resolution region among the multiple resolution regions. Also, in this modification, in the column direction of the pixel array 100 (the scanning direction of the vertical scanning circuit 200), the lengths of the light emitting regions of the pixel drive circuit 602 in the medium resolution region and the pixel drive circuit 604 in the low resolution region during light emission are the same as the light emitting region of the high resolution region during light emission. As a result, even if the pixel areas differ between regions of different resolutions in the display device 2, the light emitting areas in the pixel array 100 can be made uniform regardless of the region.

[0075] [Organic light-emitting element] Next, an example of an organic light-emitting element that can be used in the display devices according to the first and second embodiments will be described.

[0076] In the display devices according to the first and second embodiments, the organic light-emitting element has a first electrode, a second electrode, and an organic compound layer disposed between these electrodes. One of the first and second electrodes is an anode, and the other is a cathode. In the first and second embodiments, the organic compound layer may be a single layer having a light-emitting layer, or may be a laminate consisting of multiple layers. When the organic compound layer is a laminate consisting of multiple layers, the organic compound layer may further include a hole injection layer, a hole transport layer, an electron blocking layer, a hole / exciton blocking layer, a hole blocking ... The organic compound layer may have a doping layer, an electron transport layer, an electron injection layer, etc. The light-emitting layer may be a single layer or a laminate consisting of multiple layers. When the light-emitting layer has multiple layers, a charge generation layer may be provided between the light-emitting layers. The charge generation layer may be composed of a compound having a lower LUMO than the hole transport layer, and the LUMO of the charge generation layer may be lower than the HOMO of the hole transport layer. Here, the molecular orbital energy of the organic compound layer may be the molecular orbital energy of the organic compound having the largest weight ratio in the organic compound layer.

[0077] In Embodiments 1 and 2, when an organic compound is contained in the light-emitting layer, the light-emitting layer may be a layer consisting of only the organic compound, or may be a layer consisting of an organometallic complex and other compounds. Here, when the light-emitting layer is a layer consisting of an organometallic complex and other compounds, the organic compound may be used as a host or a guest of the light-emitting layer. It may also be used as an assist material that can be contained in the light-emitting layer. Here, the host is the compound with the largest mass ratio among the compounds constituting the light-emitting layer. The guest is a compound with a mass ratio smaller than that of the host among the compounds constituting the light-emitting layer, and is responsible for the main emission of light. The assist material is a compound with a mass ratio smaller than that of the host among the compounds constituting the light-emitting layer, and assists the emission of the guest. The assist material is also called a second host. The host material can also be called the first compound, and the assist material can also be called the second compound.

[0078] Here, the organic compound may be used in combination with conventionally known low-molecular-weight and high-molecular-weight hole-injecting or hole-transporting compounds, host compounds, light-emitting compounds, electron-injecting or electron-transporting compounds, etc., as needed.

[0079] The hole injection / transport material is preferably a material with high hole mobility that facilitates the injection of holes from the anode and transports the injected holes to the light-emitting layer. Furthermore, a material with a high glass transition temperature is preferred to reduce deterioration of film quality, such as crystallization, in the organic light-emitting device.

[0080] The electron transporting material can be arbitrarily selected from those capable of transporting electrons injected from the cathode to the light-emitting layer, and is selected in consideration of the balance with the hole mobility of the hole transporting material, etc. The electron transporting material is also preferably used in the hole blocking layer.

[0081] The electron-injecting material can be arbitrarily selected from those that allow easy injection of electrons from the cathode, and is selected in consideration of the balance with hole-injecting properties, etc. It can also be used in combination with an electron-transporting material.

[0082] [Configuration of organic light-emitting element] An organic light-emitting element is provided by forming an insulating layer, a first electrode, an organic compound layer (sometimes called a functional layer), and a second electrode on a substrate. A protective layer, a color filter, a microlens, etc. may be provided on the cathode. When a color filter is provided, a planarizing layer may be provided between the protective layer. The planarizing layer may be made of acrylic resin, etc. The same applies when a planarizing layer is provided between the color filter and the microlens.

[0083] [substrate] Examples of the substrate include quartz, glass, silicon wafer, resin, and metal. The substrate may also be provided with switching elements such as transistors and wiring, and an insulating layer (sometimes called an insulating film) on top of these. When a silicon wafer is used as the substrate, the active layer, source region, and drain region of the transistor are formed within the substrate. This is also preferable because it allows for densely arranged transistors.

[0084] Any material can be used for the insulating layer as long as it allows for the formation of contact holes so that wiring can be formed between the first electrode and the insulating layer, and ensures insulation from wiring that is not connected. For example, resins such as polyimide, silicon oxide, silicon nitride, etc. can be used.

[0085] [electrode] A pair of electrodes can be used. The pair of electrodes may be an anode (sometimes referred to as an anode electrode) and a cathode (sometimes referred to as a cathode electrode). When an electric field is applied in the direction in which the organic light-emitting element emits light, the electrode with a higher potential is the anode, and the other is the cathode. It can also be said that the electrode that supplies holes to the light-emitting layer is the anode, and the electrode that supplies electrons is the cathode.

[0086] The material for the anode should have as high a work function as possible. Examples of suitable materials include simple metals such as gold, platinum, silver, copper, nickel, palladium, cobalt, selenium, vanadium, and tungsten. Mixtures containing these metals, alloys of these metals, and metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide can also be used. Conductive polymers such as polyaniline, polypyrrole, and polythiophene can also be used.

[0087] These electrode materials may be used alone or in combination of two or more. The anode may be composed of one layer or multiple layers.

[0088] When used as a reflective electrode, for example, chromium, aluminum, silver, titanium, tungsten, molybdenum, or alloys or laminates thereof can be used. The above materials can also function as a reflective film without functioning as an electrode. When used as a transparent electrode, transparent conductive oxide layers such as indium tin oxide (ITO) and indium zinc oxide can be used, but are not limited to these. Photolithography technology can be used to form the electrode.

[0089] On the other hand, materials with a low work function are preferable for the cathode. Examples include alkali metals such as lithium, alkaline earth metals such as calcium, and metals such as aluminum, titanium, manganese, silver, lead, and chromium, as well as mixtures containing these metals. Alloys combining these metals can also be used. Examples include magnesium-silver, aluminum-lithium, aluminum-magnesium, silver-copper, and zinc-silver. Metal oxides such as indium tin oxide (ITO) can also be used.

[0090] These electrode materials may be used alone or in combination of two or more. The cathode may have a single layer structure or a multi-layer structure. Among these, silver is preferably used, and a silver alloy is more preferable to reduce silver aggregation. The alloy ratio is not important as long as it can reduce silver aggregation. For example, the silver:other metal ratio may be 1:1, 3:1, etc.

[0091] The cathode may be a top-emission element using an oxide conductive layer such as ITO, or a bottom-emission element using a reflective electrode such as aluminum (Al), and is not particularly limited. The method for forming the cathode is not particularly limited, but DC and AC sputtering methods are more preferred because they provide good film coverage and make it easier to reduce resistance.

[0092] [Pixel isolation layer] The pixel isolation layer is formed of a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, or a silicon oxide (SiO) film formed by chemical vapor deposition (CVD). In order to increase the in-plane resistance of the organic compound layer, it is preferable that the thickness of the organic compound layer, particularly the hole transport layer, is thin on the sidewall of the pixel separation layer. Specifically, the thickness of the sidewall can be thinned by increasing the taper angle of the sidewall of the pixel separation layer or the thickness of the pixel separation layer, thereby increasing vignetting during vapor deposition.

[0093] On the other hand, it is preferable to adjust the sidewall taper angle and film thickness of the pixel separation layer to such an extent that voids are not formed in the protective layer formed on top of it. Since voids are not formed in the protective layer, the occurrence of defects in the protective layer can be reduced. Since the occurrence of defects in the protective layer is reduced, it is possible to reduce deterioration in reliability, such as the occurrence of dark spots and poor conduction of the second electrode.

[0094] By adjusting the taper angle of the sidewall of the pixel separation layer, it is possible to effectively suppress charge leakage to adjacent pixels. For example, a taper angle between 60 degrees and 90 degrees can sufficiently reduce charge leakage. The thickness of the pixel separation layer is preferably between 10 nm and 150 nm. Similar effects can also be achieved by using only pixel electrodes without a pixel separation layer. However, in this case, it is preferable to make the thickness of the pixel electrode less than half that of the organic layer or to make the edge of the pixel electrode forward tapered by less than 60 degrees, as this reduces short circuits in the organic light-emitting element.

[0095] [Organic compound layer (functional layer)] The organic compound layer may be formed as a single layer or as multiple layers. When multiple layers are present, they may be called hole injection layer, hole transport layer, electron blocking layer, light-emitting layer, hole blocking layer, electron transport layer, or electron injection layer depending on their functions. The organic compound layer is mainly composed of organic compounds but may also contain inorganic atoms or inorganic compounds. For example, it may contain copper, lithium, magnesium, aluminum, iridium, platinum, molybdenum, zinc, etc. The organic compound layer may be disposed between the first electrode and the second electrode, or may be disposed in contact with the first electrode and the second electrode.

[0096] When the device has multiple light-emitting layers, a charge generation section may be provided between the first and second light-emitting layers. The charge generation section may have an organic compound with a lowest unoccupied molecular orbital energy (LUMO) of -5.0 eV or less. The same applies when the charge generation section is provided between the second and third light-emitting layers.

[0097] [Protective layer] A protective layer such as an insulating film may be provided on the second electrode. For example, by adhering glass with a moisture absorbent on the second electrode, the intrusion of water and other contaminants into the organic compound layer can be reduced, thereby reducing the occurrence of display defects. In another embodiment, a passivation film such as silicon nitride may be provided on the cathode to reduce the intrusion of water and other contaminants into the organic compound layer. For example, after forming the cathode, the cathode may be transferred to another chamber without breaking the vacuum, and a 2 μm-thick silicon nitride film may be formed by CVD to serve as a protective layer. A protective layer may be formed using atomic layer deposition (ALD) after the CVD film formation. The material of the film formed by ALD is not limited, and may be silicon nitride, silicon oxide, aluminum oxide, or the like. Silicon nitride may be further formed on the film formed by ALD by CVD. The film formed by ALD may have a thickness smaller than that of the film formed by CVD. Specifically, the thickness may be 50% or less, or even 10% or less.

[0098] [Color Filter] A color filter may be provided on the protective layer. For example, a color filter taking into consideration the size of the organic light-emitting element may be provided on a separate substrate and then bonded to the substrate on which the organic light-emitting element is provided, or a color filter may be patterned on the protective layer described above using photolithography technology. The color filter may be made of a polymer.

[0099] [Planarization layer] A planarization layer may be provided between the color filter and the protective layer. The planarization layer is provided for the purpose of reducing the unevenness of the underlying layer. It may also be called a material resin layer without limiting its purpose. The planarization layer may be composed of an organic compound, and may be either a low molecular weight or a high molecular weight, but a high molecular weight is preferred.

[0100] The planarizing layer may be provided above or below the color filter, and may be made of the same or different materials, such as polyvinyl carbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0101] [Microlens] The display device may have an optical component such as a microlens on its light-emitting side. The microlens may be made of acrylic resin, epoxy resin, or the like. The purpose of the microlens may be to increase the amount of light extracted from the display device and to control the direction of the extracted light. The microlens may have a hemispherical shape. When the microlens has a hemispherical shape, among the tangents to the hemisphere, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the hemisphere is the vertex of the microlens. The vertex of the microlens can be determined in the same way in any cross-sectional view. In other words, among the tangents to the semicircle of the microlens in the cross-sectional view, there is a tangent that is parallel to the insulating layer, and the point of contact between this tangent and the semicircle is the vertex of the microlens.

[0102] It is also possible to define the midpoint of a microlens. In the cross section of the microlens, a line segment is imagined from the point where an arc shape ends to the point where another arc shape ends, and the midpoint of this line segment can be called the midpoint of the microlens. The cross section for determining the vertex and midpoint may be a cross section perpendicular to the insulating layer.

[0103] The microlens has a first surface having a convex portion and a second surface opposite the first surface. The second surface is preferably disposed closer to the functional layer than the first surface. To achieve this configuration, it is necessary to form the microlens on the display device. When the functional layer is an organic layer, it is preferable to avoid processes that result in high temperatures during the manufacturing process. Furthermore, when the second surface is disposed closer to the functional layer than the first surface, it is preferable that the glass transition temperatures of all organic compounds that make up the organic layer are 100°C or higher, and more preferably 130°C or higher.

[0104] [Counter substrate] An opposing substrate may be provided on the planarization layer. The opposing substrate is called the opposing substrate because it is provided at a position corresponding to the aforementioned substrate. The constituent material of the opposing substrate may be the same as that of the aforementioned substrate. When the aforementioned substrate is defined as the first substrate, the opposing substrate may be the second substrate.

[0105] [Organic layer] The organic compound layers (hole injection layer, hole transport layer, electron blocking layer, light emitting layer, hole blocking layer, electron transport layer, electron injection layer, etc.) constituting the organic light emitting device are formed by the following method.

[0106] The organic compound layer constituting the organic light-emitting device can be formed by dry processes such as vacuum deposition, ionization deposition, sputtering, plasma, etc. Alternatively to the dry process, a wet process can be used in which the compound is dissolved in an appropriate solvent and a layer is formed by a known coating method (e.g., spin coating, dipping, casting, LB method, inkjet method, etc.).

[0107] Here, when the layer is formed by a vacuum deposition method or a solution coating method, crystallization is unlikely to occur. It has excellent stability over time. When forming a film by coating, it can also be formed by combining it with an appropriate binder resin.

[0108] Examples of the binder resin include, but are not limited to, polyvinylcarbazole resin, polycarbonate resin, polyester resin, ABS resin, acrylic resin, polyimide resin, phenol resin, epoxy resin, silicone resin, and urea resin.

[0109] These binder resins may be used singly or in combination as homopolymers or copolymers, and may further contain known additives such as plasticizers, antioxidants, and ultraviolet absorbers, if necessary.

[0110] [Pixel driving circuit] The display device has a pixel drive circuit connected to a light-emitting element. The pixel drive circuit may be an active matrix type that controls the light emission of a first light-emitting element and a second light-emitting element independently. The active matrix type circuit may be voltage-programmed or current-programmed. The display device has a pixel drive circuit for each pixel. The pixel drive circuit may include a light-emitting element, a transistor that controls the light emission brightness of the light-emitting element, a transistor that controls the light emission timing, a capacitor that holds the gate voltage of the transistor that controls the light emission brightness, and a transistor for connecting to GND without going through the light-emitting element.

[0111] The display device has a display area and a peripheral area surrounding the display area. The display area includes the pixel drive circuit described in the first and second embodiments, and the peripheral area includes a display control circuit. The mobility of the transistors constituting the pixel drive circuit may be smaller than the mobility of the transistors constituting the display control circuit.

[0112] The slope of the current-voltage characteristics of the transistors that make up the pixel drive circuit may be smaller than the slope of the current-voltage characteristics of the transistors that make up the display control circuit. The slope of the current-voltage characteristics can be measured using the so-called Vg-Ig characteristics.

[0113] The transistors that make up the pixel driving circuit may be transistors that are connected to a light emitting element such as the first light emitting element.

[0114] [Pixels] The display device has a plurality of pixels as described above in the first and second embodiments. The pixels may each have, for example, RGB light emission colors.

[0115] A pixel has an area, also called a pixel aperture, that emits light. This area is the same as the first area. The pixel aperture may be 15 μm or less, or 5 μm or more. More specifically, it may be 11 μm, 9.5 μm, 7.4 μm, 6.4 μm, etc. The distance between pixels (from center to center of adjacent pixels) may be 10 μm or less, or more specifically, 8 μm, 7.4 μm, 6.4 μm, or less.

[0116] The pixels may be arranged in a known manner in a plan view. For example, they may be in a stripe arrangement, a delta arrangement (honeycomb arrangement), a pentile arrangement, or a Bayer arrangement. The shape of the pixels in a plan view may be any known shape. For example, they may be rectangular, quadrilaterals such as diamonds, or hexagons. Of course, a shape that is close to a rectangle, rather than an exact shape, is included in the rectangle. The pixel shape and pixel arrangement may be used in combination.

[0117] [Use of the display device according to the first and second embodiments] The display devices according to the first and second embodiments can be used as components of various devices and equipment, etc. For example, they can be used as display devices having a white light source and a color filter.

[0118] A device having the display device according to embodiment 1 or 2 may be an image information processing device having an image input unit that inputs image information from an area CCD, a linear CCD, a memory card, etc., and an information processing unit that processes the input information, and displays the input image on a display unit. The display unit may have the display device according to embodiment 1 or 2.

[0119] Furthermore, the display unit of an imaging device or an inkjet printer may include the display device according to embodiment 1 or 2. The display unit may have a touch panel function. The driving method for this touch panel function may be an infrared method, a capacitance method, a resistive film method, or an electromagnetic induction method, and is not particularly limited. Furthermore, the display device may be used in the display unit of a multifunction printer.

[0120] Next, a cross section of an example of a part of the display devices of Embodiments 1 and 2 will be described with reference to Fig. 23. For convenience of explanation, different reference numerals may be used for elements and the like already mentioned above.

[0121] The display device includes a substrate 11, an insulating layer 14, and a light-emitting element 2300. The insulating layer 14 is located on the substrate 11. The light-emitting element 2300 is located on the insulating layer 14. In other words, the insulating layer 14 is located between the substrate 11 and the light-emitting element 2300.

[0122] The substrate 11 has a main surface (upper surface in FIG. 23) on which a drive transistor 2301, a write control transistor 2303, and a light-emitting control transistor 2302 are formed. The substrate 11 may be formed of, for example, a P-type semiconductor. A P-type well region 13 is formed on the main surface side of the substrate 11 (i.e., the upper side of the substrate 11). The substrate 11 other than the well region 13 becomes a P-type semiconductor region 12.

[0123] The substrate 11 has a plurality of impurity regions that function as source regions or drain regions of the transistors in the well region 13. The conductivity type of the impurity regions can be, for example, N-type.

[0124] A conductive layer 2365, a conductive layer 2363G, and a conductive layer 2364G are arranged on the main surface (upper surface) of the substrate 11. The conductive layer 2363G functions as the gate of the light-emitting control transistor 2363. One of the N-type impurity regions functions as the source 2363S of the light-emitting control transistor 2363, and another of the N-type impurity regions functions as the drain 2363D. The conductive layer 2365 functions as the gate of the driving transistor 2361. The impurity region that functions as the drain 2363D of the light-emitting control transistor 2363 also functions as the source 2368 of the driving transistor 2301. Another one of the N-type impurity regions functions as the drain 2367 of the driving transistor 2301.

[0125] Furthermore, the conductive layer 2364G functions as the gate of the reset transistor 2364. Moreover, the impurity region that functions as the source 2368 of the drive transistor 2301 also functions as the drain 2364D of the reset transistor 2364. Moreover, another one of the N-type impurity regions functions as the source 2364S of the reset transistor 2364.

[0126] The substrate 11 further has an element isolation section 2330 formed between adjacent pixels. The element isolation section 2330 may be formed by STI (Shallow Trench Isolation), LOCOS (LOCal Oxidation of Silicon) isolation, or P-type Diffusion layer separation or the like may also be used.

[0127] The light-emitting element has a cathode 2316, an organic light-emitting layer 2315, and an anode 2314. The cathode 2316 is electrically connected to the power line 2308. The anode 2314 is electrically connected to the main terminal (here, the drain) of the driving transistor 2301. The organic light-emitting layer 2315 is located between the cathode 2316 and the anode 2314. A bank portion 2317 is arranged at the end of the anode 2314. The bank portion 2317 prevents the current flowing between the anode 2314 and the cathode 2316 from leaking to adjacent pixels.

[0128] Conductive patterns, electrodes of capacitor elements, and plugs are embedded in the insulating layer 14. The insulating layer 14 may be, for example, silicon oxide. Each of the conductive patterns may be a wiring layer. For example, as shown in FIG. 23, the conductive pattern may have wiring WR1, wiring WR2, and wiring WR3.

[0129] The capacitor 2305 has electrodes 2305a and 2305b, and the capacitor 2306 has electrodes 2306a and 2306b. Within the insulating layer 14, the electrodes 2305a and 2306a may be disposed on the same insulating layer. Alternatively, the electrodes 2305b and 2306b may be disposed on the same insulating layer. The electrodes 2305a and 2305b face each other across the insulating layer. The electrodes 2306a and 2306b face each other across the insulating layer. This forms a capacitor with an MIM (Metal-Insulator-Metal) structure.

[0130] The multiple plugs may include, for example, plug PL1, plug PL2, plug PL3, plug PL4, and plug PL5. The multiple plugs may all have the same thickness or may have different thicknesses, or some may have the same thickness and some may have different thicknesses.

[0131] The plug PL1 may connect the wiring WR1 to a terminal (any of the gate, source, and drain) of the transistor. The plug PL2 may connect the wiring WR2 to the wiring WR2. The lower electrode of the capacitor element (2305 or 2306) may be connected to the driving transistor 2301 via the plug PL3, the wiring WR2, the plug PL2, the wiring WR1, and the plug PL1. The upper electrode of the capacitor element (2305 or 2306) may be connected to the wiring WR3 via the plug PL5.

[0132] The wiring WR3 may be connected to a transistor (in FIG. 23, any one of the drive transistor, current control transistor, and reset transistor) via the plug PL4, wiring R2, plug PL2, wiring WR1, and plug PL1. The anode 2314 may be connected to the drain 2367 of the drive transistor 2301 via the plug PL6, wiring WR3, plug PL4, wiring WR2, plug PL2, wiring WR1, and plug PL1.

[0133] The plugs may be formed in a separate process from the wiring, or may be formed in the same process as the wiring disposed on the plugs. For example, the wiring WR2 and the plug PL2 may be formed in the same process and made of the same material. Also, the wiring WR3 and the plug PL4 may be formed in the same process and made of the same material. The wiring and the plugs may be formed using a metal such as copper, tungsten, aluminum, or titanium, or an alloy thereof.

[0134] In this way, by using a semiconductor substrate as the substrate and using MOS transistors as the transistors in each pixel, the transistors can be arranged more densely than when thin film transistors are used. Therefore, by configuring the display device of embodiment 1 to have a semiconductor substrate and MOS transistors as the transistors, the display device can be made to have higher definition, can be made smaller.

[0135] Fig. 24 is a cross-sectional view showing an example of a display device having an organic light-emitting element and a transistor connected to the organic light-emitting element. A transistor is an example of an active element. Here, an example in which the transistor is a thin-film transistor (TFT) is shown, but a MOSFET using a semiconductor substrate can also be used. By using a MOSFET, the transistors in each pixel can be arranged in a smaller area.

[0136] 24 shows an example of a pixel that is a component of the display device according to the first and second embodiments. Pixels 2410 are divided into 2410R, 2410G, and 2410B based on their light emission. The emitted light color may be distinguished by the wavelength of light emitted from the light-emitting layer, or light emitted from the pixel may be selectively transmitted or color-converted using a color filter or the like. Each pixel has a reflective electrode 242 serving as a first electrode on an interlayer insulating layer 241, an insulating layer 243 covering the edge of the reflective electrode 242, an organic compound layer 244 covering the second electrode and the insulating layer, a second electrode 245, a protective layer 246, and a color filter 247.

[0137] A transistor and a capacitor may be disposed below or inside the interlayer insulating layer 241. The transistor and the first electrode may be electrically connected via a contact hole or the like (not shown).

[0138] The insulating layer 243 is also called a bank or a pixel separation film. It covers the edges of the first electrode and is disposed to surround the first electrode. The part where the insulating layer is not disposed contacts the organic compound layer 244 and becomes the light-emitting region.

[0139] The organic compound layer 244 includes a hole injection layer 41 , a hole transport layer 42 , a first light-emitting layer 43 , a second light-emitting layer 44 , and an electron transport layer 45 .

[0140] The second electrode 245 may be a transparent electrode, a reflective electrode, or a semi-transparent electrode.

[0141] The protective layer 246 reduces the penetration of moisture into the organic compound layer. Although the protective layer is illustrated as a single layer, it may be multiple layers. Each layer may include an inorganic compound layer and an organic compound layer.

[0142] The color filters 247 are divided into 247R, 247G, and 247B depending on their colors. The color filters may be formed on a planarization film (not shown). A resin protective layer (not shown) may be provided on the color filters. The color filters may be formed on a protective layer 246. Alternatively, the color filters may be provided on an opposing substrate such as a glass substrate and then bonded thereto.

[0143] (Embodiment 3) 25 is a schematic diagram illustrating an example of a display component according to embodiment 3. A display device 2500 may have a touch panel 2503, a display panel 2505, a frame 2506, a circuit board 2507, and a battery 2508 between an upper cover 2501 and a lower cover 2509. Flexible printed circuits FPCs 2502 and 2504 are connected to the touch panel 2503 and the display panel 2505.

[0144] The display panel 2505 has the display device according to embodiment 1 or 2. A transistor is printed on a circuit board 2507. The battery 2508 may not be provided if the display component is not used in a portable device, or may be provided in a different location if the display component is used in a portable device.

[0145] The display component according to the third embodiment may have color filters having red, green, and blue colors, and the red, green, and blue colors may be arranged in a delta configuration in the color filters.

[0146] The display component according to the third embodiment may be used in a display unit of a mobile terminal. In this case, the display component may have both a display function and an operation function. Examples of the mobile terminal include a mobile phone such as a smartphone, a tablet, and a head-mounted display.

[0147] The display component according to the third embodiment may be used in a display unit of an imaging device having an optical unit with a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may have a display unit that displays information acquired by the imaging element. The display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed within a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0148] (Embodiment 4) 26A is a schematic diagram illustrating an example of an imaging device according to the fourth embodiment. The imaging device 2600 may include a viewfinder 2601, a rear display 2602, an operation unit 2603, and a housing 2604. The viewfinder 2601 may include the display device according to the first or second embodiment. In this case, the display device may display not only an image to be captured, but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject is moving, the possibility that the subject will be blocked by an obstruction, and the like.

[0149] Since the optimum timing for capturing an image is very short, it is better to display information as quickly as possible. Therefore, it is preferable to use a display device using organic light-emitting elements, because organic light-emitting elements have a fast response speed. When display speed is required, a display device using organic light-emitting elements can be used more preferably than a liquid crystal display device.

[0150] The imaging device 2600 has an optical section (not shown). The optical section has multiple lenses, which form an image on an imaging element housed in a housing 2604. The focus of the multiple lenses can be adjusted by adjusting their relative positions. This operation can also be performed automatically. The imaging device may also be called a photoelectric conversion device. Instead of sequentially capturing images, the photoelectric conversion device may include an imaging method that detects the difference from the previous image, or a method of cutting out an image from a constantly recorded image, etc.

[0151] (Embodiment 5) 26B is a schematic diagram illustrating an example of an electronic device according to embodiment 5. An electronic device 2610 has a display unit 2611, an operation unit 2612, and a housing 2613. The housing 2613 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit.

[0152] The display unit 2611 may have the display device according to embodiment 1 or 2. The operation unit 2612 may be a button or a touch panel type reaction unit. The operation unit may be a biometric recognition unit that recognizes a fingerprint to unlock the device, etc. An electronic device having a communication unit may also be called a communication device. The electronic device may further have a camera function by including a lens and an image sensor. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone and a laptop computer.

[0153] (Embodiment 6) FIG. 27A is a schematic diagram showing an example of an image display device (monitor) according to embodiment 6. The image display device 2700 in FIG. 27A is a television monitor, a PC monitor, or the like. The image display device 2700 has a frame 2701 and a display unit 2702 surrounded by the frame 2701. The display unit 27 02 may have the display device according to the first or second embodiment.

[0154] The image display device 2700 further includes a frame 2701 and a base 2703 that supports a display unit 2702. The base 2703 is not limited to the form shown in Fig. 27A. For example, the bottom side of the frame 2701 may also serve as the base.

[0155] The frame 2701 and the display unit 2702 may be curved. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0156] FIG. 27B is a schematic diagram illustrating another example of an image display device according to embodiment 6. The image display device 2710 in FIG. 27B is configured to be foldable, and is a so-called foldable image display device. The image display device 2710 has a first display unit 2711, a second display unit 2712, a housing 2713, and a bending point 2714. The first display unit 2711 and the second display unit 2712 may include the display devices according to embodiment 1 or 2. The first display unit 2711 and the second display unit 2712 may be a single, seamless image display device. The first display unit 2711 and the second display unit 2712 can be separated by the bending point. The first display unit 2711 and the second display unit 2712 may display different images, or the first and second display units may display a single image.

[0157] (Embodiment 7) 28A and 28B, an application example of the display device according to the first or second embodiment will be described. The display device can be applied to a system that can be worn as a wearable device, such as smart glasses, a head mounted display (HMD), or smart contact lenses. The image capture device and the display device used in such an application example can be an image capture device capable of photoelectrically converting visible light, and a display device capable of emitting visible light.

[0158] 28A illustrates glasses 2800 (smart glasses) according to one application example. An imaging device 2802 such as a CMOS sensor or SPAD is provided on the front side of a lens 2801 of the glasses 2800. Furthermore, a display device 2804 according to embodiment 1 or 2 is provided on the back side of the lens 2801.

[0159] The glasses 2800 further include a control device 2803. The control device 2803 functions as a power source that supplies power to the image capturing device 2802 and the display device 2804. The control device 2803 also controls the operations of the image capturing device 2802 and the display device 2804. The lens 2801 has an optical system formed therein for focusing light onto the image capturing device 2802.

[0160] 28B, glasses 2810 (smart glasses) according to one application example will be described. Glasses 2810 have a control device 2812. Control device 2812 is equipped with an imaging device corresponding to imaging device 2802 and a display device 2814 corresponding to display device 2804. An optical system for projecting light emitted by display device 2814 in control device 2812 is formed in lens 2811, and an image is projected onto lens 2811. Control device 2812 functions as a power source that supplies power to the imaging device and display device 2814, and controls the operations of the imaging device and display device 2814.

[0161] The control device 2812 may have a gaze detection unit that detects the gaze of the wearer. Infrared rays may be used to detect the gaze. The infrared light emitting unit emits infrared light toward the eyeball of the user gazing at the displayed image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By having a reduction means for reducing light from the infrared light emitting unit to the display unit in a planar view, degradation of image quality is reduced.

[0162] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using the image of the eyeball. As an example, a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea can be used.

[0163] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0164] The glasses 2810 may have an imaging device with a light receiving element, and may control the image displayed on the display device based on information on the user's line of sight from the imaging device.

[0165] Specifically, the display device 2814 determines a first display area where the user gazes and a second display area other than the first display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the glasses 2810, or may be determined by an external control device and received. In the display area of ​​the display device 2814, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than that of the first field of view area.

[0166] The display area includes a first display area and a second display area different from the first display area, and a high-priority area is determined from the first display area and the second display area based on line-of-sight information. The first and second view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0167] Note that AI (Artificial Intelligence) may be used to determine the first display area and the area with high priority. The AI ​​may be a model configured to estimate the angle of gaze and the distance to an object in the line of sight from the image of the eyeball, using as training data an image of the eyeball and the direction in which the eyeball in the image was actually looking. The AI ​​program may be included in the display device, the imaging device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0168] When display control is performed based on visual recognition detection, the smart glasses can be preferably applied to smart glasses that further include an imaging device for capturing images of the outside world. The smart glasses can display captured external information in real time.

[0169] (Embodiment 8) FIG. 29A is a diagram showing the configuration of an HMD (head-mounted display) 2901 as an image observation device according to the eighth embodiment. The HMD 2901 is worn on the head of an observer. Reference numeral 2902 denotes the observer's right eye, and reference numeral 2903 denotes the observer's left eye. Display lenses 2904 and 2905 constitute an eyepiece optical system for the right eye OR1, and display lenses 2906 and 2907 constitute an eyepiece optical system for the left eye OL1. Each eyepiece optical system is a coaxial optical system composed of multiple (two) display lenses. The observer's right eye 2902 is positioned at the exit pupil ER1 of the eyepiece optical system for the right eye OR1, and the observer's left eye 2903 is positioned at the exit pupil EL1 of the eyepiece optical system for the left eye OL1. The exit pupil ER1 is located at a distance E1 from the eyepiece optical system for the right eye OR1. Similarly, the exit pupil EL1 is located at a distance E1 from the eyepiece optical system for the left eye OL1. The surface of the eyepiece optical system OR1 for the right eye (the surface on the right eye 2902 side) and the surface of the eyepiece optical system OL1 for the left eye (the surface on the left eye 2903 side) are provided with optical lenses for lens protection, light collection, etc. A film 2914 is provided.

[0170] Reference numerals 2908 and 2909 denote display devices for the right and left eyes, respectively. These display devices may be the display devices according to the first or second embodiment. FIG. 29B is a diagram showing the appearance of an HMD 2901 and a personal computer 2950 connected thereto. Each display device displays a display image (original image) corresponding to an image signal output from the personal computer 2950. In this embodiment, the display devices are connected by wire, but they may also be connected wirelessly. Furthermore, the HMD 2901 may be a device that incorporates an image processing device and operates as a stand-alone device.

[0171] The eyepiece optical systems OR1 and OL1 guide light from the display devices 2908 and 2909 to the exit pupils ER1 and EL1, respectively, to project enlarged virtual images of the displayed images onto the observer's right eye 2902 and left eye 2903. This allows the observer to observe the (virtual images of) the displayed images displayed on the display devices 2908 and 2909 through the eyepiece optical systems OR1 and OL1.

[0172] Although not shown, the HMD 2901 may have a control device. The control device functions as a power source that supplies power to the display devices 2908 and 2909, and also controls the operations of the display devices 2908 and 2909.

[0173] The control device may have a gaze detection unit that detects the gaze of the wearer. The gaze detection may use infrared rays. The infrared light emitting unit emits infrared light toward the eyeball of the user gazing at the displayed image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, thereby obtaining an image of the eyeball. By having a reduction means that reduces light from the infrared light emitting unit to the display unit in a planar view, degradation of image quality is reduced.

[0174] The gaze of the user relative to the displayed image is detected from an image of the eyeball obtained by capturing infrared light. Any known method can be used for gaze detection using the image of the eyeball. As an example, a gaze detection method based on the Purkinje image formed by reflection of irradiated light on the cornea can be used.

[0175] More specifically, gaze detection processing is performed based on the pupil-corneal reflex method, which calculates a gaze vector representing the direction (rotation angle) of the eyeball based on the pupil image and Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0176] Specifically, the display devices 2908 and 2909 determine a first display area where the user gazes and a second display area other than the first display area based on the line-of-sight information. The first and second display areas may be determined by the control device, or may be determined by an external control device and received. In the display areas of the display devices 2908 and 2909, the display resolution of the first display area may be controlled to be higher than the display resolution of the second display area. In other words, the resolution of the second display area may be lower than that of the first field of view area.

[0177] The display area includes a first display area and a second display area different from the first display area, and a high-priority area is determined from the first display area and the second display area based on line-of-sight information. The first and second view areas may be determined by a control device of the display device, or may be determined by an external control device and received. The resolution of the high-priority area may be controlled to be higher than the resolution of areas other than the high-priority area. In other words, the resolution of an area with a relatively low priority may be lowered.

[0178] AI may be used to determine the first display area and areas with high priority. The AI ​​uses the image of the eyeball and the direction in which the eyeball in the image was actually looking as training data, and The AI ​​program may be a model configured to estimate the angle of the line of sight from the camera and the distance to an object in the line of sight. The AI ​​program may be included in the display device, the imaging device, or an external device. If included in the external device, it is transmitted to the display device via communication.

[0179] In this way, the display device according to the first or second embodiment can be applied to various display components, imaging devices, electronic devices, and image display devices according to this embodiment.

[0180] The embodiments and modifications described above can be appropriately modified or combined without departing from the scope of the technical concept of the present invention. The disclosure of this specification includes not only what is described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto.

[0181] The disclosure of the above embodiment includes the following configurations. (Configuration 1) a display area including a plurality of pixels arranged in a matrix, each pixel including a light-emitting element, a light-emitting control transistor that causes the light-emitting element to emit light, a drive transistor that drives the light-emitting element, and a write control transistor that writes a signal voltage into the drive transistor; a first selection line provided for each row of the plurality of pixels and connected to the write control transistors of the pixels arranged in the row direction; a second selection line provided for each row of the plurality of pixels and connected to the light emission control transistors of the pixels arranged in the row direction; a first scanning circuit that sequentially scans the plurality of first selection lines; a second scanning circuit that sequentially scans the second selection lines; and The display area displays image data, The image data is divided into a plurality of areas with different resolutions, and the plurality of areas are arranged in a column direction so as to include at least two or more areas; a scanning speed by the first scanning circuit differs for each of the regions arranged in the column direction; The scanning speed by the second scanning circuit is equal to or greater than the minimum speed and less than the maximum speed of the scanning speed by the first scanning circuit. A display device characterized by: (Configuration 2) 2. The display device according to configuration 1, wherein the speed of scanning by the second scanning circuit across the plurality of regions is constant. (Configuration 3) 3. The display device according to configuration 1 or 2, wherein one frame period for displaying the image data in the display area is determined according to the time required for one scan of the plurality of regions by the first scanning circuit. (Configuration 4) 3. The display device according to configuration 1 or 2, wherein one frame period for displaying the image data in the display area is determined according to the time required for one scan of the plurality of regions by the second scanning circuit. (Configuration 5) The display device according to any one of configurations 1 to 4, characterized in that the time required for one scan of the plurality of regions by the first scanning circuit is the same as the time required for one scan of the plurality of regions by the second scanning circuit. (Configuration 6) 6. The display device according to any one of configurations 1 to 5, wherein the plurality of pixels in the display area are uniform in size. (Configuration 7) 6. The display device according to any one of configurations 1 to 5, wherein the size of the plurality of pixels varies for each of the resolution regions of the plurality of regions. (Configuration 8) The display device according to configuration 7, wherein scanning by the second scanning circuit is performed so that the amount of light emitted by the pixels in a region having a relatively high resolution among the plurality of regions is determined according to the size of the pixels in a region having a relatively low resolution among the plurality of regions. (Configuration 9) The display device according to configuration 7, wherein scanning by the second scanning circuit is performed so that the amount of light emitted by the pixels in a region having a relatively low resolution among the plurality of regions is determined according to the size of the pixels in a region having a relatively high resolution among the plurality of regions. (Configuration 10) an optical unit; an imaging element that receives light that has passed through the optical unit; a display device that displays an image captured by the imaging element; and The display device is a display device according to any one of configurations 1 to 9. A photoelectric conversion device characterized by: (Configuration 11) The display device according to any one of configurations 1 to 9, a housing in which the display device is provided; a communication unit provided in the housing for communicating with the outside; An electronic device comprising: [Explanation of symbols]

[0182] 1: display device, 100: pixel array, 101: pixel drive circuit, 102: write selection line, 104: light emission selection line, 201: write scanning circuit, 202: light emission scanning circuit, 201a, 201b, 202a, 202b: shift register circuits, 204: output control logic gate circuit, 300: signal output circuit, 400: control circuit, 502: pixel drive circuit that emits light with twice the amount of light emitted by unit pixel drive circuit 101, 503: pixel drive circuit that emits light with twice the amount of light emitted by unit pixel drive circuit 101, 504: pixel drive circuit that emits light with four times the amount of light emitted by unit pixel drive circuit 101

Claims

1. a display area including a plurality of pixels arranged in a matrix, each pixel including a light-emitting element, a write control transistor that writes a signal voltage to the light-emitting element, a light-emitting control transistor that causes the light-emitting element to emit light, and a drive transistor that drives the light-emitting element; a first selection line provided for each row of the plurality of pixels and connected to the write control transistors of the pixels arranged in the row direction; a second selection line provided for each row of the plurality of pixels and connected to the light emission control transistors of the pixels arranged in the row direction; a first scanning circuit that sequentially scans the plurality of first selection lines; a second scanning circuit that sequentially scans the second selection lines; and The display area displays image data, The image data is divided into a plurality of areas with different resolutions, and the plurality of areas are arranged in a column direction so as to include at least two or more areas; a scanning speed by the first scanning circuit differs for each of the regions arranged in the column direction; The scanning speed by the second scanning circuit is equal to or greater than the minimum speed and less than the maximum speed of the scanning speed by the first scanning circuit. A display device characterized by:

2. 2. The display device according to claim 1, wherein the speed of scanning by the second scanning circuit across the plurality of regions is constant.

3. 2. The display device according to claim 1, wherein one frame period for displaying the image data in the display area is determined in accordance with the time required for one scan of the plurality of regions by the first scanning circuit.

4. 2. The display device according to claim 1, wherein one frame period for displaying the image data in the display area is determined according to the time required for one scan of the plurality of regions by the second scanning circuit.

5. 2. The display device according to claim 1, wherein the time required for one scan of the plurality of regions by the first scanning circuit is the same as the time required for one scan of the plurality of regions by the second scanning circuit.

6. 2. The display device according to claim 1, wherein the plurality of pixels in the display area are uniform in size.

7. 2. The display device according to claim 1, wherein the size of the plurality of pixels differs for each of the plurality of resolution regions.

8. 8. The display device according to claim 7, wherein scanning by the second scanning circuit is performed so that the amount of light emitted by the pixels in a region having a relatively high resolution among the plurality of regions is determined according to the size of the pixels in a region having a relatively low resolution among the plurality of regions.

9. 8. The display device according to claim 7, wherein scanning by the second scanning circuit is performed so that the amount of light emitted by the pixels in the area having a relatively low resolution among the plurality of areas is determined according to the size of the pixels in the area having a relatively high resolution among the plurality of areas. Place.

10. an optical unit; an imaging element that receives light that has passed through the optical unit; a display device that displays an image captured by the imaging element; and The display device is a display device according to any one of claims 1 to 9. A photoelectric conversion device characterized by:

11. A display device according to any one of claims 1 to 9; a housing in which the display device is provided; a communication unit provided in the housing for communicating with the outside; An electronic device comprising:

Images