Memory controller and memory system performing write disturb management

Abstract

In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes a memory cell. A write count for a first one of the memory cells is determined. In response to a write count of a first memory cell reaching one of the preset values, a flipped bit count (FBC) of a second of the memory cells that is physically adjacent to the first memory cell is obtained. In response to the FBC of the second memory cell exceeding the threshold, the second memory cell is refreshed.

Description

Technical Field

[0001] The present disclosure relates to a memory device and an operating method of the memory device. Background Art

[0002] Storage class memory (SCM) is a type of non-volatile memory that bridges the gap between traditional volatile memory (e.g., dynamic random-access memory (DRAM)) and non-volatile storage devices (e.g., NAND flash or hard drives). SCM combines the advantages of both types, providing low latency, high-speed data access similar to DRAM, as well as the persistence and higher capacity typically found in non-volatile storage devices. SCM is increasingly being adopted in data centers and other high-performance computing environments, where it helps reduce latency, improve overall system efficiency, and provide more efficient data management solutions. Summary of the invention

[0003] In one aspect, a method for operating a nonvolatile memory device is provided. The nonvolatile memory device includes memory cells. A write count of a first memory cell in the memory cells is determined. In response to the write count of the first memory cell reaching a preset value among preset values, a flipped bit count (FBC) of a second memory cell in the memory cells that is physically adjacent to the first memory cell is obtained. In response to the FBC of the second memory cell exceeding a threshold, the second memory cell is refreshed.

[0004] In some implementations, each of the memory cells includes a storage cell coupled to a corresponding one of the bit lines.

[0005] In some implementations, the storage unit includes a phase-change memory (PCM) unit.

[0006] In some implementations, to determine the write count for the first memory cell, a number of write operations applied to the first codeword is tracked.In some implementations, the first codeword includes a first page corresponding to the first memory cell.

[0007] In some implementations, a mapping table between a physical address and a logical address is stored for each of the memory cells. In some implementations, to determine a write count for a first memory cell, a logical address of the first memory cell is determined based on the first page, and a physical address of the first memory cell is determined based on the logical address of the first memory cell and the mapping table.

[0008] In some implementations, to obtain the FBC of the second memory cell, a second memory cell physically adjacent to the first memory cell is determined based on a physical address of the first memory cell and a physical address of the second memory cell.

[0009] In some implementations, to obtain the FBC of the second memory cell, a second page corresponding to the second memory cell is read, and a number of flipped bits in the second page is determined based on the reading and a second codeword including the second page.

[0010] In some implementations, to obtain the FBC of the second memory cell, a logical address of the second memory cell is determined based on the physical address of the second memory cell and a mapping table, and a second page is determined based on the logical address of the second memory cell.

[0011] In some implementations, to refresh the second memory cell, the second memory cell is rewritten with the data stored in the second memory cell.

[0012] In some implementations, the first memory cell and the second memory cell are coupled to the same word line.

[0013] In another aspect, a memory system includes a nonvolatile memory device and a memory controller coupled to the nonvolatile memory device. The nonvolatile memory device includes memory cells. The memory controller is configured to determine a write count of a first memory cell in the memory cells. The memory controller is further configured to obtain a FBC of a second memory cell in the memory cells that is physically adjacent to the first memory cell in response to the write count of the first memory cell reaching one of the preset values. The memory controller is further configured to refresh the second memory cell in response to the FBC of the second memory cell exceeding a threshold.

[0014] In some implementations, the nonvolatile memory device further includes bit lines. In some implementations, each of the memory cells includes a storage cell coupled to a corresponding one of the bit lines.

[0015] In some implementations, the storage cells include PCM cells.

[0016] In some implementations, to determine the write count of the first memory cell, the memory controller is configured to: track a number of write operations applied to the first codeword. In some implementations, the first codeword includes a first page corresponding to the first memory cell.

[0017] In some implementations, the memory system further includes a volatile memory configured to store a mapping table between a physical address and a logical address for each of the memory cells. In some implementations, to determine the write count of the first memory cell, the memory controller is further configured to determine a logical address of the first memory cell based on the first page, and determine a physical address of the first memory cell based on the logical address of the first memory cell and the mapping table.

[0018] In some implementations, to obtain the FBC of the second memory cell, the memory controller is configured to determine a second memory cell that is physically adjacent to the first memory cell based on a physical address of the first memory cell and a physical address of the second memory cell.

[0019] In some implementations, to obtain the FBC of the second memory cell, the memory controller is further configured to: read a second page corresponding to the second memory cell, and determine a number of flipped bits in the second page based on reading and including a second codeword of the second page.

[0020] In some implementations, to obtain the FBC of the second memory unit, the memory controller is further configured to: determine a logical address of the second memory unit based on the physical address of the second memory unit and a mapping table, and determine the second page based on the logical address of the second memory unit.

[0021] In some implementations, to refresh the second memory cell, the memory controller is configured to rewrite the second memory cell with the data stored in the second memory cell.

[0022] In some implementations, the nonvolatile memory device further includes a word line. In some implementations, the first memory cell and the second memory cell are coupled to the same one of the word lines.

[0023] In another aspect, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a memory controller, cause the memory controller to perform the following operations: determine a write count of a first memory cell in a non-volatile memory device; in response to the write count of the first memory cell reaching a preset value among preset values, obtain an FBC of a second memory cell in the memory cells that is physically adjacent to the first memory cell; and in response to the FBC of the second memory cell exceeding a threshold, refresh the second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0025] Figure 1 A block diagram of a system including a memory system according to some aspects of the present disclosure is shown.

[0026] Figure 2 A schematic diagram of an SCM device according to some aspects of the present disclosure is shown.

[0027] Figure 3 A perspective view of a phase change memory (PCM) cell array is shown in accordance with some aspects of the present disclosure.

[0028] Figure 4 A detailed diagram of an SCM device according to some aspects of the present disclosure is shown.

[0029] Figure 5 A write disturb of a PCM cell due to a reset process in a write operation is shown according to some aspects of the present disclosure.

[0030] Figure 6 An example of write disturb and refresh of a PCM cell according to some aspects of the present disclosure is shown.

[0031] Figure 7 A detailed diagram of a memory system including a memory controller that performs periodic scans to manage write disturbs according to some aspects of the present disclosure is shown.

[0032] Figure 8 A detailed diagram of a memory controller is shown in accordance with some aspects of the present disclosure.

[0033] Fig. 9 Codewords according to some aspects of the present disclosure are shown.

[0034] Fig.10A mapping table between logical addresses and physical addresses of memory cells according to some aspects of the present disclosure is shown.

[0035] Fig.11 A scheme for determining logical addresses of memory cells on a page basis according to some aspects of the present disclosure is shown.

[0036] Fig.12 A flow chart of a method for operating a non-volatile memory device according to some aspects of the present disclosure is shown.

[0037] Fig.13 A flow chart of a method for performing periodic scanning to manage write disturb according to some aspects of the present disclosure is shown.

[0038] Fig.14 A flow chart of a method for converting between a page of memory cells and a physical address is shown in accordance with some aspects of the present disclosure.

[0039] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] Typically, a term can be understood at least in part from its use in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, again, terms such as "a", "an" or "the" can be understood to convey singular usage or to convey plural usage, which depends at least in part on the context. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but on the contrary, additional factors that are not necessarily explicitly described can be allowed to exist, again, this depends at least in part on the context.

[0041] Phase change memory (PCM) is a promising nonvolatile memory technology that can be used as storage class memory (SCM). PCM uses chalcogenide materials (e.g., compounds containing germanium (Ge), antimony (Sb), and tellurium (Te)) that can be reversibly switched between crystalline and amorphous phases. These phases exhibit different resistance levels that represent binary data. The phase transition is induced by applying heat to the memory cell, which raises the temperature of the chalcogenide material above a certain threshold.

[0042] The chalcogenide material in the PCM can be transformed into a crystalline phase by a set process, in which the chalcogenide material is heated to a temperature above its crystallization temperature but below its melting temperature. In other words, the set process changes the phase of the material from an amorphous state to a crystalline state, which results in a lower resistance state. Conversely, the chalcogenide material in the PCM can be transformed into an amorphous phase by a reset process, in which the chalcogenide material is rapidly heated to a temperature above its melting temperature, causing the material to melt. The temperature is then rapidly reduced, causing the material to rapidly cool and transforming it into an amorphous state, which corresponds to a higher resistance state. The reset process generally requires more energy and time than the set process, thereby generating more heat than the set process.

[0043] However, the heat generated during the write operation, especially the heat generated during the reset process of writing the bit "0" to the PCM cell, may have a thermal effect (also called thermal crosstalk) on the adjacent PCM cells, thereby causing so-called write interference to the adjacent PCM cells, for example, by causing the phase of the chalcogenide of the adjacent PCM cell to change from an amorphous state to a crystalline state (flipping the bit from "0" to "1"). In other words, the heat generated during the write operation can spread to nearby PCM cells, thereby causing undesirable phase transitions in these cells and may cause unintentional data modification in the adjacent PCM cells. Based on experiments, continuous write operations using the reset process may cause data corruption due to write interference and may even eventually damage the adjacent PCM cells (making the PCM cells uncorrectable).

[0044] In order to solve one or more of the above problems, the present disclosure introduces a scheme for managing write disturbance of SCM products such as PCM devices using periodic scanning based on the write count of each memory cell (e.g., corresponding to a codeword). Write disturbance scanning can be periodically performed on adjacent memory cells (e.g., cells coupled to adjacent bit lines) according to a scanning interval based on an increase in the write count for each memory cell. When the write disturbance scan shows that the adjacent memory cell is at risk of data corruption or even damage, the risky memory cell can be refreshed to mitigate the risk, thereby improving the life of the memory device. In some implementations, when the flip bit count (FBC, also known as the fail bit count) of the adjacent memory cell exceeds a preset threshold, the adjacent memory cell is rewritten with the same data stored in the adjacent memory cell to eliminate the accumulated write disturbance effect. In some implementations, various conversions between the logical address and the physical address of the memory cell and the operation unit are performed to enable the memory controller to directly manage write disturbance.

[0045] Figure 1A block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to the memory system 102 or receive data (also referred to as user data or host data) from the memory system 102. The memory system 100 may be a storage product that integrates a memory controller 106 and one or more memory devices such as an SCM system.

[0046] The memory device 104 may be any memory device disclosed in the present disclosure, including a non-volatile memory device, such as an SCM device. For example, the non-volatile memory device may include a PCM device. In some implementations, the memory device 104 also includes one or more volatile memory devices, such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device.

[0047] According to some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment, where a solid-state disk (SSD) or an embedded multimedia card (eMMC) is used as a data storage device for mobile devices (e.g., smart phones, tablet computers, laptop computers, etc.) and enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, program / write and / or erase operations. The memory controller 106 can also be configured to manage various functions regarding data stored in the memory device 104 or data to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical (L2P) address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. Any other suitable functions (e.g., formatting the memory device 104) may also be performed by the memory controller 106. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a particular communication protocol.For example, the memory controller 106 can communicate with an external device through at least one of various interface protocols (for example, a non-volatile memory express (NVMe) protocol, an NVMe-over-fabrics (NVMe-oF) protocol, a PCI-express (PCI-E) protocol, a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, etc.).

[0048] Consistent with the scope of the present disclosure and disclosed in detail below, the memory controller 106 may be configured to determine a write count of each memory cell in the non-volatile memory device of the memory device 104, and in response to the write count of the memory cell reaching one of the preset values, obtain the FBC of the neighboring memory cell. The memory controller 106 may also be configured to: in response to the FBC of the neighboring memory cell exceeding a threshold, refresh the neighboring memory cell to mitigate write disturbance to the neighboring memory cell.

[0049] Figure 2 A schematic diagram of an SCM device 200 according to some aspects of the present disclosure is shown. The SCM device 200 may be Figure 12 is an example of a memory device 104 in FIG. The SCM device 200 may include an SCM cell array 202 and a peripheral circuit 204 coupled to the SCM cell array 202. The SCM cell array 202 may include a word line (WL) 206, a bit line (BL) 208, and an SCM cell 210 at a cross point between the word line 206 and the bit line 208. In some implementations, each SCM cell 210 includes an SCM element 212 connected in series with an access device 214 (also referred to as a selector). The SCM element 212 may be configured to persistently store binary data (e.g., 0 and 1) by maintaining a continuous analog value (e.g., voltage or charge), for example, even when power is interrupted or turned off. According to some implementations, the SCM element 212 includes, but is not limited to, a PCM element, a resistive memory element, a magnetoresistive memory element, a ferroelectric memory element, a spin-transfer torque (STT) memory element, and the like. The access device 214 may be configured to control the access of the peripheral circuit 204 to the corresponding SCM element 212. According to some implementations, the access device 214 includes, but is not limited to, a transistor, a diode, an ovonic threshold switch (OTS), a mixed ionic-electronic conductor (MIEC), a conductive oxide tunnel barrier, etc.

[0050] like Figure 2 As shown, the SCM cell array 202 may include an array of SCM cells 210 arranged in rows and columns. The rows of the SCM cells 210 may be respectively coupled to word lines 206, and the columns of the SCM cells 210 may be respectively coupled to bit lines 208. The peripheral circuit 204 may be coupled to the SCM cell array 202 via the bit lines 208 and the word lines 206.

[0051] Peripheral circuits 204 may include any suitable analog, digital, and mixed signal circuits for facilitating operation of SCM cell array 202 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from SCM cells 210 via bit lines 208 and word lines 206. Peripheral circuits 204 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0052] It should be understood that, depending on the underlying memory technology forming the SCM element 212, the SCM device 200 may include any suitable type of SCM device, such as a PCM device, a resistive RAM (ReRAM) device, a magnetoresistive RAM (MRAM) device, a ferroelectric RAM (FeRAM) device, an STT-RAM device, etc. It should also be understood that the SCM device 200 is an example of a non-volatile memory device and can be extended to any other suitable non-volatile memory device (including a non-volatile memory (NVM) cell array having a non-volatile memory (NVM) element and an access device).

[0053] Figure 3 A perspective view of a PCM cell array 300 is shown according to some aspects of the present disclosure. The PCM cell array 300 may be Figure 2 The PCM cell array 300 may be formed in a three-dimensional (3D) vertical chain cell type architecture, wherein an access device 310 and a PCM cell 308 forming a PCM cell 306 are connected in series and located at the intersection of a word line 302 and a bit line 304, such as Figure 3 Note that the x-axis and y-axis are contained in Figure 3 The two orthogonal directions in the wafer plane are shown in FIG. The x direction is the word line direction, and the y direction is the bit line direction. Note that the z axis is also included in Figure 3 300 to further illustrate the spatial relationship of the components in the PCM cell array 300. The substrate (not shown) of the PCM cell array 300 includes two side surfaces extending laterally in the xy plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite to the front side of the wafer. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate is located in the lowest plane of the semiconductor device in the z-direction, whether one component (e.g., a layer or device) of a semiconductor device (e.g., PCM cell array 300) is "on", "above" or "below" another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the z-direction (a vertical direction perpendicular to the xy plane). The same concepts used to describe spatial relationships are applied throughout this disclosure.

[0054] In some implementations, the PCM cell array 300 includes parallel word lines 302 and parallel bit lines 304 in different planes in a vertical direction. According to some implementations, each bit line 304 extends laterally along a bit line direction in a plan view (parallel to the wafer plane), and each word line 302 extends laterally in the word line direction in a plan view. Therefore, each word line 302 can be perpendicular to each bit line 304.

[0055] like Figure 3 As shown, according to some implementations, the PCM cell array 300 includes a plurality of PCM cells 306, each of which is disposed at the intersection of a bit line 304 and a corresponding word line 302. Each PCM cell 306 may have a vertical column shape. In some implementations, each PCM cell 306 includes a vertically stacked PCM element 308 and an access device 310. Each PCM cell 306 may store data that may be written or read by changing a voltage applied to a corresponding access device 310. Each PCM cell 306 may be individually accessed by a current applied through a top conductor and a bottom conductor (e.g., a corresponding word line 302 and a bit line 304) in contact with each PCM cell 306.

[0056] In some implementations, the PCM cell 308 is a chain cell type PCM cell, which includes polysilicon transistors and phase-phase layers connected in parallel. The polysilicon transistors and phase-phase layers can be formed by gate oxide, channel polysilicon, and phase change materials formed on the hole side of the stacked gate 312. In some implementations, the access device 310 is a polysilicon diode. In a write operation, a turn-off voltage can be applied to the selected gate 312, and a positive turn-on voltage can be applied to the unselected gate 312. When a set / reset pulse voltage is applied to the drain, a current can flow through the phase change layer at the selected gate 312, and the temperature can be increased by Joule heating, resulting in a set / reset state. In the same way, by applying a voltage suitable for a read operation to the drain, the resistance of the phase change layer at the selected gate 312 can be determined.

[0057] It should be understood that the PCM cell array 300 can be formed in any other suitable two-dimensional (2D) or 3D architecture (e.g., a lateral chain cell type architecture or a 3D cross-point (XPoint) architecture). It should also be understood that the PCM element 308 can include any other suitable PCM element, such as a phase-phase layer vertically stacked between two carbon electrodes. It should also be understood that the access device 310 can include any other suitable access device, such as an OTS selector.

[0058] The SCM device can be divided into multiple physical modules, each of which includes an SCM cell array and peripheral circuits for the corresponding SCM cell array to achieve parallel processing of the SCM device. The physical module can be a die and / or a memory bank. For example, Figure 4 A detailed diagram of an SCM device 400 is shown according to some aspects of the present disclosure. The SCM device 400 may be Figure 2 An example of an SCM device 200 in FIG. Figure 4As shown, the SCM device 400 can be divided into multiple memory banks 402 (e.g., 0, 1, 2, and 3), each memory bank 402 including an SCM cell array 404. Although not shown, it should be understood that in some examples, multiple memory banks 402 can be on the same die, and the SCM device 400 can include multiple dies, each die including multiple memory banks 402.

[0059] In some implementations, each memory bank 402 further includes peripheral circuits for the corresponding SCM cell array 404, including a data buffer / sense amplifier 406, a column decoder / bit line driver 408, a row decoder / word line driver 410, a control logic 412, a register 414, an interface (I / F) 416, and a data bus 418. It is understood that in some examples, other peripheral circuits not shown in the SCM cell array 404 may also be included. Figure 4 Additional peripheral circuits are shown in the , for example, voltage generators, charge pumps, and any suitable type of bus.

[0060] The data buffer / sense amplifier 406 may be configured to sense (read) data from the SCM cell array 404 and program (write) data to the SCM cell array 404 according to control signals from the control logic 412. For example, the sense amplifier may detect small voltage or current changes in the SCM cell array 404 during a read operation, while the data buffer may temporarily store data being read from or written to the SCM cell array 404.

[0061] The column decoder / bit line driver 408 may be configured to be controlled by an address signal from the control logic 412 and to select / deselect one or more columns of SCM cells in the SCM cell array 404 by applying a bit line voltage to the corresponding bit line. The column decoder / bit line driver 408 may also be configured to drive the selected bit line. The row decoder / word line driver 410 may be configured to be controlled by an address signal from the control logic 412 and to select / deselect one or more rows of SCM cells in the SCM cell array 404 by applying a word line voltage to the corresponding word line. The row decoder / word line driver 410 may also be configured to drive the selected word line.

[0062] The control logic 412 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The control logic 412 may include fixed logic units, such as logic gates, multiplexers, flip-flops, state machines, or discrete hardware circuits that perform given logic functions known when the device is manufactured. In some implementations, the control logic 412 is implemented by a microprocessor, a microcontroller (also referred to as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gating logic, discrete hardware circuits, and other suitable hardware, firmware, and / or software configured to perform the various functions described herein. It should be understood that although Figure 4 Each memory bank 402 is shown to include separate control logic 412 , but in some examples, multiple memory banks 402 may share the same control logic 412 .

[0063] Registers 414 may be coupled to control logic 412 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address to control the operation of each peripheral circuit. Interface 416 may be coupled to control logic 412 and used as a control buffer to transfer data from a memory controller (not shown, for example, Figure 1 106) and / or a host (not shown, e.g., Figure 1 The interface 416 may also be coupled to the data buffer / sense amplifier 406 via the data bus 418 and used as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the SCM cell array 404.

[0064] Figure 5 1 shows a write disturbance of a PCM cell due to a reset process in a write operation according to some aspects of the present disclosure. Figure 5As shown, PCM cells may be formed at the intersections between word lines WL and bit lines BL, each of which includes one or more PCM cells. As described in detail above, when the reset process in a write operation is repeatedly applied to a PCM cell at the intersection between WLn and BLm (referred to herein as an "aggressor" 502) to write a bit "0" into the attacker 502, the heat introduced by the reset process may have a thermal crosstalk effect on other PCM cells (particularly PCM cells (adjacent PCM cells) coupled to bit lines BLm+1, BLm-1 that are physically adjacent to the attacker 502 and located on the same word line WLn as the attacker 502). Those PCM cells (e.g., PCM cells in a reset state "0") that have the most significant write interference due to thermal crosstalk from the attacker 502 are referred to herein as "victims" 504. Figure 5 As shown, write disturbances to other PCM cells 506 can be neglected due to heat dissipation because of the increased distance of these PCM cells 506 from the aggressor 502 and / or the relatively small dimensions of the bit lines compared to the word lines. In some implementations, the victim 504 includes only PCM cells that are in reset state "0" and are physically adjacent to the aggressor 502 on the same word line WLn.

[0065] On the other hand, by resetting the victim 504 (e.g., by rewriting the victim 504 with the same data stored on the victim 504 again), the write disturbance accumulated on the victim 504 can be removed before causing data corruption or damage to the victim 504. That is, the accumulated effect of thermal crosstalk caused by the repeated reset process in the write operation to the aggressor 502 can be cleared by reading the data stored on the victim 504 and writing the data back to the victim 504 again. For example, Figure 6 An example of write disturb and refresh of a PCM cell according to some aspects of the present disclosure is shown. Figure 6As shown, assume that the number of write operations (write count, WC) on the attacker 502 (A) and the victim 504 (V) may be 100 at the beginning (A WC = 100, V WC = 100). Then, the attacker 502 may be written to 100 times again, thereby increasing its write count to 200; at the same time, the victim 504 may not be written to at all during this period, thereby maintaining the same write count of 100 (A WC = 200, V WC = 100). That is, the victim 504 may have been disturbed 100 times by writing to the attacker 502. If the victim 504 is subsequently written to once (V WC = 101), the cumulative write disturb effect on the victim 504 may be reset to zero. Then, the attacker 502 may be written to 50 times again, thereby increasing its write count to 250; meanwhile, the victim 504 may not be written to at all during this period, thereby maintaining the same write count of 101 (A WC=250, V WC=101). That is, the victim 504 may have been disturbed 50 times again by writing to the attacker 502 after the reset. In some implementations, in the write operation, only the write count for the reset process is increased, and the write count for the set process is not increased.

[0066] like Figure 5 and Figure 6 As shown, write disturbances from an aggressor 502 to a victim 504 can be managed by refreshing the victim 504 before the write count of the aggressor 502 reaches a level that will cause data corruption or even damage to the victim 504. In practice, it is not feasible to record the write disturbance effects on each PCM cell (e.g., the increment of the write count of the aggressor 502 since the last write to each victim 504). In addition, thermal crosstalk occurs between physically adjacent PCM cells, and the memory controller that manages the write disturbances only knows the logical index of the operating unit (e.g., page number, codeword number, etc.) that may not directly reflect the physical location.

[0067] Consistent with the scope of the present disclosure, a write disturbance management scheme is disclosed herein, which can be implemented by the memory controller disclosed herein without recording the write disturbance effects on each memory cell. Write disturbance scans can be periodically performed on adjacent memory cells based on a scan interval based on an increase in the write count for each memory cell. When the write disturbance scan shows that the adjacent memory cell is at risk of data corruption or even damage, the at-risk memory cell can be refreshed to mitigate the risk, thereby improving the life of the memory device. In some implementations, when the FBC of an adjacent memory cell exceeds a preset threshold, the adjacent memory cell is rewritten with the same data stored in the adjacent memory cell to eliminate the accumulated write disturbance effects. In some implementations, various conversions between the logical addresses and physical addresses of the memory cells and the operating units are performed to enable the memory controller to directly manage write disturbances.

[0068] Figure 7 Detailed diagram of a memory system 700 including a memory controller 702 that performs periodic scans to manage write disturbs according to some aspects of the present disclosure. The memory system 700 may be Figure 1 An example of a memory system 102 in FIG. 1 , and the memory controller 702 may be Figure 1 The memory system 700 may also include one or more non-volatile memory devices 704 and one or more volatile memory devices 706. The non-volatile memory devices 704 and the volatile memory devices 706 may be Figure 1 In some implementations, the non-volatile memory device 704 includes an SCM device, such as the SCM devices 200 and 400 or any SCM device disclosed herein. In one example, the SCM device may include a PCM device. In some implementations, the volatile memory device 706 includes a DRAM or SRAM. It is understood that although Figure 7 The volatile memory device 706 in FIG. 7 is shown as a standalone device separate from the memory controller 702 , but in some examples, part or all of the volatile memory device 706 may be part of the memory controller 702 .

[0069] like Figure 7As shown, the memory controller 702 may include an L2P module 710, a write count module 712, and an FBC scan module 716. Each of the L2P module 710, the write count module 712, and the FBC scan module 716 may be implemented as a firmware module in the form of code or instructions that can be executed by a processing unit such as a microcontroller unit (MCU). Additionally or alternatively, each of the L2P module 710, the write count module 712, and the FBC scan module 716 may be implemented as an ASIC, including digital circuits, analog circuits, and / or mixed signal circuits.

[0070] In some implementations, a memory cell (e.g., a PCM cell) of the nonvolatile memory device 704 is divided into memory cells (e.g., a PCM unit). In other words, the nonvolatile memory device 704 may include a plurality of memory cells, each of which may include one or more memory cells. For example, each memory cell may include a memory cell coupled to a corresponding one of the bit lines of the nonvolatile memory device 704. In other words, according to some implementations, memory cells coupled to the same bit line (in the same column) are considered to be memory cells. The memory cell, which is a physical unit of a memory cell, may correspond to an operation unit (e.g., a page, a codeword, etc.) known to the memory controller 702. In some implementations, each memory cell corresponds to a page 722 in a codeword 720. It should be understood that in some examples, a plurality of memory cells may be grouped into a memory group corresponding to a codeword 720 including a plurality of pages 722.

[0071] refer to Fig. 9 , codeword 720 may be a one-shot operation size in memory system 700. In other words, codeword 720 may be a basic unit for performing a write operation in memory system 700. For example, the size of codeword 720 may be 512 bytes, 4096 bytes, 16384 bytes, etc. Codeword 720 may be a single error correction code (ECC) codeword or a combination of multiple ECC codewords. In one example, codeword 720 may be a combination of 16 ECC codewords (each codeword having a size of 256 bytes) of a size of 4096 bytes. Fig. 9As shown, the codeword 720 may include multiple pages of user / host data 902 and multiple pages of spare data 904. In one example, the user / host data 902 of each codeword 720 may come from a page with the same page number (e.g., page 0) of each bank (e.g., bank 0, bank 1, bank 2, and bank 3) and / or die. Each page may correspond to a memory cell in the non-volatile memory device 704. The spare data 904 may include parity data 908 for ECC and metadata 906, such as a write count of the codeword 720. For example, each time the memory controller 702 controls the non-volatile memory device 704 to perform a write operation on the codeword 720, the word count of the codeword 720 may be increased by 1. Therefore, the word count of each codeword 720 may indicate the word count of the page, as well as the word count of the memory cells corresponding to those pages in the corresponding codeword 720 in the non-volatile memory device 704. It should be understood that codeword 720 and page 722 are used as examples of possible logical organizations and hierarchies of storage cells in nonvolatile memory device 704 for write disturb management, and any other examples of logical organizations and hierarchies may also be applicable to the write disturb management scheme disclosed herein.

[0072] Return to reference Figure 7 , the volatile memory device 706 may store various data structures for managing the write disturb management scheme disclosed herein, including an L2P table 724 and a write count 730. As described above, according to some implementations, the write count of the codeword 720 also reflects the write count of each page 722 of the codeword 720, and the write count of each memory cell corresponding to the corresponding page 722. For example, the write count of the codeword 720 may be the same as the write count of each page 722 of the codeword 720 and the write count of each memory cell corresponding to the corresponding page 722. In some implementations, the write count 730 includes the write count of the memory cell (corresponding to the page 722) or the write count of the memory group (corresponding to the codeword 720), which is based on the write count of the codeword 720 in the metadata 906 of the codeword 720 stored in the non-volatile memory device 704, for example.

[0073] The write count module 712 of the memory controller 702 may be configured to manage the write count 730, for example, by tracking the number of write operations applied to the codeword 720 and storing it in the non-volatile memory device 704 as metadata 906 for the codeword 720. The write count module 712 may also be configured to load the tracked number from the metadata 906 of the codeword 720 from the non-volatile memory device 704 and store it in the volatile memory device 706 as the write count 730 when performing write disturb management. Due to the large number of codewords 720 in the non-volatile memory device 704, the size of the write counts of all the codewords 720 may be too large to be loaded into the volatile memory device 706 at the same time. Therefore, in some implementations, the write count module 712 loads only some of the write counts into the volatile memory device 706 as the write count 730.

[0074] In some implementations, the L2P table 724 includes a mapping table between the physical address and the logical address of each memory cell. According to some implementations, the physical address of the memory cell reflects the physical location of the memory cell and the relative location of the memory cells, for example, whether two memory cells are physically adjacent to each other. On the other hand, according to some implementations, the logical address of the memory cell is directly linked to the index (e.g., page number) of the page known to the memory controller 702. For example, if Fig.10 As shown, the mapping table can indicate the mapping relationship between the physical addresses and logical addresses of the 64 memory cells. The 64 memory cells can be arranged sequentially from 0 to 63 from the upper left corner to the lower right corner according to their logical addresses, and each logical address can be mapped to a corresponding one of the 64 physical addresses. For example, as shown in the shaded portion of the mapping table, logical address 0 can be mapped to physical address 0, logical address 1 can be mapped to physical address 42, logical address 3 can be mapped to physical address 16, and so on.

[0075] The L2P module 710 of the memory controller 702 may be configured to store the L2P table 724 in the non-volatile memory device 704, and maintain and manage the L2P table 724. The L2P module 710 may also be configured to load the L2P table 724 from the non-volatile memory device 704 when performing write disturb management, and store the L2P table 724 in the volatile memory device 706. The L2P module 710 of the memory controller 702 may also be configured to convert between the physical address and the logical address of each memory cell based on the L2P table 724.

[0076] As described above, according to some implementations, the memory controller 702 controls the operation of the non-volatile memory device 704 based on the operation unit (e.g., page 722 and codeword 720) rather than the physical unit of the storage unit (e.g., memory cell and memory group). The L2P module 710 may also be configured to determine the logical address of the memory cell based on the corresponding page, or vice versa. In some implementations, the memory cells are divided into a plurality of sets (M sets), and each set of memory cells includes a plurality of memory cells (N memory cells) and a corresponding L2P table 724. It should be understood that in some examples, the same L2P table 724 may be used for each set of memory cells. For example, there may be 64 sets of memory cells (M=64), and each set may include 64 memory cells (N=64), so that there may be a total of 4096 memory cells (4096 pages 722). The set index may be from 0 to M-1 (e.g., 63), which may be the same for both the physical address and the logical address of the memory cell. The cell index may be from 0 to N-1 (eg, 63), which may be different for the physical address and the logical address of the memory cell, for example, Fig.10 shown.

[0077] In some implementations, the L2P module 710 determines the set index (ID1) and the unit index (ID2) of the logical address of the memory cell based on the index of the corresponding page 722 (referred to herein as the page number) using the following formula: ID1 = INT (page number / N) and ID2 = MOD (page number / N), where N is the number of memory cells in each set. In other words, the set index and the unit index may be the quotient and remainder of the page number divided by the number of memory cells in each set, respectively. In the example Fig.11 In an example shown, when N=64 (2 6 ), a binary right shift operation (>>) can be performed on page number 6. Log2N (6 in this example) bits (101001 in this example) starting from the least significant bit (LSB) can be the cell index of the logical address in the set. In this example, the page number is ANDed with 0x4F. Similarly, in some implementations, the index of page 722 can be determined by the L2P module 710 based on the set index (ID1) and the cell index (ID2) of the logical address of the corresponding memory cell, using a modified operation as described above (e.g., using the equation: page number = N×ID1+ID2), where N is the number of memory cells in each set.

[0078] Return to reference Figure 7, the FBC scan module 716 can be configured to determine whether to trigger a write disturb scan of an adjacent memory cell based on the write count and the scan interval of each memory cell of the non-volatile memory device 704. In some implementations, the FBC scan module 716 determines whether the write count of the memory cell reaches a preset value, for example, one of the preset values ​​determined based on the preset scan interval (WD_WC_interval). For example, the preset value can be K×WD_WC_interval, where K is a positive integer. In one example, when WD_WC_interval=200, the FBC scan module 716 can trigger a write disturb scan of the memory cell when the word count of the memory cell increases by every multiple of 200 (e.g., 200, 400, 600, 800, etc.).

[0079] The FBC scanning module 716 can also be configured to obtain the FBC of each adjacent memory cell that is physically adjacent to the memory cell that triggered the write disturb scan, for example, when the write count of the memory cell reaches one of the preset values. The FBC can be the number of bits in the memory cell (e.g., corresponding to the page 722) that are flipped from the written bit value (i.e., failed bits), for example, due to write disturbance. Therefore, the FBC can indicate the level of data corruption and the risk of physical damage due to the cumulative write disturbance effects. In some implementations, in order to obtain the FBC of the adjacent memory cell, the FBC scanning module 716 is configured to read the page 722 corresponding to the adjacent memory cell and determine the FBC based on reading and including the codeword 720 of the page 722. As described above with respect to Fig. 9 As described, the codeword 720 may include parity data 908 for ECC, which may be used by the FBC scanning module 716 to compare with data read from adjacent memory cells to determine the FBC of the adjacent memory cells. It is understood that in some examples, the parity data 908 in the codeword 720 may be used for ECC of all pages of user / host data 902 in the codeword 720, and the FBC may be determined for all memory cells corresponding to all pages of user / host data 902 in the codeword 720. In other words, according to some implementations, two or more adjacent memory cells are scanned for FBC.

[0080] The FBC scanning module 716 may also be configured to determine whether the FBC of one or more neighboring memory cells exceeds an FBC threshold. The FBC threshold may be preset based on, for example, a scan interval and / or a maximum number of FBCs (the FBC capability of the memory controller 702) that the FBC scanning module 716 of the memory controller 702 may determine. For example, the FBC threshold may decrease as the scan interval increases and / or the FBC capability decreases. By comparing the FBC to the FBC threshold, the need to mitigate the cumulative write disturb effects on neighboring memory cells may be evaluated by the FBC scanning module 716 without recording the write disturb effects on each memory cell.

[0081] The FBC scanning module 716 may also be configured to refresh the adjacent memory cell when the FBC of the adjacent memory cell exceeds the FBC threshold. In some implementations, the FBC scanning module 716 is configured to rewrite the adjacent memory cell with the same data stored in the adjacent memory cell, thereby eliminating the cumulative write disturbance effects on the adjacent memory cell. For example, the FBC scanning module 716 may read the page 722 corresponding to the adjacent memory cell and write the read data back to the same adjacent memory cell.

[0082] Figure 8 Detailed diagram of memory controller 802 is shown in accordance with some aspects of the present disclosure. Memory controller 802 may be Figure 7 An example of a memory controller 702 in FIG. Figure 8 As shown, the memory controller 802 may include a processing unit 840, an SRAM 850, and a read-only memory (ROM) 860. In some implementations, the processing unit 840 includes one or more MCUs. Figure 7 The various firmware modules in the described memory controller 702 may be implemented as firmware codes or instructions stored in ROM 860 and executed by the processing unit 840. In some implementations, the various data structures in the volatile memory device 706 may be stored in SRAM 850. In some implementations, the memory controller 802 also includes a memory module coupled to the SCM device 806 (e.g., Figure 1 The memory controller 802 may include an SCM interface 830 configured to transmit data, commands, clocks, or any suitable signals between the SCM device 806 and the processing unit 840. In some implementations, the memory controller 802 may also include various I / O layers to implement various communication protocols, thereby facilitating communication between the host 804 (e.g., Figure 18 and NVMe layer 820).

[0083] Fig.12 A flow chart of a method 1200 for operating a non-volatile memory device according to some aspects of the present disclosure is shown. The non-volatile memory device may be any suitable memory device disclosed herein, for example, the non-volatile memory device 704. The method 1200 may be implemented by a memory controller such as the memory controller 702 or any other suitable memory controller disclosed herein. It should be understood that the operations shown in the method 1200 may not be exhaustive, and other operations may also be performed before, after, or between any of the operations shown. In addition, some of the operations may be performed simultaneously, or in different order. Fig.12 Execute in the order shown.

[0084] A non-volatile memory device may include a plurality of memory cells. In some implementations, each of the memory cells corresponds to a page in a codeword. For example, Figure 7 As shown, each memory cell may correspond to a page 722 in a codeword 720. In some implementations, each cell comprises a memory cell coupled to a corresponding one of the bit lines of a non-volatile memory device. In some implementations, the memory cell comprises a PCM cell.

[0085] refer to Fig.12 , method 1200 begins at operation 1202, where a write count of a first memory cell in the memory cells is determined. In some implementations, to determine the write count, a number of write operations applied to a first codeword is tracked. The first codeword may include a first page corresponding to the first memory cell. For example, Figure 7 As shown, the write count module 712 of the memory controller 702 can track the write count of each codeword 720 and use the same write count for the memory cells corresponding to the pages 722 in the codeword 720. Fig.13 As shown, a write operation on a codeword may be performed at 1302. At operation 1304, each time a write operation is performed on a codeword, a write count (WC) of the codeword may be increased by 1 (WC=WC+1).

[0086] Method 1200 proceeds to operation 1204, such as Fig.12 As shown, in operation 1204, in response to the write count of the first memory cell reaching one of the preset values, the FBC of a second memory cell physically adjacent to the first memory cell is obtained. Figure 7As shown, the FBC scanning module 716 can obtain the FBC of the adjacent memory cell when the write count of the memory cell reaches one of the preset values ​​determined based on the scanning interval. In some implementations, to obtain the FBC of the second memory cell, the second page corresponding to the second memory cell is read (scanned), and the number of flipped bits in the second page is determined based on reading and including a second codeword of the second page (e.g., parity data of the second codeword). In some implementations, the first memory cell and the second memory cell are coupled to the same word line. As shown in FIG. Fig.13 As shown, at operation 1306, it is determined whether the write count of the codeword reaches K times the scan interval (WD_WC_interval), where K is a positive integer. If the answer to operation 1306 is "yes", then at operation 1308, the page of adjacent bit lines on the same word line can be scanned (read) for FBC. Otherwise, at operation 1302, the write operation is tracked again.

[0087] like Fig.14 As shown, in order to determine the write count of the first memory cell and the FBC of the second memory cell, at operation 1402, a mapping table between the physical address and the logical address for each memory cell is stored. The mapping table can be Fig.10 At operation 1404, a logical address of a first memory cell is determined based on the first page (eg, a page number), for example, Fig.11 At operation 1406, a physical address of the first memory unit is determined based on the logical address of the first memory unit and the mapping table, for example, Fig.10 At operation 1408, a second memory cell physically adjacent to the first memory cell is determined based on the physical address of the first memory cell and the physical address of the second memory cell. Fig.10 As shown, memory cells having physical addresses 1 and 3 (underlined) may be adjacent memory cells physically adjacent to the memory cell having physical address 2. Therefore, when the scan interval of the memory cells is reached, the adjacent memory cells on which the FBC scan needs to be performed may be identified.

[0088] Since the FBC scan needs to be performed based on an operation unit (e.g., a page) visible to the memory controller, the page corresponding to the adjacent memory can be identified through the modified operation. At operation 1410, the logical address of the second memory unit is determined based on the physical address of the second memory unit and the mapping table. For example, Fig.10As shown, according to the mapping table, the logical addresses of the memory cells with physical address 1 and physical address 3 (underlined) may be 33 and 49, respectively. At operation 1412, a second page (eg, a page number) is determined based on the logical address of the second memory cell. Figure 7 As shown, the L2P module 710 of the memory controller 702 may perform operations 1402 to 1412 .

[0089] Return to reference Fig.12 , method 1200 proceeds to operation 1206, in which, in response to the FBC of the second memory cell exceeding the threshold, the second memory cell is refreshed. Figure 7 As shown, the FBC scanning module 716 can refresh the adjacent memory cells when the FBC of the adjacent memory cells exceeds the FBC threshold. Fig.13 As shown, at operation 1310, it is determined whether the FBC of the scanned page exceeds the FBC threshold (FBC_RF_TH). If the answer to operation 1310 is "yes", then at operation 1312, the scanned page is refreshed. Otherwise, at operation 1308, the page of adjacent bit lines is scanned again. In some implementations, to refresh the second memory cell, the second memory cell is rewritten with the data stored in the second memory cell.

[0090] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be a computer program that can be accessed by a memory controller (e.g., Figure 7Any available medium accessed by the memory controller 702 in the computer. By way of example and not limitation, such computer readable media may include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, hard disk drive (HDD) (e.g., disk storage or other magnetic storage device), flash drive, SSD, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a processing system such as a mobile device or a computer. As used herein, disks and discs include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, where disks typically copy data magnetically, while optical discs use lasers to copy data optically. The above combinations should also be included within the scope of computer readable media.

[0091] The description of the above specific implementations can be easily modified and / or adapted to various applications. Therefore, based on the teaching and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and range of equivalents of the disclosed implementations.

[0092] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0093] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the subject matter described in the present disclosure may also be used in a variety of other applications. The functions and structural features described in the present disclosure may be combined, adjusted, modified, and rearranged with each other, and in a manner consistent with the scope of the present disclosure.

Claims

1. A method for operating a non-volatile memory device, the non-volatile memory device comprising a memory cell, the method comprising: determining a write count for a first memory cell of the memory cells; In response to the write count of the first memory cell reaching one of the preset values, obtaining a flipped bit count (FBC) of a second memory cell among the memory cells that is physically adjacent to the first memory cell; and In response to the FBC of the second memory cell exceeding a threshold, the second memory cell is refreshed.

2. The method according to claim 1, wherein: Each of the memory cells includes a storage cell coupled to a corresponding one of the bit lines.

3. The method according to claim 2, wherein: The memory cell comprises a phase change memory (PCM) cell.

4. The method according to any one of claims 1 to 3, wherein: Determining a write count of the first memory cell includes: A number of write operations applied to a first codeword including a first page corresponding to the first memory cell is tracked.

5. The method according to claim 4, further comprising: storing a mapping table between a physical address and a logical address for each of the memory cells, Wherein, determining the write count of the first memory unit further includes: determining a logical address of the first memory cell based on the first page; and A physical address of the first memory unit is determined based on the logical address of the first memory unit and the mapping table.

6. The method according to claim 5, wherein: Obtaining the FBC of the second memory unit comprises: The second memory cell physically adjacent to the first memory cell is determined based on the physical address of the first memory cell and the physical address of the second memory cell.

7. The method according to claim 6, wherein: Obtaining the FBC of the second memory unit further includes: reading a second page corresponding to the second memory cell; and A number of flipped bits in the second page is determined based on the reading and a second codeword including the second page.

8. The method according to claim 7, wherein: Obtaining the FBC of the second memory unit further includes: determining a logical address of the second memory unit based on the physical address of the second memory unit and the mapping table; and The second page is determined based on a logical address of the second memory cell.

9. The method according to any one of claims 1 to 8, wherein: Refreshing the second memory unit comprises: The second memory cell is rewritten with the data stored in the second memory cell.

10. The method according to any one of claims 1 to 9, wherein: The first memory cell and the second memory cell are coupled to the same word line.

11. A memory system comprising: A non-volatile memory device, the non-volatile memory device comprising a memory cell; as well as a memory controller coupled to the non-volatile memory device and configured to: determining a write count for a first memory cell of the memory cells; In response to the write count of the first memory cell reaching one of the preset values, obtaining a flipped bit count (FBC) of a second memory cell among the memory cells that is physically adjacent to the first memory cell; and In response to the FBC of the second memory cell exceeding a threshold, the second memory cell is refreshed.

12. The memory system according to claim 11, wherein: The nonvolatile memory device also includes a bit line; and Each of the memory cells includes a storage cell coupled to a corresponding one of the bit lines.

13. The memory system according to claim 12, wherein: The memory cell comprises a phase change memory (PCM) cell.

14. The memory system according to any one of claims 11 to 13, wherein: To determine a write count of the first memory cell, the memory controller is configured to: A number of write operations applied to a first codeword including a first page corresponding to the first memory cell is tracked.

15. The memory system according to claim 14, further comprising a volatile memory configured to: store a mapping table between a physical address and a logical address for each of the memory cells, in, To determine a write count of the first memory cell, the memory controller is further configured to: determining a logical address of the first memory cell based on the first page; and A physical address of the first memory unit is determined based on the logical address of the first memory unit and the mapping table.

16. The memory system of claim 15, wherein: To obtain the FBC of the second memory unit, the memory controller is configured to: The second memory cell physically adjacent to the first memory cell is determined based on the physical address of the first memory cell and the physical address of the second memory cell.

17. The memory system of claim 16, wherein: In order to obtain the FBC of the second memory unit, the memory controller is further configured to: reading a second page corresponding to the second memory cell; as well as A number of flipped bits in the second page is determined based on the reading and a second codeword including the second page.

18. The memory system according to claim 17, in order to obtain the FBC of the second memory unit, the memory controller is further configured to: determining a logical address of the second memory unit based on the physical address of the second memory unit and the mapping table; and The second page is determined based on a logical address of the second memory cell.

19. The memory system according to any one of claims 11 to 18, wherein: To refresh the second memory unit, the memory controller is configured to: The second memory cell is rewritten with the data stored in the second memory cell.

20. The memory system according to any one of claims 11 to 19, wherein: The non-volatile memory device further includes a word line; and The first memory cell and the second memory cell are coupled to the same one of the word lines.

21. A non-transitory computer-readable storage medium comprising instructions, which when executed by a memory controller, cause the memory controller to perform the following operations: determining a write count of a first memory cell of the memory cells in the non-volatile memory device; In response to the write count of the first memory cell reaching one of the preset values, obtaining a flipped bit count (FBC) of a second memory cell among the memory cells that is physically adjacent to the first memory cell; and In response to the FBC of the second memory cell exceeding a threshold, the second memory cell is refreshed.

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