Hard mask for high aspect ratio dielectric etch at low and high temperatures

Abstract

Various embodiments herein relate to methods, devices, and systems for etching high aspect ratio features in dielectric materials. The dielectric material is etched using a multilayer or graded hard mask having at least two different compositions. When different portions of the hard mask are exposed, different etch schemes are used. For example, when a higher portion of the hard mask is exposed, the feature may be etched to a first depth at a first temperature, and then when a lower portion of the hard mask is exposed, the feature is etched to a final depth at a second temperature, the second temperature being higher than the first temperature.

Description

Incorporated by Reference

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application identified in the concurrently filed PCT application form to which this application claims the benefit or priority is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] One process often used during semiconductor device fabrication is the etching of dielectric materials to form recessed features therein. Exemplary contexts in which such processes may be performed include, but are not limited to, memory applications such as DRAM and 3D NAND structures. As the semiconductor industry advances and device dimensions become smaller, such features become increasingly difficult to etch.

[0003] The background description provided here is for the purpose of generally presenting the background of the present disclosure. The work of the currently designated inventors within the scope described in this background section and aspects of the specification that were not determined to be prior art at the time of filing the application are neither explicitly nor implicitly admitted to be prior art against the present disclosure. Summary of the invention

[0004] Various embodiments herein relate to methods, apparatus, and systems for etching features into a substrate. The substrate is typically a semiconductor substrate, and the features are etched into a dielectric material.

[0005] In one aspect of the disclosed embodiment, a method of etching a feature into a substrate is provided. The method includes: receiving a substrate in a processing chamber, the substrate including: a dielectric material, and a hard mask including an upper portion and a lower portion, the upper portion including carbon and the lower portion including at least one material selected from the group consisting of doped carbon, silicon, a metal, a metal-containing material, and combinations thereof, wherein the upper portion and the lower portion of the hard mask have different compositions, wherein the hard mask is patterned to define a location at which the feature is etched into the dielectric material, and wherein the hard mask is located above the dielectric material; etching the feature into the substrate to a first depth when the substrate is at a first temperature and when the upper portion of the hard mask is exposed; and etching the feature to a final depth when the substrate is at a second temperature and when the lower portion of the hard mask is exposed, wherein the second temperature is higher than the first temperature.

[0006] In various embodiments, specific temperatures may be used. In some cases, the first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C. In some such cases, the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

[0007] The hard mask may include a material having a particular composition. For example, in some embodiments, the lower portion of the hard mask includes one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In various embodiments, the lower portion of the hard mask has a composition of at least about 5 atomic % metal.

[0008] The method may include one or more additional steps. For example, the method may expose the substrate to an oxygen-containing plasma after etching the feature into the substrate to the first depth and before etching the feature to the final depth to ash away any remaining higher portions of the hard mask. In these and other embodiments, the method may also include depositing a liner on the sidewalls of the feature after etching the feature into the substrate to the first depth and before etching the feature to the final depth. In these and other embodiments, the method may also include depositing additional masking material on the hard mask after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

[0009] The hard mask may include multiple differentiated layers, or it may be graded. In some embodiments, the upper portion and the lower portion of the hard mask are differentiated layers. In other embodiments, the hard mask has a graded composition such that the composition of the upper portion of the hard mask is graded to the composition of the lower portion of the hard mask.

[0010] In another aspect of the disclosed embodiment, an apparatus for etching a substrate is provided. The apparatus comprises: a processing chamber; a substrate support configured to support the substrate in the processing chamber; an inlet leading to the processing chamber for introducing one or more reactants into the processing chamber; an outlet leading to the processing chamber for removing material from the processing chamber; a controller comprising a memory and a processor, wherein the controller is configured to cause: receiving the substrate in the processing chamber, the substrate comprising: a dielectric material, and a hard mask comprising an upper portion and a lower portion, the upper portion comprising carbon, and the lower portion comprising a material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof The invention relates to a method of etching a dielectric material comprising: etching the feature into the dielectric material and etching the feature to a first depth when the substrate is at a first temperature and when the upper portion of the hard mask is exposed; and etching the feature to a final depth when the substrate is at a second temperature and when the lower portion of the hard mask is exposed, wherein the second temperature is higher than the first temperature.

[0011] The controller can be configured to cause etching under specific processing conditions. For example, in some embodiments, the first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C. In some such embodiments, the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

[0012] The hard mask may include a material having a particular composition. In some embodiments, the lower portion of the hard mask includes one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In some such embodiments, the lower portion of the hard mask has a composition of at least about 5 atomic % metal.

[0013] The controller may also be configured to cause additional operations. For example, in some embodiments, the controller is further configured to cause: after etching the feature into the substrate to the first depth and before etching the feature to the final depth, exposing the substrate to an oxygen-containing plasma to ash away any remaining higher portion of the hard mask. In these or other embodiments, the controller is further configured to cause: after etching the feature into the substrate to the first depth and before etching the feature to the final depth, depositing a liner on the sidewall of the feature. In these or other embodiments, the controller is further configured to cause: after etching the feature into the substrate to the first depth and before etching the feature to the final depth, depositing additional masking material on the hard mask.

[0014] The hard mask may include multiple differentiated layers, or it may be graded. In some embodiments, the upper portion and the lower portion of the hard mask are differentiated layers. In other embodiments, the hard mask has a graded composition such that the composition of the upper portion of the hard mask grades to the composition of the lower portion of the hard mask.

[0015] These and other aspects are further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1A and Figure 1B Showing high aspect ratio features and the different etching mechanisms that can be used, Figure 1A Shows that etching at low temperatures, Figure 1B Shows an etching process at normal temperature.

[0017] Figure 2A and 2B It shows that when the Figure 2A ) or at normal temperature ( Figure 2B ) is a mechanism that can be used to etch various types of mask materials when etching.

[0018] Figures 3A-3D Depicts the etching mechanisms that may occur during reactive ion etching using different etching temperature regimes and different types of mask layers.

[0019] Figure 4 A flow chart showing a method of etching a feature in a dielectric material.

[0020] Figures 5A-5C Shows the basis Figure 4 Schematic representation of the profile evolution of the treatments described in .

[0021] Figure 6A flow chart showing a method of etching features in a dielectric material with intermittent top mask removal.

[0022] Figures 7A-7D Shows the basis Figure 6 Schematic representation of the profile evolution of the treatments described in .

[0023] Figure 8 A flow chart is shown of a method of etching features in a dielectric material with intermittent top mask removal and liner deposition.

[0024] Figures 9A-9E Shows the basis Figure 8 Schematic representation of the profile evolution of the treatments described in .

[0025] Fig.10 A flow chart is shown of a method of etching features in a dielectric material by intermittent top mask removal, liner deposition, and mask regrowth.

[0026] Figures 11A-11E Shows the basis Fig.10 Schematic representation of the profile evolution of the treatments described in .

[0027] According to various embodiments herein, Figures 12A-12C An embodiment of a capacitively coupled confined RF plasma reactor with adjustable gap is depicted.

[0028] Fig.13 A semiconductor processing cluster architecture is shown having various modules interfaced with a vacuum transfer module. DETAILED DESCRIPTION

[0029] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other cases, well-known processing operations are not described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in conjunction with specific embodiments, it should be understood that they are not intended to limit the disclosed embodiments. Background and Application

[0030] In various embodiments herein, features are etched into a substrate (typically a semiconductor wafer) having a dielectric material on the surface. The etching process is typically a plasma-based etching process, such as a reactive ion etching process. The features are recesses in the substrate surface. The features can have many different shapes, including but not limited to cylinders, ellipses, rectangles, squares, other polygonal recesses, grooves, etc.

[0031] The aspect ratio is the depth of a feature compared to the critical dimension of the feature (often its width / diameter). For example, a cylinder with a depth of 2 μm and a width of 50 nm has an aspect ratio of 40:1, often more simply stated as 40. As used herein, unless otherwise specified, the aspect ratio is measured based on the critical dimension near the feature opening.

[0032] The features formed by the disclosed methods can be high aspect ratio features. In some applications, the aspect ratio of the high aspect ratio features is at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100. The critical dimensions of the features formed by the disclosed methods can be about 200 nm or less, such as about 100 nm or less, about 50 nm or less, or about 20 nm or less.

[0033] In various cases, the material in which the feature is etched may be a dielectric material. Exemplary materials include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, oxynitride, oxycarbon, carbonitride, doped forms of these materials (e.g., doped with boron, phosphorus, etc.), and laminated materials from any combination of these materials. Specific exemplary materials include stoichiometric and non-stoichiometric formulations of SiO2, SiN, SiON, SiOC, SiCN, etc. In various embodiments, the material in which the feature is etched includes a stack of alternating materials (e.g., silicon oxide and silicon nitride). In various cases, one or more materials etched may also include other elements, such as hydrogen. In some embodiments, the nitride and / or oxide material etched has a composition containing hydrogen. When used herein, it should be understood that silicon oxide materials, silicon nitride materials, etc. include stoichiometric and non-stoichiometric forms of such materials, and such materials may have other elements, as described above.

[0034] One application of the disclosed method is in the context of forming a DRAM device. In this case, features may be etched primarily in silicon oxide. For example, the substrate may also include one, two, or more layers of silicon nitride. In one example, the substrate includes a silicon oxide layer sandwiched between two silicon nitride layers, wherein the silicon oxide layer has a thickness between about 800nm-1200nm, and one or more of the silicon nitride layers has a thickness between about 300nm-400nm. The etched feature may be a cylinder having a final depth between about 1-3μm, such as between about 1.5-2μm. The cylinder may have a width between about 20nm-50nm, such as between about 25nm-30nm. After etching the cylinder, a capacitor memory cell may be formed therein.

[0035] Another application of the disclosed method is in the context of forming a vertical NAND (VNAND, also known as 3D NAND) device. In this case, the material in which the features are etched may have a repeating layered structure. For example, the material may include alternating layers of oxide (e.g., SiO2) and nitride (e.g., SiN), or alternating layers of oxide (e.g., SiO2) and polysilicon. The alternating layers form material pairs. In some cases, the number of pairs may be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 70. The thickness of the oxide layer may be between about 20nm-50nm, such as between about 30nm-40nm. The thickness of the nitride or polysilicon layer may be between about 20nm-50nm, such as between about 30nm-40nm. The depth of the features etched into the alternating layers may be between about 2μm-8μm, such as between about 3μm-5μm. The width of the features may be between about 50 nm and 150 nm, such as between about 50 nm and 100 nm. challenge

[0036] Many problems may arise when etching recessed features. These problems include, for example, non-vertical etch profiles, bowing, distortion, ellipticity, and selectivity. In many etching applications, recessed features are etched more heavily near the top of the feature (compared to the bottom of the feature). Such non-vertical etch profiles (e.g., features with sloping sidewalls) are undesirable, at least because such profiles limit how closely features can be positioned adjacent to each other without compromising the integrity of the semiconductor device.

[0037] In various etching applications, recessed features are etched more heavily near the middle of the feature (compared to the top and bottom of the feature). This can produce a bow near the middle of the feature, where it is widest. Similar to the non-vertical etch profile described above, such a bow is undesirable, at least because it limits how closely features can be positioned adjacent to each other without compromising the integrity of the semiconductor device.

[0038] Distortion is another problem that can occur during etching. Distortion refers to the deviation of a feature from its intended position as it is etched further into the dielectric material. Another factor to consider when etching is ellipticity, which is related to the shape of the recessed feature. In many cases, the recessed feature is a cylinder. When viewed from above, the cross-sectional shape of such a feature is circular. During etching, the circle may be distorted into an ellipse with a major axis and a minor axis. Ellipticity is a measurement that compares the major axis to the minor axis (e.g., ellipticity = (BA) / B, where A is the length of the minor axis and B is the length of the major axis) to provide a measure of the roundness of the feature versus the ellipticity. An ellipticity of 0 means that the feature has a perfectly circular cross-section, which is ideal.

[0039] Another important issue that is relevant during etching is selectivity. Selectivity refers to the extent to which the etching process removes a first material relative to a second material. Typically, the dielectric material being etched is located between an underlying layer (e.g., an etch stop layer or other type of layer) and an upper mask layer. The mask layer is patterned by photolithography and related processes to define the locations where features will be formed in the dielectric material. High selectivity between the mask layer and the dielectric material allows features to be etched deep into the dielectric material. Conversely, when the selectivity between the mask layer and the dielectric material is not high enough, the mask layer may be etched away before the features reach the desired depth in the dielectric material. Another type of selectivity that should be considered is the selectivity between the dielectric material and the underlying material. It is desirable to have a high selectivity between these materials to ensure that the dielectric material can be completely removed, but the underlying material is not substantially removed.

[0040] Various etching strategies have been developed to address these challenges. Typically, strategies adopted to address the first challenge will provide poor performance for the second challenge. Therefore, it can be difficult to design a process that properly balances all of the related issues. method

[0041] One strategy that can be used to address the above challenges is to combine two different etching techniques to form features in dielectric materials. In various embodiments herein, etching is performed by a two-stage process involving: (1) a first reactive ion etching process performed at a cryogenic etching temperature; and (2) a second reactive ion etching process performed at a normal etching temperature. The first etching process can be used to etch most of the feature depth. The second etching process can be used to etch the remaining portion of the feature. A multilayer hard mask is provided above the etched dielectric material. The multilayer hard mask includes: (1) a higher layer, which is designed to be used during the first reactive ion etching process performed at low temperatures; and (2) a lower layer, which is designed to be used during the second reactive ion etching process performed at normal temperatures. Exemplary materials for each layer of the multilayer hard mask are discussed below. Using a multilayer hard mask allows optimization of each portion of the etching process, resulting in excellent etching performance.

[0042] As used herein, the term "normal etching" is intended to mean a reactive ion etching process performed at normal, non-cryogenic temperatures. A low temperature etching process may be performed at a temperature between about -100°C and about 0°C. A normal etching process may be performed at a temperature between about 0°C and about 100°C. More detailed temperature ranges are discussed below.

[0043] Figure 1A and Figure 1Bshows high aspect ratio features and the different etching mechanisms that can be used, where Figure 1A Shows that etching at low temperatures, Figure 1B Shows an etching process at normal temperature. Figure 1A and 1B Each of the figures depicts a substrate having features formed in dielectric material 101. The features are formed at openings in mask 102. Figure 1A As shown, in many cases where etching is performed at low temperatures, etching relies on the transport of fluorine neutral particles to the bottom of the feature, which occurs via surface diffusion of fluorine-containing physically adsorbed molecules 103. Activation occurs by ion bombardment. In contrast, Figure 1B As shown, in many cases where etching is performed at normal temperatures, etching is performed via C x F y Chemical sputtering of ions 104 occurs.

[0044] Figure 2A and 2B It is shown that when the Figure 2A ) or at normal temperature ( Figure 2B ) is a mechanism that can be used to etch various types of mask materials when etching. Figure 2A and 2B 2 shows four substrates, each with a different material for the mask layer. The first mask layer 201 is silicon oxide (e.g., SiO2), the second mask layer 202 is silicon nitride (e.g., Si3N4), the third mask layer 203 is carbon (e.g., amorphous carbon), and the fourth mask layer 204 is metal (e.g., boron, tungsten, molybdenum, etc.). Figure 2A As shown, when etching is performed at low temperatures, after exposing the substrate to the etching reactants and plasma, a thin fluorinated layer 205 is formed on the surface of the mask layers 201-204. The fluorinated layer 205 can be about 1nm thick. The mask etching rate is driven by the intermolecular chemical bonding between the fluoride in the etching reactants and the materials of the mask layers 201-204. In this example, the etching reactants include a mixture of CH2F2, H2, NF3, Cl2 and HBr. However, other chemicals and combinations of chemicals can be used in various embodiments, as described further below.

[0045] like Figure 2B As shown, when etching is performed at a normal temperature, after the substrate is exposed to the etching reactant and the plasma, C x F y The remedial layer 206 is formed on the surface of the mask layers 201-204. x F yThe remedial layer 206 may have a thickness on the order of about 5 nm to 10 nm, which is significantly thicker than the fluorinated layer 205 formed when etching is performed at low temperatures. The mask etch rate in this example is driven by carbon consumption (e.g., at C x F y within the remediation layer 206), and through C x F y The etching process is driven by diffusion of the remediation layer 206. In this example, the etching reactants include a mixture of C4F8, C4F6, and O2. However, other chemicals and combinations of chemicals may be used in various embodiments, as further described below.

[0046] exist Figure 1A-1B The etching mechanisms described in 2A-2B produce different performance advantages and disadvantages for each type of mechanism. Figure 1A and 2A The described cryogenic etching scheme provides a relatively fast etch with excellent profile control, high selectivity between dielectric and mask materials, low ellipticity, low distortion, and low bow. These factors make cryogenic etching a good candidate for etching most feature depths. On the other hand, regarding Figure 1B and 2B The general etching scheme described provides excellent selectivity performance with respect to etching dielectric materials to underlying layer materials. This factor makes the general etching a good candidate for etching a feature to its final depth after partially etching the feature (e.g., to a first depth) at low temperature.

[0047] As described above, in the embodiments of the present invention, a multilayer hard mask is used. The hard mask includes a higher layer used when etching is performed at low temperatures, and a lower layer used when etching is performed at normal temperatures. When etching is performed at low temperatures, the higher layers of the hard mask may be substantially exhausted, thereby exposing the lower layers of the hard mask. The use of a multilayer hard mask allows each layer of the hard mask to be optimized for the type of etching process used when a specific layer of the hard mask is exposed. This makes fast, high-quality etching results possible while minimizing material and operating costs. For example, material costs can be minimized because the required mask thickness may be thinner than the thickness required using a single homogeneous mask layer. Similarly, since features can be etched quickly, operating costs can be minimized, thereby requiring less energy and providing greater throughput (compared to slower methods).

[0048] In order to maximize the benefits of the disclosed embodiments, the materials used for the upper and lower layers of the multilayer hardmask can be selected to optimize each portion of the etching process. Typically, the upper layers of the multilayer hardmask are carbon (e.g., amorphous carbon) and the lower layers of the multilayer hardmask are different materials, such as doped carbon, silicon, metal, or metal-containing materials (e.g., metal oxides, metal nitrides, metal silicides, metal carbides, metal alloys, etc.). These materials will be discussed further below.

[0049] Figures 3A-3D The etching mechanisms that may occur during reactive ion etching using different etching temperature regimes, and different types of mask layers are depicted. Figure 3A The etching is shown at low temperature using the carbon mask 302. Figure 3B shows etching at low temperature using a doped carbon mask 303, Figure 3C The etching is performed at a normal temperature using a carbon mask 302. Figure 3D Etching performed at normal temperature using a doped carbon mask 303 is shown. In the case of using a doped carbon mask 303, carbon is doped with metal. Figure 3B and 3D Only the metal in the mask layer is shown (eg, carbon is not included in the mask layer), but it is understood that the metal may be provided in the form of carbon doped with one or more metals or otherwise mixed with the associated metal or metals.

[0050] Figures 3A-3D Each of the diagrams depicts a substrate having features formed in a layer of dielectric material 301. The locations of the features are defined by openings in a mask layer (e.g., carbon mask 302 or doped carbon mask 303). Figure 3A As shown, when etching is performed at low temperature using a carbon mask 302, a sidewall film 310 is formed on the sidewalls of the feature. The sidewall film 310 is a silicon-containing ammonium fluoride film, which helps protect the sidewalls from being over-etched, thereby providing a vertical etch profile with a low degree of bow, tilt, distortion and ellipticity. These results are very satisfactory. As described above with respect to Figure 2A As described, during the low temperature etching, a thin fluorinated layer 305 is formed on the surface of the carbon mask 302 .

[0051] like Figure 3B As shown, when etching is performed at low temperatures using the doped carbon mask 303, a sidewall film 311 is formed on the sidewalls of the feature. The sidewall film 311 is a silicon-containing ammonium fluoride film having metal and / or metal fluoride therein. The metal may originate from the doped carbon mask 303. The metal from the doped carbon mask 303 in the sidewall film 311 may result in the formation of a non-vertical, tapered etch profile. These results are not ideal. As described above with respect to Figure 2A As described, during the low temperature etching, a thin fluorinated layer 305 is formed on the surface of the carbon doped mask 303 .

[0052] like Figure 3C As shown in FIG. 1 , when etching is performed at a normal temperature using the carbon mask 302, a sidewall film 312 is formed on the sidewalls of the feature. The sidewall film 312 is C x F y film, similar to the C formed on top of the carbon mask 302 x F y Remedial layer 306. Sidewall film 312 may be deposited in a non-conformal manner, depositing thicker near the top of the feature and not depositing or depositing less near the bottom of the feature. This may lead to the formation of bows and other undesirable etch profile features.

[0053] like Figure 3D As shown, when etching is performed at a normal temperature using the doped carbon mask 303, a sidewall film 313 is formed on the sidewalls of the feature. The sidewall film 313 is a C film that may include some metal and / or metal fluoride. x F y The metal in the sidewall film may be derived from the metal in the doped carbon mask 303. During etching at normal temperature, C x F y The remedial layer 306 may be formed on the doped carbon mask 303, as described above with respect to Figure 2B Similar to Figure 3C The mechanism shown in Figure 3D The mechanism shown in FIG. 3 may form the sidewall film 313 in a non-conformal manner, resulting in the formation of bows, twists, and other undesirable etch profile features. Generally speaking, the sidewall film 313 formed during etching at normal temperatures contains less metal than the sidewall film 311 formed during etching at low temperatures. Therefore, the sidewall film 313 is less likely to form a tapered profile than the sidewall film 311.

[0054] Because in Figure 3C and 3D The usual temperature etching mechanisms shown in often result in undesirable etch profiles, so these techniques should not be used to etch large feature depths. Figure 3A The majority of the feature depth is etched using the technique described in , which involves etching at low temperatures using a carbon mask. The final portion of the feature depth can be etched using Figure 3D The etching is performed using the mechanism shown in , which provides significant benefits with respect to selectivity (particularly with respect to underlying layers directly beneath the dielectric material).

[0055] According to various embodiments herein, Figure 4is a flow chart of a method of etching features in a dielectric material. Figure 4 The method is described in Figures 5A-5C In the Figure 4 semiconductor substrates for various processing operations. Figure 4 The method begins at operation 401, where a substrate is received in a processing chamber. Figure 5A , the substrate includes one or more dielectric material 501 layers into which features will be etched. Below the dielectric material 501 is an etch stop layer 508. Above the dielectric material 501 is a patterned multilayer hard mask 520, which includes a higher layer 520a and a lower layer 520b. The higher layer 520a of the multilayer hard mask 520 is carbon (e.g., amorphous carbon). In various embodiments, the higher layer 520a may have a specific thickness. For example, the higher layer 520a may have a minimum thickness of about 1500nm, or about 1250nm, or about 1000nm. In these or other embodiments, the higher layer 520a may have a maximum thickness of about 2500nm, or about 3000nm, or about 3500nm.

[0056] The material of the lower layer 520b of the multilayer hard mask 520 is, for example, doped carbon, silicon, metal, or metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.). Exemplary metals and other materials for the lower layer 520b are further discussed below. In various embodiments, the lower layer 520b may have a specific thickness. For example, the lower layer 520b may have a minimum thickness of about 1000nm, or about 500nm, or about 200nm. In these or other embodiments, the lower layer 520b may have a maximum thickness of about 2000nm, or about 1500nm, or about 1250nm.

[0057] The multilayer hard mask 520 may have a specific total thickness. The total thickness includes the thickness of both the higher layer 520a and the lower layer 520b before etching the dielectric material 501. The minimum value of the total thickness can be about 2500nm, or about 2000nm, or about 1500nm. In these or other embodiments, the maximum value of the total thickness can be about 4000nm, or about 3500nm, or about 3000nm. The multilayer hard mask 520 is patterned to include a plurality of openings therein. The opening defines the location where features will be etched in the dielectric material 501. The opening can be formed by photolithography and related processing. The opening can have a size as described herein.

[0058] Back to Figure 4 In an embodiment of the present invention, the method continues with operation 403, wherein a cryogenic etching temperature is used to etch a feature into the dielectric material to a first depth. The cryogenic etching process is used to etch a large portion of the feature depth, such as Figure 5BAs shown. In various embodiments, cryogenic etching temperatures can be used to etch a specific portion of a feature (e.g., at the top of the feature). For example, the portion can be at least about 50% of the final etch depth, at least about 75% of the final etch depth, at least about 90% of the final etch depth, at least about 95% of the final etch depth, at least about 98% of the final etch depth, or at least about 99% of the final etch depth.

[0059] During cryogenic etching, the substrate is cooled to a relatively low temperature. For example, the substrate support may be cooled to maintain a low temperature on the substrate. Exemplary minimum substrate support temperatures may be about -100°C, about -80°C, about -60°C, or about -40°C. Exemplary maximum substrate support temperatures may be about -50°C, about -20°C, or about 0°C.

[0060] Etching reactants and plasma are provided to the processing chamber, and the substrate is exposed to the etching reactants and plasma. During this etching operation (or a majority thereof), the upper layer 520a of the multilayer hard mask 520 is exposed to the processing conditions, and the lower layer 520b of the multilayer hard mask 520 is protected by the upper layer 520a. In some embodiments, the upper layer 520a may be consumed at some point near the end of operation 403 or the beginning of operation 411 to expose the lower layer 520b. In some embodiments, the upper layer 520a may be only partially consumed during etching, and a separate optional step may be taken to remove any remaining upper layer 520a, as described below with respect to Figure 6 and Figures 7A-7D In various embodiments, during operation 403, the Figure 3A (which shows low temperature etching using a carbon mask) The mechanism shown etches dielectric material 501.

[0061] The etching reactants used during operation 403 typically include a mixture of reactants. An exemplary mixture is shown in Figure 2A , 3Aand 3B, and include CH2F2, H2, NF3, Cl2 and HBr. However, in various embodiments, other chemicals and combinations of chemicals may be used, as further described below. Such chemicals may include, for example, fluorocarbons and hydrofluorocarbons (e.g., trifluoromethane (CHF3), tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), etc.), iodine-containing fluorocarbons (e.g., trifluoromethyl iodide (CF3I), iodine pentafluoroethane (C2IF5), diiodotetrafluoroethane (C2I2F4), pentafluoroethyl iodide (C2F5I), etc.), iodine-containing fluorides (e.g., iodine monofluoride (IF), iodine trifluoride (IF3), iodine pentafluoride (IF5), iodine heptafluoride (IF 7), etc.), hydrogen iodide (HI), bromine-containing fluorocarbons (e.g., tribromotrifluoroethane (C2Br3F3), dibromotetrafluoroethane (C2Br2F4), bromopentafluoroethane (C2BrF5), bromotrifluoromethane (CF3Br)), etc.), other bromine-containing reactants (e.g., iodine monobromide (IBr), hydrogen bromide (HBr), etc.), sulfur-containing reactants (e.g., sulfur hexafluoride (SF6), hydrogen sulfide (H2S), sulfur dioxide (SO2), carbon disulfide (CS2), carbonyl sulfide (COS), and other sulfur-containing reactants). In these or other embodiments, the chemicals may include one or more etchants, such as nitrogen trifluoride (NF3), difluoromethane (CH2F2), fluoromethane (CH3F), octafluorocyclobutane (C4F8), 1,3-hexafluorobutadiene (C4F6), pentafluoroethane (C2HF5), tetrafluoroethane (C2H2F4, two isomers: 1,1,1,2-tetrafluoroethane and 1,1,2,2-tetrafluoroethane). In addition, in these or other embodiments, the chemicals may include one or more co-reactants, such as methane (CH4), nitrogen (N2), oxygen (O2), and / or hydrogen (H2). Noble gases (helium, neon, argon, krypton, xenon) may also be added as diluents and / or carrier gases. These chemicals may be combined as required for a particular application.

[0062] When performing cryogenic etching in operation 403, specific processing conditions can be used. For example, the minimum value of the pressure in the processing chamber can be about 10mTorr or about 20mTorr. In these or other embodiments, the maximum value of the pressure in the processing chamber can be about 100mTorr or about 50mTorr. The minimum value of the flow rate of the etching reactant (excluding any inert gas or other non-reactive gas) can be about 200sccm or about 300sccm. The maximum value of the flow rate can be about 500sccm or about 1000sccm. The minimum value of the flow rate of non-reactive gases (e.g., Ar, He, Kr, etc.) can be about 200sccm or about 100sccm. In these or other embodiments, the maximum value of the flow rate of non-reactive gases can be about 500sccm or about 300sccm. Plasma can be generated at one or more frequencies. Exemplary frequencies include 60MHz, 27MHz, 13.65MHz, 2MHz, 1MHz and 400kHz. The plasma may be generated at a specific power level. For example, the minimum value of the source power level may be about 10 kW, or about 15 kW. In these or other cases, the maximum value of the power level may be about 20 kW, or about 30 kW. These power levels relate to a single 300 mm diameter semiconductor substrate and may be appropriately scaled for other substrates or substrates of other sizes. During etching, a bias may be applied to the substrate, with the bias power (e.g., at about 400 kHz) ranging between a minimum of about 30 W or about 50 W and a maximum of about 75 W or about 100 W. Various types of plasma may be used, including, for example, inductively coupled plasma, capacitively coupled plasma, transformer coupled plasma, and microwave induction plasma. The plasma may be a direct plasma generated in a processing chamber.

[0063] Next, at operation 411, the feature is further etched into the dielectric material by etching at a normal temperature. Operation 411 can be used to etch the feature to its final depth, such as Figure 5C In some cases, operation 411 may occur in a single stage. In some other cases, operation 411 may occur in multiple stages, such as etching a first portion of a feature and over-etching a second portion of the feature.

[0064] In various embodiments, the upper layer 520a is carbon and the lower layer 520b is carbon doped with one or more metals. The metal doped into the lower layer 520b slows down the rate at which the lower layer 520b is consumed. Because the rate at which the dielectric is etched is substantially constant (e.g., compared to the case of using a single carbon hard mask), the reduced mask etch rate results in a higher etch selectivity. This selective capability is particularly advantageous for the end of the etching process. It is expected that various other possible materials listed for the lower layer 520b will provide similar benefits as doped carbon.

[0065] During etching at normal temperatures, the substrate may or may not be temperature controlled, for example by heating and / or cooling. For example, the substrate support may be heated and / or cooled to maintain a desired temperature on the substrate. Exemplary minimum substrate support temperatures may be about 20°C, or about 40°C, or about 60°C. Exemplary maximum substrate support temperatures may be about 60°C, or about 80°C, or about 100°C. Higher temperatures may be used in some cases.

[0066] During operation 411, an etching reactant and plasma are provided to the processing chamber and the substrate is exposed to the etching reactant and plasma. During this etching operation (or during a majority of it), the lower layer 520a of the multi-layer hard mask 520 is exposed to the processing conditions. As described above, the upper layer 520a may be exhausted at some point near the end of operation 403 or the beginning of operation 411 to expose the lower layer 520b, or any remaining upper layer 520a may be removed in a separate step. In various embodiments, during operation 411, the dielectric material 501 may be removed according to the etching conditions. Figure 3D (which shows normal temperature etching using a doped carbon mask) is etched by the mechanism shown.

[0067] The etching reactants used during operation 411 typically include a mixture of reactants. An exemplary mixture is shown in Figure 2B , 3C and 3D, and include C4F8, C4F6, and O2. However, other chemicals and combinations of chemicals may be used in various embodiments. Generally speaking, any chemical described for the low temperature etching at operation 403 may be used for the normal temperature etching at operation 411. Such chemicals may be combined as required for a particular application.

[0068] When performing normal temperature etching in operation 411, specific processing conditions can be used. For example, the minimum value of the pressure in the processing chamber can be about 10mTorr or about 20mTorr. In these or other embodiments, the maximum value of the pressure in the processing chamber can be about 50mTorr or about 100mTorr. The minimum value of the flow rate of the etching reactant (excluding any inert gas or other non-reactive gas) can be about 200sccm or about 300sccm. The maximum value of the flow rate can be about 500sccm or about 1000sccm. The minimum value of the flow rate of non-reactive gases (e.g., Ar, He, Kr, etc.) can be about 200sccm or about 100sccm. In these or other embodiments, the maximum value of the flow rate of non-reactive gases can be about 500sccm or about 300sccm. Plasma can be generated at one or more frequencies. Exemplary frequencies include 60MHz, 27MHz, 13.65MHz, 2MHz, 1MHz, and 400kHz. Plasma can be generated at a specific power level. For example, the minimum value of the source power level can be about 10kW or about 15kW. In these or other cases, the maximum value of the power level can be about 20kW or about 30kW. These power levels are about a single 300mm diameter semiconductor substrate, and can be appropriately scaled for other substrates or substrates of other sizes. During etching, a bias voltage can be applied to the substrate, and the bias voltage range is between a minimum value of about 30W or about 50W of 400kHz power and a maximum value of about 75W or about 100W. Various types of plasma can be used, including, for example, inductively coupled plasma, capacitively coupled plasma, transformer coupled plasma, and microwave induction plasma. In various embodiments, capacitively coupled plasma is preferred.

[0069] According to various embodiments herein, Figure 6 is a flow chart of a method of etching features in a dielectric material. Figure 6 The method in Figures 7A-7D described in Figure 6 semiconductor substrates for various processing operations. Figure 6 The method is similar to Figure 4 For example, Figure 6 Operations 601, 603 and 611 are similar to Figure 4 For the sake of brevity, most of the details about operations 601, 603 and 611 are excluded. However, it should be understood that the details provided about operations 401, 403 and 411 can be applied to operations 601, 603 and 611, respectively.

[0070] Fig. 7AA substrate is shown received in a processing chamber in operation 601. The substrate includes a dielectric material 701 between an etch stop layer 708 and a multi-layer hard mask 720 including an upper layer 720a and a lower layer 720b. Figure 7B The substrate is shown after etching a feature into the dielectric material 701 to a first depth at a cryogenic etch temperature in operation 603. Return to Figure 6 In an embodiment of the present invention, the method continues with operation 605, wherein any remaining portion of the upper layer 720a of the multi-layer hard mask 720 is removed, such as Figure 7C . This removal can be done in a separate step. In many embodiments, the higher layer 720a is removed by ashing, which involves exposing the substrate to an oxygen plasma. The oxygen in the oxygen plasma reacts with the carbon in the higher layer 720a of the multilayer hard mask 720, thereby removing the higher layer 720a.

[0071] One advantage of removing the remaining portion of the upper layer 720a is that it provides a substantially uniform mask height for future processing, thereby eliminating any non-uniformity that may occur when etching at low temperatures in operation 703. Such mask height non-uniformity is seen in Figure 7B These non-uniformities are often a consequence of feature layout / density non-uniformities, often referred to as isolated / dense loading. Providing uniform mask heights for future processing steps can enable such future processing steps to be performed in a more uniform manner. Another advantage of removing the remainder of the higher layer 720a is that it removes any necking that may have occurred when etching at low temperatures in operation 703.

[0072] The processing conditions for ashing the remaining higher layer 720a may depend on several factors, including, for example, the amount of material to be removed. The oxygen plasma may be generated at one or more frequencies, such as 13.65 MHz, 27 MHz, 40 MHz, and 60 MHz. The oxygen plasma may be generated at a specific power level. The minimum value of the power level may be about 200 W, or about 500 W. In these or other embodiments, the maximum value of the power level may be about 3000 W, or about 6000 W. The substrate may be controlled to a specific temperature, such as by controlling the temperature of the substrate support. An exemplary minimum temperature of the substrate support may be about 20° C., or about 50° C. An exemplary maximum temperature of the substrate support may be about 200° C., or about 250° C. The pressure in the processing chamber may be controlled. An exemplary minimum chamber pressure may be about 500 mTorr, or about 750 mTorr. An exemplary maximum chamber pressure may be about 2 Torr, or about 4 Torr. The flow rate of oxygen entering the processing chamber may be controlled. Exemplary minimum oxygen flow rates include about 500 sccm, or about 1000 sccm. Exemplary maximum oxygen flow rates include about 2000 sccm, or about 4000 sccm. A carrier gas may also be provided. CF4 may also be added to enhance the dissociation of oxygen and provide fluorine to remove silicon-containing etch products.

[0073] After removing any remaining portions of the higher layer 720a in operation 605, Figure 6 The method continues with operation 611, where a typical etching temperature is used to further etch features into the dielectric material 701, as described with respect to Figure 4 After etching in operation 611, the feature is at its final depth (e.g., reaching the etch stop layer 708), as shown in FIG. Fig.7D as shown in .

[0074] Although Figure 6 605 is presented in the context of an embodiment in which all remaining portions of the upper layer 720a are removed, but it should be understood that the removal may also be partial. In such an embodiment, operation 605 may involve removing some, but not all, of the remaining portions of the upper layer 720a. Partial removal may be sufficient to obtain one or more of the benefits described above, such as providing uniform mask height and / or removing necking.

[0075] According to various embodiments herein, Figure 8 is a flow chart of a method of etching features in a dielectric material. Figure 8 The method in Figures 9A-9E described in Figure 8 semiconductor substrates for various processing operations. Figure 8 The method is similar to Figure 4 and Figure 6 For example, Figure 8The operation 801 is similar to Figure 4 Operation 401 and Figure 6 Operation 601, Figure 8 The operation 803 is similar to Figure 4 Operation 403 and Figure 6 Operation 603, Figure 8 The operation 805 is similar to Figure 6 Operation 605, Figure 8 The operation of 811 is similar to Figure 4 Operation 411 and Figure 6 For the sake of brevity, most of the details about operations 801, 803, 805 and 811 are excluded. However, it should be understood that the details about operations 401 / 601, 403 / 603, 605 and 411 / 611 can also be applied to operations 801, 803, 805 and 811 respectively.

[0076] In this example, features are etched in dielectric material 901 between an etch stop layer 908 and a multi-layer hard mask 920 having an upper layer 920a and a lower layer 920b, as shown in FIG. Fig.9A shown. Fig. 9B The substrate is shown after operation 803 . Fig. 9C The substrate is shown after operation 805. Generally speaking, removing the upper layers 920a of the multi-layer hard mask in a separate step (e.g., operation 805) is optional, and in some embodiments, Figure 8 The method may be implemented without operation 805 .

[0077] Figure 8 The method continues with operation 807, where a liner 930 is deposited along the sidewalls of the partially etched feature, such as Fig.9D As shown. In many embodiments, this deposition occurs by chemical vapor deposition (CVD), which may or may not involve exposure to a plasma. However, other deposition methods may also be used, such as atomic layer deposition (ALD), self-assembled monolayer (SAM), etc. In many cases, the liner 930 may be a carbon liner. Other types of liners, such as metal-doped carbon, metal nitrides, or metal oxides, may also be used as desired for a particular application.

[0078] The processing conditions for forming the liner can be controlled. In various examples using CVD to deposit the carbon liner, the following conditions can be used. The minimum pressure in the process chamber can be about 1 Torr, or about 5 Torr. The maximum pressure can be about 10 Torr, or about 15 Torr. The substrate can be temperature controlled, for example by heating and / or cooling the substrate support. The substrate support can be controlled to a minimum temperature of about 200°C, or about 300°C. The substrate support can be controlled to a maximum temperature of about 500°C, or about 700°C. The reactants provided to the process chamber may include C x H y (e.g., CH4, C2H2, C3H6, C4H8, etc.). A carrier gas may be provided. An exemplary minimum flow rate of the reactants (excluding the carrier gas) may be about 20 sccm, or about 100 sccm. An exemplary maximum flow rate of the reactants (excluding the carrier gas) may be about 5 slm, or about 10 slm. The plasma may be capacitively or inductively coupled with various frequencies.

[0079] As mentioned above, other types of deposition may also be used to form the liner. In this case, the processing conditions should be adapted to the type of process used and the type of material deposited.

[0080] After the liner 930 is deposited on the sidewalls in operation 807, Figure 8 The method continues with operation 811, where a typical etching temperature is used to further etch features into the dielectric material 901, such as Fig.9E shown.

[0081] In various embodiments, depositing the liner 930 in operation 807 and etching the feature at a normal temperature in operation 911 may be cycled with each other. All other things being equal, such cycling may result in the feature being etched deeper into the dielectric material than would otherwise be possible.

[0082] According to various embodiments herein, Fig.10 is a flow chart of a method of etching features in a dielectric material. Fig.10 The method in Figures 11A-11E described in Fig.10 semiconductor substrates for various processing operations. Fig.10 The method is similar to Figure 4 , 6 and 8. For example, Fig.10 Operation 1001 is similar to operations 401, 601, and 801. Fig.10 Operation 1003 is similar to operations 403, 603, and 803, Fig.10 Operation 1005 is similar to operations 605 and 805, Fig.10 Operation 1007 is similar to operation 807, Fig.10 Operation 1011 is similar to operations 411, 611, and 811. For the sake of brevity, most of the details about operations 1001, 1003, 1005, 1007, and 1011 are excluded. However, it should be understood that the details about operations 401 / 601 / 801, 403 / 603 / 803, 605 / 805, 807, and 411 / 611 / 811 can also be applied to operations 1001, 1003, 1005, 1007, and 1011, respectively.

[0083] exist Fig.10 In the method, features are etched into a substrate having a dielectric material 1101 between an etch stop layer 1108 below and a multi-layer hard mask 1120 above, the multi-layer hard mask 1120 having an upper layer 1120a and a lower layer 1120b, such as Fig.11A as shown in . Fig. 11B The substrate is shown after etching at low temperature in operation 1003 . Fig. 11C The substrate is shown after removing the remaining upper layers 1120a of the multi-layer hard mask 1120 in operation 1005 . Fig.10 The method continues with operation 1007, where a liner 1130 is deposited along the sidewalls of the partially etched features, and operation 1009, where additional mask material 1135 is deposited on the remaining portion of the multilayer hard mask 1120. These operations may occur simultaneously, or one may occur before the other. In various embodiments, operations 1007 and / or 1009 are performed by chemical vapor deposition, which may or may not involve exposure to a plasma.

[0084] In various embodiments, the additional mask material 1135 is carbon. The additional mask material 1135 may have the same composition as the carbon forming the upper layer 1120a of the multilayer hard mask 1120, or it may have the same composition as the doped carbon or other material forming the lower layer 1120b of the multilayer hard mask 1120, or it may be a different material from both.

[0085] The processing conditions used to form the liner and / or additional mask material can be controlled. In various examples using CVD, the following conditions can be used. The minimum pressure in the processing chamber can be about 1 Torr, or about 5 Torr. The maximum pressure can be about 10 Torr, or about 15 Torr. The substrate can be temperature controlled, for example by heating and / or cooling the substrate support. The substrate support can be controlled to a minimum temperature of about 200°C, or about 300°C. The substrate support can be controlled to a maximum temperature of about 500°C, or about 700°C. The reactants provided to the processing chamber may include C x H y(CH4, C2H2, C3H6, C4H8, etc.). A carrier gas may be provided. An exemplary minimum flow rate of the reactants (excluding the carrier gas) may be about 20 sccm, or about 100 sccm. An exemplary maximum flow rate of the reactants (excluding the carrier gas) may be about 5 slm, or about 10 slm. The plasma may be capacitively or inductively coupled with various frequencies.

[0086] Other types of deposition may also be used to form the liner and / or additional mask material. In this case, the processing conditions should be adapted to the type of process used and the type of material deposited.

[0087] Any of the methods described herein may be modified such that one or more steps may be repeated. Figure 6 , the removal of a portion of the multi-layer hard mask in operation 605 may be repeatedly performed. In some embodiments, the partial mask removal in operation 605 may be cycled with the etching at a normal temperature in operation 611. Figure 8 , certain additional steps may be performed repeatedly. For example, the removal of a portion of the multi-layer hard mask in operation 805, the deposition of the liner in operation 807, and / or the etching of the feature at a typical etching temperature in operation 811 may be repeated. In various embodiments, two or more of these operations may be cycled with each other. Similarly, Fig.10 Additional steps are presented that may be repeated in some embodiments. For example, removal of a portion of the multi-layer hard mask in operation 1005, deposition of a liner in operation 1007, deposition of additional mask material in operation 1009, and / or etching at a typical etching temperature in operation 1011 may be repeated. In various embodiments, two or more of these operations may be cycled with each other. Such cycling may enable features to be etched to greater depths than would otherwise be possible. Materials for multi-layer hardmasks

[0088] The multi-layer hard mask includes at least an upper layer and a lower layer. Additional layers may be provided as required for a particular application. Typically, the upper layer is carbon and the lower layer is a different material, such as doped carbon, silicon, metal, or a metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.).

[0089] The carbon in the higher layers of the multi-layer hard mask can be quite pure, for example at least about 85% carbon, at least about 90% carbon, at least about 95% carbon, at least about 99% carbon, or at least about 99.9% carbon. These measurements are based on atomic % (at%). In various embodiments, the higher layers contain only carbon and trace amounts of impurities. In some embodiments, the higher layers may be lightly doped carbon, as defined below. Such carbon may be doped with one or more metals, as described below. Lightly doped higher layers may be paired with lower layers that are doped in larger amounts, or lower layers made of different materials. The higher layers may be amorphous, or polycrystalline with a grain size less than 2 nm.

[0090] The higher layers of the multi-layer hard mask can be formed by any suitable deposition method. In some embodiments, it can be formed by CVD.

[0091] The material of the lower layer 520b of the multi-layer hard mask 520 is, for example, doped carbon, silicon, metal, or metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.). In general, when the lower layer 520b includes a metal, the metal may be present at a minimum concentration of about 0.1%, or about 0.5%, or about 1%, or about 2%, or about 5%, or about 10%, or about 20%, or about 30%, or about 50%. In these or other embodiments, the metal may be present in the lower layer 520b at a maximum concentration of about 5%, about 10%, about 20%, about 50%, or even up to about 100% (e.g., pure metal, or metal containing only trace impurities, or metal alloy). These measurements are based on at%.

[0092] In some embodiments, the lower layers are carbon that has been lightly doped with one or more metals. For example, the carbon lightly doped with a metal may have up to about 10% metal. In some embodiments, the lower layers are carbon that has been moderately doped with one or more metals. For example, the carbon moderately doped with a metal may have between about 15%-35% metal. In some embodiments, the lower layers are carbon that has been heavily doped with one or more metals. For example, the carbon heavily doped with a metal may have between about 40-50% metal. These measurements are based on at%.

[0093] In some embodiments, the lower layer is silicon. The silicon can be relatively pure, for example containing only trace amounts of impurities.

[0094] In some embodiments, the lower layer is a metal or metal-containing material. Metal-doped carbon has been discussed above. Metal-doped oxides, metal-doped nitrides, metal-doped carbides, and / or metal-doped silicides may also be used. Other metal-containing materials that may be used for the lower layer include, for example, metal oxides, metal nitrides, metal carbides, and metal silicides. In such embodiments, the metal may be present at stoichiometric levels, substoichiometric levels, or superstoichiometric levels.

[0095] A variety of different metals can be used. For example, the lower layer can include one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In some embodiments, other metals can be used.

[0096] In several embodiments, the metal included in the lower layer (e.g., in the form of pure metal, metal-doped carbon, metal oxide, metal nitride, metal carbide, metal silicide, or other metal-doped layer described herein) is one that has a relatively high boiling point when combined with fluorine. For example, the boiling point of the relevant metal fluoride can be approximately equal to or higher than the boiling point of tungsten fluoride at the relevant etching temperature, and in some cases, equal to or higher than the boiling point of molybdenum fluoride or chromium fluoride or tantalum fluoride. Because the metal in the lower layer reacts with the fluorine in the etching chemistry (e.g., through C x F y Chemicals and related chemical sputtering) lead to the formation of metal fluorides. When these metal fluorides are relatively more stable (e.g., higher boiling points, lower volatility), more energy is required to remove them. Therefore, metals with high boiling point metal fluorides are good candidates for inclusion in the lower layers. Tantalum fluoride (TaF5), niobium fluoride (NbF5), titanium fluoride (TiF4), and hafnium fluoride (HfF4) are known to have relatively high boiling points.

[0097] In some embodiments, the metal included in the lower layer is a metal that has a relatively low reactivity with fluorine. For example, the reactivity of the metal in question with fluorine may be the same as or lower than that of ruthenium. Because the metal in the lower layer will react with the fluorine in the etching chemistry (e.g., via C x F y Chemicals are used for etching), so choosing a metal with low reactivity to fluorine will result in a relatively low mask etch rate when etching the lower layers of the multi-layer hard mask. As mentioned above, this results in improved etch selectivity.

[0098] The lower layer of the multi-layer hard mask can be formed by any suitable deposition method. In some embodiments, it can be formed by CVD. The lower layer can be amorphous or polycrystalline with a grain size less than 2nm.

[0099] In addition to differences in composition, the upper and lower layers may also have other differences in material properties. For example, the lower layer may be denser than the upper layer. Gradient multi-layer hard mask

[0100] In various embodiments, the multi-layer hard mask described herein may be replaced by a graded layer hard mask, or a multi-layer hard mask having at least one graded layer. Figure 5A In the case of a multilayer hard mask 520, the gradient layer may include a first end or portion similar to the higher layer 520a, a second end or portion similar to the lower layer 520b, and a gradient composition between these ends or portions (e.g., the composition gradients to the next one along the thickness of the layer). In general, any details presented herein with respect to a multilayer hard mask may also be applied to embodiments in which the multilayer hard mask (or layers therein) is replaced by a gradient layer hard mask. For example, a gradient layer hard mask may be used instead of Figure 4 , 6 , 8 and 10 in the context of a multilayer hard mask. Device

[0101] Figures 12A-12C An embodiment of an adjustable gap capacitively coupled confined RF plasma reactor 1200 that can be used to perform etching operations described herein is shown. As depicted, a vacuum chamber 1202 includes a chamber housing 1204 that surrounds an interior space that houses a lower electrode 1206. In the upper portion of the chamber 1202, an upper electrode 1208 is vertically spaced from the lower electrode 1206. The planar surfaces of the upper electrode 1208 and the lower electrode 1206 are substantially parallel and orthogonal to the vertical direction between the electrodes. Preferably, the upper electrode 1208 and the lower electrode 1206 are circular and coaxial with respect to the vertical axis. The lower surface of the upper electrode 1208 faces the upper surface of the lower electrode 1206. The surfaces spaced apart from the opposing electrodes define an adjustable gap 1210 therebetween. During operation, the lower electrode 1206 is supplied with RF power by an RF power source (matching) 1220. RF power is supplied to the lower electrode 1206 through the RF supply line 1222, the RF strap 1224, and the RF power component 1226. A grounded shield 1236 may surround the RF power component 1226 to supply a more uniform RF field to the lower electrode 1206. As described in commonly owned U.S. Pat. No. 7,732,728 (the entire contents of which are incorporated herein by reference and for all purposes), a wafer is inserted through a wafer port 1282 and supported in the gap 1210 on the lower electrode 1206 for processing, and a process gas (e.g., via one or more inlets) is supplied to the gap 1210 and excited into a plasma state by the RF power. The upper electrode 1208 may be powered or grounded.

[0102] exist Figure 12A-12C In the embodiment shown in FIG. 1 , the lower electrode 1206 is supported on a lower electrode support plate 1216. An insulating ring 1214 inserted between the lower electrode 1206 and the lower electrode support plate 1216 insulates the lower electrode 1206 from the support plate 1216.

[0103] The RF bias housing 1230 supports the lower electrode 1206 on an RF bias housing basin 1232. The basin 1232 is connected to the conduit support plate 1238 through an opening in the chamber wall plate 1218 by an arm 1234 of the RF bias housing 1230. In a preferred embodiment, the RF bias housing basin 1232 and the RF bias housing arm 1234 are integrally formed as one component, however, the arm 1234 and basin 1232 may also be two separate components that are bolted or joined together.

[0104] RF bias housing arm 1234 includes one or more hollow passages for passing RF power and utilities, such as gas coolant, liquid coolant, RF energy, cables for lift pin control, electrical monitoring and start-up signals from outside vacuum chamber 1202 to a space inside vacuum chamber 1202 on the back side of lower electrode 1206. RF supply conduit 1222 is insulated from RF bias housing arm 1234, which provides a return path for RF power to RF power source 1220. Facility conduit 1240 provides access for facility components. Further details of facility components are described in U.S. Pat. No. 5,1248,704 and U.S. Pat. No. 7,732,728, and are not shown here for simplicity of description. Gap 1210 is preferably surrounded by a confinement ring assembly or hood (not shown), details of which can be found in commonly owned published U.S. Pat. No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 1202 is maintained at a low pressure via connection to a vacuum pump through a vacuum port 1280 (also referred to as an outlet).

[0105] The catheter support plate 1238 is attached to an actuation mechanism 1242. Details of the actuation mechanism are described in the commonly owned U.S. Patent No. 7,732,728, which has been incorporated above. The actuation mechanism 1242, such as a servomechanical motor, a stepper motor, or the like, is attached to a vertical linear bearing 1244 by, for example, a helical gear 1246 (such as a ball screw) and a motor for rotating the ball screw. During the operation of adjusting the size of the gap 1210, the actuation mechanism 1242 travels along the vertical linear bearing 1244. Fig. 12A The arrangement is shown when the actuation mechanism 1242 is in a high position on the linear bearing 1244 creating a small gap 1210a. Fig. 12BThe arrangement is shown when the actuator mechanism 1242 is in an intermediate position on the linear bearing 1244. As shown, the lower electrode 1206, RF bias housing 1230, conduit support plate 1238, and RF power source 1220 are all moved downward relative to the chamber housing 1204 and the upper electrode 1208, thereby creating an intermediate sized gap 1210b.

[0106] Fig. 12C A large gap 1210c is shown when the actuator 1242 is in a low position on the linear bearing. Preferably, the upper electrode 1208 and the lower electrode 1206 remain coaxial during gap adjustment and the opposing surfaces of the upper and lower electrodes across the gap remain parallel.

[0107] For example, to maintain uniform etching across large diameter substrates (e.g., 300 mm wafers or flat panel displays), the present embodiment enables adjustment of the gap 1210 between the upper electrode 1208 and the lower electrode 1206 in the CCP chamber 1202 during a multi-step etch process recipe (BARC, HARC, and STRIP, etc.). In particular, the chamber involves a mechanical device that enables the linear motion required to provide an adjustable gap between the lower electrode 1206 and the upper electrode 1208.

[0108] Fig. 12A A laterally deflected bellows 1250 is shown sealed proximal to the catheter support plate 1238 and distal to the stepped flange 1228 of the chamber wall plate 1218. The inner diameter of the stepped flange defines an opening 1212 in the chamber wall plate 1218 through which the RF bias housing arm 1234 passes. The distal end of the bellows 1250 is clamped by a clamping ring 1252.

[0109] The laterally deflected bellows 1250 provide a vacuum seal while allowing vertical movement of the RF bias housing 1230, the conduit support plate 1238, and the actuation mechanism 1242. The RF bias housing 1230, the conduit support plate 1238, and the actuation mechanism 1242 may be referred to as a cantilever assembly. Preferably, the RF power source 1220 moves with the cantilever assembly and may be attached to the conduit support plate 1238. Fig. 12B The bellows 1250 is shown in a neutral position when the boom assembly is in a neutral position. Fig. 12C The bellows 1250 is shown deflected laterally when the boom assembly is in a low position.

[0110] The labyrinth seal 1248 provides a particle barrier between the bellows 1250 and the interior of the plasma processing chamber housing 1204. The fixed shield 1256 is non-movably connected to the interior wall of the chamber housing 1204 at the chamber wall plate 1218 to provide a labyrinth slot 1260 (gap) in which the movable shield plate 1258 moves vertically to accommodate the vertical movement of the cantilever assembly. The exterior of the movable shield plate 1258 remains in the gap at all vertical positions of the lower electrode 1206.

[0111] In the illustrated embodiment, the labyrinth seal 1248 includes a fixed shield 1256 attached to the inner surface of the chamber wall plate 1218 at a perimeter of the opening 1212 of the chamber wall plate 1218 defining a labyrinth slot 1260. A movable shield plate 1258 is attached to and extends radially from the RF bias housing arm 1234, wherein the arm 1234 passes through the opening 1212 in the chamber wall plate 1218. The movable shield plate 1258 extends into the labyrinth slot 1260 while being spaced apart from the fixed shield 1256 by a first gap and from the inner surface of the chamber wall plate 1218 by a second gap, thereby enabling vertical movement of the cantilever assembly. The labyrinth seal 1248 prevents particles that are flaked from the bellows 1250 from migrating into the vacuum chamber interior 1205 and blocks radicals from the process gas plasma from migrating to the bellows 1250 where they can form deposits that subsequently flak off.

[0112] Fig. 12A The movable shield plate 1258 is shown in a higher position in the labyrinth slot 1260 above the RF bias housing arm 1234 when the cantilever assembly is in a high position (small gap 1210a). Fig. 12C The movable shield plate 1258 is shown in a lowered position in the labyrinth slot 1260 above the RF bias housing arm 1234 when the cantilever assembly is in a low position (large gap 1210c). Fig. 12B The movable shield plate 1258 is shown in a medium or intermediate position within the labyrinth slot 1260 when the cantilever assembly is in a neutral position (medium gap 1210b). Although the labyrinth seal 1248 is shown as being symmetrical relative to the RF bias housing arm 1234, in other embodiments the labyrinth seal 1248 may be asymmetrical relative to the RF bias housing arm 1234.

[0113] Fig.13A semiconductor processing cluster architecture is depicted with various modules that interface with a vacuum transfer module 1338 (VTM). A transfer module arrangement that "transfers" substrates between multiple storage devices and processing modules may be referred to as a "cluster tool architecture" system. An airlock 1330 (also referred to as a load lock or transfer module) is shown at the VTM 1338 with four processing modules 1320a-1320d, which may be individually optimized to perform various manufacturing processes. For example, the processing modules 1320a-1320d may be implemented to perform substrate etching, deposition, ion implantation, wafer cleaning, sputtering, and / or other semiconductor processing, as well as laser measurement and other defect detection and defect identification methods. One or more of the processing modules (any one of 1320a-1320d) may be implemented as disclosed herein, i.e., for etching recessed features into a substrate using a multi-station etching process utilizing a multi-layer hard mask. The airlock 1330 and the processing modules 1320a-1320d may be referred to as "stations". Each station has a facet 1336 that connects the station to a VTM 1338. Inside the facet, sensors 1-18 are used to detect substrates 1326 as they move through between stations.

[0114] The robot 1322 transfers the substrate between stations. In one implementation, the robot may have one arm, while in another implementation, the robot may have two arms, each with an end effector 1324 to pick up a substrate for transport. In an atmospheric transport module (ATM) 1340, a front end robot 1332 may be used to transfer substrates from a wafer box or front opening wafer box (FOUP) 1334 in a load port module (LPM) 1342 to an airlock 1330. A module center 1328 within a processing module 1320a-1320d may be a location for placing a substrate. An aligner 1344 in the ATM 1340 may be used to align the substrate.

[0115] In an exemplary processing method, a substrate is placed in one of a plurality of FOUPs 1334 in an LPM 1342. A front-end robot 1332 transfers the substrate from the FOUP 1334 to an aligner 1344, which allows the substrate 1326 to be properly centered before being etched or deposited or otherwise processed thereon. After alignment, the substrate is moved by the front-end robot 1332 to an airlock 1330. Since the airlock module has the ability to match the environment between the ATM and the VTM, the substrate can be moved between the two pressure environments without being damaged. From the airlock module 1330, the substrate is moved by the robot 1322 through the VTM 1338 and into one of the processing modules 1320a-1320d, such as the processing module 1320a. To achieve this substrate movement, the robot 1322 uses an end effector 1324 on each of its arms. In the processing module 1320a, the substrate undergoes etching as described. Next, the robot 1322 moves the substrate out of the processing module 1320a and into the next desired station.

[0116] It should be noted that the computer controlling the substrate movement may be local to the cluster architecture, or it may be located external to the cluster architecture in the manufacturing facility, or at a remote location and connected to the cluster architecture via a network. in conclusion

[0117] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many different ways of implementing the processes, systems, and devices of the presented embodiments. Therefore, the presented embodiments are to be regarded as illustrative rather than restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. A method of etching a feature into a substrate, comprising: A substrate is received in a processing chamber, the substrate comprising: Dielectric materials, and a hard mask comprising an upper portion and a lower portion, the upper portion comprising carbon and the lower portion comprising at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof, wherein the upper portion and the lower portion of the hard mask have different compositions, wherein the hard mask is patterned to define locations where the features are etched into the dielectric material, and wherein the hard mask is located above the dielectric material; etching the feature into the substrate to a first depth when the substrate is at a first temperature and when the higher portion of the hard mask is exposed; and The features are etched to a final depth when the substrate is at a second temperature and when the lower portion of the hard mask is exposed, wherein the second temperature is higher than the first temperature. 2 . The method of claim 1 , wherein the first temperature is between about −100° C. and about 0° C., and the second temperature is between about 0° C. and about 100° C.

3. The method of claim 2, wherein the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

4. The method of claim 1 , wherein the lower portion of the hard mask comprises one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof.

5. The method of claim 4, wherein the lower portion of the hard mask has a composition of at least about 5 atomic % metal.

6. The method according to claim 1, further comprising: After etching the features into the substrate to the first depth and before etching the features to the final depth, the substrate is exposed to an oxygen-containing plasma to ash away any remaining higher portions of the hard mask.

7. The method according to claim 1, further comprising: After etching the feature into the substrate to the first depth and before etching the feature to the final depth, a liner is deposited on a sidewall of the feature.

8. The method according to claim 1, further comprising: After etching the features into the substrate to the first depth and before etching the features to the final depth, additional masking material is deposited over the hard mask.

9. The method of claim 1, wherein the upper portion and the lower portion of the hard mask are differentiated layers.

10. The method of claim 1, wherein the hard mask has a graded composition such that a composition of the upper portion of the hard mask grades to a composition of the lower portion of the hard mask.

11. An apparatus for etching a substrate, comprising: Processing room; a substrate support configured to support the substrate in the processing chamber; an inlet to the process chamber for introducing one or more reactants into the process chamber; an outlet to the process chamber for removing material from the process chamber; A controller comprising a memory and a processor, wherein the controller is configured to cause: receiving the substrate in the processing chamber, the substrate comprising: Dielectric materials, and a hard mask comprising an upper portion and a lower portion, the upper portion comprising carbon and the lower portion comprising at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof, wherein the upper portion and the lower portion of the hard mask have different compositions, wherein the hard mask is patterned to define locations where the features are etched into the dielectric material, and wherein the hard mask is located above the dielectric material; etching the feature into the substrate to a first depth when the substrate is at a first temperature and when the higher portion of the hard mask is exposed; as well as The features are etched to a final depth when the substrate is at a second temperature and when the lower portion of the hard mask is exposed, wherein the second temperature is higher than the first temperature.

12. The apparatus of claim 11, wherein the first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C.

13. The device of claim 12, wherein the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

14. The device of claim 11, wherein the lower portion of the hard mask comprises one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof.

15. The apparatus of claim 14, wherein the lower portion of the hard mask has a composition of at least about 5 atomic % metal.

16. The apparatus of claim 11, wherein the controller is further configured to cause: After etching the features into the substrate to the first depth and before etching the features to the final depth, the substrate is exposed to an oxygen-containing plasma to ash away any remaining higher portions of the hard mask.

17. The apparatus of claim 11, wherein the controller is further configured to cause deposition of a liner on a sidewall of the feature after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

18. The apparatus of claim 11, wherein the controller is further configured to cause additional masking material to be deposited over the hard mask after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

19. The apparatus of claim 11, wherein the upper portion and the lower portion of the hard mask are differentiated layers.

20. The apparatus of claim 11, wherein the hard mask has a graded composition such that a composition of the upper portion of the hard mask grades to a composition of the lower portion of the hard mask.

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