Semiconductor device package with enhanced thermomechanical reliability

Abstract

The invention relates to a thin semiconductor device package, and methods and systems for forming the same. Embodiments of the present disclosure include methods and apparatus for forming a semiconductor device package including a frame coated with a layer of a coupling agent over which a subsequent layer is formed. By mitigating stress induced by any subsequently formed insulating layer and / or RDL, and by providing improved coupling between these layers and the relatively smooth surface of the frame, the use of coupling agents between the frame and subsequently formed layers enhances the thermal mechanical reliability of the package frame.

Description

background Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor device packages and methods of forming the same. More specifically, embodiments described herein relate to structures of thin semiconductor device packages and methods of forming the same. Background Art

[0002] The continuing trend in semiconductor device technology development has resulted in semiconductor components having reduced size and increased circuit density. In response to the need to continually shrink semiconductor components while increasing performance capabilities, these components and circuits are integrated into complex 3D semiconductor device packages that facilitate significant reductions in device footprint and enable shorter and faster connections between components. These packages can integrate, for example, semiconductor chips and multiple other electronic components for mounting on circuit boards of electronic devices.

[0003] Conventionally, semiconductor device packages have been fabricated on organic packaging substrates due to the ease of forming features and connections in organic packaging substrates and the relatively low packaging manufacturing costs associated with organic composites. However, as circuit density increases and semiconductor devices are further miniaturized, it becomes impractical to maintain device scaling and associated performance requirements using organic packaging substrates due to limited material structure resolution.

[0004] Recently, silicon-based substrates have been utilized to fabricate 2.5D and / or 3D packages to compensate for some of the limitations associated with organic packaging substrates. The use of silicon-based materials for these packaging applications is driven by their superior thermal properties, low coefficient of thermal expansion (CTE), smooth surface, and availability in large wafer and panel formats.

[0005] However, silicon-based material substrates are not without their disadvantages. For example, it is difficult and expensive to form features (such as through-silicon vias (TSV)) in silicon-based substrates. Specifically, the high cost is caused by high aspect ratio silicon via etching, chemical mechanical planarization, and semiconductor back end of line (BEOL) interconnection. In addition, silicon-based substrates often exhibit cracks and / or other defects when cut from larger panels or wafers and / or caused by stress induced by subsequently formed insulating layers and / or redistribution layers (RDL). In addition, these layers often fall off or delaminate from the silicon-based substrate due to their weak adhesion to the silicon-based substrate.

[0006] Therefore, there is a need in the art for an improved semiconductor device packaging structure and a method of forming the same for advanced packaging applications. Summary of the invention

[0007] Embodiments of the present disclosure relate to a structure of a thin semiconductor device package and a method of forming the same.

[0008] In certain embodiments, a packaging component is provided, the packaging component comprising: a frame, the frame having a first surface opposite to a second surface, the frame further comprising: a frame material comprising a first material (including silicon), at least one cavity having a semiconductor die disposed therein, a via comprising a via surface defining an opening extending from the first surface through the frame to the second surface, and a coupling layer formed on the frame, the coupling layer comprising a silane coupling agent and contacting at least the first surface and the second surface; an insulating layer disposed above the coupling layer on the first surface and the second surface of the frame, the insulating layer contacting at least a portion of each side of the semiconductor die; and an electrical interconnect disposed within the via, wherein the insulating layer and the coupling layer are disposed between the via surface and the electrical interconnect.

[0009] In certain embodiments, a packaging component is provided, comprising: an embedded die component, comprising: a frame comprising a first material (including silicon), a coupling layer disposed above the frame (the coupling layer comprising a silane coupling agent), one or more semiconductor die disposed within the frame (the one or more semiconductor die having integrated circuits formed thereon), and an insulating layer formed on the coupling layer, the insulating layer comprising an epoxy resin material having ceramic particles disposed therein; and one or more metal interconnects, the one or more metal interconnects being disposed within a portion of the embedded die component.

[0010] In certain embodiments, a packaging component is provided, the packaging component comprising: an embedded die component, comprising: a frame comprising a first material (including silicon), a coupling layer formed over the frame and comprising a silane coupling agent, one or more semiconductor die arranged in the frame, a first insulating layer formed on the frame (the first insulating layer comprises an epoxy resin material, which includes ceramic particles), and one or more electrical interconnects arranged to pass through the frame or the first insulating layer; and a redistribution layer formed on the embedded die assembly, the redistribution layer comprising: a second insulating layer formed on the first insulating layer; and one or more electrical redistribution connectors arranged to pass through the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of their scope, and may admit to other equally effective embodiments.

[0012] Figure 1 The figure shows a flow chart of a process for forming a semiconductor device package according to embodiments described herein.

[0013] Figure 2 The diagram illustrates a flow chart of a process for constructing and preparing a frame for forming a semiconductor device package according to embodiments described herein.

[0014] FIG. 3A to FIG. 3D Schematic diagram of a substrate according to an embodiment described herein Figure 2 Cross-sectional views of the framework construction and different stages of the fabrication process depicted in FIG.

[0015] 4A to 4F Schematic diagrams illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal according to embodiments described herein.

[0016] FIG. 5A to FIG. 5F Schematic diagrams illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal according to embodiments described herein.

[0017] FIG. 6A to FIG. 6E Schematic diagrams illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal according to embodiments described herein.

[0018] 7A to 7D Schematic diagrams illustrate cross-sectional views of a substrate at different stages of feature formation and subsequent damage removal according to embodiments described herein.

[0019] Figure 8 The diagram illustrates the use of Figure 2 , FIG. 3A to FIG. 3D , 4A to 4F , FIG. 5A to FIG. 5F , FIG. 6A to FIG. 6E and 7A to 7D Schematic top view of a frame constructed and prepared according to the process depicted in .

[0020] Fig. 9 A flow chart of a process for forming an embedded die assembly with through-assembly vias and contact holes according to embodiments described herein is shown.

[0021] FIG. 10A to FIG. 10KSchematic diagram of an embedded die assembly according to an embodiment described herein Fig. 9 Cross-sectional views at different stages of the process depicted.

[0022] Fig.11 A flow chart of a process for forming an embedded die assembly with through-assembly vias and contact holes according to embodiments described herein is shown.

[0023] FIG. 12A to FIG. 12G Schematic diagram of an embedded die assembly according to an embodiment described herein Fig.11 Cross-sectional views at different stages of the process depicted.

[0024] Fig.13 A flow chart of a process for forming interconnects in an embedded die assembly according to embodiments described herein is shown.

[0025] FIG. 14A to FIG. 14H Schematic diagram of an embedded die assembly according to an embodiment described herein Fig.13 Cross-sectional views at different stages of the interconnect formation process depicted in FIG.

[0026] Fig.15 The figure shows a flow chart of a process for forming a redistribution layer on an embedded die assembly followed by package dicing according to embodiments described herein.

[0027] FIG. 16A to FIG. 16L Schematic diagram of an embedded die assembly according to an embodiment described herein in Fig.15 Cross-sectional views at different stages of forming a redistribution layer followed by package dicing are depicted in FIG.

[0028] Fig.17 Schematically illustrates a method for communicating with a Figures 1 to 7D and Figures 9 to 16L An exemplary apparatus for use with the process.

[0029] Fig.18A and Fig.18B Schematically illustrates a method according to an embodiment described herein including utilizing Figures 1 to 7D and Figures 9 to 16L A cross-sectional view of a dynamic random access memory (DRAM) stack of multiple semiconductor device packages formed by the process depicted in FIG.

[0030] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0031] The methods and apparatus disclosed herein include novel thin semiconductor device packages that are intended to replace more conventional packaging structures that utilize organic substrates as frames (which are limited by material construction resolution) and further improve newer packaging structures that utilize silicon-based or similar substrates as frames. Current packaging frames can provide low mechanical reliability because they sometimes exhibit cracks and / or other defects caused by stress induced by subsequently formed insulating layers and / or redistribution layers (RDLs). In addition, during high temperature processing, layers laminated directly onto silicon-based substrates may fall off or delaminate from the silicon-based substrate due to weak adhesion between silicon and dielectric materials. The methods and apparatus disclosed herein provide semiconductor device packages that overcome many of the disadvantages associated with the above-mentioned conventional packaging architectures by utilizing a frame coated with a layer of a coupling agent (such as a silane coupling agent). The thermomechanical reliability of the packaging frame is enhanced by utilizing a coupling agent between the frame and subsequently formed layers by alleviating stress induced by any subsequently formed insulating layers and / or RDLs, and by providing improved coupling between these layers and the relatively smooth surface of the frame.

[0032] As described in further detail below, Figure 1 A flow chart of a representative method 100 for forming a thin semiconductor device package having a frame coated with silane is shown. The method 100 has a plurality of operations 110, 120, 130, and 140. Figures 2 to 16L Each operation is described in more detail. The method may include one or more additional operations, performed before any of the defined operations, between two of the defined operations, or after all of the defined operations (unless the context excludes such a possibility).

[0033] Generally speaking, method 100 includes constructing and preparing a substrate for use as a package frame at operation 110, referring to Figure 2 , FIG. 3A to FIG. 3D , 4A to 4F , FIG. 5A to FIG. 5F , FIG. 6A to FIG. 6E , 7A to 7D and Figure 8 At operation 120, an embedded die assembly having one or more embedded dies and an insulating layer is formed, referring to Fig. 9 and FIG. 10A to FIG. 10K , Fig.11 and FIG. 12A to FIG. 12G At operation 130, one or more interconnects are formed in and / or through the embedded die assembly for interconnecting the embedded die frame assembly, see Fig.13 and FIG. 14A to FIG. 14HAt operation 140, a first redistribution layer is formed on the embedded die assembly to reposition the contact points of the interconnects to desired lateral locations on the surface of the embedded die assembly. In some embodiments, in addition to the first redistribution layer, one or more additional redistribution layers may be formed before individual packages are cut from the embedded die assembly, as described in detail in the accompanying drawings. Fig.15 and FIG. 16A to FIG. 16L Describe in more detail.

[0034] Figure 2 A flow chart of a representative method 200 for constructing and preparing a substrate for use as a package frame is shown. FIG. 3A to FIG. 3D Schematic map showing the Figure 2 2 is a cross-sectional view of a substrate 302 at different stages of the method 200 shown in FIG. Therefore, for the sake of clarity, the following are described together herein. Figure 2 and FIG. 3A to FIG. 3D .

[0035] Method 200 includes operation 210 and corresponding Figure 3A Substrate 302 is formed of any suitable frame material, including but not limited to Group III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, aluminum oxide, and ceramics. In some embodiments, substrate 302 is a single crystal p-type or n-type silicon substrate. In some embodiments, substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, substrate 302 is a p-type or n-type silicon solar substrate. Substrate 302 may further have a polygonal shape or a circular shape. For example, substrate 302 may include a generally square silicon substrate having a lateral dimension between about 120 mm and about 180 mm, with or without chamfered edges. In another example, substrate 302 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 500 mm, for example, about 300 mm.

[0036] Unless otherwise noted, the embodiments and examples described herein are performed on a substrate having a thickness between about 50 μm and about 1000 μm, such as between about 90 μm and about 780 μm. For example, the substrate 302 has a thickness between about 100 μm and about 300 μm, such as between about 110 μm and about 200 μm. In another example, the substrate 302 has a thickness between about 60 μm and about 160 μm, such as between about 80 μm and about 120 μm.

[0037] Prior to operation 210, the substrate 302 may be cut and separated from the bulk material by wire sawing, scribing and breaking, mechanical abrasive sawing, or laser cutting. Cutting typically results in mechanical defects or deformations in the substrate surface formed thereby, such as scratches, microcracks, chips, and other mechanical defects. Therefore, at operation 210, the substrate 302 is exposed to a first damage removal process to smooth and planarize the substrate surface and remove any mechanical defects in preparation for later construction and packaging operations. In some embodiments, the substrate 302 may be further thinned by adjusting the process parameters of the first damage removal process. For example, the thickness of the substrate 302 may decrease with increasing exposure to the first damage removal process.

[0038] The damage removal process at operation 210 includes exposing the substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing and drying process. In some embodiments, operation 210 includes a chemical mechanical polishing (CMP) process. In some embodiments, the etching process is a wet etching process including a buffered etching process, which is selective for removing desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process using an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the wet etching process. In some embodiments, the substrate 302 is immersed in an HF etching solution for etching. In another embodiment, the substrate 302 is immersed in a KOH etching solution for etching.

[0039] In some embodiments, the etching solution is heated to a temperature between about 30°C and about 100°C, such as between about 40°C and about 90°C, during the etching process. For example, the etching solution is heated to a temperature of about 70°C. In yet other embodiments, the etching process at operation 210 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes. The thickness of substrate 302 is adjusted by controlling the time that substrate 302 is exposed to the etchant (e.g., etching solution) used during the etching process. For example, the final thickness of substrate 302 decreases as exposure to the etchant increases. Alternatively, substrate 302 may have a greater final thickness as exposure to the etchant is reduced.

[0040] At operations 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features, such as vias 303 and cavities 305, patterned and smoothed therein (in Figure 3B3. A cavity 305 and four vias 303 are depicted in a lower cross-section of substrate 302. Vias 303 are used to form direct contact electrical interconnects through substrate 302, and cavity 305 is used to receive and enclose (ie, embed) one or more semiconductor dies therein. FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7B The figure shows a cross-sectional view of a substrate 302 at different stages of a feature formation and damage or defect removal (eg, smoothing) process according to embodiments described herein. FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7B Operations 220 and 230 are described in more detail.

[0041] Now turn FIG. 4A to FIG. 4C and FIG. 5A to FIG. 5C In some embodiments, the substrate 302 may be patterned by a micro-sandblasting process. In these embodiments, if the substrate 302 has a thickness less than about 200 μm (such as a thickness of about 100 μm, or a thickness of about 50 μm), the substrate 302 may first be coupled to a substrate such as Figure 4A and Figure 5A Optional carrier plate 406 depicted in . Carrier plate 406 provides mechanical support for substrate 302 during substrate construction process 200 and prevents substrate 302 from breaking. Carrier plate 406 is formed of any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramic, metal, etc. Carrier plate 406 has a thickness between about 1 mm and about 10 mm, such as, a thickness between about 2 mm and about 5 mm. In some embodiments, carrier plate 406 has a textured surface. In other embodiments, carrier plate 406 has a polished or smooth surface.

[0042] In some embodiments, the substrate 302 may be coupled to the carrier plate 406 via an adhesive layer 408. The adhesive layer 408 is formed by any suitable temporary bonding material, including but not limited to wax, glue or similar bonding materials. The adhesive layer 408 is applied to the carrier plate 406 by mechanical rolling, pressing, laminating, spin coating or doctor blade coating. In some embodiments, the adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, the adhesive layer 408 is a UV release adhesive layer. In yet other embodiments, the adhesive layer 408 is a thermal release adhesive layer. In these embodiments, the bonding properties of the adhesive layer 408 are degraded with exposure to heat treatment (e.g., by exposing the adhesive layer 408 to a temperature higher than 110°C, such as, higher than 150°C). The adhesive layer 408 may further include one or more layers of additional films (not shown), such as, liner, base film, pressure-sensitive film and other appropriate layers.

[0043] In some embodiments, after bonding the substrate 302 to the carrier plate 406, a resist film is applied to the substrate 302 to form the resist layer 404, such as Figure 4A and Figure 5A . In embodiments where substrate 302 has a thickness greater than about 200 μm, such as a thickness of about 250 μm, a resist layer 404 is formed on substrate 302 without first coupling substrate 302 to carrier plate 406. Resist layer 404 is used to transfer a desired pattern to substrate 302, and during subsequent processing operations, resist layer 404 is formed on substrate 302. After patterning, resist layer 404 protects selected areas of underlying substrate 302 during later construction operations.

[0044] The substrate 302 generally has a substantially flat surface on which the resist layer 404 is formed. Figure 5A In some embodiments, the resist layer 404 is bonded to the substrate 302 via a resist bonding layer 409. The resist bonding layer 409 is formed of any suitable temporary bonding material, including but not limited to polyvinyl alcohol, triesters with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In some embodiments, the resist bonding layer 409 is formed of a material different from the bonding layer 408. In some embodiments, the resist bonding layer 409 is generally similar to the bonding layer 408 in composition. The resist bonding layer 409 is applied to the substrate 302 by mechanical rolling, pressing, laminating, spin coating, or doctor blade coating. In other embodiments, the resist layer 404 is formed of a temporary bonding material such as polyvinyl alcohol, so that the resist layer 404 can be directly coated and bonded to the surface of the substrate 302. The resist layer 404 may include one or more layers, for example, a first resist layer and a second resist layer (not shown).

[0045] In some embodiments (such as Figure 4AIn the embodiment illustrated in the figure), the resist layer 404 is a photosensitive layer (e.g., a photoresist). The resist layer 404 may include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin may be any positive photoresist resin or any negative photoresist resin. Representative photoresist resins include acrylates, novolac resins, poly(methyl methacrylate), and poly(olefin sulfone). Other photoresist resins may also be used. Upon exposure to electromagnetic radiation, the photoacid generator may generate charged species, such as acidic cations and anions. The photoacid generator may also generate polarized species. The photoacid generator makes the resin sensitive to electromagnetic radiation. Representative photoacid generators include sulfonic acid compounds, such as sulfonated salts, sulfonated esters, and sulfonyloxyketones. Other suitable photoacid generators include onium salts, such as aromatic diazonium salts, halide ammonium salts, aromatic sulfonium salts, and sulfonium salts or selenium salts. Other representative photoacid generators include nitrophenyl esters, s-triazine derivatives, ionic iodine sulfonates, perfluoroalkyl sulfonates, aryl trifluoroethers and their derivatives and analogs, pyrogallol derivatives, and alkyl disulfides. Other photoacid generators may also be used. In certain embodiments (such as, Figure 5A In the embodiment illustrated in FIG. 4 ), the resist layer 404 is a laser sensitive resist.

[0046] After forming the resist layer 404, the substrate 302 having the resist layer 404 formed thereon is exposed to electromagnetic radiation to pattern the resist layer 404, such as in Figure 4B and Figure 5B Depicted in. Figure 4B In the illustrated embodiment, the substrate 302 having the resist layer 404 formed thereon is exposed to electromagnetic radiation in the ultraviolet (UV) range. (Multiple) portions of the resist layer 404 are selectively exposed, and (Multiple) portions of the resist layer 404 are selectively not exposed to the UV radiation. After exposure to the UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (shown by the hatching), while the selectively unexposed portions maintain their structural integrity. In certain embodiments, before UV radiation exposure, a mask 412 having a desired pattern is formed on or adjacent to the photosensitive resist layer 404. In other embodiments, the mask 412 is a mask positioned between the resist layer 404 and the UV radiation source. The mask 412 is configured to transfer the desired pattern of UV radiation to the resist layer 404. The mask 412 is formed of any suitable polymeric material, including but not limited to PTFE, PVDP, FEP, polyimide, etc.

[0047] exist Figure 5BIn the illustrated embodiment, the substrate 302 having the laser-sensitive resist layer 404 formed thereon is exposed to electromagnetic radiation generated by a laser source 307 rather than a UV radiation source. In this way, patterning is achieved by targeted laser ablation without the use of a mask. The laser source 307 may be any suitable type of laser for patterning the resist layer 404. In some examples, the laser source 307 is a femtosecond green laser. In other examples, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the resist layer 404. For example, the laser source 307 may generate a pulsed laser beam 310 having a frequency between 100kHz and 1200kHz, such as between about 200kHz and about 1000kHz. The laser source 307 is generally configured to form any desired pattern in the resist layer 404. It is further contemplated that the electromagnetic radiation at the operating location may alternatively include an electron beam or an ion beam rather than a laser beam.

[0048] exist Figure 4B In the embodiment of the present invention, the resist layer 404 can be formed by any material having a suitable hardness after the resist layer 404 has been patterned, such as, after the negative photoresist is exposed to electromagnetic radiation to cause the material in the resist to be cross-linked. In general, after the resist layer 404 has been patterned (e.g., deposited, exposed and developed), the resist layer 404 needs to have one or more ideal mechanical properties. In certain embodiments, the resist layer 404 is formed by a material having a Shore A scale hardness value between 40 and 90 after patterning, such as, between 60 and 70. For example, the resist layer 404 is formed by a material having a Shore A scale hardness value of about 65 after patterning. In certain embodiments, the resist layer 404 is formed by a material having a tensile strength between about 0.5MPa and about 10MPa (such as, between about 1MPa and about 8MPa) after patterning. For example, the resist layer 404 can be formed by a material having a tensile strength of about 7MPa after patterning. In some embodiments, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, the resist layer 404 is formed of polyvinyl alcohol, triester with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and the like.

[0049] After patterning the resist layer 404, the substrate 302 on which the resist layer 404 is formed is micro-sandblasted to form a desired pattern in the substrate 302, such as Figure 4C and Figure 5C During the micro-sandblasting process, a stream of powder particles 309 is pushed toward the substrate 302 using a high pressure carrier gas to drive away exposed portions of the substrate 302 and / or layers formed thereon. The micro-sandblasting process is performed using any suitable substrate abrasion system.

[0050] The micro-sandblasting process is determined by the material properties of the powder particles 309, the momentum of the powder particles striking the exposed surface of the substrate 302, and the material properties of the substrate 302, along with (where applicable) the selectively exposed portion of the resist layer 404. To achieve the desired substrate patterning characteristics, adjustments are made to the type and size of the powder particles 309, the size of the applicator nozzle of the abrasive system and the distance from the substrate 302, the pressure of the carrier gas used to propel the powder particles 309 (which is related to the velocity and flow rate), and the density of the powder particles 309 in the fluid stream. For example, the required fluid pressure of the carrier gas used to propel the powder particles 309 toward the substrate 302 for a desired fixed micro-sandblasting device nozzle hole size is determined based on the materials of the substrate 302 and the powder particles 309. In certain embodiments, the fluid pressure for micro-blasting the substrate 302 ranges from about 50 psi to about 150 psi (e.g., between about 75 psi and about 125 psi) to achieve a carrier gas and particle velocity between about 300 meters per second (m / s) and about 1000 meters per second (m / s) and / or at about 0.001 cubic meter per second (m / s). 3 / s) and about 0.002 cubic meters per second (m 3 / s). For example, the fluid pressure of the inert gas (e.g., nitrogen (N2), CDA, argon) used to propel the powder particles 309 during micro-sandblasting is about 95 psi to achieve a carrier gas and particle velocity of about 2350 m / s. In certain embodiments, the applicator nozzle for micro-blasting the substrate 302 has an inner diameter between about 0.1 millimeters (mm) and about 2.5 millimeters (mm), which is disposed at a distance between about 1 mm and about 5 mm from the substrate 302, such as, between about 2 mm and about 4 mm. For example, the applicator nozzle is disposed at a distance of about 3 mm from the substrate 302 during micro-sandblasting.

[0051] In general, the micro-sandblasting process is performed by powder particles 309 having sufficient hardness and a high melting point to prevent the particles from sticking when in contact with the substrate 302 and / or any layer formed thereon. For example, the micro-sandblasting process is performed using powder particles 309 formed of a ceramic material. In certain embodiments, the powder particles 309 used in the micro-sandblasting process are formed of aluminum oxide (Al2O3). In another embodiment, the powder particles 309 are formed of silicon carbide (SiC). Other suitable materials for powder particles 309 are also contemplated. The size range of the powder particles 309 is generally between about 15 μm and about 60 μm in diameter, such as between about 20 μm and about 40 μm in diameter. For example, the powder particles 309 have an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

[0052] At operation 220 and at Figure 4C and Figure 5C The effectiveness of the micro-blasting process depicted in is further dependent upon the material properties of the resist layer 404. Utilizing a material having a Shore A scale hardness that is too high may result in undesirable rebounding of the powder particles 309 between the sidewalls of the resist layer 404, thereby reducing the rate at which the powder particles 309 strike the substrate 302 and ultimately reducing the effectiveness of the powder particles 309 in corroding or removing exposed areas of the substrate 302. Conversely, utilizing a material having a Shore A scale hardness that is too low may result in undesirable adhesion of the powder particles 309 to the resist layer 404. It is contemplated that a Shore A scale hardness value between about 40 and about 90 will be used for the resist layer 404 material, as described above.

[0053] In embodiments where the resist layer 404 is a photoresist (such as, Figure 4C ), at the beginning of the micro-sandblasting process, the substrate 302 remains unexposed. Therefore, the powder particles 309 first bombard the surface of the photoresist, causing material from the UV-exposed and structurally weakened portions of the photoresist to be driven off and removed. The powder particles 309 eventually penetrate and remove the fragile UV-exposed portions to form voids in the resist layer 404, thereby exposing the desired areas of the substrate 302, while other areas remain shielded by the non-UV-exposed portions of the photoresist. Micro-sandblasting then continues until the powder particles 309 drive off and remove the desired amount or depth of material from the exposed areas of the substrate 302, thereby forming the desired pattern in the substrate 302. In embodiments in which the resist layer 404 is patterned by laser ablation (such as, Figure 5C ), prior to the micro-sandblasting process, desired areas of the substrate 302 are already exposed by voids in the resist layer 404. Therefore, it is contemplated that minimal or even no removal of the resist layer 404 is performed during micro-sandblasting.

[0054] The above-described process for forming features in the substrate 302 at operation 220 may cause undesirable mechanical defects, such as flaking and cracking, on the surface of the substrate 302. Therefore, after performing operation 220 to form the desired features in the substrate 302, the substrate 302 is exposed to a second damage removal and cleaning process at operation 230 to smooth the surface of the substrate 302 and remove undesirable debris, followed by stripping the resist layer 404 and optionally releasing the substrate 302 from the carrier plate 406. FIG. 4D to FIG. 4F and FIG. 5D to FIG. 5F The figure shows a cross-sectional view of a substrate 302 at different stages of a second damage removal, cleaning, resist stripping and substrate peeling process according to embodiments described herein. FIG. 4D to FIG. 4F and FIG. 5D to FIG. 5F Operation 230 is described in more detail.

[0055] The second damage removal process at operation 230 is generally similar to the first damage removal process at operation 210 and includes exposing the substrate 302 to an etching process followed by rinsing and drying. The etching process is performed for a predetermined duration to smooth the surface of the substrate 302, and specifically the surface exposed to the micro-sandblasting process. In another aspect, the etching process is used to remove undesirable debris retained from the micro-sandblasting process. Remaining powder particles bonded to the substrate 302 may be removed during the etching process. Figure 4D and Figure 5D The substrate 302 is shown after debris removal and surface smoothing.

[0056] In some embodiments, the etching process is a wet etching process using a buffered etching process, which preferentially etches the substrate surface relative to the resist layer 404 material. For example, the buffered etching process is selective to polyvinyl alcohol. In other embodiments, the etching process is a wet etching process using an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the wet etching process. In some embodiments, the substrate 302 is immersed in an HF etching solution for etching. In another embodiment, the substrate 302 is immersed in a KOH etching solution for etching. The etching solution can be further heated to a temperature between about 40°C and about 80°C during the etching process, such as between about 50°C and about 70°C. For example, the etching solution is heated to a temperature of about 60°C. The etching process can be isotropic or anisotropic. In another embodiment, the etching process at operation 230 is a dry etching process. Examples of dry etching processes include plasma-based dry etching processes.

[0057] After the debris has been removed and the substrate surface has been smoothed, the substrate 302 is exposed to a resist stripping process. The stripping process is used to remove the resist layer 404 from the substrate 302, such as Figure 4E and Figure 5E . In some embodiments, a wet process is used to release the resist layer 404 from the substrate 302 by dissolving / solubilizing the resist adhesion layer 409. Other types of etching processes are also contemplated for releasing the resist adhesion layer 409. In some embodiments, a mechanical rolling process is used to physically peel the resist layer 404 or the resist adhesion layer 409 from the substrate 302. In some embodiments, an ashing process is used to remove the resist layer 404 from the substrate 302 by using, for example, an oxygen plasma assisted process.

[0058] After the resist stripping process, the substrate 302 is exposed to an optional carrier stripping process, such as Figure 4F and Fig. 5FThe use of a carrier peeling process depends on whether the substrate 302 is coupled to the carrier plate 406 and the type of bonding material used to couple the substrate 302 to the carrier plate 406. 4A to 4F and FIG. 5A to FIG. 5F , in an embodiment where the substrate 302 has a thickness of less than about 200 μm, the substrate 302 is coupled to a carrier plate 406 for mechanical support during the formation of features in operation 220. The substrate 302 is coupled to the carrier plate 406 via an adhesive layer 408. Thus, after micro-sandblasting and subsequent substrate etching and resist stripping, the substrate 302 coupled to the carrier plate 406 is exposed to a carrier peeling process to peel the substrate 302 from the carrier plate 406 by releasing the adhesive layer 408.

[0059] In some embodiments, the adhesive layer 408 is released by exposing the substrate 302 to a baking process. The substrate 302 is exposed to a temperature between about 50° C. and about 300° C., such as between about 100° C. and about 250° C. For example, the substrate 302 is exposed to a temperature between about 150° C. and about 200° C., such as about 160° C., for a desired period of time in order to release the adhesive layer 408. In other embodiments, the adhesive layer 408 is released by exposing the substrate 302 to UV radiation.

[0060] Figure 4F and Fig. 5F The substrate 302 is shown after completing operations 210 - 230 . Figure 4F and Fig. 5F The cross section of substrate 302 in FIG. 3 depicts a single cavity 305 formed through substrate 302 and surrounded on either lateral side by two vias 303. Figure 8 Depicted in the completed reference 4A to 4F and FIG. 5A to FIG. 5F A schematic top view of the substrate 302 after the described operation is shown, as described in further detail below.

[0061] FIG. 6A to FIG. 6E The figure shows a schematic, cross-sectional view of a substrate 302 during an alternative micro-sandblasting process (similar to those described above) of operations 220 and 230. The alternative process sequence depicted for operations 220 and 230 involves patterning the substrate 302 on two major opposing surfaces (as compared to only one surface), thereby enabling increased efficiency during the construction of the substrate 302. FIG. 6A to FIG. 6E The embodiments described in the reference include 4A to 4F and FIG. 5A to FIG. 5F Essentially all the processes described. For example, Fig. 6A and Figure 4A and Figure 5A Correspondingly, Figure 6B and Figure 4Band Figure 5B Correspondingly, Figure 6C and Figure 4C and Figure 5C Correspondingly, Fig.6D and Figure 4D and Figure 5D Correspondingly, Fig. 6E and Figure 4F and Fig. 5F However, unlike the previous embodiment, FIG. 6A to FIG. 6E The embodiment of operation 220 depicted in FIG. 4 includes a substrate 302 having two resist layers 404 formed on major opposing surfaces 606, 608 thereof, rather than one resist layer 404 formed on a single surface. Therefore, the processes performed during operations 210-230 will need to be performed at the same time (i.e., simultaneously), or performed one after another (i.e., sequentially) on both sides of the substrate during each operation. Although FIG. 6A to FIG. 6E Only the formation of vias 303 is illustrated, but the process described herein may also be used to form cavities 305 , or cavities 305 and vias 303 .

[0062] Thus, after the resist layer 404 on one side of the substrate 302 (such as the side including the surface 608) is exposed to electromagnetic radiation for patterning, the substrate 302 may be flipped over so that the resist layer 404 on the opposite surface 606 is also exposed to electromagnetic radiation for patterning, such as Figure 6B Similarly, after the micro-sandblasting process is performed on the surface 608 of the substrate 302, the substrate 302 may be flipped over as appropriate so that the micro-sandblasting may be performed against the opposite surface 606, as shown in FIG. Figure 6C Thereafter, the substrate 302 is exposed to a second damage removal and cleaning process and a resist stripping process, as in FIG. 6D to FIG. 6E By performing the micro-blasting process with two resist layers 404 on major opposing surfaces 606, 608 of substrate 302 and against surfaces 606 and 608, potential tapering of features formed therein caused by the micro-blasting process may be reduced or eliminated, and the efficiency of the process for constructing substrate 302 may be increased.

[0063] 7A to 7D FIG. 2 shows a schematic, cross-sectional view of a substrate 302 during another alternative process sequence for operations 220 and 230, wherein a desired pattern is formed in the substrate 302 by direct laser ablation. Fig. 7A, a substrate 302 (such as a solar substrate or even a semiconductor wafer) is placed on a support 706 of a laser ablation system (not shown). The support 706 can be any suitable rigid and flat or textured (e.g., constructed) surface for providing mechanical support for the substrate 302 during laser ablation. In some embodiments, the support 706 includes an electrostatic chuck for electrostatically clamping the substrate 302 to the support 706. In some embodiments, the support 706 includes a vacuum chuck for vacuum clamping the substrate 302 to the support 706. After the substrate 302 is placed on the support 706, a desired pattern is formed in the substrate 302 by laser ablation, such as in Figure 7B Depicted in.

[0064] The laser ablation system may include any suitable type of laser source 307 for patterning substrate 302. In some examples, laser source 307 is an infrared (IR) laser. In some examples, laser source 307 is a picosecond UV laser. In other examples, laser source 307 is a femtosecond UV laser. In yet other examples, laser source 307 is a femtosecond green laser. Laser source 307 generates a continuous or pulsed laser beam 310 for patterning substrate 302. For example, laser source 307 may generate a pulsed laser beam 310 having a frequency between 5 kHz and 500 kHz, such as between 10 kHz and about 200 kHz. In one example, laser source 307 is configured to deliver a pulsed laser beam having a wavelength between about 200 nm and about 1200 nm and a pulse duration between about 10 ns and about 5000 ns with an output power between about 10 watts and about 100 watts. Laser source 307 is configured to form any desired patterns and features in substrate 302 , including cavity 305 and via 303 .

[0065] Similar to micro-sandblasting, the process of direct laser patterning of substrate 302 may cause undesirable mechanical defects, including chips and cracks, on the surface of substrate 302. Therefore, after the desired features are formed in substrate 302 by direct laser patterning, substrate 302 is exposed to a second damage removal and cleaning process substantially similar to the above-described embodiments. FIG. 7C to FIG. 7D The structured substrate 302 is shown before and after a second damage removal and cleaning process is performed, resulting in a smoothed substrate 302 having a cavity 305 and four vias 303 formed therein.

[0066] In certain embodiments, after mechanical defects in the substrate 302 are removed at operation 230, the substrate 302 may be exposed to an oxidation process to grow or deposit an insulating oxide film (ie, layer) 314 on a desired surface thereof, such as Figure 3C. For example, the oxide film 314 may be formed on all surfaces of the substrate 302 so that it surrounds the substrate 302. The insulating oxide film 314 acts as a passivation layer on the substrate 302 and provides a protective external barrier layer against corrosion and other forms of damage. In some embodiments, the oxidation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800°C and about 1200°C, such as between about 850°C and about 1150°C. For example, the thermal oxidation process is performed at a temperature between about 900°C and about 1100°C, such as between about 950°C and about 1050°C. In some embodiments, the thermal oxidation process is a wet oxidation process using water vapor as an oxidant. In some embodiments, the thermal oxidation process is a dry process using molecular oxygen as an oxidant. It is contemplated that the substrate 302 may be exposed to any suitable oxidation process at operation 240 to form the oxide film 314 thereon. Oxide film 314 generally has a thickness between about 100 nm and about 3 μm, such as between about 200 nm and about 2.5 μm. For example, oxide film 314 has a thickness between about 300 nm and about 2 μm, such as about 1.5 μm.

[0067] In operation 240 and Figure 3D At the desired surface of the substrate 302, the coupling layer 316 is formed. For example, the coupling layer 316 may be formed on all surfaces of the substrate 302 (eg, Figure 3D ), or only formed on some surfaces (such as major surfaces 606 and 608 ). In some embodiments, coupling layer 316 is formed over oxide film 314 .

[0068] The coupling layer 316 generally comprises a coating formed of one or more coupling agents to facilitate bonding of the substrate 302 to any subsequently formed insulating and / or redistribution layers (such as those described below). Fig. 9 and FIG. 10A to FIG. 10KThe invention relates to an improved bonding between the insulating layer 1018 and the substrate 302. Conventionally, an insulating layer and / or redistribution layer, which usually includes organic and / or dielectric materials, is formed directly above the frame of the semiconductor package device. However, when a silicon-based frame is utilized, poor bonding between the frame and the subsequently formed insulating layer and / or redistribution layer allows moisture to penetrate therebetween. When the packaged device is exposed to high temperature conditions, the moisture may subsequently expand, for example, during subsequent processing, causing the insulating layer and / or redistribution layer to delaminate or separate from the frame, thereby severely compromising the structural integrity and electrical performance of the semiconductor package device. By forming a coupling layer 316 between the substrate 302 and (for example) the insulating layer 1018, the bonding of the insulating layer 1018 to the substrate 302 is improved, thereby enhancing the thermomechanical reliability of the final semiconductor package device. In addition, the coupling layer 316 provides an additional protective barrier layer around the substrate 302 and relieves any stress on the substrate 302 that may be caused by expansion and / or warping of the insulating layer 1018.

[0069] In some embodiments, the coupling layer 316 includes one or more silane coupling agents, which can produce a waterproof interface between the organic polymer of the insulating layer (e.g., insulating layer 1018) and the inorganic substrate (e.g., substrate 302) because it can react or interact with the substrate and the polymer. The silane coupling agent is an organic silicon compound that includes an organic functional group for reacting / interacting with an organic material (e.g., an insulating layer and / or a redistribution layer) and a hydrolyzable group for reacting / interacting with an inorganic material (e.g., a silicon-based framework). In some embodiments, the silane coupling agent may have a general formula X3-Si-(CH2)nY, where X is a hydrolyzable group, such as a methoxy or ethoxy group, Y is a functional group, and n is equal to 0-3. Examples of suitable functional groups include vinyl, epoxy or epoxide groups, styryl, acryl, methacryl, methacryl, amine, phenyl, urea, isocyanate, isocyanurate, thiol, and the like.In a specific embodiment, the coupling layer 316 may include dodecyltrimethoxysilane, octadecyltrimethoxysilane, n-octyltriethoxysilane, methyltrimethoxysilane, methyltriethoxysilane, γ-methacryloxypropyltrimethoxysilane, vinyltriacetoxysilane, vinyltrimethoxysilane, vinyltriethoxysilane, dichloromethylvinylsilane, dimethoxymethylvinylsilane, diethoxymethylvinylsilane, chlorodimethylvinylsilane, vinyltrichlorosilane, vinyltri(2-methoxyethoxy)silane, 1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane , γ-isocyanatepropyl triethoxysilane, γ-glycidyloxypropyl trimethoxysilane, β-(3,4-epoxycyclohexyl)ethyl trimethoxysilane, phenyltrichlorosilane, phenyltrimethoxysilane, phenyltrimethoxysilane, dichlorodiphenylsilane, diphenyldimethoxysilane, diphenyldiethoxysilane, methylphenyldimethoxysilane, methylphenyldiethoxysilane, 3-aminopropyltriethoxysilane, n-2-(aminoethyl)-3-aminopropyltrimethoxysilane, n-2-(aminoethyl)-3-aminopropyltriethoxysilane, n-2-(aminoethyl)-3-aminopropylmethyldimethoxysilane 3-aminopropyl trimethoxysilane, 3-aminopropyl methyl diethoxysilane, 3-ureidopropyl trimethoxysilane, 3-ureidopropyl triethoxysilane, 3-glycidoxypropyl trimethoxysilane, 3-glycidoxypropyl methyl dimethoxysilane, 3-glycidoxypropyl methyl diethoxysilane, 3-glycidoxypropyl triethoxysilane, 2-(3,4-epoxycyclohexyl)ethyl trimethoxysilane, 2-(3,4-epoxycyclohexyl)ethyl triethoxysilane, 2-(3,4-epoxycyclohexyl)ethyl methyl dimethoxysilane, 2-(3,4-epoxycyclohexyl)ethyl methyl diethyl Oxysilane, 3-methacryloxypropyltrimethoxysilane, 3-methacryloxypropylmethyldimethoxysilane, 3-methacryloxypropylmethyldiethoxysilane, 3-methacryloxypropyltriethoxysilane, bis[3-(triethoxysilyl)propyl]tetrasulfide, bis[3-(triethoxysilyl)propyl]sulfide, 3-mercaptopropyltrimethoxysilane, 3-mercaptopropyltriethoxysilane, 1,2-bis(trimethoxysilyl)ethane, 1,2-bis(triethoxysilyl)ethane, tetramethoxysilane, tetraethoxysilane, tetrapropoxysilane, trimethoxysilane, triethoxysilane, and the like.

[0070] In general, the coupling layer 316 may be formed by any suitable method, including any suitable chemical and / or deposition processes, as well as self-assembly. In certain embodiments, the coupling layer 316 is formed by sol-gel or one or more other chemical processes. In certain embodiments, the coupling layer 316 is formed by chemical vapor deposition (CVD) or other deposition processes. In certain embodiments, an organosilane self-assembled monolayer (SAM) is formed over the surface of the substrate 302 via liquid phase deposition (LPD) or vapor phase deposition (VPD). In LPD, the silane may be diluted in a solvent and thereafter the substrate 302 may be immersed in the solution for a desired period of time. In VPD, the silane may be evaporated by, for example, applying heat, and thereafter the substrate 302 may be exposed to the vapor.

[0071] After forming the coupling layer 316 , the substrate 302 may proceed to method 900 or method 1100 described below, where an embedded die assembly 1002 is formed using the substrate 302 as a frame.

[0072] Figure 8 A schematic top view of an exemplary structured substrate 302 is shown according to one embodiment. Figure 2 , FIG. 3A to FIG. 3D , 4A to 4F , FIG. 5A to FIG. 5F , FIG. 6A to FIG. 6E and 7A to 7D As described, the substrate 302 may be constructed during operations 210-240. The substrate 302 is illustrated as having two quadrilateral cavities 305, and each cavity 305 is surrounded by a plurality of vias 303. In certain embodiments, each cavity 305 is surrounded by two columns 801, 802 of vias 303, which are arranged along each edge 306a-306d of the quadrilateral cavity 305. Although ten vias 303 are depicted in each column 801, 802, it is contemplated that any desired number of vias 303 may be formed in a column. Additionally, any desired number and arrangement of cavities 305 and vias 303 may be formed in the substrate 302 during operation 220. For example, the substrate 302 may have more or less than two cavities 305 formed therein. In another example, the substrate 302 may have more or less than two columns of vias 303 formed along each edge 306a-306d of the cavity 305. In another example, the substrate 302 may have two or more columns of vias 303 , wherein the vias 303 in each column are staggered and misaligned with the vias 303 in another column.

[0073] In some embodiments, the cavity 305 and the via 303 have a depth equal to the thickness of the substrate 302, thereby forming a hole on the opposite surface of the substrate 302 (e.g., through the thickness of the substrate 302). For example, depending on the thickness of the substrate 302, the cavity 305 and the via 303 formed in the substrate 302 may have a depth between about 50 μm and about 1 mm, such as between about 100 μm and about 200 μm, such as between about 110 μm and about 190 μm. In other embodiments, the cavity 305 and / or the via 303 may have a depth equal to or less than the thickness of the substrate 302, thereby forming a hole in only one surface (e.g., side) of the substrate 302.

[0074] In certain embodiments, depending on the semiconductor die or dies 1026 that will be embedded in cavity 305 during package fabrication (described in more detail below), Fig. 10B 1026 ) in size, each cavity 305 has a lateral dimension ranging between about 3 mm and about 50 mm, such as between about 8 mm and about 12 mm, such as between about 9 mm and about 11 mm. The semiconductor die generally includes a plurality of integrated electronic circuits formed on and / or within a substrate material, such as a sheet of semiconductor material. In certain embodiments, the cavities 305 are sized to have lateral dimensions that are generally similar to the lateral dimensions of the die 1026 to be embedded therein. For example, each cavity 305 is formed to have lateral dimensions that exceed those of the die 1026 by less than about 150 μm, such as less than about 120 μm, such as less than 100 μm. Reducing the variation in the size of the cavities 305 and the die 1026 to be embedded therein reduces the amount of gap fill material utilized thereafter.

[0075] In some embodiments, each via 303 has a diameter ranging between about 50 μm and about 200 μm, such as between about 60 μm and about 130 μm, such as between about 80 μm and 110 μm. The minimum spacing 807 between the center of a via 303 in column 801 and the center of an adjacent via 303 in column 802 is between about 70 μm and about 200 μm, such as between about 85 μm and about 160 μm, such as between about 100 μm and 140 μm. Although reference is made to Figure 8 To describe the embodiment, but the above reference operations 210-240 and Figure 2 , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4C , FIG. 5A to FIG. 5C , FIG. 6A to FIG. 6C and FIG. 7A to FIG. 7B The described structure construction process can be used to form patterned features in substrate 302 having any desired depth, lateral dimensions, and topography.

[0076] Fig. 9 and Fig.11 Flowcharts 900 and 1100 , respectively, illustrate representative methods for fabricating an intermediate embedded die assembly 1002 around a substrate 302 prior to final package formation. FIG. 10A to FIG. 10K The schematic diagram shows the substrate 302 in Fig. 9 900 at different stages of the method 900 depicted in FIG. 1 , and FIG. 12A to FIG. 12G The schematic diagram shows the substrate 302 in Fig.11 1100 at different stages of the method 1100 depicted in FIG. For clarity, the following are described together in this document. Fig. 9 and FIG. 10A to FIG. 10K , and are described together in this article Fig.11 and FIG. 12A to FIG. 12G .

[0077] Method 900 includes operations 902 and Fig. 10A Initially, the first side 1075 of the substrate 302 (now having the desired features formed therein and the coupling layer 316 formed thereon) is placed on the first insulating film 1016a. In some embodiments, the first insulating film 1016a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 1016a includes one or more layers formed of a flowable accumulation material. Fig. 10A In the embodiment depicted in , the first insulating film 1016a includes a flowable layer 1018a. The flowable layer 1018a can be formed of an epoxy resin containing ceramic fillers, such as, for example, an epoxy resin filled with (e.g., containing) silica (SiO2) particles. Other examples of ceramic fillers or particles that can be used to form the flowable layer 1018a and other layers of the insulating film 1016a include aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12), magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the ceramic filler used to form the flowable layer 1018a has particles with a size range between about 40nm and about 1.5μm, such as, between about 80nm and about 1μm. For example, the ceramic filler used to form the flowable layer 1018a has particles with a size range between about 200nm and about 800nm, such as, between about 300nm and about 600nm. In some embodiments, the ceramic filler used to form the flowable layer 1018a includes particles having a size less than about 25% of the width or diameter of a desired feature (e.g., a via, a cavity, or a through-component via), such as, less than about 15% of the desired feature width or diameter.

[0078] The flowable layer 1018a typically has a thickness of less than about 60 μm, such as between about 5 μm and about 50 μm. For example, the flowable layer 1018a has a thickness between about 10 μm and about 25 μm. In some embodiments, the insulating film 1016a further includes one or more support layers. For example, the insulating film 1016a includes a lightweight plastic support layer 1022a of polyethylene terephthalate (PET) or similar. However, it is contemplated that any suitable combination of layers and insulating materials will be used for the insulating film 1016a. In some embodiments, the entire insulating film 1016a has a thickness of less than about 120 μm, such as less than about 90 μm.

[0079] The substrate 302 (which is coupled to the insulating film 1016a on the first side 1075 thereof, and specifically to the flowable layer 1018a of the insulating film 1016a) may further be placed on a carrier 1024 for mechanical support during later processing operations as appropriate. The carrier is formed of any suitable mechanically and thermally stable material. For example, the carrier 1024 is formed of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

[0080] At operation 904 and at Fig. 10B , one or more semiconductor dies 1026 are placed within a cavity 305 formed in substrate 302 such that semiconductor die 1026 is now on one side (on Fig. 10B1026) is bounded by insulating film 1016a. In some embodiments, die 1026 is a multi-purpose die having an integrated circuit formed on its active surface 1028. Die 1026 is placed within cavity 305 and positioned to the surface of insulating film 1016a exposed by cavity 305. In some embodiments, die 1026 is placed on an adhesive layer (not shown) disposed or formed on insulating film 1016a.

[0081] After placing die 1026 within cavity 305, at operation 906 and Fig. 10C 1060 is placed above the second side 1077 of the substrate 302 (e.g., above the surface 608). The protective film 1060 is coupled to the second side 1077 of the substrate 302 and opposite to the first insulating film 1016a so that it contacts and covers the active surface 1028 of the die 1026 disposed in the cavity 305. In some embodiments, the protective film 1060 is formed of a material similar to that of the support layer 1022a. For example, the protective film 1060 is formed of PET, such as biaxial PET. However, the protective film 1060 can be formed of any suitable protective material. In some embodiments, the protective film 1060 has a thickness between about 50 μm and about 150 μm.

[0082] At operation 908, the substrate 302 (now secured to the insulating film 1016a on the first side 1075 and the protective film 1060 on the second side 1077 and further having the die 1026 disposed therein) is exposed to a lamination process to bond the insulating film 1016 to the substrate 302, and more specifically to the coupling layer 316 formed on the substrate 302. During the lamination process, the substrate 302 is exposed to high temperatures, causing the flowable layer 1018a of the insulating film 1016a to soften and flow into the open voids or volumes between the insulating film 1016a and the protective film 1060, such as into the via 303 and into the gap 1051 between the inner wall of the cavity 305 and the die 1026. As a result, the semiconductor die 1026 becomes at least partially embedded within the material of the insulating film 1016a and the substrate 302, as shown in FIG. Fig. 10D Described in.

[0083] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed by using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C and lasts for a cycle between about 5 seconds and about 1.5 minutes, such as between about 30 seconds and about 1 minute. In some embodiments, the lamination process includes applying a pressure between about 1psig and about 50psig, while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016a for a cycle between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5psig and about 40psig, at a temperature between about 100°C and about 120°C for a cycle between about 10 seconds and about 1 minute. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 20 seconds.

[0084] At operation 910, the protective film 1060 is removed and the substrate 302 (now with the laminated insulating material of the flowable layer 1018a at least partially surrounding the substrate 302 and the one or more dies 1026) is placed on the second protective film 1062. Fig. 10E , the second protective film 1062 is coupled to the first side 1075 of the substrate 302 so that the second protective film 1062 is disposed against (e.g., adjacent to) the support layer 1022a of the insulating film 1016a. In some embodiments, the substrate 302 (now coupled to the protective film 1062) may be placed on a carrier 1024 for providing additional mechanical support on the first side 1075 as appropriate. In some embodiments, the protective film 1062 is placed on the carrier 1024 before coupling the protective film 1062 to the substrate 302, the protective film 1062 now being laminated with the insulating film 1016a. In general, the protective film 1062 is generally similar in composition to the protective film 1060. For example, the protective film 1062 may be formed of PET, such as biaxial PET. However, the protective film 1062 may be formed of any suitable protective material. In some embodiments, the protective film 1062 has a thickness between about 50 μm and about 150 μm.

[0085] After coupling the substrate 302 to the second protective film 1062, at operation 912 and Fig.10F, a second insulating film 1016b substantially similar to the first insulating film 1016a is placed on the second side 1077 of the substrate 302, thereby replacing the protective film 1060. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 so that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the tube core 1026 within the cavity 305. In some embodiments, placing the second insulating film 1016b on the substrate 302 can form one or more gaps between the insulating film 1016b and the laminated insulating material of the flowable layer 1018a that partially surrounds one or more tube cores 1026. The second insulating film 1016b may include one or more layers formed of a flowable, polymer-based dielectric material. As shown in FIG. Fig.10F , the second insulating film 1016b includes a flowable layer 1018b, which is similar to the flowable layer 1018a described above. The second insulating film 1016b may further include a support layer 1022b formed of a material similar to the support layer 1022a, such as PET or other lightweight plastic materials.

[0086] At operation 914, a third protective film 1064 is placed over the second insulating film 1016b, as shown in FIG. Figure 10G . In general, protective film 1064 is substantially similar in composition to protective films 1060, 1062. For example, protective film 1064 is formed of PET, such as biaxial PET. However, protective film 1064 may be formed of any suitable protective material. In some embodiments, protective film 1064 has a thickness between about 50 μm and about 150 μm.

[0087] At operation 916 and Fig. 10H 9, the substrate 302 is exposed to a second lamination process, the substrate 302 now being secured to the insulating film 1016b and support layer 1064 on the second side 1077 and the protective film 1062 and optional carrier 1024 on the first side 1075. Similar to the lamination process at operation 908, the substrate 302 is exposed to an elevated temperature, causing the flowable layer 1018b of the insulating film 1016b to soften and flow into any open voids or volumes between the insulating film 1016b and the laminated insulating material of the flowable layer 1018a, thereby integrating itself with the insulating material of the flowable layer 1018a. As a result, the cavity 305 and the via 303 become filled (e.g., packed, sealed) with insulating material, and the semiconductor die 1026 previously placed within the cavity 305 becomes fully embedded within the insulating material of the flowable layers 1018a, 1018b.

[0088] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed by using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C and lasts for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10psig and about 150psig, while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016b for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 20psig and about 100psig and a temperature between about 100°C and about 120°C for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of about 5 minutes.

[0089] After lamination, at operation 918, the substrate 302 is detached from the carrier 1024 and the protective films 1062, 1064 are removed, resulting in a laminated embedded die assembly 1002. Fig.10I , the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of a flowable layer 1018a, 1018b, and an embedded die 1026 within the cavity 305. The insulating dielectric material of the flowable layer 1018a, 1018b encapsulates the substrate 302 (and the coupling layer 316) such that the insulating material is disposed over at least two surfaces or sides (such as the two major surfaces 606, 608) of the substrate 302 and covers all sides of the embedded semiconductor die 1026. In some examples, the support layers 1022a, 1022b are also removed from the embedded die assembly 1002 at operation 918. In general, the support layers 1022 a and 1022 b , the carrier 1024 , and the protective films 1062 and 1064 are removed from the embedded die assembly 1002 by any suitable mechanical process, such as by peeling therefrom.

[0090] After removing the support layers 1022a, 1022b and the protective films 1062, 1064, the embedded die assembly 1002 is exposed to a curing process to fully cure (i.e., harden via chemical reaction and cross-linking) the insulating dielectric material of the flowable layers 1018a, 1018b, thereby forming a cured insulating layer 1018. The insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least the sides 1075, 1077 (including the surfaces 606, 608) of the substrate 302 and at least six sides or surfaces of each semiconductor die 1026, each of which has a rectangular prism shape, such as Fig. 10H, as illustrated in (ie, only four surfaces 1028 and 1029 are shown in the 2D view).

[0091] In some embodiments, the curing process is performed at an elevated temperature to fully cure the embedded die assembly 1002. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. for a period between about 15 minutes and about 45 minutes, such as at a temperature between about 160° C. and about 200° C. for a period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process at operation 916 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0092] After curing, at operation 920, one or more through-assembly vias 1003 are drilled through the embedded die assembly 1002, thereby forming a channel through the entire thickness of the embedded die assembly 1002 for subsequent interconnect formation. In some embodiments, the embedded die assembly 1002 may be placed on a carrier, such as carrier 1024, which is used for mechanical support during the formation of the through-assembly vias 1003 and subsequent contact holes 1032. The through-assembly vias 1003 are drilled through the holes 303 formed in the substrate 302 and subsequently filled with the insulating layer 1018. Thus, the through-assembly vias 1003 may be circumferentially surrounded by the insulating layer 1018 filled in the vias 303 as well as the coupling layer 316 and the substrate 302. By lining the walls of via 303 with the ceramic filler-containing epoxy material of insulating layer 1018, the completed package 1602 (see FIG. Fig.15 and Figure 16K and Figure 16L Description), the conductive silicon-based substrate 302 and the interconnect 1444 (reference Fig.13 and FIG. 14E to FIG. 14H ) and thus the capacitive coupling between adjacently positioned vias 303 and / or redistribution connectors 1644 (refer to Fig.15 and FIG. 16H to FIG. 16L In addition, the flowable nature of the epoxy material enables more consistent and reliable packaging and insulation, thereby enhancing electrical performance by minimizing leakage current of the completed package 1602.

[0093] In some embodiments, the through-component via 1003 has a diameter less than about 100 μm, such as less than about 75 μm. For example, the through-component via 1003 has a diameter less than about 60 μm, such as less than about 50 μm. In some embodiments, the through-component via 1003 has a diameter between about 25 μm and about 50 μm, such as between about 35 μm and about 40 μm. In some embodiments, the through-component via 1003 is formed using any suitable mechanical process. For example, the through-component via 1003 is formed using a mechanical drilling process. In some embodiments, the through-component via 1003 is formed through the embedded die component 1002 by laser ablation. For example, the through-component via 1003 is formed using an ultraviolet laser. In some embodiments, the laser source used for laser ablation has a frequency between about 5 kHz and about 500 kHz. In certain embodiments, the laser source is configured to deliver a pulsed laser beam with a pulse duration between about 10 ns and about 100 ns, with a pulse energy between about 50 microjoules (μJ) and about 500 μJ. Utilizing an epoxy material with small ceramic filler particles further facilitates more precise and accurate laser patterning of small diameter vias, such as via 1003, because the small ceramic filler particles therein exhibit reduced reflection, scattering, diffraction, and transmission of the laser light away from the area where the via is to be formed during the laser ablation process.

[0094] At operation 922 and Figure 10K In the embodiment, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. The contact holes 1032 are drilled through the insulating layer 1018 by laser ablation so that all outer surfaces of the semiconductor die 1026 are covered and surrounded by the insulating layer 1018 and the contacts 1030 are exposed. Therefore, the contacts 1030 are exposed by forming the contact holes 1032. In some embodiments, the laser source may generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In some embodiments, the laser source is configured to deliver a pulse having a wavelength between about 100 nm and about 2000 nm and a pulse duration of about 1.0×10 -3 ns and about 1.0×10 -1 A pulsed laser beam with a pulse energy between about 10 μJ and about 300 μJ is used. In some embodiments, a CO2, green or UV laser is used to drill the contact hole 1032. In some embodiments, the contact hole 1032 has a diameter between about 5 μm and about 60 μm, such as between about 20 μm and about 50 μm.

[0095] After forming the contact hole 1032, the embedded die assembly 1002 is exposed to a decontamination process at operation 922 to remove any undesirable residues and / or debris caused by laser ablation during the formation of the through assembly via 1003 and the contact hole 1032. The decontamination process thus cleans the through assembly via 1003 and the contact hole 1032 and fully exposes the contact 1030 on the active surface 1028 of the embedded die 1026 for subsequent metallization. In some embodiments, the decontamination process is a wet decontamination process. Any suitable aqueous etchant, solvent and / or combination thereof can be used for the wet decontamination process. In one example, a potassium permanganate (KMnO4) solution can be used as an etchant. Depending on the thickness of the residue, changes can be made to exposing the embedded die assembly 1002 to the wet decontamination process at operation 922. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process may be a plasma decontamination process using an O2:CF4 mixed gas. The plasma decontamination process may include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a time period between about 60 seconds and about 120 seconds. In further embodiments, the decontamination process is a combination of wet and dry processes.

[0096] After the decontamination process at operation 922, the embedded die assembly 1002 is ready for forming interconnect paths therein, as described below with reference to Fig.13 and FIG. 14A to FIG. 14H describe.

[0097] As mentioned above, Fig. 9 and FIG. 10A to FIG. 10K A representative method 900 for forming an intermediate embedded die assembly 1002 is illustrated. Fig.11 and FIG. 12A to FIG. 12G An alternative method 1100 is illustrated that is substantially similar to method 900, but has fewer operations. Method 1100 generally includes eight operations 1110-1180. However, operations 1110, 1120, 1160, and 1190 of method 1100 are substantially similar to operations 902, 904, 920, and 922, respectively, of method 900. Therefore, for clarity, only operations 1130, 1140, and 1150 (in Fig. 12C , Fig.12D and Fig.12E (depicted in).

[0098] After placing one or more semiconductor dies 1026 on the surface of the insulating film 1016a exposed through the cavity 305, before lamination, at operation 1130 and Fig. 12CThe second insulating film 1016b is positioned over the second side 1077 of the substrate 302. In some embodiments, the second insulating film 1016b is positioned on the second side 1077 of the substrate 302 such that the flowable layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within the cavity 305. In some embodiments, the second carrier 1025 is secured to the support layer 1022b of the second insulating film 1016b for providing additional mechanical support during later processing operations. Fig. 12C As depicted in , one or more gaps 1050 are formed between insulating films 1016 a and 1016 b via vias 303 and gaps 1051 between semiconductor die 1026 and the inner wall of cavity 305 .

[0099] At operation 1140 and Fig.12D , the substrate 302 (now secured to the insulating films 1016a and 1016b and having the die 1026 disposed therein) is exposed to a single lamination process to bond both the insulating films 1016a and 1016b to the substrate 302, and more specifically to the coupling layer 316. During the single lamination process, the substrate 302 is exposed to an elevated temperature, causing the flowable layers 1018a and 1018b of both the insulating films 1016a, 1016b to soften and flow into the open voids or volumes between the insulating films 1016a, 1016b, such as into the gap 1051 between the inner walls of the via 303 and the cavity 305 and the die 1026. As a result, the semiconductor die 1026 becomes embedded within the material of the insulating films 1016a, 1016b and the via 303 filled with the material.

[0100] Similar to reference Fig. 9 and FIG. 10A to FIG. 10K The lamination process described, the lamination process at operation 1140 may be a vacuum lamination process, which may be performed in an autoclave or other suitable equipment. In another embodiment, the lamination process is performed by using a hot pressing process. In certain embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C and lasts for a cycle between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1psig and about 150psig, while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1016a, 1016b layer for a cycle between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10psig and about 100psig, at a temperature between about 100°C and about 120°C for a cycle between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a cycle of about 5 minutes.

[0101] At operation 1150, one or more supporting layers of insulating films 1016a and 1016b are removed from substrate 302, thereby obtaining a laminated embedded die assembly 1002. Fig.12E , the embedded die assembly 1002 includes a substrate 302 having one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of a flowable layer 1018a, 1018b, and an embedded die 1026 within the cavity 305. The insulating material encapsulates the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, e.g., surfaces 606, 608. In one example, the support layers 1022a, 1022b are removed from the embedded die assembly 1002, and thus the embedded die assembly 1002 is released from the carrier 1024, 1025. Typically, the support layers 1022a, 1022b and the carrier 1024, 1025 are removed by any suitable mechanical process, such as peeling therefrom.

[0102] After the support layers 1022a, 1022b are removed, the embedded die assembly 1002 is exposed to a curing process to fully cure the insulating dielectric material of the flowable layers 1018a, 1018b. Curing the insulating material results in the formation of a cured insulating layer 1018. Fig.12E Depicted in and similar to Fig.10I Corresponding to operation 918 , insulating layer 1018 substantially surrounds substrate 302 and semiconductor die 1026 embedded therein.

[0103] In some embodiments, the curing process is performed at an elevated temperature to fully cure the embedded die assembly 1002. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. for a period between about 15 minutes and about 45 minutes, such as at a temperature between about 160° C. and about 200° C. for a period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In further embodiments, the curing process at operation 1150 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0104] After curing at operation 1150, method 1100 is substantially similar to operations 920 and 922 of method 900. For example, embedded die assembly 1002 has one or more through-assembly vias 1003 and one or more contact holes 1032 drilled through insulating layer 1018. Subsequently, embedded die assembly 1002 is exposed to a desmear process, after which embedded die assembly 1002 is ready for forming interconnect paths therein, as described below.

[0105] Fig.13A flow chart of a representative method 1300 of forming electrical interconnects through an embedded die assembly 1002 is shown. FIG. 14A to FIG. 14H The embedded die assembly 1002 is schematically shown in FIG. Fig.13 1300 at different stages of the process. Therefore, for the sake of clarity, the present invention describes Fig.13 and FIG. 14A to FIG. 14H .

[0106] In some embodiments, the electrical interconnects formed through the embedded die assembly 1002 are formed of copper. Thus, the method 1300 may optionally be performed with operations 1310 and 1320. Fig.14A Initially, here the embedded die assembly 1002 (having through assembly vias 1003 and contact holes 1032 formed therein) has an adhesive layer 1440 and / or a seed layer 1442 formed thereon. For reference, Fig.14H 14 and 14. An enlarged partial view of the adhesive layer 1440 and the seed layer 1442 formed on the embedded die assembly 1002 is depicted in FIG. The adhesive layer 1440 may be formed on the desired surface of the insulating layer 1018, such as the major surfaces 1005, 1007 of the embedded die assembly 1002, and on the active surface 1028 of the contact hole 1032 on each die 1026 and the inner wall of the through assembly via 1003 to assist in promoting adhesion and blocking the diffusion of the subsequently formed seed layer 1442 and copper interconnect 1444. Thus, in some embodiments, the adhesive layer 1440 acts as an adhesive layer; in another embodiment, the adhesive layer 1440 acts as a barrier layer. However, in both embodiments, the adhesive layer 1440 will be described as an "adhesion layer" hereinafter.

[0107] In some embodiments, the optional adhesion layer 1440 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In some embodiments, the adhesion layer 1440 has a thickness between about 10 nm and about 300 nm, such as, between about 50 nm and about 150 nm. For example, the adhesion layer 1440 has a thickness between about 75 nm and about 125 nm, such as, about 100 nm. The adhesion layer 1440 is formed by any suitable deposition process, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (plasma enhanced CVD; PECVD), atomic layer deposition (atomic layer deposition; ALD), etc.

[0108] Optional seed layer 1442 may be formed on bonding layer 1440 or directly on insulating layer 1018 (e.g., without forming bonding layer 1440). Seed layer 1442 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In some embodiments, seed layer 1442 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, seed layer 1442 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In some embodiments, seed layer 1442 has a thickness between about 0.1 μm and about 1.5 μm. Similar to bonding layer 1440, seed layer 1442 is formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In certain embodiments, a molybdenum adhesion layer 1440 is formed on the embedded die assembly, in combination with a copper seed layer 1442. The Mo-Cu adhesion and seed layer combination enables improved adhesion to the surface of the insulating layer 108 and reduced undercutting of the conductive interconnects during the subsequent seed layer etch process at operation 1370.

[0109] At operations 1320 and 1330 (corresponding to Fig. 14B and Fig. 14C ), a spin-coated / spray-coated or dry resist film 1450 (such as a photoresist) is applied on the two major surfaces 1005, 1007 of the embedded die assembly 1002, and then patterned. In some embodiments, the resist film 1450 is patterned by selective exposure to UV radiation. In some embodiments, before forming the resist film 1450, an adhesion promoter (not shown) is applied to the embedded die assembly 1002. The adhesion promoter improves the adhesion of the resist film 1450 to the embedded die assembly 1002 by creating an interfacial bonding layer for the resist film 1450 and by removing any moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed of bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0110] At operation 1340 and Fig.14D In the embodiment, the embedded die assembly 1002 is exposed to a resist film development process. Fig.14D, the development of the resist film 1450 results in the exposure of the through-component via 1003 and the contact hole 1032, which now have the adhesion layer 1440 and the seed layer 1442 formed thereon. In some embodiments, the film development process is a wet process, such as a wet process that includes exposing the resist to a solvent. In some embodiments, the film development process is a wet etching process that utilizes an aqueous etching process. In other embodiments, the film development process is a wet etching process that utilizes a buffered etching process that is selective to the desired material. Any suitable wet solvent or combination of wet etchants can be used for the resist film development process.

[0111] At operations 1350 and 1360 (corresponding to Fig.14E and Fig.14F ), forming interconnection 1444 passing through the exposed through-component via 1003 and contact hole 1032, and then removing resist film 1450. Interconnection 1444 is formed by any suitable method including electroplating and electroless deposition. In some embodiments, resist film 1450 is removed via a wet process. Fig.14E and Fig.14F , after removing the resist film 1450, the formed interconnect 1444 fills the through-component via 1003 and the contact hole 1032 and / or covers the inner circumferential wall thereof and protrudes from the surface 1005, 1007 and 1028 of the embedded die component 1002. In some embodiments, the interconnect 1444 is formed of copper. In other embodiments, the interconnect 1444 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0112] At operation 1370 and Figure 14G In some embodiments, the embedded die assembly 1002 having the interconnect 1444 formed therein is exposed to an adhesion layer and / or seed layer etching process to remove the adhesion layer 1440 and the seed layer 1442. In some embodiments, the seed layer etching is a wet etching process that includes rinsing and drying of the embedded die assembly 1002. In some embodiments, the seed layer etching process is a buffered etching process that is selective to the desired material (such as copper, tungsten, aluminum, silver, or gold). In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0113] After the seed layer etching process at operation 1370, one or more electrically functional packages may be cut from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 may optionally have one or more redistribution layers 1658 and / or 1660 formed thereon (in the Figures 16K to 16L), so that the contact points of the interconnect 1444 can be rerouted to the desired locations on the surface of the embedded tube die assembly 1002. Fig.15 A flow chart of a representative method 1500 of forming a redistribution layer 1658 on an embedded die assembly 1002 is shown. FIG. 16A to FIG. 16L The embedded die assembly 1002 is schematically shown in FIG. Fig.15 1500 at different stages of the method 1500 depicted in FIG. Therefore, for the sake of clarity, the present invention will be described together. Fig.15 and FIG. 16A to FIG. 16L .

[0114] Method 1500 is substantially similar to methods 900, 1100, and 1300 described above. In general, method 1500 includes operations 1502 and Fig.16A Initially, an insulating film 1616 is placed on the embedded die assembly 1002 and then laminated. The insulating film 1616 may be substantially similar to the insulating film 1016 and include one or more layers formed of a polymer-based flowable dielectric material. In some embodiments, such as Fig.16A , the insulating film 1616 includes a flowable layer 1618 and one or more support layers 1622. In some embodiments, the insulating film 1616 may include a flowable layer 1618 of epoxy resin containing ceramic filler and one or more support layers 1622. In another example, the insulating film 1616 may include a photo-definable polyimide flowable layer 1618 and one or more support layers 1622. The material properties of the photo-definable polyimide enable the formation of smaller (e.g., narrower) vias through the resulting interconnect layer formed therefrom. However, it is contemplated that any suitable combination of layers and insulating materials will be used for the insulating film 1616. For example, the insulating film 1616 may include a non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide and / or silicon nitride flowable layer 1618. Examples of suitable materials for one or more support layers 1622 include PET and polypropylene (PP).

[0115] In some examples, flowable layer 1618 includes a polymer-based flowable dielectric material different from flowable layers 1018a, 1018b described above. For example, flowable layer 1018 may include an epoxy resin containing ceramic fillers, and flowable layer 1618 may include a photo-definable polyimide. In another example, flowable layer 1618 is formed of an inorganic dielectric material different from flowable layers 1018a, 1018b. For example, flowable layers 1018a, 1018b may include an epoxy resin containing ceramic fillers, and flowable layer 1618 may include a silicon dioxide layer.

[0116] The insulating film 1616 has a thickness of less than about 200 μm, such as, a thickness between about 10 μm and about 180 μm. For example, the insulating film 1616 including the flowable layer 1618 and the PET support layer 1622 has a total thickness between about 50 μm and about 100 μm. In some embodiments, the flowable layer 1618 has a thickness of less than about 60 μm, such as a thickness between about 5 μm and about 50 μm, such as a thickness of about 20 μm. The insulating film 1616 is placed on the surface of the embedded tube core assembly 1002 having the exposed interconnect 1444, which is coupled to the contact 1030 on the active surface 1028 of the tube core 1026 and / or coupled to the metallized straight-through assembly via 1003, such as, the main surface 1005.

[0117] After the insulating film 1616 is placed, the embedded die assembly 1002 is exposed to a lamination process that is substantially similar to the lamination process described with reference to operations 908, 916, and 1140. The embedded die assembly 1002 is exposed to an elevated temperature to soften the flowable layer 1618, which is then bonded to the insulating layer 1018 that has been formed on the embedded die assembly 1002. Thus, in certain embodiments, the flowable layer 1618 becomes integrated with the insulating layer 1018 and forms an extension thereof. The integration of the flowable layer 1618 with the insulating layer 1018 results in the expanded and integrated insulating layer 1018 covering the previously exposed interconnects 1444. Thus, the bonded flowable layer 1618 and the insulating layer 1018 will be collectively described herein as the insulating layer 1018. However, in other embodiments, the lamination and subsequent curing of the flowable layer 1618 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a material layer different from the insulating layer 1018 .

[0118] In some embodiments, the lamination process is a vacuum lamination process, which can be performed in an autoclave or other suitable equipment. In some embodiments, the lamination process is performed by using a hot pressing process. In some embodiments, the lamination process is performed at a temperature between about 80°C and about 140°C and lasts for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10psig and about 100psig, while applying a temperature between about 80°C and about 140°C to the substrate 302 and the insulating film 1616 for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30psig and about 80psig and a temperature between about 100°C and about 120°C for a period between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for a period of about 5 minutes. In a further example, the lamination process is performed at a pressure between about 30psig and about 70psig, such as about 50psig.

[0119] At operation 1504 and Fig. 16B , the support layer 1622 and the carrier 1624 are removed from the embedded die assembly 1002 by a mechanical process. After the support layer 1622 and the carrier 1624 are removed, the embedded die assembly 1002 is exposed to a curing process to fully cure the newly expanded insulating layer 1018. In some embodiments, the curing process is substantially similar to the curing process described with reference to operations 918 and 1150. For example, the curing process is performed at a temperature between about 140° C. and about 220° C. and for a period between about 15 minutes and about 45 minutes, such as, at a temperature between about 160° C. and about 200° C. and for a period between about 25 minutes and about 35 minutes. For example, the curing process is performed at a temperature of about 180° C. for a period of about 30 minutes. In a further embodiment, the curing process at operation 1504 is performed under ambient pressure conditions or near ambient pressure conditions.

[0120] Then at operation 1506 and Fig. 16CIn some embodiments, the embedded die assembly 1002 is selectively patterned by laser ablation. The laser ablation at operation 1506 forms a redistribution via 1603 that passes through the newly expanded insulating layer 1018 and exposes the required interconnect 1444 for redistribution of its contact points. In some embodiments, the redistribution via 1603 has a diameter between about 5 μm and about 60 μm, such as a diameter between about 10 μm and about 50 μm, such as between about 20 μm and about 45 μm. In some embodiments, the laser ablation process at operation 1506 is performed using a CO2 laser. In some embodiments, the laser ablation process at operation 1506 is performed using a UV laser. In some embodiments, the laser ablation process at operation 1506 is performed using a green laser. For example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulse having a wavelength between about 100 nm and about 2000 nm and a pulse duration between about 1.0×10 -3 ns and about 1.0×10 -1 ns and wherein the pulse energy is between about 10 μJ and about 300 μJ.

[0121] After patterning the embedded die assembly 1002, the embedded die assembly 1002 is exposed to a decontamination process, which is substantially similar to the decontamination process at operations 922 and 1180. During the decontamination process at operation 1506, undesirable residues and debris formed by laser ablation during the formation of the redistribution vias 1603 are removed from the redistribution vias 1603 to clean (e.g., clean) their surfaces for subsequent metallization. In some embodiments, the decontamination process is a wet process. Any suitable aqueous etchant, solvent, and / or combination thereof may be used for the wet decontamination process. In one example, a KMnO4 solution may be used as an etchant. In another embodiment, the decontamination process is a dry decontamination process. For example, the decontamination process may be a plasma decontamination process performed by an O2:CF4 mixed gas. In a further embodiment, the decontamination process is a combination of wet and dry processes.

[0122] At operation 1508 and Fig.16D, an optional adhesion layer 1640 and / or seed layer 1642 are formed on insulating layer 1018. In some embodiments, adhesion layer 1640 is formed of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combination thereof. In some embodiments, adhesion layer 1640 has a thickness between about 10 nm and about 300 nm, such as between about 50 nm and about 150 nm. For example, adhesion layer 1640 has a thickness between about 75 nm and about 125 nm, such as about 100 nm. Adhesion layer 1640 can be formed by any suitable deposition process, including but not limited to CVD, PVD, PECVD, ALD, etc.

[0123] The optional seed layer 1642 is formed of a conductive material, such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In some embodiments, the seed layer 1642 has a thickness between about 50 nm and about 500 nm, such as between about 100 nm and about 300 nm. For example, the seed layer 1642 has a thickness between about 150 nm and about 250 nm, such as about 200 nm. In some embodiments, the seed layer 1642 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesion layer 1640, the seed layer 1642 can be formed by any suitable deposition process, such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In some embodiments, the molybdenum adhesion layer 1640 and the copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce the undercut of the conductive interconnect line during the subsequent seed layer etching process at operation 1520.

[0124] At operations 1510, 1512, and 1514 (corresponding to Fig.16E , Fig.16F and Figure 16G), a spin-coated / sprayed or dried resist film 1650 (such as a photoresist) is applied over the bonding surface and / or seed surface of the embedded die assembly 1002, and then the resist film 1650 is patterned and developed. In some embodiments, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 before the resist film 1650 is placed. The exposure and development of the resist film 1650 causes the redistribution vias 1603 to open. Therefore, the patterning of the resist film 1650 can be performed by selectively exposing a portion of the resist film 1650 to UV radiation and then developing the resist film 1650 by a wet process (such as a wet etching process). In some embodiments, the resist film development process is a wet etching process using a buffered etching process that is selective to the desired material. In other embodiments, the resist film development process is a wet etching process using an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the resist film development process.

[0125] At operations 1516 and 1518 (corresponding to Fig.16H and Fig.16I ), forming a redistribution connector 1644 passing through the exposed redistribution via 1603, and then removing the resist film 1650. The redistribution connector 1644 is formed by any suitable method including electroplating and electroless deposition. In some embodiments, the resist film 1650 is removed via a wet process. Fig.16H and Fig.16I , after removing the resist film 1650, the redistribution connectors 1644 fill the redistribution vias 1603 and protrude from the surface of the embedded die assembly 1002. In some embodiments, the redistribution connectors 1644 are formed of copper. In other embodiments, the redistribution connectors 1644 may be formed of any suitable conductive material, including but not limited to aluminum, gold, nickel, silver, palladium, tin, etc.

[0126] At operation 1520 and Fig.16J In operation 1370, the embedded die assembly 1002 with the redistribution connectors 1644 formed thereon is exposed to a seed layer etching process that is substantially similar to the seed layer etching process of operation 1370. In some embodiments, the seed layer etching is a wet etching process that includes rinsing and drying of the embedded die assembly 1002. In some embodiments, the seed layer etching process is a wet etching process that utilizes a buffered etching process that is selective to the desired material of the seed layer 1642. In other embodiments, the etching process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used for the seed layer etching process.

[0127] At operation 1522 and at Figure 16K and Figure 16L1002, one or more completed packages 1602 are cut from the embedded die assembly 1002. However, prior to operation 1522, additional redistribution layers may be formed on the embedded die assembly 1002 using the sequence and process described above, such as Figure 16L Described in ( Figure 16K 16. Depicted is a completed package 1602 with one additional redistribution layer 1658. For example, one or more additional redistribution layers 1660 may be formed on a side or surface (such as major surface 1007) of embedded die assembly 1002 opposite to first additional redistribution layer 1658. Alternatively, one or more additional redistribution layers 1660 may be formed on the same side or surface (such as major surface 1005) of first additional redistribution layer 1658 (not shown). After all desired redistribution layers are formed, completed packages 1602 may then be cut from embedded die assembly 1002.

[0128] Fig.17 An exemplary package manufacturing system 1700 for use with the methods described herein is schematically illustrated. The performance of the operations described herein is achieved in an efficient and streamlined manner using system 1700, thereby facilitating improved manufacturing of semiconductor packaged devices. System 1700 may include one or more processing stations 1702, each of which is configured to perform one or more operations for manufacturing semiconductor packaged devices (such as, package 1602). Processing stations 1702 may be arranged in sequence with one or more transfer robots 1704 or other transfer devices disposed therebetween, or processing stations 1702 may be arranged around a centrally disposed transfer robot 1704 or transfer device (e.g., such as on a platform-type device), such as Fig.17 As shown in Fig.17 In the example of , system 1700 is shown as having four processing stations 1702a, 1702b, 1702c, and 1702d, which can each be used to perform one or more different operations. For example, processing station 1702a may include a laser ablation system for constructing a substrate to be used as a package frame; processing station 1702b may include a coupling layer station, such as a CVD chamber, for forming a coupling layer on the substrate; processing station 1702c may include a lamination / curing system, such as a processing chamber or an oven, for performing lamination and / or curing of an insulating layer; and processing station 1702d may include a metallization station for electroplating or interconnection. However, fewer or additional processing stations are also contemplated.

[0129] Now turn Fig.18A and Fig.18B , the package structures formed by the methods described herein, such as package 1602, can be utilized in any suitable packaging application and in any suitable configuration. Fig.18AIn one exemplary embodiment depicted in , four packages 1602 are utilized to form a stacked DRAM structure 1800. Thus, each package 1602 includes a memory die 1826 (i.e., a memory chip) embedded within the substrate 302 and encapsulated by the insulating layer 1018 (e.g., with a portion of each side in contact with the insulating layer 1018). One or more interconnects 1444 are formed to pass through the entire thickness of each package 1602 and to be in direct contact with one or more solder bumps 1846 disposed between the major surfaces 1005 and 1007 of adjacent (i.e., stacked above or below) packages 1602. For example, as depicted in the stacked DRAM structure 1800, four or more solder bumps 1846 are disposed between adjacent packages 1602 to bridge (e.g., connect, couple) the interconnects 1444 of each package 1602 with the interconnects 1444 of adjacent packages 1602.

[0130] In some embodiments, the gaps between adjacent packages 1602 connected by solder bumps 1848 are filled with encapsulation material 1846 to enhance the reliability of solder bumps 1846. Encapsulation material 1848 can be any suitable type of encapsulant or underfill. In one example, encapsulation material 1848 includes pre-assembly underfill material, such as no-flow underfill (NUF) material, nonconductive paste (NCP) material, and nonconductive film (NCF) material. In one example, encapsulation material 1848 includes post-assembly underfill material, such as capillary underfill (CUF) material and molded underfill (MUF) material. In some embodiments, encapsulation material 1848 includes a resin containing a low expansion filler, such as, filled with (e.g., containing) SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O16, ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12 , MgO, TiO2, ZnO and other epoxy resins.

[0131] In some embodiments, solder bump 1846 is formed by one or more intermetallic compounds, such as a combination of tin (Sn) and lead (Pb), silver (Ag), Cu or any other suitable metal therein. For example, solder bump 1846 is formed by a solder alloy, such as Sn-Pb, Sn-Ag, Sn-Cu or any other suitable material or combination thereof. In some embodiments, solder bump 1846 includes a C4 (controlled collapse chip connection) bump. In some embodiments, solder bump 1846 includes a C2 (chip connection, such as a Cu column with a solder cap) bump. C2 solder bumps are used to achieve a smaller spacing between contact pads and improved thermal and / or electrical properties of stacked DRAM structure 1800. In some embodiments, solder bump 1846 has a diameter between about 10 μm and about 150 μm, such as a diameter between about 50 μm and about 100 μm. The solder bumps 1846 may further be formed by any suitable flip chip bonding process, including but not limited to electrochemical deposition (ECD) and electroplating.

[0132] exist Fig.18B In another exemplary embodiment depicted in , a stacked DRAM structure 1801 is formed by stacking four packages 1602 and directly bonding one or more interconnects 1444 of each package 1602 to the interconnects 1444 of one or more adjacent packages 1602. As depicted, the packages 1602 may be bonded by hybrid bonding, wherein the major surfaces 1005 and 1007 of adjacent packages are planarized and in full contact with each other. Thus, the one or more interconnects 1444 of each package 1602 are formed to pass through the entire thickness of each package 1602 and to be in direct contact with the one or more interconnects 1444 of at least another adjacent package 1602.

[0133] The stacked DRAM structures 1800 and 1801 provide multiple advantages over conventional DRAM structures. These benefits include thinness and high die-to-package volume ratio, which enables greater I / O scalability to meet the growing bandwidth and power efficiency needs of artificial intelligence (AI) and high performance computing (HPC). Utilizing a constructed silicon frame provides optimal material stiffness and thermal conductivity to obtain improved electrical performance, thermal management, and reliability of three-dimensional integrated circuit (3D IC) architectures. In addition, the manufacturing methods for through-component vias and via-in-via structures described herein provide high performance and flexibility of 3D integration at a relatively low manufacturing cost compared to conventional TSV technology.

[0134] The embodiments described herein advantageously provide improved methods for substrate construction and die assembly for manufacturing advanced integrated circuit packages. By utilizing the above methods, high aspect ratio features can be formed on glass and / or silicon substrates, thereby achieving economical formation of thinner and narrower semiconductor device packages. The thin and small packages manufactured by utilizing the above methods provide benefits, not only providing high I / O density and improved bandwidth and power, but also providing greater thermomechanical reliability through improved stress distribution. Other advantages of the above methods include economical manufacturing with dual-sided metallization capabilities and high yields by eliminating flip chip attachment and overmolding steps (which are prone to feature damage in high-volume manufacturing of conventional and advanced packages).

[0135] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, and the scope of the disclosure is determined by the following claims.

Claims

1. A packaging component, comprising: A frame having a first surface opposite to a second surface, the frame further comprising: A frame material including a first material, wherein the first material includes silicon; at least one cavity having a semiconductor die disposed in the at least one cavity; a via including a via surface defining an opening extending from the first surface through the frame to the second surface; and a coupling layer formed on the frame, the coupling layer comprising a silane coupling agent and contacting at least the first surface and the second surface; an insulating layer disposed over the coupling layer on the first and second surfaces of the frame, the insulating layer contacting at least a portion of each side of the semiconductor die; and An electrical interconnect is disposed in the via, wherein the insulating layer and the coupling layer are disposed between a surface of the via and the electrical interconnect. 2 . The package assembly of claim 1 , wherein the first material comprises silicon carbide or silicon nitride. 3 . The package assembly of claim 1 , wherein the at least one cavity extends from the first surface to the second surface. 4 . The package assembly of claim 1 , wherein the insulating layer extends from the first surface to the second surface through the via and the at least one cavity. The package assembly of claim 1 , wherein the insulating layer comprises an epoxy material.

6. The package assembly of claim 5, wherein the epoxy material further comprises ceramic particles having a size ranging between about 40 nm and about 1.5 μm.

7. The package assembly of claim 6, wherein the ceramic particles include one or more of the following: aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 Ceramics, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), and zinc oxide (ZnO).

8. The package assembly of claim 1, wherein the coupling layer further contacts one or more sidewalls of the at least one cavity and the via surface.

9. The packaging assembly of claim 1, wherein the silane coupling agent comprises a vinyl functional group, an epoxy functional group, a styrene functional group, an acryl functional group, a methacryl functional group, a methacryl functional group, an amine functional group, a phenyl functional group, a urea functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

10. A packaging component, comprising: Embedded die assembly, comprising: a frame comprising a first material, wherein the first material comprises silicon; A coupling layer, disposed above the frame, wherein the coupling layer comprises a silane coupling agent; one or more semiconductor dies disposed within the frame, the one or more semiconductor dies having integrated circuits formed thereon; and an insulating layer formed on the coupling layer, the insulating layer comprising an epoxy resin material having ceramic particles disposed therein; and One or more metal interconnects are disposed within a portion of the embedded die assembly.

11. The package assembly of claim 10, wherein the frame further comprises: one or more cavities extending from the first surface of the frame to the second surface of the frame, the one or more cavities having the one or more semiconductor dies embedded in the one or more cavities; as well as One or more vias are formed in the frame, each of the one or more vias comprising a via surface defining an opening extending through the frame from the first surface to the second surface, wherein the one or more metal interconnects are disposed to pass through the one or more vias. 12 . The package assembly of claim 11 , wherein the coupling layer contacts at least the first surface and the second surface.

13. The package assembly of claim 12, wherein the coupling layer further contacts one or more sidewalls of the one or more cavities and the via surface. 14 . The package assembly of claim 11 , wherein the insulating layer extends from the first surface to the second surface through the one or more vias and the one or more cavities.

15. The package assembly of claim 10, wherein the ceramic particles include one or more of the following: aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 Ceramics, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12 ), magnesium oxide (MgO), titanium dioxide (TiO2), and zinc oxide (ZnO).

16. The package assembly of claim 10, wherein the silane coupling agent comprises a vinyl functional group, an epoxy functional group, a styrene functional group, an acryl functional group, a methacryl functional group, a methacryl functional group, an amine functional group, a phenyl functional group, a urea functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

17. A packaging component, comprising: Embedded die assembly, comprising: a frame comprising a first material, wherein the first material comprises silicon; a coupling layer formed over the frame and comprising a silane coupling agent; one or more semiconductor dies disposed within the frame; a first insulating layer formed on the frame, the first insulating layer comprising an epoxy resin material, the epoxy resin material comprising ceramic particles; and one or more electrical interconnects disposed through the frame or the first insulating layer; and a redistribution layer formed on the embedded die assembly, the redistribution layer comprising: a second insulating layer formed on the first insulating layer; and One or more electrical redistribution connectors are disposed through the second insulating layer.

18. The packaging assembly of claim 17, wherein the silane coupling agent comprises a vinyl functional group, an epoxy functional group, a styrene functional group, an acryl functional group, a methacryl functional group, a methacryl functional group, an amine functional group, a phenyl functional group, a urea functional group, an isocyanate functional group, an isocyanurate functional group, or a mercapto functional group.

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