Vertical IGBT with complementary channel for hole extraction

Abstract

A semiconductor device (100) includes a semiconductor device body (1) having a top side (10), a main electrode (2) and a gate electrode (3) on the top side. The semiconductor body comprises a drift layer (11) of a first conductivity type, a first base region (12) of a second conductivity type, a second base region (13) of the first conductivity type, a first contact region (14) of the first conductivity type, and a second contact region (15) of the second conductivity type. The second base region has a greater doping concentration than the drift layer. The first contact region adjoins the first base region and the top side. The second contact region adjoins the second base region and the top side. The main electrode is in electrical contact with the first contact region and the second contact region. In the first lateral direction, at least a portion of the gate electrode is disposed between the first contact region and the second contact region. When turned off, a hole reversal channel is induced in the second base region (13) to extract holes.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and to a method for manufacturing a semiconductor device. Background Art

[0002] There is a need for an improved semiconductor device, for example, a semiconductor device that can effectively remove charge carriers (eg, holes) from a semiconductor body during a turn-off transient without compromising on-state losses. There is also a need for an improved method for manufacturing such a semiconductor device. Summary of the invention

[0003] Embodiments of the present disclosure relate to an improved semiconductor device and an improved method for manufacturing the semiconductor device.

[0004] First, specify the semiconductor device.

[0005] According to an embodiment, a semiconductor device includes a semiconductor body having a top side, a main electrode on the top side, and a gate electrode. The semiconductor body includes a drift layer of a first conductivity type. The semiconductor body further includes a first base region of a second conductivity type vertically arranged between the drift layer and the top side. In addition, the semiconductor body also includes a second base region of the first conductivity type vertically arranged between the drift layer and the top side. The second base region has a greater doping concentration than the drift layer and is adjacent to the drift layer. In addition, the semiconductor body also includes a first contact region of the first conductivity type. The first contact region is adjacent to the first base region and the top side. In addition, the semiconductor body also includes a second contact region of the second conductivity type. The second contact region is adjacent to the second base region and the top side. The main electrode is in electrical contact with the first contact region and the second contact region. In a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region and between the first base region and the second base region.

[0006] Bipolar semiconductor devices (such as IGBTs) are devices in which both electrons and holes participate in the conduction process. The injection of both electrons and holes leads to the formation of a high-density plasma in the drift layer, which reduces the resistance of this layer and thus reduces the losses during the on-state. However, during the off-state, the stored plasma needs to be removed quickly in order to minimize the switching losses. Therefore, there is a trade-off between the on-state voltage drop (Vce-sat) and the off-switching losses (Eoff) of such devices.

[0007] In the present invention, a complementary transistor for controlled extraction of a second type of charge carriers (e.g., holes) is introduced by means of a second base region and a second contact region. The complementary transistor provides an additional extraction path for the second type of charge carriers that remain valid only during the off period of the main transistor, wherein the main transistor includes a first base region and a first contact region. Therefore, the switching loss of the semiconductor device is reduced without compromising its on state. The function of the semiconductor device is not limited by, for example, the trench spacing. In addition, since no additional gate connection is required, the Miller capacitance (Cgc) is not adversely affected. This concept is applied, for example, to MOS-based bipolar devices such as IGBTs, reverse-conducting (RC)-IGBTs, bidirectional IGBTs (BIGTs), MOS-controlled diodes, and can be converted into trench structures as well as planar structures.

[0008] The semiconductor body may be based on Si or SiC or GaN or any other semiconductor material. A lateral direction in this document refers to a direction parallel to the top side of the semiconductor body. A vertical direction in this document refers to a direction perpendicular to the top side.

[0009] The main electrode can be formed of metal. The gate electrode can include or consist of highly doped metal or polysilicon. In particular, the gate electrode is isolated from the semiconductor body by an electrical isolation material (such as SiO2) or any other dielectric material or a combination of two or more dielectric materials. Therefore, the semiconductor device can be an isolated gate device. In particular, the gate electrode and the main electrode are electrically isolated from each other so that they can be set to different potentials for operation.

[0010] The drift layer may extend over the entire lateral extension of the semiconductor body. The drift layer is of a first conductivity type. The first conductivity type may be electron-conducting or hole-conducting. The second conductivity type is different from the first conductivity type, i.e., hole-conducting or electron-conducting. The electron-conducting region or layer is n-doped and the hole-conducting region or layer is p-doped. For example, the doping concentration in the drift layer is at least 10 8 cm -3 and at most 10 15 cm -3 .

[0011] The first base region is arranged vertically between the drift layer and the top side, that is, arranged between the drift layer and the top side in the vertical direction. For example, the doping concentration in the first base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 The first base region may adjoin the drift layer and / or the top side, ie may be in direct contact with the drift layer and / or may form a part of the top side.

[0012] The second base region is of the same conductivity type as the drift layer, but has a greater doping concentration than the drift layer. For example, the doping concentration in the second base region is at least 10 times or at least 100 times greater than the doping concentration in the drift layer. 15 cm -3 and / or at most 10 18 cm -3

[0013] The second base region adjoins the drift layer, ie is in direct contact with the drift layer. In particular, there is no vertically arranged region of the second conductivity type between the drift layer and the second base region. Furthermore, the second base region may adjoin the top side, ie may form a part thereof.

[0014] Herein, when comparing the doping concentrations of layers or regions, what is compared is the average doping concentration or the maximum doping concentration of these layers or regions. When defining the upper and lower limits of the doping concentrations in a layer or region, it means that the maximum doping concentration in the corresponding layer / region does not exceed the upper limit and the minimum doping concentration in the corresponding layer / region does not drop below the lower limit.

[0015] The first contact region is adjacent to the first base region and the top side, i.e., is in direct contact with the first base region and forms a part of the top side. For example, the first contact region is vertically arranged between the first base region and the top side and is adjacent to the first base region in the vertical direction. Additionally or alternatively, the first contact region may be adjacent to the first base region in the first lateral direction.

[0016] The first contact region may be at least partially embedded in the first base region. In particular, the first contact region may be at least partially laterally surrounded by the first base region. The doping concentration in the first contact region is, for example, greater than the doping concentration in the first base region, for example at least 10 times greater or at least 100 times greater. For example, the doping concentration in the first contact region is at least 10 17 cm -3 , or at least 10 18 cm -3 , or at least 10 19 cm -3 .

[0017] The second contact region is adjacent to the second base region and the top side, i.e., is in direct contact with the second base region and forms a part of the top side. For example, the second contact region is vertically arranged between the second base region and the top side and is adjacent to the second base region in the vertical direction. Additionally or alternatively, the second contact region may be adjacent to the second base region in the first lateral direction.

[0018] The second contact region may be at least partially embedded in the second base region. In particular, the second contact region may be at least partially laterally surrounded by the second base region. The doping concentration in the second contact region is, for example, greater than the doping concentration in the second base region, for example at least 10 times greater or at least 100 times greater. For example, the doping concentration in the second contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0019] The contact region is also called the source region.

[0020] The thickness of the first base region and the second base region measured in the vertical direction may be at least 1 micrometer and / or at most 8 micrometers. In each case, the thickness of the first contact region and the second contact region may be at least 50 nanometers and / or at most 1 micrometer. In each case, the lateral extension of the first contact region and the second contact region in the first lateral direction may be at least 50 nanometers and / or at most 5 micrometers. In each case, the lateral extension of the first base region and the second base region in the first lateral direction may be at least 500 nanometers and / or at most 5 micrometers.

[0021] The main electrode is in electrical contact with the first contact region and the second contact region, i.e., in direct electrical contact. For example, the main electrode adjoins the first contact region and the second contact region at the top side. For example, the main electrode is not in direct electrical contact with the second base region. An ohmic contact may be formed between the main electrode and the contact region.

[0022] In the first lateral direction, at least a portion of the gate electrode (e.g. a major portion of the gate electrode or the entire gate electrode) is laterally arranged between the first contact region and the second contact region and between the first base region and the second base region. For example, only one gate electrode is arranged between the first contact region and the second contact region and between the first base region and the second base region in the first lateral direction. For example, the distance between the first contact region and the second contact region measured in the first lateral direction is at most twice or 1.5 times the lateral extension of the gate electrode in the first lateral direction. For example, the distance between the first contact region and the second contact region in the first lateral direction is at most 10 micrometers.

[0023] According to another embodiment, the semiconductor device is configured to invert a region in the first base region (i.e., invert the conductivity type in this region) by means of the gate electrode by setting the potential of the gate electrode, and thereby enable a current flow of first type charge carriers between the drift layer and the first contact region through this region. The inversion region faces the gate electrode, i.e., is the region in the first base region that is closest to the gate electrode.

[0024] Alternatively, a region in the second base region is inverted by means of the gate electrode, thereby enabling a current flow of second type charge carriers between the drift layer and the second contact region through this region. Furthermore, the inversion region faces the gate electrode, ie is the region in the second base region closest to the gate electrode.

[0025] Therefore, the drift layer, the first base region and the first contact region form part of a first transistor (main transistor), and the drift layer, the second base region and the second contact region form part of a second transistor (complementary transistor).

[0026] In the case where the first conductivity type is electron conduction, the first type of charge carriers are electrons. Correspondingly, in the case where the second conductivity type is hole conduction, the second type of charge carriers are holes.

[0027] For example, in the first case, when the zones in the first base region are inverted, the first type of charge carriers are enabled to flow from the main electrode through the first contact region, through the inversion region in the first base region, and into the drift layer. For example, in the second case, when the zones in the second base region are inverted, the second type of charge carriers are enabled to flow from the drift layer through the inversion region in the second base region, through the second contact region, and into the main electrode.

[0028] According to another embodiment, the semiconductor device is a planar device, i.e. a planar structure, wherein the gate electrode is arranged on the top side. For example, in a first lateral direction, the gate electrode is at least partially aligned with the first and second contact regions and / or with the first and second base regions. Thereby, the gate electrode is isolated from the contact regions by the electrical isolation layer. For example, in a top view of the top side, the gate electrode at least partially overlaps the first and second contact regions and the first and second base regions.

[0029] According to another embodiment, the semiconductor device is a trench device, i.e. a trench structure, in which the gate electrode is arranged in an active trench. The active trench extends from the top side into the semiconductor body in a vertical direction. For example, the first contact area and the second contact area and / or the first base area and the second base area are at least partially aligned with the gate electrode in a vertical direction. That is, in a side view along the first lateral direction, the active trench and the gate electrode therein partially or completely overlap with the first and second contact areas and / or the first and second base areas. For example, the active trench extends deeper into the semiconductor body than the first and second contact areas and / or than the first and second base areas. For example, the active trench and the gate electrode extend into the semiconductor body by at least 2 microns, or at least 4 microns, and / or at most 10 microns in a vertical direction.

[0030] According to another embodiment, a semiconductor device includes a dummy trench arranged adjacent to an active trench and spaced apart from the active trench in a first lateral direction.

[0031] A trench having a gate electrode therein is referred to herein as an "active trench". A trench not having a gate electrode therein is referred to herein as a "dummy trench". For example, the second base region and the second contact region are arranged between the active trench and the dummy trench in the first lateral direction. The second base region may be adjacent to the active trench and the dummy trench in the first lateral direction.

[0032] According to another embodiment, the dummy trench is filled with a conductive material, such as highly doped polysilicon. The conductive material is electrically isolated from the semiconductor body, for example, by an isolation material. For example, the conductive material in the dummy trench is electrically connected to the main electrode.

[0033] The trenches of the semiconductor device, whether they are active trenches or dummy trenches, can have the same dimensions within the limits of manufacturing tolerances. Alternatively, the dummy trenches can be deeper or shallower than the active trenches.

[0034] For example, exactly one active trench is arranged between the first and second contact regions and between the first and second base regions. The first contact region and the second contact region may adjoin the active trench on different sides relative to the first lateral direction. Similarly, the first base region and the second base region may adjoin the active trench on different sides relative to the first lateral direction.

[0035] According to another embodiment, the enhancement region of the first conductivity type is arranged vertically between the first base region and the drift layer. For example, the enhancement region extends laterally over the entire lateral extension of the first base region. Thus, the enhancement layer is arranged between the drift layer and the first base region over the entire lateral extension of the first base region. The enhancement region may adjoin the first base region and / or the drift layer. This enhancement region is also referred to herein as the "first enhancement region".

[0036] According to another embodiment, the enhancement region has a greater doping concentration than the drift layer. For example, the doping concentration in the first enhancement region is at least 10 times or at least 100 times greater than the doping concentration in the drift layer. For example, the doping concentration in the enhancement region is at least 10 15 cm -3 and / or at most 10 19 cm -3 The thickness of the enhanced zone measured in the vertical direction is, for example, at least 1 micrometer and / or at most 3 micrometers.

[0037] The enhancement region is a blocking region for the second type of charge carriers (eg, holes). Therefore, it may be referred to as a "hole blocking region" or "hole blocking layer" accordingly.

[0038] According to another embodiment, the semiconductor device includes a third base region of the second conductivity type. The third base region is arranged adjacent to the second base region in the first lateral direction so that the second base region is arranged between the first base region and the third base region in the first lateral direction. The second base region and the third base region can be spaced apart from each other in the first lateral direction by a trench (e.g., by exactly one trench). This trench can be an active trench or a dummy trench.

[0039] The third base region is also arranged vertically between the top side and the drift layer. It may abut the top side and / or the drift layer. The doping concentration in the third base region may be in the same or different range as the doping concentration in the first base region. The thickness of the third base region measured in the vertical direction is, for example, greater than the thickness of the first base region, for example, at least 1 micron greater.

[0040] According to a further embodiment, the third base region extends from the top side into the semiconductor body. For example, the third base region extends deeper into the semiconductor body than the active trench or than the trench. For example, the third base region extends at least 1 micrometer deeper into the semiconductor body than the trench. The third base region is, for example, a so-called p-well.

[0041] According to another embodiment, the thickness of the insulating material between the first contact region and / or the first base region and the gate electrode is greater than the thickness of the insulating material between the second contact region and / or the second base region and the gate electrode. For example, the thickness between the first contact region / the first base region and the gate electrode is at least 1.5 times or at least twice greater than the thickness between the second contact region / the second base region and the gate electrode.

[0042] According to another embodiment, the main electrode is not in direct electrical contact with the second base region. This means that charge carriers cannot flow directly from the main electrode into the second base region and vice versa. Instead, the charge carrier exchange always has to take place via the second contact region.

[0043] According to another embodiment, the semiconductor device includes a further gate electrode. The further gate electrode is spaced apart from the gate electrode in the first lateral direction. For example, the further gate electrode is at the same potential as the gate electrode. In other words, the gate electrode and the further gate electrode may be short-circuited.

[0044] Furthermore, a further gate electrode may be arranged in an active trench extending from the top side into the semiconductor body.

[0045] According to another embodiment, the second base region is arranged between the gate electrode and the further gate electrode in the first lateral direction. For example, in the first lateral direction, no further gate electrode is arranged between the gate electrode and the further gate electrode. The second base region may be adjacent to two active trenches including the gate electrode and the further gate electrode in the first lateral direction.

[0046] According to another embodiment, the semiconductor device is configured to invert a region in the second base region by means of another gate electrode by setting the potential of the other gate electrode, the region being located at a side of the second base region, which side is opposite to a side of the second base region at which the region in the second base region is inverted by means of the gate electrode. Thus, the other gate electrode provides a current path at this opposite side. "Opposite" here refers to the first lateral direction. In other words, the gate electrode and the other gate electrode invert the region in the second base region, they are arranged at opposite sides and they are spaced apart, for example, in the first lateral direction.

[0047] In other words, the gate electrode and the further gate electrode establish two channels for transporting charge carriers, for example hole channels.

[0048] According to a further embodiment, the first contact area and / or the second contact area is an elongated area extending in a second lateral direction which is inclined to the first lateral direction, for example perpendicular to the first lateral direction. This means that in each case the lateral extension of the first and / or second contact area is greater in the second lateral direction than in the first lateral direction. For example, in each case the lateral extension in the second lateral direction is at least two times or at least five times greater than in the first lateral direction. The first contact area and the second contact area may adjoin the top side over the entire lateral extension in the first and / or second lateral direction.

[0049] Likewise, the first and second base regions may be elongated and extend in the second lateral direction.The trench may also be elongated and extend in the second lateral direction.

[0050] According to another embodiment, the semiconductor device comprises a plurality of first contact regions adjacent to the top side and the first base region and in electrical contact with the main electrode. These first contact regions are separated and spaced apart from each other in the second lateral direction. For example, each first contact region has a lateral extension of at least 500 nanometers or at least 1 micrometer in the second lateral direction. In each case, the distance between each two adjacent first contact regions in the second lateral direction can be at least 500 nanometers or at least 1 micrometer. All features disclosed so far for one first contact region are also disclosed for all other first contact regions, in particular with respect to doping concentration and conductivity type.

[0051] According to another embodiment, the semiconductor device comprises a plurality of second contact regions adjacent to the top side and the second base region and in electrical contact with the main electrode. These first contact regions are separated and spaced apart from each other in the second lateral direction. For example, each second contact region has a lateral extension of at least 500 nanometers or at least 1 micrometer in the second lateral direction. In each case, the distance between each two adjacent second contact regions in the second lateral direction can be at least 500 nanometers or at least 1 micrometer. All features disclosed so far for one second contact region are also disclosed for all other second contact regions, in particular with respect to doping concentration and conductivity type.

[0052] According to another embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured to handle a current of at least 1 ampere (A) and / or a voltage of at least 100 volts (V). The semiconductor device is, for example, a so-called vertical semiconductor device.

[0053] According to another embodiment, the semiconductor device is a vertical device, ie is a vertical structure.The cathode and the anode are then arranged at opposite sides of the semiconductor body.

[0054] According to another embodiment, the semiconductor device is a bipolar semiconductor device, in which both electrons and holes contribute to the current flow during operation.

[0055] According to another embodiment, the semiconductor device is an insulated gate bipolar transistor (IGBT) or a MOS-controlled diode. The semiconductor device is, for example, a reverse conducting (RC)-IGBT or a bidirectional IGBT (BIGT).

[0056] According to a further embodiment, the semiconductor device includes a further main electrode applied to a back side of the semiconductor body opposite the top side.The semiconductor body may include a contact layer (anode layer) and / or a buffer layer between the drift layer and the further main electrode.

[0057] Next, a method for manufacturing a semiconductor device is described. The method is particularly suitable for manufacturing a semiconductor device according to any of the embodiments described herein. Therefore, all features disclosed for the semiconductor device are also disclosed for the method, and vice versa.

[0058] According to an embodiment of a method for manufacturing a semiconductor device, the method includes the step of providing a semiconductor body having a top side and a drift layer of a first conductivity type. In a further step, a first base region, a second base region, a first contact region, and a second contact region are manufactured. The first base region is of the second conductivity type and is manufactured so that the first base region is vertically located between the drift layer and the top side. The second base region is of the first conductivity type and is manufactured so that the second base region is vertically located between the drift layer and the top side, wherein the second base region has a greater doping concentration than the drift layer and is adjacent to the drift layer. The first contact region is of the first conductivity type and is manufactured so that the first contact region is adjacent to the first base region and the top side. The second contact region is of the second conductivity type and is manufactured so that the second contact region is adjacent to the second base region and the top side. In a further step, a main electrode is applied to the top side, and electrical contact is established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step, a gate electrode is formed so that at least a portion of the last gate electrode is located between the first contact region and the second contact region and between the first base region and the second base region in a first lateral direction.

[0059] Before forming the first and second base regions and the first and second contact regions, the drift layer may reach the top side, for example forming the top side. Fabricating the base region and / or the contact region may include implanting dopants (for example through the top side). For example, a mask is used to define the regions where dopants for different regions should be implanted. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Next, a semiconductor device and a method for manufacturing a semiconductor will be explained in more detail with reference to the accompanying drawings according to exemplary embodiments. The accompanying drawings are included to provide further understanding. In the accompanying drawings, elements of the same structure and / or function may be represented by the same reference numerals. It should be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale. In the case where the functions of elements or components in different figures correspond to each other, their descriptions will not be repeated in the following figures. For clarity, elements may not have corresponding reference symbols in all figures.

[0061] Figures 1 to 5 , Fig. 9 , Fig.16 , Figures 18 to 29 and Fig.31 Different exemplary embodiments of semiconductor devices are shown in different views,

[0062] Figure 6 and Fig.10 shows a reference semiconductor device,

[0063] Figure 7 , Figure 8 and Figures 11 to 15Simulation results illustrating the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device are shown.

[0064] Fig.17 shows an example of a semiconductor device,

[0065] Fig.30 A flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device is shown. DETAILED DESCRIPTION

[0066] Figure 1 A section of a first exemplary embodiment of a semiconductor device 100 is shown in cross-sectional view. The semiconductor device 100 comprises a semiconductor body 1, for example made of Si or SiC or GaN. A main electrode 2 is applied on a top side 10 of the semiconductor body 1. The main electrode 2 is, for example, a metal electrode.

[0067] The semiconductor body 1 comprises a drift layer 11 of a first conductivity type. In the following it is assumed that the first conductivity type is electron conduction and the corresponding doping is n-doping. Thus, the drift layer 11 is n-doped. However, the described embodiment will also work if the first conductivity type is hole conduction.

[0068] The first base region 12 and the second base region 13 are each vertically located between the drift layer 11 and the top side 10. "Vertically" herein means in a vertical direction V, which is a direction perpendicular to the top side 10. The first base region 12 and the second base region 13 are arranged adjacent to each other in a first lateral direction L1, which is a direction parallel to the top side 10. The first base region 12 is a second conductivity type different from the first conductivity type, i.e., p-doped in this example. The second base region 13 is a first conductivity type, i.e., n-doped. Both base regions 12, 13 are adjacent to the drift layer 11 and the top side 10.

[0069] A first contact region 14 is embedded in the first base region 12. The first contact region 14 is of the first conductivity type (i.e., n-doped) and adjoins the first base region 12 and the top side 10. At the top side 10, the first contact region 14 is in direct mechanical and electrical contact with the main electrode 2. The first base region 12 is also in direct mechanical and electrical contact with the main electrode 2 at the top side 10.

[0070] The second contact region 15 is embedded in the second base region 13. The second contact region 15 is of the second conductivity type (i.e. p-doped) and adjoins the second base region 13 as well as the top side 10. At the top side 10, the second contact region 15 is in direct mechanical and electrical contact with the main electrode 2. However, the main electrode is not in direct mechanical or electrical contact with the second base region 13, so that the exchange of charge carriers between the main electrode 2 and the second base region 13 always has to occur via the second contact region 15.

[0071] Laterally between the base regions 12, 13 and the contact regions 14, 15, an active trench 4 extends from the top side 10 into the semiconductor body 1 and opens into the drift layer 11. The depth of the active trench 4 measured in the vertical direction V is greater than the thickness of the base regions 12, 13 and the contact regions 14, 15, also measured in the vertical direction V. A gate electrode 3 is arranged inside the active trench 4. The gate electrode 3 is made of, for example, highly doped polysilicon. The gate electrode 3 is electrically isolated from the semiconductor body 1, in particular from the base regions 12, 13 and the contact regions 14, 15, by an electrically isolating material 5 (for example, which is SiO2). Figure 1 The semiconductor device 100 is a so-called trench device.

[0072] The doping concentration of the drift layer 11 is, for example, 10 8 cm -3 with 10 15 cm -3 The doping concentration of each base region 12, 13 is, for example, between 10 15 cm -3 with 10 18 cm -3 The doping concentration in the contact regions 14, 15 is in each case, for example, in the range of 10 18 cm -3 with 10 21 cm -3 in the range between.

[0073] During the on-state of the semiconductor device 100, the gate electrode 3 may be at a positive potential relative to the semiconductor body 1. Thereby, an inversion zone is formed in the first base region 12 at the side facing the active trench 4, which extends along the active trench 4 from the first contact region 14 to the drift layer 11. This enables electrons to be injected from the main electrode 2 into the contact region 14 and travel from there inside the inversion zone into the drift layer 11.

[0074] In the off state of the semiconductor device 100, the gate electrode 3 may be at a negative potential relative to the semiconductor body 1. The potentials of the main electrode 2 and the other main electrode may be the same as in the on state. Thus, an inversion zone is formed in the second base region 13 at the side facing the active trench 4, which extends from the second contact region 15 to the drift layer 11 along the active trench 4. This enables holes to come out of the drift layer 11 via the inversion zone and travel along the inversion zone, then pass through the second contact region 15 and enter the main electrode 2.

[0075] Particularly in the case of the semiconductor device 100 being a bipolar device such as an IGBT, a very efficient hole removal can be achieved in this way, which leads to reduced turn-off losses.

[0076] The transistor implemented with the first base region 12 and the first contact region 14 is referred to herein as a "main transistor", and the transistor implemented with the second base region 13 and the second contact region 15 is referred to herein as a "complementary transistor". In the exemplary embodiment described herein, the main transistor is an NMOS transistor and the complementary transistor is a PMOS transistor.

[0077] Figure 2 The exemplary embodiments of the present invention show a so-called planar device, which does not use Figure 1 Instead, the gate electrode 3 is arranged on the top side 10 and is electrically isolated from the semiconductor body 1 by the electrically isolating material 5. In a plan view on the top side 10, the gate electrode 3 partially covers (ie overlaps) the first contact area 14 and the second contact area 15. Although Figure 1 The inversion regions and associated current paths in the MOSFET are oriented primarily in the vertical direction V, but Figure 2 The inversion regions and the associated current paths are mainly oriented in the first lateral direction L1.

[0078] Figure 3 An exemplary embodiment of shows a semiconductor device 100, which is an insulated gate bipolar transistor, abbreviated IGBT. On the back side of the semiconductor body 1, opposite the top side 10, a further main electrode 6 is applied, which is, for example, a metal. The semiconductor body 1 comprises a further layer 20 of a second conductivity type (i.e. p-doped), which forms the back side and is in direct electrical and mechanical contact with the further main electrode 6. The doping concentration of the further layer 20 is, for example, greater than the doping concentration in the drift layer 11. Between the drift layer 11 and the layer 20, a layer 19 of the first conductivity type is applied. The layer 19 adjoins the layer 20 and the drift layer 11. The doping concentration in the layer 19 is, for example, greater than the doping concentration in the drift layer 11. The layer 19 is a so-called buffer layer.

[0079] exist Figure 3 , the first base region 12 adjoins the active trench 4 at both sides relative to the first lateral direction L1. Both active trenches 4 are connected to the gate electrode 3. Also relative to the first lateral direction L1, the second base regions 13 are arranged on both sides of the first base region 12, each of the second base regions 13 being spaced apart from the first base region 12 by one of the active trenches 4.

[0080] The second base region 13 is located between and adjacent to the two trenches 4, 40, respectively. In both cases, only the trench closer to the first base region 12 is an active trench 4. The corresponding other trench 40 is a dummy trench. The dummy trench 40 is filled with a conductive material, which is, for example, electrically connected to the main electrode 2 and is therefore at the same potential as the main electrode 2. The dummy trench 40 helps to reduce the capacitance between the gate electrode 3 and the other main electrode 6, also called Miller capacitance or gate-collector capacitance (Cgc).

[0081] Figure 3 Other figures may only show a portion of the semiconductor device. The structure including the base regions 12, 13 and the contact regions 14, 15 shown in these figures may be repeated several times in the first transverse direction L1.

[0082] exist Figure 4 In an exemplary embodiment of the present invention, the semiconductor body 1 comprises a third base region 18 of the second conductivity type (i.e., p-doped), and the third base region 18 adjoins the dummy trench 40 at a side facing away from the second base region 13. The doping concentration in the third base region 18 can be the same as or different from the doping concentration in the first base region 12. The third base region 18 constitutes a p-well, which extends deeper into the semiconductor body 1 than the trenches 4, 40. With the third base region 18, an improved breakdown voltage can be obtained.

[0083] Figure 5 Shows Figure 4 FIG. 1 is a detailed view of an exemplary embodiment of FIG. 1 , in which only the first base region 12 , the adjacent second base region 13 and half of the third base region 18 are shown. Figure 5 The doping profile is shown by using different shading. The higher the lattice density of the shading, the higher the doping concentration.

[0084] Figure 6 A reference semiconductor device 200 is shown, for example a reference IGBT. Figure 5 Compared to the IGBT of FIG. 4 , the second base region 13 and the second contact region 15 are eliminated. Instead, laterally between the dummy trench 40 and the active trench 4, the semiconductor body 1 adjoining the top side 10 is also made of a semiconductor material of the second conductivity type, for example with the same doping concentration as the first base region 12. The main electrode 2 is in electrical and mechanical contact with the semiconductor body 1 in the region between the two trenches 4, 40 (dummy contact).

[0085] Figure 7 and 8 Shown according to Figure 5 The relationship between the output characteristics Ic and Vce of the IGBT (curve 100) and the Figure 6 A simulation comparing the output characteristic Ic versus Vce (curve 200) of a reference IGBT (ie, without the second base region and the second contact region). Figure 7 shows a range from 0 to 2 volts, Figure 8 shows a range from 0 to 25 volts. Figure 6 Compared with the reference IGBT, according to Figure 5 The IGBT of FIG. 4 shows an improvement of about 130 mV on Vce-sat. In the reference IGBT, the extraction of injected holes between the dummy trench 40 and the active trench 4 in the on-state leads to a deterioration of the plasma concentration in the drift region (drift layer 11) and thus to higher on-state losses. Figure 5 In the IGBT of FIG. 1 , this hole extraction between the dummy trench 40 and the active trench 4 is significantly suppressed (about 50%, see also Fig. 9 ). This is the result of placing the second base region and the second contact region (PMOS transistor) between the active trench 4 and the dummy trench 40. This PMOS transistor is off during the IGBT on-state (Vge>Vth), thereby virtually eliminating the hole extraction path in the region between the active trench 4 and the dummy trench 40. This explains the superb Vce-sat of the IGBT, which is very close to the Vce-sat of an IGBT that does not have any electrical contact of the semiconductor body with the main electrode in the lateral top side region between the dummy trench 40 and the active trench 4 (i.e., no dummy contact).

[0086] In short, the electrical contact to the main electrode 2 in the region between the active trench 4 and the dummy trench 40 is effectively not visible during the IGBT on-state, which is required to maintain the plasma concentration.

[0087] Fig. 9 Shown in accordance with Figure 5 The simulated hole current flow path during the on-state operation of the IGBT, while Fig.10 Shows that according to Figure 6 Simulated hole current flow path of the reference IGBT. The density of the contour lines is proportional to the hole current. Fig. 9 and 10 In this example, Vce is chosen to be 3 volts. As can be seen, for Figure 5 and Fig. 9 In the IGBT of FIG. 1 , the flow of hole current between the active trench 4 and the dummy trench 40 is significantly suppressed.

[0088] Fig.11 Shown according to Figure 5 The relationship between the simulated hole current and the voltage Vce at the second contact region during the on-state operation of the IGBT (curve 100) and the reference IGBT (curve 200). Figure 5 The IGBT can achieve about 50% reduction in hole current in the on state.

[0089] Fig.12 The simulation of the relationship between Ic and Vce is shown in the case of Vge = -15 volts. As can be seen, according to Figure 5 The blocking capability of the IGBT (curve 100) and according to Figure 6 The blocking capability of the reference IGBT (curve 200 ) is almost the same.

[0090] Fig.13 Shown according to Figure 5 IGBT (curve 100_i) and according to Figure 6 The simulation of the turn-off switching characteristics of the reference IGBT (curve 200_i) is shown in Fig. 1. Curves 100_1 and 200_1 show the relationship between Vce and time T, curves 100_2 and 200_2 show the relationship between Vge and time T, and curves 100_3 and 200_3 show the relationship between Ic and time T. Figure 5 The IGBT turn-off switching loss (Eoff) is related to Figure 6 The turn-off switching losses of the reference IGBT are very close. It should also be noted that according to Figure 5 The Eoff of the IGBT of FIG. 1 is lower than the Eoff of the reference IGBT, in which there is no electrical contact to the main electrode in the region between the trenches (see table below). This means that the PMOS transistor that prevents holes from flowing out in the on-state is now active in the IGBT off-state and can effectively extract holes from the IGBT device, which in turn reduces its switching losses. In other words, the contact to the main electrode in the region between the dummy trench and the active trench, which is effectively invisible during the IGBT on-state, is visible during the IGBT off-state, which is required to improve both the on-state and switching losses.

[0091] Fig.14 Shows that with Fig.13 Simulation of the turn-on switching characteristics of the same terms in Figure 6 Compared with the reference IGBT, according to Figure 5 The IGBT shows lower conduction losses (Eon) due to its lower gate-emitter capacitance (Cge). However, the total losses Etotal (i.e., Erec+Eon) remain the same, where Erec is the diode reverse recovery loss (see table below).

[0092] Fig.15 Shown according to Figure 5 The IGBT (curve 100) and Figure 6 Compared with the reference IGBT (curve 200) at 25°C, the simulated technology curve (Eoff vs. Vce_sat) is Figure 5 The IGBT has a superior technology curve. For the same Vce-sat, compared with the reference IGBT, according to Figure 5 The Eoff of the IGBT is 18% lower. However, for the same Eoff, compared with the Vce-sat of the reference IGBT, according to Figure 5 The Vce-sat of the IGBT is 5% lower.

[0093] The following table shows the Figure 5 The IGBT (row 100) is Figure 6 Compared with the reference IGBT (row 200) and with the fact that there is no electrical contact of the main electrode to the semiconductor body in the region between the active trench 4 and the dummy trench 40 (ie, no dummy contact) Figure 6 Summary of simulation results compared to the IGBT (row 300).

[0094]

[0095] Fig.16 Shown with Figure 3 Another exemplary embodiment of a similar semiconductor device 100 is shown in FIG. Figure 3 In contrast to the exemplary embodiment of the present invention, the first enhancement region 16 is arranged between the drift layer 11 and the first base region 12. The first enhancement region 16 is of the first conductivity type (i.e., n-doped) and has a greater doping concentration than the drift layer 11, for example, a doping concentration at least 10 times greater. The enhancement region 16 improves the on-state loss or Vce-sat by reducing hole leakage.

[0096] Fig.17 Shown with Fig.16 An example of a similar IGBT in FIG. 1 , but in which the second enhancement regions 17 are of the second conductivity type (i.e., p-doped) and are arranged vertically between the second base region 13 and the drift layer 11. These enhancement regions 17 reduce the electron leakage via the electrical contact of the main electrode 2 with the second contact region 15 and improve the hole collection during turn-off.

[0097] Fig.18 An exemplary embodiment is shown, which is similar to Figure 4 but it additionally comprises a first enhancement region 16 between the first base region 12 and the drift layer 11 .

[0098] Fig.19 An exemplary embodiment is similar to Fig.18 However, in the active trench 4, the electrical isolation layer 5 is thicker between the gate electrode 3 and the first contact region 14 than between the second contact region 15 and the gate electrode 3. This design can reduce the Vth of the PMOS transistor, thereby allowing it to turn on early during the IGBT off state, so as to further reduce switching losses. Furthermore, the doping concentration in the second base region 13 can be further increased to reduce hole leakage via diffusion in the IGBT on state.

[0099] exist Fig. 20In an exemplary embodiment of the present invention, the first contact region 14 extends in the first lateral direction L1 over the entire lateral extension of the first base region 12. In other words, the first contact region 14 extends in the first lateral direction L1 from one active trench 4 to the next active trench 4. In this way, a hole path from the drift layer 11 to the main electrode 2 via the first base region 12 can be completely suppressed.

[0100] exist Fig.21 In the exemplary embodiment of , the second contact region 15 has the same lateral extension in the first lateral direction L1 as the second base region 13. In other words, the second contact region 15 extends from the corresponding active trench 4 to the next dummy trench 40 in the first lateral direction L1.

[0101] Fig. 22 An exemplary embodiment is similar to Fig.21 However, now the trenches on both sides of the second base region 13 are active trenches 4. In this embodiment, a PMOS transistor is formed at two active trenches 4 adjacent to the respective second base regions 13.

[0102] Fig.23 The exemplary embodiments show Fig. 22 , but with an additional dummy trench 40 sandwiching the four active trenches 4 in the first lateral direction L1. An additional second base region 13 is formed between the dummy trench 40 and the active trench 4. With the additional dummy trench 40, the Miller capacitance (Cgc) can be further reduced.

[0103] exist Fig.24 In an exemplary embodiment of Fig.23 In contrast, second contact regions 15 are formed in the further second base region 13. The main electrode 2 can also be in electrical contact with these second contact regions 15.

[0104] exist Fig.25 In the exemplary embodiment of the present invention, the second base region 13 is formed only between the active trench 4 and the dummy trench 40. On the other side of the dummy trench 40, a third base region 18 of the second conductivity type is formed. The dummy trench 40 and the active trench 4 extend deeper into the semiconductor body 1 than the base regions 12, 13, 18.

[0105] exist Fig.26 In an exemplary embodiment of Figure 2 In addition, the enhancement region 16 of the first conductivity type is provided between the first base region 12 and the drift layer 11 .

[0106] Fig.31 An exemplary embodiment of a planar IGBT 100 with an electrically isolating layer 5 of non-uniform thickness for reducing gate capacitance is shown.

[0107] Fig. 27 An exemplary embodiment of a semiconductor device 100 is shown in a plan view of a top side 10. As can be seen from the figure, base regions 12, 13 and contact regions 14, 15 are elongated, with a main extension direction in each case parallel to a second lateral direction L2 perpendicular to the first lateral direction L1.

[0108] exist Fig.28 In the exemplary embodiment of FIG. 1 , a plurality of first contact regions 14 are embedded in the same first base region 12. These first contact regions 14 are arranged one after another and are spaced apart from each other in the second lateral direction L2.

[0109] exist Fig.29 In the embodiment, a plurality of second contact regions 15 are embedded in the second base region 13. The second contact regions 15 are arranged one after another and are spaced apart from each other in the second lateral direction L2. Fig.29 Unlike what is shown in FIG. 1 , the first contact regions 14 do not have to be completely opposite to the second contact regions 15 , but may be arranged in a staggered configuration.

[0110] Compared to what is shown in the exemplary embodiment, the thicknesses (depths) of the first base region 12 and the second base region 13 may be different from each other. Furthermore, the intervals between the trenches 4, 40 may also be different from each other.

[0111] Fig.30 A flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device is shown.

[0112] In step S1, a semiconductor body having a top side and a drift layer of a first conductivity type is provided. In further steps S2, S3, S4 and S5, a first base region, a second base region, a first contact region and a second contact region are manufactured. The first base region is of the second conductivity type and is manufactured so that the first base region is vertically located between the drift layer and the top side. The second base region is of the first conductivity type and is manufactured so that the second base region is vertically located between the drift layer and the top side, wherein the second base region has a greater doping concentration than the drift layer and is adjacent to the drift layer. The first contact region is of the first conductivity type and is manufactured so that the first contact region is adjacent to the first base region and the top side. The second contact region is of the second conductivity type and is manufactured so that the second contact region is adjacent to the second base region and the top side. In a further step S6, a main electrode is applied on the top side and electrical contact is established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step S7, a gate electrode is formed so that the gate electrode is located between the first contact region and the second contact region and between the first base region and the second base region in the first lateral direction.

[0113] The embodiments shown in the figures represent exemplary embodiments of the improved semiconductor device and the improved method for manufacturing the semiconductor device; therefore, they do not constitute a complete list of all embodiments according to the improved semiconductor device and the improved method. The actual semiconductor device and method may differ from the embodiments shown in terms of arrangement and elements.

[0114] Reference numerals

[0115] 1 Semiconductor body

[0116] 2 Main electrode

[0117] 3. Gate electrode

[0118] 4 Active trench

[0119] 5 Electrical isolation materials

[0120] 6 Another main electrode

[0121] 10 Top side

[0122] 11 Drift layer

[0123] 12 First base region

[0124] 13 Second base region

[0125] 14 First contact area

[0126] 15 Second contact area

[0127] 16 First Enhancement Zone

[0128] 17 Second Enhancement Zone

[0129] 18 Third base region

[0130] 19th floor

[0131] 20th floor

[0132] 40 dummy groove

[0133] 100 Semiconductor Devices

[0134] 200 Reference Semiconductor Devices

[0135] Si method steps

[0136] L1 First transverse direction

[0137] L2 Second lateral direction

[0138] V Vertical direction

[0139] 100_i Label for the curve

[0140] 200_i Label of the curve

Claims

1. A semiconductor device (100), comprising: - a semiconductor body (1) having a top side (10), - a main electrode (2) on the top side (10) and - a gate electrode (3), wherein - The semiconductor body (1) comprises: - a drift layer (11) of a first conductivity type, - a first base region (12) of a second conductivity type arranged vertically between the drift layer (11) and the top side (10), a second base region (13) of the first conductivity type arranged vertically between the drift layer (11) and the top side (10), the second base region (13) having a greater doping concentration than the drift layer (11) and adjoining the drift layer (11), a first contact region (14) of a first conductivity type, said first contact region (14) adjoining said first base region (12) and said top side (10), a second contact region (15) of a second conductivity type, said second contact region (15) adjoining said second base region (13) and said top side (10), - the main electrode (2) is in electrical contact with the first contact area (14) and the second contact area (15), In a first lateral direction (L1), at least a portion of the gate electrode (3) is arranged between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13).

2. The semiconductor device according to claim 1, wherein - the semiconductor device (100) is configured such that, by setting the potential of the gate electrode (3), - inverting a region in the first base region (12) by means of the gate electrode (3) and enabling a current flow of charge carriers of the first type between the drift layer (11) and the first contact region (14) through this region, - or inverting a region in the second base region (13) by means of the gate electrode (3) and enabling a current flow of charge carriers of the second type between the drift layer (11) and the second contact region (14) through this region.

3. The semiconductor device (100) according to claim 1 or 2, wherein The semiconductor device (100) is a planar device having the gate electrode (3) arranged on the top side (10).

4. The semiconductor device (100) according to claim 1 or 2, wherein - the semiconductor device (100) is a trench device, wherein The gate electrode (3) is arranged in an active trench (4) extending in a vertical direction (V) from the top side (10) into the semiconductor body (1).

5. The semiconductor device (100) according to claim 4, further comprising: - at least one dummy trench (40) arranged adjacent to the active trench (4) and spaced apart from the active trench (4) in the first lateral direction (L1), wherein - The dummy trench (40) is filled with a conductive material electrically connected to the main electrode (2).

6. The semiconductor device (100) according to any one of the preceding claims, wherein - an enhancement region (16) of a first conductivity type is vertically arranged between the first base region (12) and the drift layer (11), - The enhancement region (16) has a greater doping concentration than the drift layer (11).

7. The semiconductor device (100) according to any one of the preceding claims, wherein A third base region (18) of the second conductivity type is arranged adjacent to the second base region (13) in the first lateral direction (L1) so that the second base region (13) is arranged between the first base region (12) and the third base region (18) in the first lateral direction (L1).

8. A semiconductor device (100) according to claim 7 as appended to claim 4, wherein The third base region (18) extends from the top side (10) into the semiconductor body (1) and extends deeper into the semiconductor body (1) than the active trench (4).

9. The semiconductor device (100) according to any one of the preceding claims, wherein - the thickness of the insulating material (5) between the first contact region (14) and / or the first base region (12) and the gate electrode (3) is greater than the thickness of the insulating material (5) between the second contact region (15) and / or the second base region (13) and the gate electrode (3).

10. The semiconductor device (100) according to any one of the preceding claims, wherein The main electrode (2) is not in direct electrical contact with the second base region (13).

11. The semiconductor device (100) according to claim 2 or any one of claims 3 to 10 when dependent on claim 2, further comprising: - a further gate electrode (3) spaced apart from the gate electrode (3) in the first lateral direction (L1), wherein - the second base region (13) is arranged between the gate electrode (3) and the further gate electrode (3) in the first transverse direction (L1), - The semiconductor device (100) is configured to invert a region in the second base region (13) by means of the other gate electrode (3) by setting the potential of the other gate electrode (3), the region being located at a side of the second base region (13), the side being opposite to a side of the second base region (13) at which the region in the second base region (13) is inverted by means of the gate electrode (3), thereby providing a current path at this opposite side.

12. The semiconductor device (100) according to any one of the preceding claims, wherein - The first contact area (14) and / or the second contact area (15) is an elongated area extending in a second transverse direction (L2) inclined to the first transverse direction (L1).

13. The semiconductor device (100) according to any one of the preceding claims, comprising: a plurality of first contact regions (14) adjoining the top side (10) and the first base region (12) and being in electrical contact with the main electrode (2), wherein the first contact regions (14) are separated and spaced apart from one another in a second lateral direction (L2) oblique to the first lateral direction (L1), and / or - a plurality of second contact regions (15) adjoining the top side (10) and the second base region (13) and being in electrical contact with the main electrode (2), wherein the second contact regions (15) are separated and spaced apart from one another in a second lateral direction (L2) inclined to the first lateral direction (L1).

14. The semiconductor device (100) according to any one of the preceding claims, wherein - The semiconductor device (100) is an IGBT.

15. A method for manufacturing a semiconductor device (100), the method comprising: - providing a semiconductor body (1) having a top side (10) and a drift layer (11) of a first conductivity type, -manufacture - a first base region (12) of a second conductivity type, such that the first base region (12) is located vertically between the drift layer (11) and the top side (10), - a second base region (13) of the first conductivity type, such that the second base region (13) is located vertically between the drift layer (11) and the top side (10), wherein the second base region (13) has a greater doping concentration than the drift layer (11) and adjoins the drift layer (11), - a first contact region (14) of a first conductivity type, such that the first contact region (14) adjoins the first base region (12) and the top side (10), - a second contact region (15) of a second conductivity type, such that the second contact region (15) adjoins the second base region (13) and the top side (10), - applying a main electrode (2) on the top side (10) and establishing electrical contact between the main electrode (2) and the first contact area (14) and between the main electrode (2) and the second contact area (15), - forming the gate electrode (3) so that at least a portion of the gate electrode (3) is located between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13) in the first lateral direction (L1).

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