Vertical igbt with complementary trenches for hole extraction
By introducing a complementary transistor structure into a semiconductor device, and utilizing the second base region and contact region to provide a charge carrier extraction path during the turn-off period, the problem of high switching losses is solved, and a balance between low-loss conduction and switching states is achieved.
Patent Information
- Application Number
- CN202280096353.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-15
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2042-06-15
AI Technical Summary
Existing semiconductor devices have difficulty effectively removing charge carriers (such as holes) during the turn-off transient, resulting in high switching losses, and also significant losses during the on-state.
By employing a complementary transistor structure, a second base region and a second contact region are introduced into the semiconductor body to provide a charge carrier extraction path during the off-time, reducing switching losses without affecting the on-state.
It effectively reduces the switching losses of semiconductor devices while maintaining low losses in the on-state, without increasing trench spacing limitations and gate capacitance.
Smart Images
Figure CN119234314B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to a semiconductor device and to a method for manufacturing a semiconductor device. BACKGROUND
[0002] There is a need for an improved semiconductor device, for example for a semiconductor device capable of efficiently removing charge carriers (e.g. holes) from a semiconductor body during turn-off transients without compromising the on-state losses. Furthermore, there is also a need for an improved method for manufacturing such a semiconductor device. SUMMARY
[0003] Embodiments of the present disclosure relate to an improved semiconductor device and to an improved method for manufacturing a semiconductor device.
[0004] First, a semiconductor device is specified.
[0005] According to an embodiment, the semiconductor device comprises a semiconductor body having a top side, a main electrode on the top side, and a gate electrode. The semiconductor body comprises a drift layer of a first conductivity type. The semiconductor body further comprises a first base region of a second conductivity type arranged vertically between the drift layer and the top side. Furthermore, the semiconductor body comprises a second base region of the first conductivity type arranged vertically between the drift layer and the top side. The second base region has a greater doping concentration than the drift layer and adjoins the drift layer. Furthermore, the semiconductor body comprises a first contact region of the first conductivity type. The first contact region adjoins the first base region and the top side. Furthermore, the semiconductor body comprises a second contact region of the second conductivity type. The second contact region adjoins the second base region and the top side. The main electrode is in electrical contact with the first contact region and the second contact region. At least a portion of the gate electrode is arranged between the first contact region and the second contact region and between the first base region and the second base region in a first lateral direction.
[0006] Bipolar semiconductor devices, like IGBTs, are devices in which both electrons and holes participate in the conduction process. The injection of both electrons and holes leads to the formation of a high-density plasma in the drift layer, which reduces the resistance of this layer and thus reduces the losses during the on-state. However, during the off-state, the stored plasma needs to be removed quickly in order to minimize the switching losses. Thus, there is a trade-off between the on-state voltage drop (Vce-sat) and the turn-off switching losses (Eoff) of such devices.
[0007] In the present invention, a complementary transistor for a controlled extraction of charge carriers of a second type, like holes, is introduced by means of a second base region and a second contact region. The complementary transistor provides an additional extraction path for charge carriers of the second type which is only active during the turn-off period of a main transistor comprising a first base region and a first contact region. Thus, the switching losses of the semiconductor device are reduced without impairing its on-state. The functionality of the semiconductor device is not limited by, for example, the trench pitch. Furthermore, the Miller capacitance (Cgc) is not adversely affected since no additional gate connection is required. This concept is applied, for example, to MOS-based bipolar devices such as IGBTs, reverse conducting (RC)-IGBTs, bidirectional IGBTs (BIGTs), MOS-controlled diodes, and can be transferred to trench structures as well as to planar structures.
[0008] The semiconductor body can be based on Si or SiC or GaN or any other semiconductor material. The lateral direction refers herein to a direction parallel to the top side of the semiconductor body. The vertical direction refers herein to a direction perpendicular to the top side.
[0009] The main electrode can be formed of a metal. The gate electrode can comprise or consist of a highly doped metal or polysilicon. In particular, the gate electrode is separated from the semiconductor body by an electrically isolating material, like SiO2, or any other dielectric material or a combination of two or more dielectric materials. Thus, the semiconductor device can be an isolated gate device. In particular, the gate electrode and the main electrode are electrically isolated from each other such that they can be set to different potentials for operation.
[0010] The drift layer can extend over the entire lateral extension of the semiconductor body. The drift layer is of a first conductivity type. The first conductivity type can be electron-conducting or hole-conducting. The second conductivity type is different from the first conductivity type, i.e. is hole-conducting or electron-conducting. Regions or layers which are electron-conducting are n-doped, and regions or layers which are hole-conducting are p-doped. For example, the doping concentration in the drift layer is at least 10 8 cm -3 and at most 10 15 cm -3 .
[0011] The first base region is arranged vertically between the drift layer and the top side, i.e. in the vertical direction between the drift layer and the top side. For example, the doping concentration in the first base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 The first base region can adjoin the drift layer and / or the top side, i.e. can be in direct contact with the drift layer and / or can form part of the top side.
[0012] The second base region is of the same conductivity type as the drift layer, but has a larger doping concentration than the drift layer, for example, the doping concentration in the second base region is at least 10 times larger or at least 100 times larger than the doping concentration in the drift layer. For example, the doping concentration in the second base region is at least 10 15 cm -3 and / or at most 10 18 cm -3
[0013] The second base region is adjacent to the drift layer, i.e. directly in contact with the drift layer. In particular, there is no region of the second conductivity type arranged vertically between the drift layer and the second base region. Furthermore, the second base region can be adjacent to the top side, i.e. can form a part thereof.
[0014] Herein, when comparing the doping concentration of layers or regions, the average doping concentration or the maximum doping concentration of these layers or regions is compared. When defining an upper limit and a lower limit for the doping concentration in a layer or region, it is meant that the maximum doping concentration in the corresponding layer / region does not exceed the upper limit and the minimum doping concentration in the corresponding layer / region does not fall below the lower limit.
[0015] The first contact region is adjacent to the first base region and the top side, i.e. directly in contact with the first base region and forms a part of the top side. For example, the first contact region is arranged vertically between the first base region and the top side and is adjacent to the first base region in the vertical direction. Additionally or alternatively, the first contact region can be adjacent to the first base region in the first lateral direction.
[0016] The first contact region can be at least partially embedded in the first base region. In particular, the first contact region can be at least partially laterally surrounded by the first base region. The doping concentration in the first contact region is for example larger than the doping concentration in the first base region, for example at least 10 times larger or at least 100 times larger. For example, the doping concentration in the first contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .
[0017] The second contact region is adjacent to the second base region and the top side, i.e. directly in contact with the second base region and forms a part of the top side. For example, the second contact region is arranged vertically between the second base region and the top side and is adjacent to the second base region in the vertical direction. Additionally or alternatively, the second contact region can be adjacent to the second base region in the first lateral direction.
[0018] The second contact region can be at least partially embedded in the second base region. In particular, the second contact region can be at least partially laterally surrounded by the second base region. The doping concentration in the second contact region is, for example, greater than the doping concentration in the second base region, for example at least 10 times greater or at least 100 times greater. For example, the doping concentration in the second contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .
[0019] The contact region is also referred to as source region.
[0020] The thickness of the first base region and the second base region, measured in the vertical direction, can be at least 1 micrometer and / or at most 8 micrometers. In each case, the thickness of the first contact region and the second contact region can be at least 50 nanometers and / or at most 1 micrometer. In each case, the lateral extension of the first contact region and the second contact region in the first lateral direction can be at least 50 nanometers and / or at most 5 micrometers. In each case, the lateral extension of the first base region and the second base region in the first lateral direction can be at least 500 nanometers and / or at most 5 micrometers.
[0021] The main electrode is in electrical contact, i.e. direct electrical contact, with the first contact region and the second contact region. For example, the main electrode adjoins the first contact region and the second contact region at the top side. For example, the main electrode is not in direct electrical contact with the second base region. An ohmic contact can be formed between the main electrode and the contact regions.
[0022] In the first lateral direction, at least a portion of the gate electrode, for example a main portion of the gate electrode or the entire gate electrode, is arranged laterally between the first contact region and the second contact region and between the first base region and the second base region. For example, only one gate electrode is arranged in the first lateral direction between the first contact region and the second contact region and between the first base region and the second base region. By way of example, the distance between the first contact region and the second contact region, measured in the first lateral direction, is at most twice or 1.5 times the lateral extension of the gate electrode in the first lateral direction. For example, the distance between the first contact region and the second contact region in the first lateral direction is at most 10 micrometers.
[0023] According to a further embodiment, the semiconductor device is configured to reverse a region in the first base region, i.e. to reverse the conductivity type in this region, by means of the gate electrode by setting a potential of the gate electrode, and thereby enable a current flow of charge carriers of the first type between the drift layer and the first contact region to pass through this region. The inversion region faces the gate electrode, i.e. is the region in the first base region that is closest to the gate electrode.
[0024] Alternatively, a region in the second base region is inverted by means of the gate electrode, thereby enabling a current flow of the second type of charge carriers between the drift layer and the second contact region to pass through this region. Moreover, the inverting region faces the gate electrode, i.e. is the region in the second base region closest to the gate electrode.
[0025] Thus, the drift layer, the first base region and the first contact region form part of a first transistor (main transistor), and the drift layer, the second base region and the second contact region form part of a second transistor (complementary transistor).
[0026] In case the first conductivity type is electron conduction, the first type of charge carriers are electrons. Correspondingly, the second conductivity type is hole conduction, and the second type of charge carriers are holes.
[0027] For example, in the first case, when a region in the first base region is inverted, the first type of charge carriers are enabled to flow from the main electrode, through the first contact region, through the inverting region in the first base region and into the drift layer. For example, in the second case, when a region in the second base region is inverted, the second type of charge carriers are enabled to flow from the drift layer, through the inverting region in the second base region, through the second contact region and into the main electrode.
[0028] According to another embodiment, the semiconductor device is a planar device, i.e. a planar structure, wherein the gate electrode is arranged on the top side. For example, in the first lateral direction, the gate electrode is at least partially aligned with the first and second contact regions and / or with the first and second base regions. Thereby, the gate electrode is separated from the contact regions by the electrically isolating layer. For example, in a top view on the top side, the gate electrode at least partially overlaps the first and second contact regions and the first and second base regions.
[0029] According to another embodiment, the semiconductor device is a trench device, i.e. a trench structure, wherein the gate electrode is arranged in an active trench. The active trench extends in the vertical direction from the top side into the semiconductor body. For example, the first and second contact regions and / or the first and second base regions are at least partially aligned with the gate electrode in the vertical direction. That is, in a side view along the first lateral direction, the active trench and the gate electrode therein partially or completely overlap the first and second contact regions and / or the first and second base regions. For example, the active trench extends deeper into the semiconductor body than the first and second contact regions and / or than the first and second base regions. For example, the active trench and the gate electrode extend at least 2 micrometers, or at least 4 micrometers, and / or at most 10 micrometers into the semiconductor body in the vertical direction.
[0030] According to another embodiment, the semiconductor device comprises a dummy trench arranged adjacent to the active trench and spaced apart from the active trench in the first lateral direction.
[0031] The trenches with a gate electrode therein are referred to herein as "active trenches". The trenches without a gate electrode therein are referred to herein as "dummy trenches". For example, the second base region and the second contact region are arranged between an active trench and a dummy trench in the first lateral direction. The second base region can adjoin the active trench and the dummy trench in the first lateral direction.
[0032] According to another embodiment, the dummy trench is filled with an electrically conductive material, for example, highly doped polysilicon. The electrically conductive material is electrically isolated from the semiconductor body, for example, by the isolation material. For example, the electrically conductive material in the dummy trench is electrically connected to the main electrode.
[0033] The trenches of the semiconductor device, whether they are active trenches or dummy trenches, can have the same dimensions within the limits of manufacturing tolerances. Alternatively, the dummy trenches can be deeper or shallower than the active trenches.
[0034] For example, exactly one active trench is arranged between the first and second contact regions and between the first and second base regions. The first and second contact regions can adjoin the active trench on different sides with respect to the first lateral direction. Likewise, the first and second base regions can adjoin the active trench on different sides with respect to the first lateral direction.
[0035] According to another embodiment, an enhancement region of the first conductivity type is arranged vertically between the first base region and the drift layer. For example, the enhancement region extends laterally over the entire lateral extension of the first base region. Thus, the enhancement layer is arranged between the drift layer and the first base region over the entire lateral extension of the first base region. The enhancement region can adjoin the first base region and / or the drift layer. This enhancement region is also referred to herein as "first enhancement region".
[0036] According to another embodiment, the enhancement region has a greater doping concentration than the drift layer. For example, the doping concentration in the first enhancement region is at least 10 times or at least 100 times greater than the doping concentration in the drift layer. For example, the doping concentration in the enhancement region is at least 10 15 cm -3 and / or at most 10 19 cm -3 . The thickness of the enhancement region, measured in the vertical direction, is for example at least 1 micrometer and / or at most 3 micrometers.
[0037] The enhancement region is a barrier region for charge carriers of the second type, for example, holes. It can thus be referred to as "hole barrier region" or "hole barrier layer", respectively.
[0038] According to another embodiment, the semiconductor device comprises a third base region of the second conductivity type. The third base region is arranged adjacent to the second base region in the first lateral direction, such that the second base region is arranged between the first base region and the third base region in the first lateral direction. The second base region and the third base region can be spaced apart from each other in the first lateral direction by a trench (e.g. by exactly one trench). This trench can be an active trench or a dummy trench.
[0039] The third base region is also arranged vertically between the top side and the drift layer. It can abut the top side and / or the drift layer. The doping concentration in the third base region can be in the same or different range as the doping concentration in the first base region. The thickness of the third base region, measured in the vertical direction, is for example larger than the thickness of the first base region, e.g. at least 1 micron larger.
[0040] According to another embodiment, the third base region extends from the top side into the semiconductor body. For example, the third base region extends deeper into the semiconductor body than the active trench or than the trench. For example, the third base region extends at least 1 micron deeper into the semiconductor body than the trench. The third base region is for example a so-called p-well.
[0041] According to another embodiment, the thickness of the insulating material between the first contact region and / or the first base region and the gate electrode is larger than the thickness of the insulating material between the second contact region and / or the second base region and the gate electrode. For example, the thickness between the first contact region / first base region and the gate electrode is at least 1.5 times or at least twice as large as the thickness between the second contact region / second base region and the gate electrode.
[0042] According to another embodiment, the main electrode is not in direct electrical contact with the second base region. This means that charge carriers cannot directly flow from the main electrode into the second base region and vice versa. Rather, the exchange of charge carriers always has to take place via the second contact region.
[0043] According to another embodiment, the semiconductor device comprises a further gate electrode. The further gate electrode is spaced apart from the gate electrode in the first lateral direction. For example, the further gate electrode is at the same electrical potential as the gate electrode. In other words, the gate electrode and the further gate electrode can be short-circuited.
[0044] In addition, the further gate electrode can be arranged in an active trench extending from the top side into the semiconductor body.
[0045] According to another embodiment, the second base region is arranged in the first lateral direction between the gate electrode and the further gate electrode. For example, no further gate electrode is arranged in the first lateral direction between the gate electrode and the further gate electrode. The second base region can abut both active trenches comprising the gate electrode and the further gate electrode in the first lateral direction.
[0046] According to another embodiment, the semiconductor device is configured to reverse a region in the second base region at a side of the second base region opposite to the side of the second base region where the region is reversed by means of the gate electrode by setting a potential of a further gate electrode. The further gate electrode thus provides a current path at this opposite side. "Opposite" here refers to the first lateral direction. In other words, the gate electrode and the further gate electrode reverse a region in the second base region, they are arranged at opposite sides and they are spaced apart, for example, in the first lateral direction.
[0047] In other words, the gate electrode and the further gate electrode establish two channels, for example hole channels, for transporting charge carriers.
[0048] According to another embodiment, the first and / or second contact region is an elongated area extending in a second lateral direction oblique to the first lateral direction, for example perpendicular to the first lateral direction. This means that, in each case, the lateral extension of the first and / or second contact region is greater in the second lateral direction than in the first lateral direction. For example, in each case, the lateral extension in the second lateral direction is at least twice or at least five times greater than in the first lateral direction. The first and second contact region can adjoin the top side over the entire lateral extension in the first and / or second lateral direction.
[0049] Likewise, the first and second base regions can be elongated and extend in the second lateral direction. The trench can also be elongated and can extend in the second lateral direction.
[0050] According to another embodiment, the semiconductor device comprises a plurality of first contact regions adjoining the top side and the first base region and in electrical contact with the main electrode. These first contact regions are separated and spaced apart from each other in the second lateral direction. For example, each first contact region has a lateral extension in the second lateral direction of at least 500 nanometers or at least 1 micrometer. In each case, the distance between every two adjacent first contact regions in the second lateral direction can be at least 500 nanometers or at least 1 micrometer. All features disclosed so far for one first contact region are also disclosed for all other first contact regions, in particular with regard to the doping concentration and the conductivity type.
[0051] According to another embodiment, the semiconductor device comprises a plurality of second contact regions adjoining the top side and the second base region and in electrical contact with the main electrode. These first contact regions are separated and spaced apart from each other in the second lateral direction. For example, each second contact region has a lateral extension in the second lateral direction of at least 500 nanometers or at least 1 micrometer. In each case, the distance between every two adjacent second contact regions in the second lateral direction can be at least 500 nanometers or at least 1 micrometer. All features disclosed so far for one second contact region are also disclosed for all other second contact regions, in particular with respect to the doping concentration and the conductivity type.
[0052] According to another embodiment, the semiconductor device is a power semiconductor device. For example, the semiconductor device is configured for handling an electrical current of at least 1 ampere (A) and / or a voltage of at least 100 volts (V). The semiconductor device is, for example, a so-called vertical semiconductor device.
[0053] According to another embodiment, the semiconductor device is a vertical device, i.e., a vertical structure. Then the cathode and the anode are arranged at opposite sides of the semiconductor body.
[0054] According to another embodiment, the semiconductor device is a bipolar semiconductor device, in which both electrons and holes contribute to the electrical current during operation.
[0055] According to another embodiment, the semiconductor device is an insulated gate bipolar transistor (IGBT) or a MOS-controlled diode. The semiconductor device is, for example, a reverse conducting (RC)-IGBT or a bidirectional IGBT (BIGT).
[0056] According to another embodiment, the semiconductor device comprises a further main electrode applied to a back side of the semiconductor body opposite the top side. The semiconductor body can comprise a contact layer (anode layer) and / or a buffer layer between the drift layer and the further main electrode.
[0057] Next, a method for manufacturing a semiconductor device is described. The method is particularly suitable for manufacturing a semiconductor device according to any one of the embodiments described herein. Therefore, all features disclosed for the semiconductor device are also disclosed for the method and vice versa
[0058] According to an embodiment of a method for manufacturing a semiconductor device, the method comprises a step of providing a semiconductor body having a top side and a drift layer of a first conductivity type. In a further step, a first base region, a second base region, a first contact region and a second contact region are manufactured. The first base region is of a second conductivity type and is manufactured such that the first base region is vertically located between the drift layer and the top side. The second base region is of the first conductivity type and is manufactured such that the second base region is vertically located between the drift layer and the top side, wherein the second base region has a greater doping concentration than the drift layer and adjoins the drift layer. The first contact region is of the first conductivity type and is manufactured such that the first contact region adjoins the first base region and the top side. The second contact region is of the second conductivity type and is manufactured such that the second contact region adjoins the second base region and the top side. In a further step, a main electrode is applied to the top side and electrical contact between the main electrode and the first contact region and between the main electrode and the second contact region is established. In a further step, a gate electrode is formed such that at least a portion of the last gate electrode is located between the first contact region and the second contact region and between the first base region and the second base region in a first lateral direction.
[0059] Before the first and second base regions and the first and second contact regions are formed, the drift layer can reach the top side, e.g. the top side is formed. Manufacturing the base regions and / or the contact regions can comprise implantation of dopants, e.g. through the top side. For example, a mask is used to define the regions in which the dopants for the different regions shall be implanted. BRIEF DESCRIPTION OF DRAWINGS
[0060] Next, the semiconductor device and the method for manufacturing a semiconductor will be explained in more detail according to exemplary embodiments with reference to the accompanying drawings. The drawings are included to provide a further understanding of the embodiments. In the drawings, identical structures and / or functions are labeled with the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. Where elements or assemblies are shown cross-sectional, the sections are shown as solid lines through the middle of the element or group, with it being understood that the sections can be vertical or horizontal, diagonal or otherwise oriented. Descriptions of elements or assemblies with like reference numerals are not repeated in the various figures. Elements can not be present in all figures.
[0061] Figures 1 to 5 , Figure 9 , Figure 16 , Figures 18 to 29 and Figure 31 different exemplary embodiments of a semiconductor device in different views are shown,
[0062] Figure 6 and Figure 10 a reference semiconductor device is shown,
[0063] Figure 7 , Figure 8 and Figures 11 to 15Simulation results illustrating the behavior of exemplary embodiments of a semiconductor device and of a reference semiconductor device are shown,
[0064] Figure 17 An example of a semiconductor device is shown,
[0065] Figure 30 A flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device is shown. DETAILED DESCRIPTION
[0066] Figure 1 A portion of a first exemplary embodiment of a semiconductor device 100 is shown in the form of a cross-sectional view. The semiconductor device 100 comprises a semiconductor body 1, for example made of Si or SiC or GaN. A main electrode 2 is applied on a top side 10 of the semiconductor body 1. The main electrode 2 is for example a metal electrode.
[0067] The semiconductor body 1 comprises a drift layer 11 of a first conductivity type. In the following, it is assumed that the first conductivity type is electron conduction and the corresponding doping is n-doping. Thus, the drift layer 11 is n-doped. However, the embodiments will also work if the first conductivity type is hole conduction.
[0068] A first base region 12 and a second base region 13 are each located vertically between the drift layer 11 and the top side 10. "Vertically" in this context means in a vertical direction V, which is a direction perpendicular to the top side 10. The first base region 12 and the second base region 13 are arranged adjacent to each other in a first lateral direction LI, which is a direction parallel to the top side 10. The first base region 12 is of a second conductivity type different from the first conductivity type, i.e. in this example p-doped. The second base region 13 is of the first conductivity type, i.e. n-doped. Both base regions 12, 13 adjoin the drift layer 11 and the top side 10.
[0069] A first contact region 14 is embedded in the first base region 12. The first contact region 14 is of the first conductivity type (i.e. n-doped) and adjoins the first base region 12 as well as the top side 10. At the top side 10, the first contact region 14 is in direct mechanical and electrical contact with the main electrode 2. The first base region 12 is also in direct mechanical and electrical contact with the main electrode 2 at the top side 10.
[0070] A second contact region 15 is embedded in the second base region 13. The second contact region 15 is of the second conductivity type (i.e. p-doped) and adjoins the second base region 13 as well as the top side 10. At the top side 10, the second contact region 15 is in direct mechanical and electrical contact with the main electrode 2. However, the main electrode is not in direct mechanical or electrical contact with the second base region 13, so that the exchange of charge carriers between the main electrode 2 and the second base region 13 always has to take place through the second contact region 15.
[0071] Lateral to the base regions 12, 13 and the contact regions 14, 15, the active trench 4 extends from the top side 10 into the semiconductor body 1 and opens into the drift layer 11. The depth of the active trench 4, measured in the vertical direction V, is greater than the thickness of the base regions 12, 13 and the contact regions 14, 15, also measured in the vertical direction V. The gate electrode 3 is arranged inside the active trench 4. The gate electrode 3 is made of, for example, highly doped polysilicon. The gate electrode 3 is electrically isolated from the semiconductor body 1, in particular from the base regions 12, 13 and the contact regions 14, 15, by an electrically isolating material 5, for example Si02. Figure 1 The semiconductor device 100 is a so-called trench device.
[0072] The doping concentration of the drift layer 11 is, for example, in the range between 10 8 cm -3 and 10 15 cm -3 . The doping concentration of each base region 12, 13 is, for example, in the range between 10 15 cm -3 and 10 18 cm -3 . The doping concentration in the contact regions 14, 15 is in each case in the range between, for example, 10 18 cm -3 and 10 21 cm -3 .
[0073] During the on state of the semiconductor device 100, the gate electrode 3 can be at a positive potential with respect to the semiconductor body 1. Thereby, an inversion region is formed in the first base region 12 at the side facing the active trench 4, which extends along the active trench 4 from the first contact region 14 to the drift layer 11. This enables the injection of electrons from the main electrode 2 into the contact region 14 and from there inside the inversion region into the drift layer 11.
[0074] In the off state of the semiconductor device 100, the gate electrode 3 can be at a negative potential with respect to the semiconductor body 1. The potential of the main electrode 2 and of the further main electrode can be the same as in the on state. Thereby, an inversion region is formed in the second base region 13 at the side facing the active trench 4, which extends along the active trench 4 from the second contact region 15 to the drift layer 11. This enables holes to come out of the drift layer 11 via the inversion region and to travel along the inversion region, then through the second contact region 15 and into the main electrode 2.
[0075] In particular in the case of the semiconductor device 100 being a bipolar device, such as an IGBT, a very efficient hole extraction can be achieved in this way, which leads to reduced switching losses.
[0076] The transistor realized with the first base region 12 and the first contact region 14 is referred to herein as the "main transistor", the transistor realized with the second base region 13 and the second contact region 15 is referred to herein as the "complementary transistor". In the exemplary embodiments described herein, the main transistor is an NMOS transistor, the complementary transistor is a PMOS transistor.
[0077] Figure 2 The exemplary embodiments of Figure 1 show a so-called planar device, which does not use trenches as shown in. Instead, the gate electrode 3 is arranged on the top side 10 and is electrically isolated from the semiconductor body 1 by the electrically isolating material 5. In plan view on the top side 10, the gate electrode 3 partially covers, i.e. overlaps, the first contact region 14 and the second contact region 15. While Figure 1 the inverter region and the associated current path in are mainly oriented in the vertical direction V, the inverter region and the associated current path in are mainly oriented in the first lateral direction LI. Figure 2
[0078] Figure 3 The exemplary embodiments of show a semiconductor device 100, which is an insulated-gate bipolar transistor, shortly IGBT. On the back side of the semiconductor body 1, opposite to the top side 10, a further main electrode 6 is applied, which is for example a metal. The semiconductor body 1 comprises a further layer 20 of the second conductivity type, i.e. p-doped, which forms the back side and is in direct electrical and mechanical contact with the further main electrode 6. The doping concentration of the further layer 20 is for example larger than the doping concentration in the drift layer 11. Between the drift layer 11 and the layer 20, a layer 19 of the first conductivity type is applied. The layer 19 is adjacent to the layer 20 and the drift layer 11. The doping concentration in the layer 19 is for example larger than the doping concentration in the drift layer 11. The layer 19 is a so-called buffer layer.
[0079] In Figure 3 , the first base region 12 is adjacent to the active trench 4 on both sides with respect to the first lateral direction LI. Both active trenches 4 are connected to the gate electrode 3. Also with respect to the first lateral direction LI, the second base region 13 is arranged on both sides of the first base region 12, each spaced apart from the first base region 12 by one of the active trenches 4.
[0080] The second base regions 13 are each located between and adjacent to two trenches 4, 40. In both cases, only the trench closer to the first base region 12 is the active trench 4. The respective other trench 40 is a dummy trench. The dummy trench 40 is filled with an electrically conductive material, which is for example electrically connected to the main electrode 2 and thus at the same electrical potential as the main electrode 2. The dummy trench 40 helps to reduce the capacitance between the gate electrode 3 and the further main electrode 6, also referred to as Miller capacitance or gate-collector capacitance (Cgc).
[0081] Figure 3 Other accompanying figures may show only a portion of the semiconductor device. The structures shown in these figures, including base regions 12, 13 and contact regions 14, 15, may be repeated several times along the first transverse direction L1.
[0082] exist Figure 4 In an exemplary embodiment, the semiconductor body 1 includes a third base region 18 of a second conductivity type (i.e., p-doped), and the third base region 18 is adjacent to a dummy trench 40 on a side opposite to the second base region 13. The doping concentration in the third base region 18 may be the same as or different from the doping concentration in the first base region 12. The third base region 18 constitutes a p-well that extends deeper into the semiconductor body 1 than the trenches 4, 40. Improved breakdown voltage can be obtained using the third base region 18.
[0083] Figure 5 It shows Figure 4 A detailed view of an exemplary embodiment, wherein only half of the first base region 12, the adjacent second base region 13, and the third base region 18 are shown. Figure 5 Different shades are used to represent the doping distribution. The higher the lattice density of the shades, the higher the doping concentration.
[0084] Figure 6 A reference semiconductor device 200, such as a reference IGBT, is shown. (Compared to...) Figure 5 Compared to the IGBT, the second base region 13 and the second contact region 15 are eliminated. Instead, the semiconductor body 1 adjacent to the top side 10 is also made of a semiconductor material of a second conductivity type, for example, having the same doping concentration as the first base region 12, laterally between the dummy trench 40 and the active trench 4. The main electrode 2 is in electrical and mechanical contact with the semiconductor body 1 in the region between the two trenches 4, 40 (dummy contacts).
[0085] Figure 7 and 8 It shows according to Figure 5 The relationship between the output characteristics Ic and Vce of the IGBT (curve 100) and according to Figure 6 The simulation compares the output characteristics Ic of the reference IGBT (i.e., without a second base region and a second contact region) with the relationship between Vce (curve 200). Figure 7 It shows a range from 0 to 2 volts. Figure 8 The range from 0 to 25 volts is shown. (According to...) Figure 6 Compared to the reference IGBT, according to Figure 5 The IGBT exhibits an improvement of approximately 130 mV on Vce-sat. In the reference IGBT, extracting injected holes between the dummy trench 40 and the active trench 4 during the on-state leads to a deterioration in the plasma concentration in the drift region (drift layer 11), and thus results in higher on-state losses.Figure 5 In the IGBT, this hole extraction between the dummy trench 40 and the active trench 4 is significantly suppressed (approximately 50%, see also) during the on-state. Figure 9 This is the result of placing the second base region and the second contact region (PMOS transistor) between the active trench 4 and the dummy trench 40. This PMOS transistor is off during the IGBT's on-state (Vge > Vth), effectively eliminating the hole extraction path in the region between the active trench 4 and the dummy trench 40. This explains the IGBT's exceptionally high Vce-sat, which is very close to the Vce-sat of a certain IGBT that has no semiconductor body electrical contact with the main electrode in the lateral top-side region between the dummy trench 40 and the active trench 4 (i.e., no dummy contact).
[0086] In short, the electrical contact with the main electrode 2 in the region between the active trench 4 and the dummy trench 40 is effectively invisible during the IGBT conduction state, which is necessary to maintain the plasma concentration.
[0087] Figure 9 It is shown in accordance with Figure 5 The simulated hole current flow circuit during the on-state operation of the IGBT, and Figure 10 It shows that according to Figure 6 The simulation of the hole current flow path of the reference IGBT is shown. The density of the contour lines is proportional to the hole current. Figure 9 and 10 In this setting, Vce is chosen as 3 volts. As can be seen, for [the voltage]... Figure 5 and Figure 9 In the IGBT, the current flow of holes between the active trench 4 and the dummy trench 40 is significantly suppressed.
[0088] Figure 11 It shows according to Figure 5 The simulated hole current versus voltage Vce at the second contact region is shown for the IGBT (curve 100) and the reference IGBT (curve 200) during on-state operation. As illustrated, this is achieved using... Figure 5 The IGBT can reduce hole current by about 50% when it is in the on state.
[0089] Figure 12 A simulation of the relationship between Ic and Vce is shown with Vge = -15 volts. As can be seen, according to Figure 5 The blocking capability of the IGBT (curve 100) and according to Figure 6 The blocking capability (curve 200) of the reference IGBT is almost the same.
[0090] Figure 13 Simulations of turn-off switching characteristics of an IGBT according to Figure 5 (curve 100_i) and a reference IGBT according to Figure 6 (curve 200_i) are shown. Curves 100_l, 200_l show Vce versus time T, curves 100_2, 200_2 show Vge versus time T, and curves 100_3, 200_3 show Ic versus time T. The turn-off switching losses (Eoff) of the IGBT according to Figure 5 are very close to the turn-off switching losses of the reference IGBT according to Figure 6 It should also be noted that the Eoff of the IGBT according to Figure 5 is lower than the Eoff of the reference IGBT, where there is no electrical contact to the main electrode in the area between the trenches in the reference IGBT (see table below). This means that the PMOS transistor, which prevents the outflow of holes in the on-state, is now active in the IGBT off-state and can effectively draw holes out of the IGBT device, which in turn reduces its switching losses. In other words, the contact to the main electrode in the area between the dummy trenches and the active trenches, which is effectively invisible during the IGBT on-state, is visible during the IGBT off-state, which is required for simultaneously improving the on-state and the switching losses.
[0091] Figure 14 Simulations of turn-on switching characteristics with the same terminology as in Figure 13 are shown. The IGBT according to Figure 6 shows lower turn-on losses (Eon) compared to the reference IGBT according to Figure 5 , which is due to its lower gate-emitter capacitance (Cge). However, the total losses Etotal (i.e. Erec + Eon), where Erec is the diode reverse recovery losses (see table below), remain the same.
[0092] Figure 15 Simulations of the technical curves (Eoff versus Vce_sat) at 25°C of the IGBT according to Figure 5 (curve 100) compared to the reference IGBT according to Figure 6 (curve 200) are shown. The IGBT according to Figure 5 has superior technical curves compared to the reference IGBT. For the same Vce-sat, the Eoff of the IGBT according to Figure 5 is 18% lower compared to the reference IGBT. However, for the same Eoff, the Vce-sat of the IGBT according to Figure 5 is 5% lower compared to the Vce-sat of the reference IGBT.
[0093] The following table shows a summary of simulation results for an IGBT according to Figure 5 compared to a reference IGBT according to Figure 6 and compared to an IGBT according to Figure 6 without a main electrode in electrical contact with the semiconductor body in the region between the active trench 4 and the dummy trench 40 (i.e. without a dummy contact).
[0094]
[0095] Figure 16 Another exemplary embodiment of a semiconductor device 100 is shown which is similar to one of Figure 3 However, in contrast to the exemplary embodiment of Figure 3 the first enhancement region 16 is arranged between the drift layer 11 and the first base region 12. The first enhancement region 16 is of the first conductivity type (i.e. n-doped) and has a larger doping concentration than the drift layer 11, e.g. at least 10 times larger. The enhancement region 16 improves the on-state losses or Vce-sat by reducing hole leakage.
[0096] Figure 17 An example of an IGBT is shown which is similar to one of Figure 16 but in which the second enhancement region 17 is of the second conductivity type (i.e. p-doped) and is arranged vertically between the second base region 13 and the drift layer 11. These enhancement regions 17 reduce electron leakage via the electrical contact of the main electrode 2 with the second contact region 15 and improve hole collection during turn-off.
[0097] Figure 18 An exemplary embodiment is shown which is similar to one of Figure 4 but which additionally comprises a first enhancement region 16 between the first base region 12 and the drift layer 11.
[0098] Figure 19 The exemplary embodiment of Figure 18 is similar to one of However, in the active trench 4, the electrically isolating layer 5 is thicker between the gate electrode 3 and the first contact region 14 than between the second contact region 15 and the gate electrode 3. This design can reduce the Vth of the PMOS transistor, allowing it to turn on earlier during the IGBT turn-off state, in order to further reduce the switching losses. In turn, the doping concentration in the second base region 13 can be further increased to reduce hole leakage via diffusion in the IGBT on-state.
[0099] Figure 20In an exemplary embodiment of the planar IGBT 100, the first contact region 14 extends over the entire lateral extension of the first base region 12 in the first lateral direction LI. In other words, the first contact region 14 extends from one active trench 4 to the next active trench 4 in the first lateral direction LI. In this way, the hole path from the drift layer 11 to the main electrode 2 via the first base region 12 can be completely suppressed.
[0100] In an exemplary embodiment of the planar IGBT 100, the second contact region 15 is formed in the second base region 13. The main electrode 2 can also be in electrical contact with these second contact regions 15. Figure 21
[0101] Figure 22 An exemplary embodiment of the planar IGBT 100 is similar to one of the exemplary embodiments in Figure 21 However, the trenches on both sides of the second base region 13 are now active trenches 4. In this embodiment, a PMOS transistor is formed at the two active trenches 4 that adjoin the respective second base region 13.
[0102] Figure 23 An exemplary embodiment of the planar IGBT 100 shows a similar exemplary embodiment to Figure 22 but with an additional dummy trench 40 in the first lateral direction LI that sandwiches four active trenches 4. Further second base regions 13 are formed between the dummy trench 40 and the active trenches 4. With the additional dummy trench 40, the Miller capacitance (Cgc) can be further reduced.
[0103] In an exemplary embodiment of the planar IGBT 100, the second contact region 15 is formed in the further second base region 13. The main electrode 2 can also be in electrical contact with these second contact regions 15. Figure 24 Figure 23 In an exemplary embodiment of the planar IGBT 100, the second contact region 15 is formed in the further second base region 13. The main electrode 2 can also be in electrical contact with these second contact regions 15.
[0104] In an exemplary embodiment of the planar IGBT 100, only the second base regions 13 are formed between the active trenches 4 and the dummy trench 40. On the other side of the dummy trench 40, third base regions 18 of the second conductivity type are formed. The dummy trench 40 and the active trenches 4 extend deeper into the semiconductor body 1 than the base regions 12, 13, 18. Figure 25 In an exemplary embodiment of the planar IGBT 100, a planar IGBT 100 is shown that is similar to one of the exemplary embodiments in
[0105] In addition, an enhancement region 16 of the first conductivity type is provided between the first base region 12 and the drift layer 11. Figure 26 Figure 2 An exemplary embodiment of the planar IGBT 100 is shown with an electrically isolating layer 5 of non-uniform thickness for reducing the gate capacitance.
[0106] Figure 31 An exemplary embodiment of the planar IGBT 100 is shown with an electrically isolating layer 5 of non-uniform thickness for reducing the gate capacitance.
[0107] Figure 27 An exemplary embodiment of the semiconductor device 100 is shown in a plan view on the top side 10. As can be seen from the figure, the base regions 12, 13 and the contact regions 14, 15 are all elongated, and their main extension directions are in each case parallel to the second lateral direction L2, which is perpendicular to the first lateral direction L1.
[0108] exist Figure 28 In an exemplary embodiment, a plurality of first contact areas 14 are embedded in the same first base region 12. These first contact areas 14 are arranged one after another and spaced apart from each other in the second lateral direction L2.
[0109] exist Figure 29 In this configuration, multiple second contact areas 15 are embedded in the second base region 13. The second contact areas 15 are arranged one after another and spaced apart from each other in the second lateral direction L2. Figure 29 As shown, the first contact area 14 does not have to be completely opposite to the second contact area 15, but can be arranged in an alternating configuration.
[0110] Compared to the exemplary embodiment shown, the thickness (depth) of the first base region 12 and the second base region 13 may be different from each other. Furthermore, the spacing between the trenches 4 and 40 may also be different from each other.
[0111] Figure 30 A flowchart illustrating an exemplary embodiment of a method for manufacturing a semiconductor device is shown.
[0112] In step S1, a semiconductor body having a top side and a drift layer of a first conductivity type is provided. In further steps S2, S3, S4, and S5, a first base region, a second base region, a first contact region, and a second contact region are fabricated. The first base region is of a second conductivity type and is fabricated such that it is perpendicularly located between the drift layer and the top side. The second base region is of a first conductivity type and is fabricated such that it is perpendicularly located between the drift layer and the top side, wherein the second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer. The first contact region is of a first conductivity type and is fabricated such that it is adjacent to the first base region and the top side. The second contact region is of a second conductivity type and is fabricated such that it is adjacent to the second base region and the top side. In a further step S6, a main electrode is applied to the top side, and electrical contacts are established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step S7, a gate electrode is formed such that, in the last lateral direction, the gate electrode is located between the first contact region and the second contact region and between the first base region and the second base region.
[0113] The embodiments shown in the figures represent exemplary embodiments of improved semiconductor devices and improved methods for manufacturing semiconductor devices; thus, they do not constitute a complete list of all embodiments of improved semiconductor devices and improved methods. Actual semiconductor devices and methods can differ in arrangement and elements from the embodiments shown.
[0114] Reference Signs
[0115] 1 semiconductor body
[0116] 2 main electrode
[0117] 3 gate electrode
[0118] 4 active trench
[0119] 5 electrically isolating material
[0120] 6 further main electrode
[0121] 10 top side
[0122] 11 drift layer
[0123] 12 first base region
[0124] 13 second base region
[0125] 14 first contact region
[0126] 15 second contact region
[0127] 16 first enhancement region
[0128] 17 second enhancement region
[0129] 18 third base region
[0130] 19 layer
[0131] 20 layer
[0132] 40 dummy trench
[0133] 100 semiconductor device
[0134] 200 reference semiconductor device
[0135] Si method step
[0136] L1 first lateral direction
[0137] L2 second lateral direction
[0138] V vertical direction
[0139] 100_i label of curve
[0140] 200_i label of the curve
Claims
1. A bipolar semiconductor device (100), comprising: - A semiconductor body (1) having a top side (10) and a back side. - The main electrode (2) on the top side (10). -The other main electrode (6) on the back side, and - Gate electrode (3), where -The semiconductor body (1) includes: - Drift layer of the first conductivity type (11). - A first base region (12) of a second conductivity type is vertically arranged between the drift layer (11) and the top side (10). - A second base region (13) of a first conductivity type is vertically arranged between the drift layer (11) and the top side (10), the second base region (13) having a larger doping concentration than the drift layer (11) and adjacent to the drift layer (11). - A first contact region (14) of a first conductivity type, the first contact region (14) being adjacent to the first base region (12) and the top side (10). - A second contact region (15) of a second conductivity type, the second contact region (15) being adjacent to the second base region (13) and the top side (10). - The main electrode (2) is in electrical contact with the first contact area (14) and the second contact area (15). - In the first lateral direction (L1), at least a portion of the gate electrode (3) is disposed between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13). - The thickness of the electrical isolation material (5) between the first contact area (14) and / or the first base area (12) and the gate electrode (3) is greater than the thickness of the electrical isolation material (5) between the second contact area (15) and / or the second base area (13) and the gate electrode (3).
2. The bipolar semiconductor device according to claim 1, wherein... - The bipolar semiconductor device (100) is configured such that by setting the potential of the gate electrode (3), - By means of the gate electrode (3), the region in the first base region (12) is reversed, and the current flow of the first type of charge carriers between the drift layer (11) and the first contact region (14) is allowed to pass through this region. - Alternatively, the region in the second base region (13) can be reversed by means of the gate electrode (3), and the current flow of the second type of charge carriers between the drift layer (11) and the second contact region (15) can pass through this region.
3. The bipolar semiconductor device (100) according to claim 1 or 2, wherein - The bipolar semiconductor device (100) is a planar device having the gate electrode (3) arranged on the top side (10).
4. The bipolar semiconductor device (100) according to claim 1 or 2, wherein -The bipolar semiconductor device (100) is a trench device, wherein, The gate electrode (3) is arranged in an active trench (4) extending from the top side (10) into the semiconductor body (1) in a vertical direction (V).
5. The bipolar semiconductor device (100) according to claim 4, wherein the bipolar semiconductor device (100) further comprises: - At least one dummy trench (40) is arranged adjacent to the active trench (4) and spaced apart from the active trench (4) in the first lateral direction (L1), wherein - The dummy trench (40) is filled with a conductive material that is electrically connected to the main electrode (2).
6. The bipolar semiconductor device (100) according to any one of claims 1, 2, or 5, wherein - A reinforcement region (16) of the first conductivity type is vertically arranged between the first base region (12) and the drift layer (11). - The enhancement region (16) has a higher doping concentration than the drift layer (11).
7. The bipolar semiconductor device (100) according to claim 5, wherein The third base region (18) of the second conductivity type is arranged adjacent to the second base region (13) in the first lateral direction (L1) such that the second base region (13) is arranged between the first base region (12) and the third base region (18) in the first lateral direction (L1).
8. The bipolar semiconductor device (100) according to claim 7, wherein - The third base region (18) extends from the top side (10) into the semiconductor body (1) and extends deeper into the semiconductor body (1) than the active trench (4).
9. The bipolar semiconductor device (100) according to any one of claims 1, 2, or 5, wherein - The main electrode (2) is not in direct electrical contact with the second base region (13).
10. The bipolar semiconductor device (100) according to any one of claims 5, 7 or 8, further comprising: - Another gate electrode (3) spaced apart from the gate electrode (3) in the first lateral direction (L1), wherein - The second base region (13) is arranged in the first transverse direction (L1) between the gate electrode (3) and the other gate electrode (3). - The bipolar semiconductor device (100) is configured to reverse a region in the second base region (13) by means of the other gate electrode (3) by setting the potential of the other gate electrode (3), the region being located on one side of the second base region (13) opposite to the side of the second base region (13) where the region in the second base region (13) is reversed by means of the gate electrode (3), thereby providing a current path on this opposite side.
11. The bipolar semiconductor device (100) according to any one of claims 1-2, 5, 7 or 8, wherein - The first contact area (14) and / or the second contact area (15) are elongated regions extending in a second lateral direction (L2) inclined to the first lateral direction (L1).
12. The bipolar semiconductor device (100) according to any one of claims 1-2, 5, 7 or 8, wherein the bipolar semiconductor device (100) comprises: - A plurality of first contact areas (14), said plurality of first contact areas (14) being adjacent to the top side (10) and the first base region (12) and in electrical contact with the main electrode (2), wherein the first contact areas (14) are separated from each other and spaced apart in a second lateral direction (L2) inclined to the first lateral direction (L1), and / or - A plurality of second contact areas (15) adjacent to the top side (10) and the second base area (13) and in electrical contact with the main electrode (2), wherein the second contact areas (15) are separated from each other and spaced apart in a second lateral direction (L2) inclined to the first lateral direction (L1).
13. The bipolar semiconductor device (100) according to any one of claims 1-2, 5, 7 or 8, wherein - The bipolar semiconductor device (100) is an IGBT.
14. A method for manufacturing a bipolar semiconductor device (100), the method comprising: - Provide a semiconductor body (1) having a top side (10), a back side and a drift layer (11) of a first conductivity type. -manufacture - A first base region (12) of the second conductivity type, such that the first base region (12) is vertically located between the drift layer (11) and the top side (10). - A second base region (13) of a first conductivity type, such that the second base region (13) is vertically located between the drift layer (11) and the top side (10), wherein the second base region (13) has a larger doping concentration than the drift layer (11) and is adjacent to the drift layer (11). - A first contact region (14) of a first conductivity type, such that the first contact region (14) is adjacent to the first base region (12) and the top side (10). - A second contact region (15) of a second conductivity type, such that the second contact region (15) is adjacent to the second base region (13) and the top side (10). - The main electrode (2) is applied to the top side (10), and electrical contacts are established between the main electrode (2) and the first contact area (14) and between the main electrode (2) and the second contact area (15). - Apply another main electrode to the back side. - A gate electrode (3) is formed such that at least a portion of the last gate electrode (3) is located in the first lateral direction (L1) between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13). - The thickness of the electrical isolation material (5) between the first contact area (14) and / or the first base area (12) and the gate electrode (3) is greater than the thickness of the electrical isolation material (5) between the second contact area (15) and / or the second base area (13) and the gate electrode (3).
Citation Information
Patent Citations
A semiconductor device
CN110914996A
Double gate insulated gate bipolar transistor
US20090008674A1