Image sensing device with event-based vision sensor pixels and imaging pixels

Abstract

An image sensing apparatus is disclosed. In one example, an image sensing device includes a pixel cell having both an event sensing (EVS) pixel and an imaging pixel. The EVS and the imaging pixel are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit component that further includes photodiodes of the EVS and the imaging pixel. In one embodiment, the photodiode is separated by rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are disposed along (e.g., below) a boundary region formed by the RDTI, thereby maximizing space available for the photodiode and saving routing requirements for the EVS and imaging pixels.

Description

Technical Field

[0001] The present application relates generally to image sensors, and more particularly to image sensors including event-based sensor (EVS) pixels and imaging pixels. Background Art

[0002] Image sensors are used in various electronic imaging devices and systems, such as digital cameras, smart phones, medical imaging devices, night vision devices, automotive devices, etc. The two main types of image sensors used in such imaging devices are charge coupled device (CCD) sensors and active pixel complementary metal oxide semiconductor (CMOS) sensors.

[0003] CMOS image sensor devices may typically provide several processing and / or control functions directly in the sensor's integrated circuit (IC) and / or IC components. For example, some CMOS sensor functional circuits may implement one or more of the following: timing and exposure control, analog-to-digital conversion, shutter, white balance, gain adjustment, and initial signal and / or image processing. For optimal performance, it is generally necessary to properly integrate such functional circuits into the sensor.

[0004] In addition to receiving and processing images, some image sensing devices have associated event detection. Summary of the invention

[0005] Various embodiments of an image sensing device that supports both event-based vision sensor (EVS) and image capture modes of operation are disclosed herein.

[0006] In one example, an image sensing device includes a pixel cell having both an event sensing (EVS) pixel and an imaging pixel. The EVS and imaging pixels are configured to include event sensing and imaging pixel transistors formed in the same transistor layer of an integrated circuit component, which also includes the EVS and the photodiodes of the imaging pixels. The photodiodes are separated by rear deep trench isolation (RDTI), and the EVS and imaging pixel transistors are arranged along the boundary area formed by the RDTI (e.g., below it), thereby maximizing the space available for the photodiode and saving wiring requirements for the EVS and imaging pixels. These different features individually and collectively accommodate lower transistor density and larger active photodiode area.

[0007] In one example, an image sensing device includes: a pixel array, which includes imaging pixels and event sensing pixels, the pixel array is a two-dimensional array, and the imaging pixels and the event sensing pixels are staggered in the pixel array; an imaging pixel circuit, which is configured to provide an image signal from the imaging pixel; and an event sensing pixel circuit, which is configured to provide an event signal from the event sensing pixel.

[0008] The trench isolation may surround each imaging pixel and event sensing pixel in the pixel array. In addition, in a cross-sectional view, a first transistor in the imaging pixel circuit and a second transistor in the event sensing pixel circuit may be arranged under the trench isolation, respectively.

[0009] The two-dimensional array extends in the horizontal direction and the vertical direction, and the trench isolation may form a first boundary region extending in the horizontal direction and a second boundary region extending in the vertical direction. Then, in a cross-sectional view, the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit may be arranged below the first boundary region, respectively. Alternatively, in a cross-sectional view, the first transistor in the imaging pixel circuit may be arranged below the first boundary region, and in a cross-sectional view, the second transistor in the event sensing pixel circuit may be arranged below the second boundary region.

[0010] The pixel array may be formed on a first integrated circuit, wherein the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are respectively arranged in a same transistor layer of the first integrated circuit.

[0011] The image sensing device may also include a stacked assembly including a first portion bonded to a second portion, wherein the first portion includes a first integrated circuit and the second portion includes a second integrated circuit. Here, the third transistor in the event of the event sensing pixel circuit may be arranged in the second integrated circuit, and the fourth transistor in the image sensing pixel circuit may be arranged in the second integrated circuit.

[0012] The event sensing pixels each include a photodiode, and the photodiodes are connected in parallel to the event sensing pixel circuit to provide an event signal. The image sensing pixels also each include a photodiode, and corresponding different color filters may be arranged for individual ones of the image sensing pixels.

[0013] The event signal for the event sensing pixel can be connected for readout without switching gate control. At the same time, the image signal can be sequentially read out from the corresponding imaging pixel using the transfer transistor in parallel with the event signal readout. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Other aspects, features and benefits of various disclosed embodiments will become more apparent from the following detailed description and accompanying drawings, by way of example, in which:

[0015] Figure 1 is a block diagram illustrating an imaging system;

[0016] Figure 2is a perspective view showing an IC component for an imaging system;

[0017] Figure 3 It is the circuit block diagram of the IC component;

[0018] FIG. 4A to FIG. 4B are schematic diagrams and cross-sectional views showing examples of EVS and imaging pixels;

[0019] Figure 5 is a perspective view showing a portion of a metal interconnect structure of an IC component;

[0020] Figure 6A-6B is a circuit diagram showing an example of an EVS pixel circuit and an imaging pixel circuit;

[0021] Figure 7 is a layout diagram showing an example of a layout including EVS pixels and imaging pixels;

[0022] Figure 8 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0023] Fig. 9 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0024] Fig.10 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0025] Fig.11 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0026] Fig.12 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0027] Fig.13 is a circuit diagram showing another example of an EVS pixel circuit;

[0028] Fig.14 is a circuit diagram showing another example of an imaging pixel circuit;

[0029] Fig.15 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0030] Fig.16 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0031] Fig.17 is a circuit diagram showing another example of an EVS pixel circuit;

[0032] Fig.18 is a circuit diagram showing another example of an imaging pixel circuit;

[0033] Fig.19 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0034] Fig. 20 is a circuit diagram showing another example of an EVS pixel circuit;

[0035] Fig.21 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0036] Fig. 22 is a circuit diagram showing another example of an EVS pixel circuit;

[0037] Fig.23 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0038] Fig.24 is a circuit diagram showing another example of an imaging pixel circuit;

[0039] Fig.25 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0040] Fig.26 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0041] FIG. 27A to FIG. 27C is a schematic diagram showing other examples of EVS and imaging pixels;

[0042] FIG. 28A to FIG. 28C is a layout diagram showing an example of a layout including EVS pixels, imaging pixels, and an on-chip lens arrangement;

[0043] Fig.29 is a layout diagram showing another example of a layout including EVS pixels and imaging pixels;

[0044] FIG. 30A to FIG. 30B is a cross-sectional view showing an example of a rear deep trench isolation (RDTI) profile;

[0045] Figure 31 to Figure 32 is a timing diagram showing simultaneous EVS and imaging pixel readout processes; and

[0046] Fig.33 is a schematic diagram showing an implementation example of an image sensor in an automotive environment. DETAILED DESCRIPTION

[0047] Figure 11 is a block diagram illustrating an imaging system 100. The system 100 may be used, for example, in a camera for an industrial robot or an autonomous vehicle. Other uses of the system 100 are also contemplated.

[0048] As shown, system 100 includes an imaging lens 110, an electronic imaging device 120, a recording unit 130, and a control unit 140. In operation, lens 110 directs incident light 112 to form an image of a corresponding object or scene on a light receiving surface of imaging device 120. Such a light receiving surface typically includes a two-dimensional array of photodetectors (in Figure 1 is not explicitly shown; see, for example, Figure 7 ), configured to perform photoelectric conversion to generate an electrical signal representing an image. In an exemplary embodiment, the imaging device 120 is also operable to apply some signal processing to the electrical signal before outputting the corresponding digital signal 122 to the recording unit 130, for example, for storage in its memory. Such a memory may include, for example, a solid-state memory device or other suitable form of memory. The control unit 140 may use the control signals 124, 126 to control and coordinate various operations and / or functions performed by the imaging device 120 and the recording unit 130.

[0049] Figure 2 is a perspective view showing an IC assembly 200 for an imaging system. The IC assembly 200 includes a top chip 210 and a bottom chip 220 arranged in a vertical stack. In some examples, the top chip 210 may generally be a light receiving chip, and the bottom chip 220 may generally be a logic chip. The circuitry for the imaging and EVS pixels may be shared differently within the same chip, or may be arranged to be partially located on one chip and partially located on another chip, depending on the implementation as will be understood in at least the following examples.

[0050] As used herein, the term "stacked" refers to an ordered arrangement of packaged or non-packaged dies in which the principal planes of the stacked dies face each other and are close to each other. The facing dies or chips may be electrically connected, for example, using a patterned conductive (such as metal) layer, a ball grid array, solder bumps, wire bonding, etc. In some such embodiments, the stacked dies or chips may be mounted on a mechanical carrier in an orientation in which the principal planes of the stacked dies are parallel to each other and / or parallel to the principal plane of the mechanical carrier. In some such embodiments, one of the stacked dies or chips may be used as a mechanical carrier. In some embodiments, a stacked single IC may include any combination of one or more corresponding substrates, one or more redistribution layers (RDLs), one or more interposers, one or more laminates, and the like.

[0051] As used herein, a "principal plane" of an object (e.g., a die, substrate, or IC) is a plane parallel to its substantially planar surface that has approximately the largest area among the outer surfaces of the object. This substantially planar surface may be referred to as a major surface. An outer surface of an object that has one relatively large dimension (e.g., length) but a much smaller area (e.g., less than half the area of ​​the major surface) is often referred to as an edge of the object.

[0052] Here, the term “vertical” refers to a direction substantially orthogonal to a major plane of the top chip 210 or the bottom chip 220. Figure 2 In the embodiment of the present invention, the vertical direction is parallel to the Z coordinate axis. The term "horizontal" refers to a direction generally parallel to the principal plane. Figure 2 In the figure, the horizontal plane is parallel to the XY coordinate plane.

[0053] In some embodiments, the chips 210 and 220 may be flip-chip bonded using direct bonding, wherein the facing surfaces of the chips are planarized and the chips are laminated together to form the assembly 200. In some other embodiments, the chips 210 and 220 may be flip-chip bonded using Cu-to-Cu bonding, wherein copper (Cu) pads formed on the facing surfaces of the chips are bonded to provide electrical connections between the chips in the assembly 200. In some alternative embodiments, other suitable chip stacking techniques may also be used.

[0054] Figure 3 2 is a circuit block diagram of an IC assembly. The IC assembly 200 includes a pixel array unit 300, a driving circuit 310, a signal processing unit 320, an arbitrator 330, and a column analog-to-digital converter (ADC) circuit 340. In an exemplary embodiment, the top chip 210 ( Figure 2 ) may generally include pixel array unit 300, while bottom chip 220 may generally include driver circuit 310 and arbiter 330. In alternative embodiments, other suitable partitioning of circuits 310, 320, 330, and 340 between chips 210 and 220 may also be implemented, such as those further described herein.

[0055] The pixel array unit 300 includes a plurality of pixels 302 arranged in a two-dimensional matrix array, wherein the individual pixels 302 are arranged in mutually orthogonal rows and columns. The pixel matrix array 302 occupies at least a portion of the above-mentioned light receiving surface of the imaging device 120. Each pixel 302 may generally include two or more sub-pixels, for example, as described below with reference to FIG. 4A to FIG. 4B302. Some different sub-pixels of the same individual pixel unit 302 may differ, for example, in their respective sensitivities to different colors of light, the way they are connected or not connected to the arbiter 330, the way they are driven by the driver circuit 310, and / or the way they are accessed by external circuits. In an exemplary embodiment, the pixel array unit 300 may have a size in which the pixels 302 are arranged in 1280 columns and 720 rows. In other embodiments, other array sizes may also be used.

[0056] In operation, the sub-pixels of the pixel 302 can generate charge in response to received light. The drive circuit 320 can apply a drive signal (e.g., a voltage) to the pixel 302 and its sub-pixels to enable the pixel / sub-pixel to accumulate charge and then output a corresponding electrical signal to the column ADC circuit 340. The arbitrator 330 can be used in EVS mode, where the acronym EVS stands for "Event-Based Vision Sensor". More specifically, the arbitrator 330 is operable to arbitrate requests from different pixels 302 so that event-triggered readouts from different pixels 302 are performed in the order of occurrence of the corresponding events. The column ADC circuit 340 is operable to convert the received analog electrical signal into digital form and direct the resulting digital signal 318 to the signal processing unit 320. The signal processing unit 320 is operable to perform appropriate signal processing, such as correlated double sampling (CDS) processing, white balance adjustment, etc. The resulting processed signal 122 and the address of the event-triggered pixel can then be provided to the recording unit 130 (see also Figure 1 ).

[0057] Some embodiments disclosed herein may benefit from at least some of the EVS features disclosed, for example, in U.S. Patent No. 11,195,869, which is incorporated herein by reference in its entirety.

[0058] FIG. 4A to FIG. 4B is a schematic diagram and a cross-sectional diagram showing an example of an EVS and an imaging pixel. More specifically, Figure 4A A schematic plan view of a pixel unit 302 is shown. Figure 4B Shown corresponding to Figure 4A A cross-sectional side view of the assembly 200 along the vertical cross-sectional plane AA marked in FIG.

[0059] Reference Figure 4A, the pixel unit 302 includes sixteen sub-pixels arranged in a 4×4 two-dimensional matrix array (i.e., arranged in four rows and four columns). The sub-pixels include: (i) four EVS sub-pixels, labeled E; and (ii) twelve imaging sub-pixels, labeled R, G, B. For example, according to the conventional RGB color scheme, the differently labeled imaging sub-pixels have different color filters. In alternative embodiments, other color schemes known to those of ordinary skill in the art (e.g., CMY, etc.) may also be used. Sub-pixels may also be referred to as pixels, such as EVS pixels and imaging pixels.

[0060] The 16 sub-pixels E (EVS for short), R, G, and B of the pixel unit 302 are divided into four groups, each with four sub-pixels. Each group has exactly one of each of the E, R, G, and B sub-pixels arranged in a 2×2 array and is located in each of the four quadrants of the pixel unit 302. In the illustrated embodiment, each group has the same arrangement and orientation of the sub-pixels, for example, it can be regarded as having a corresponding copy of the same 2×2 ERGB sub-pixel array. In alternative embodiments, some groups may differ from each other, for example, in the relative order and / or position of the E, R, G, and B sub-pixels therein. In some alternative embodiments, the pixel unit 302 may include different numbers of sub-pixels and / or sub-pixel groups.

[0061] Reference Figure 4B , each sub-pixel of the pixel unit 302 may have a corresponding optional lens 402 adjacent to and arranged along the main surface of the light receiving chip 210. Figure 4B As shown, rear deep trench isolation (RDTI) is used at the sub-pixel boundaries to physically separate and laterally surround the photodiodes (PDs) of adjacent sub-pixels. Red, green, and blue color filters 404 may be located between the top surfaces of the corresponding PDs in the R, G, and B sub-pixels and the bottom surfaces of the corresponding lenses 402, respectively. In the cross-section shown, only the blue filter 404 is visible. The corresponding space 403 in the E sub-pixel may not have any color filters and may be filled with a suitable optically transparent, colorless filling material (e.g., silicon oxide).

[0062] On-chip transistor 410 of top chip 210 i (where i=1, 2, ..., 5, ...) are located in the device layer 406 of the chip, typically near the buried edge of its RDTI structure. The EVS pixel and the imaging (color) pixel each have a pixel circuit for signal generation and readout as further described below. For both the EVS pixel and the imaging pixel, at least some of the transistors in the pixel circuit can be formed in a shared manner in the same layer 406. In addition, these transistors can be formed below the RDTI boundary area, thus accommodating a larger active PD area.

[0063] The metal interconnect structure 408 of the optical receiving chip 210 is used to electrically connect the PD and the transistor 410. i And also used to route electrical connections between different circuit elements of the top chip 210 and the bottom chip 220 .

[0064] For purposes of illustration and without any implied limitation, metal interconnect structure 408 is Figure 4B 408 is shown as having five vertically offset metal layers labeled M1-M5. In alternative embodiments, a different (five) number of such vertically offset metal layers may be similarly used in the optical receiving chip 210. The spaces between the different electrical conductors of the metal levels M1-M5 are typically filled with an interlayer dielectric (ILD), for example, as known in the art. The ILD layers may have metal-filled vias therein to provide the desired electrical connections between selected conductors of the different metal levels of the metal interconnect structure 408. The M5 level of the metal interconnect structure 408 is illustratively shown as having a plurality of metal pads 412 that match a corresponding plurality of metal pads 414 of the bottom (e.g., logic) chip 220 to provide electrical connections between the chips.

[0065] Figure 5 A perspective three-dimensional cross-sectional view of a portion 500 of an interconnect structure 408 according to an embodiment is shown. Portion 500 includes conductors 502a and 502b of metal level Mn and conductors 506a and 506b of metal level M(n+1), where n can be 1, 2, 3, or 4. For a more clear description, Figure 5 The corresponding ILD layer is not explicitly shown.

[0066] As shown, conductors 504a, 504b and 506a, 506b are substantially planar horizontal metal traces. Typically, some such metal tracks of interconnect structure 408 may have L-shaped turns, for example, similar to the turns of conductor 506a. Some metal tracks, such as Mn-level conductor 502a and M(n+1)-level conductor 506b, may be directly electrically connected to each other using one or more metal-filled vertical vias, such as via 504. Such metal-filled vertical vias ( Figure 5 Some vias in the interconnect structure 408 (not explicitly shown) may span more than two metal levels of the interconnect structure 408 and be implemented as via stacks corresponding to the various levels of the structure.

[0067] Figure 6A-6B 2 is a circuit diagram showing an example of an EVS pixel circuit and an imaging pixel circuit. In one example, the circuit is implemented in the top (light receiving) chip 210. More specifically, Fig. 6ACircuit 602 is shown corresponding to the E sub-pixel of pixel unit cell 302. Circuit 602 may be referred to as an EVS pixel circuit and is configured to accommodate event detection using an EVS pixel. Figure 6B Circuitry 604 corresponding to a subset of the R, G, B sub-pixels of the pixel unit cell 302 is shown.

[0068] In an exemplary embodiment, pixel unit 302 may include one instance of circuit 602 and two instances of circuit 604. The different transistors of such circuits 602 and 604 may be implemented using device layer 406 of top (e.g., light receiving) chip 210. At least some electrical connections between various circuit elements of circuit 602 and between various circuit elements of circuit 604 may be implemented using interconnect structure 408 of light receiving chip 210 (see also FIG. Figure 4B and Figure 5 ).

[0069] refer to Fig. 6A , the photodiodes EPD1, EPD2, EPD3 and EPD4 of the circuit 602 are the photodiodes of the E sub-pixel of the pixel unit 302 (see also FIG. 4A to FIG. 4B ). The logarithmic transistors LGT1 and LGT2 and the amplifier transistors E_AMP1 and E_AMP2 of the circuit 602 are configured to form a logarithmic current-to-voltage conversion circuit for processing the photocurrent generated by the photodiodes EPD1-EPD4. The voltage generated by the current-to-voltage conversion circuit appears at the terminal VPR. The terminals VDD, VSS, and VRL are connected to receive a fixed power supply voltage. The voltage applied to the VRL terminal can be selected so that the photodiodes EPD1, EPD2, EPD3, and EPD4 are appropriately (e.g., negatively) biased to perform more efficient charge separation. It may also be included in Fig. 6A The transistor in the upper right corner of the circuit in (among others). It is a current control transistor that is configured to behave like a current source to help set the base current through E_AMP2 and E_AMP1.

[0070] refer to Figure 6B , the photodiodes PD1, PD2, PD3, PD4, PD5 and PD6 of circuit 604 are the photodiodes of the six R, G, B sub-pixels of pixel unit 302, which include two R sub-pixels, two G sub-pixels and two B sub-pixels. Amplifier transistor AMP, selection transistor SEL and reset transistor RST are shared by photodiodes PD1-PD6. Transfer transistors TG1-TG6 are connected between the individual photodiodes in photodiodes PD1-PD6 and the gate of transistor AMP. Terminal VSL is a signal readout terminal. Terminals VDD and VRL of circuit 604 can be connected to receive the same fixed power supply voltage as the corresponding marked terminals of circuit 602.

[0071] Figure 7 3 is a layout diagram showing an example of a pixel unit cell layout 302 including an EVS pixel and an imaging pixel. More specifically, Figure 7 Shown with Figure 4A The plan view shown in FIG. 1 corresponds to a plan view of the pixel unit 302 . Figure 7 The markings and FIG. 6A to FIG. 6B As described above, a single pixel unit 302 has a circuit 602 ( Fig. 6A ) and circuit 604 ( Figure 6B ) are two examples. Figure 6B and Figure 7 The symbol FD in FIG. 1 represents a floating diffusion region. Figure 7 The label EVS_SN in represents the nodes of the photodiodes EPD1-EPD4, which are used to electrically connect the photodiodes to the metal conductors of the interconnect structure 408. The label RDTI represents the RDTI structure of the pixel unit 302, which is used to physically separate the different photodiodes of the pixel from each other (see also Figure 4B ).

[0072] exist Figure 7 One pixel unit cell is shown in the layout 302 of FIG. The pixel unit includes two pairs of imaging pixel groups corresponding to the photodiodes PD1-6 (12 in total). There are also four EVS pixels EPD1-4 included in the pixel unit.

[0073] RST, AMP, and SEL are imaging pixel circuit transistors shared by the imaging PDs in the pixel cell (2×3 shared in this example). LGT1, LGT2, E_AMP1, and E_AMP2 are EVS pixel circuit transistors that form a logarithmic circuit for the output, and are shared by all EVS PDs (4 in this example of the pixel cell). The EVS PDs are dispersedly localized, and the EVS transistors are arranged along the middle (LGT1, E_AMP1 / E_AMP2) and bottom (LGT2) boundaries. As shown in Figure 7 As shown in the plan view of FIG, the transistors are in a shared layer (dashed line) below PD and RDTI. Figure 4B In the cross-sectional view shown, the transistor is close to and arranged below the relevant portion of the RDTI. The P-well of the PD can be formed as a shallowly doped region and can be negatively biased to VRL. Based on the device operation requirements, this value can be as low as -1.2V. The layout 302 of this example provides relatively high EVS sensitivity and a large PD area. However, due to the dispersed location of the EVS PD, there may be a relatively large EVS metal line collision area.

[0074] has the corresponding Figure 7The fabrication of the top chip 210 of the pixel unit cell of the layout 302 may generally be accomplished using two different processing stages, which are generally referred to as front-end of line (FEOL) processing and back-end of line (BEOL) processing.

[0075] During FEOL processing, the device layers of the corresponding wafer may be used (see, for example, Fig. 6A The FEOL process typically includes fabrication steps for forming photodiodes and / or isolated electrical CMOS elements. Such fabrication steps may include, but are not limited to: (a) chemical mechanical planarization (CMP) and cleaning of the wafer; (b) patterning the device layers; (c) trench isolation, e.g., RSTI; (d) well formation; (e) gate formation; (f) source and drain module formation, etc.

[0076] During BEOL processing, the various circuit devices formed during FEOL processing may be interconnected by forming appropriate metal interconnect structures (e.g., Figure 4B 408). For example, contact pads, interconnect wires, vias, and different ILD layers may be formed. Example BEOL fabrication steps may include, but are not limited to: (g) silicidation of source, drain, and polysilicon regions; (h) forming and patterning various dielectric layers, some of which may serve as optical cladding; (i) forming and patterning various metal layers, for example, to produce metal levels M1-M5, Figure 4B ; (j) making vias, e.g. Figure 5 504; (k) forming a passivation layer, etc.

[0077] After BEOL processing, the wafer may undergo post-manufacturing processing. Such processing may include, but is not limited to, wafer testing, wafer back grinding, dicing, bare die testing, and chip packaging. In contrast to FEOL and BEOL processing, at least some of the steps of post-manufacturing processing may be performed outside a clean room environment.

[0078] Circuits 602 and 604 may generally be operated using different operating modes of the imaging device 120. For example, as already mentioned above, circuit 602 may be used in an EVS operating mode, wherein the E subpixels of different pixels 302 may be continuously in an on state, and the arbiter 330 may arbitrate event-triggered requests from different pixels 302 to read out signals from their E subpixels. In contrast, circuit 604 may be used for image frame capture, wherein the R, G, and B subpixels of different pixels 302 may be operated under the control of the frame capture circuit of the imaging device 120. Thus, in some cases, circuits 602 and 604 of the same pixel unit 302 may be activated simultaneously. In such a case, the signals generated in circuits 602 and 604 may interfere and interact with each other, for example, through the phenomenon of electromagnetic crosstalk, which may cause the quality of the images generated in both the EVS and image frame capture modes to be adversely affected.

[0079] For example, significant reduction in inter-mode interference in the imaging device 120 can be achieved by using the metal interconnect structure 408 of the optical receiving chip 210, which is specifically designed to reduce the above-mentioned crosstalk by optimizing (e.g., minimizing) the spatial overlap between the metal wiring corresponding to the circuits 602 and 604 within the pixel unit 302.

[0080] Figure 8 8 is a layout diagram showing another example of a pixel unit cell layout 800 including an EVS pixel and an imaging pixel. The pixel unit cell layout 800 also uses EVS and imaging pixel circuits (e.g., Fig. 6A -B, 602, 604), which is preferably again located on the top chip (e.g., Figure 2 , 210). In this example, transistors RST, E_AMP1, E_AMP2, and LGT1 are arranged along the bottom boundary region (ie, in the case of Figure 4B Similarly, transistors SEL, AMP, and LGT2 are positioned along the intermediate boundary region (similarly, below the relevant portion of the RDTI boundary in the cross section). This arrangement preserves a relatively large PD area by positioning these transistors below the RDTI.

[0081] Fig. 9 is a layout diagram showing another example of a pixel unit cell layout 900 including an EVS pixel and an imaging pixel. The pixel unit cell layout 900 also uses EVS and imaging pixel circuits (e.g., Fig. 6A -B, 602, 604), which is preferably again located on the top chip (e.g., Figure 2, 210). Here, the EVS transistors LGT1, LGT2, E_AMP1, and E_AMP2 are arranged along the middle vertical boundary region. The SEL and AMP transistors are arranged along the middle horizontal boundary region, and the RST transistor is arranged along the bottom horizontal boundary region. The RST_Dummy transistor can also be arranged along the bottom boundary region. This configuration simplifies the BEOL metal wiring process. However, the PD area can be slightly smaller than Figures 7 and 8 PD area.

[0082] Fig.10 1 is a layout diagram showing another example of a pixel unit cell layout 1000 including an EVS pixel and an imaging pixel. The pixel unit layout 1000 is similar to Fig. 9 , but the EVS transistors LGT1, LGT2, E_AMP1 and E_AMP2 are arranged along the middle vertical boundary area.

[0083] Fig.11 1 is a layout diagram showing another example of a pixel unit cell layout 1100 including an EVS pixel and an imaging pixel. The pixel unit cell layout 1100 is similar to Figures 8 to 9 The pixel unit cell layout of FIG. 1 is similar to that of FIG. 1 , but with EVS transistors dispersedly arranged along the middle and left vertical boundary regions. Specifically, transistors LGT1 and E_AMP2 are arranged along the left vertical boundary region, and transistors LGT2 and E_AMP1 are arranged along the middle vertical boundary region. This provides a more uniform EVS pixel transistor distribution.

[0084] Fig.12 is a layout diagram showing another example of a pixel unit cell layout 1200 including an EVS pixel and an imaging pixel. In this example, EVS PDs EPD1-4 are arranged together in the middle portion of the pixel unit layout 1200. That is, each EVS PD is arranged adjacent to both the horizontal boundary region and the vertical boundary region. In addition, the EVS pixel transistor is arranged adjacent to the EVS PD. Specifically, the EVS transistors LGT1 and E_AMP1 are arranged along the vertical middle boundary region, and the EVS transistors E_AMP2 and LGT2 are arranged along the horizontal middle boundary region. For the imaging pixel, the RST transistor is arranged outside the horizontal middle boundary region, and the SEL and AMP transistors are arranged along the bottom boundary region. This arrangement further simplifies the EVS BEOL wiring and results in a relatively small EVS wiring impact area.

[0085] Fig.131 is a circuit diagram showing another example of the EVS pixel circuit 1300. Here, the number of EVS pixels / PDs in the unit cell is reduced to two (EPD1, EPD2). The remaining circuits LGT1, LGT2, E_AMP1, E_AMP2 are combined as above. Fig. 6A Elucidate and describe.

[0086] Fig.14 It shows that according to Fig.13 1400. Because there are two fewer EVS pixels in the unit cell, there are two or more imaging pixels / PD in the unit cell (PD7, PD8). Like other imaging pixels, these imaging pixels have corresponding transfer transistors TG7 and TG8. The remaining circuits AMP, SEL, RST, PD1-6, TG1-6 are as described above in combination Figure 6B Elucidate and describe.

[0087] Fig.15 1 is a layout diagram showing another example of a pixel unit cell layout 1500 including an EVS pixel and an imaging pixel. Fig.13 and Fig.14 The EVS pixel circuit is consistent with the imaging pixel circuit. Obviously, the pixel unit layout 1500 includes two EVS pixels corresponding to EPD1 and EPD2. Fig.15 In the plan view, the transistor layer includes RST, E_AMP1, E_AMP2, and LGT1 transistors arranged along the middle RDTI boundary region and SEL, AMP, LGT2 arranged along the bottom boundary region. This example maintains a relatively large PD area and increases the ratio of imaging to EVS pixels, resulting in better image quality, but potentially lower event sensitivity.

[0088] Fig.16 1 is a layout diagram showing another example of a pixel unit cell layout 1600 including an EVS pixel and an imaging pixel. The layout 1600 is also Fig.13 and Fig.14 Here, the EVS pixel and the corresponding circuit are located in the middle part of the pixel unit. In the transistor layer, the EVS pixel transistors E_AMP2 and LGT2 are arranged along the center part of the middle horizontal boundary area, and the transistors E_AMP1 and LGT1 are arranged along the center part of the middle vertical boundary area. The imaging pixel transistor RST is arranged outside the middle horizontal boundary area, and the transistors SEL and AMP are arranged along the lower (horizontal) boundary area. The proximity of the EVS pixel and the corresponding circuit results in a reduction in the EVS wiring impact area.

[0089] Figures 17 to 19This corresponds to an example in which the number of PDs in the pixel unit is increased to 8 EVS pixels and 24 imaging pixels. Fig.17 1 is a circuit diagram showing an EVS pixel circuit 1700 including EPD1-8. The remaining circuits are as follows Fig. 6A described. Fig.18 1 is a circuit diagram showing an imaging pixel circuit 1800 including PD1-12 and corresponding TG1-12. Again, there are two examples of imaging pixel circuit 1800 for a pixel unit, and the remaining circuits are as follows Figure 6B As described in. Fig.19 The pixel unit cell layout 1900 has EVS pixels (EDP1-8) concentrated in the upper right and lower left positions of the pixel unit cell. The transistor layer includes EVS pixel circuits and imaging pixel circuits dispersed along three horizontal boundary regions. Specifically, SEL, AMP, E_AMP1, and E_AMP2 transistors are arranged along the first horizontal boundary region, RST, RST_Dummy, SEL, and other AMP transistors are arranged along the second horizontal boundary region, and LGT1, LGT2, other RST, and other RST_Dummy transistors are arranged along the third horizontal boundary region.

[0090] Figure 20 to Figure 21 Another example of an EVS pixel circuit 2000 and a corresponding pixel cell layout 2100 is shown. This example implements a simplified EVS pixel circuit 2000, omitting one logarithmic transistor and one amplifier transistor to include only the logarithmic transistor LGT and the amplifier transistor E_AMP. Imaging pixel circuit for 12 imaging pixels and Figure 6B In the pixel unit cell layout 2000, the transistor layer includes transistors SEL, AMP, E_AMP along the middle horizontal boundary region and transistors RST, RST_Dummy and LGT along the bottom horizontal boundary region. This arrangement simplifies the wiring of the EVS pixel circuit.

[0091] Figure 22 to Figure 23 Another example of an EVS pixel circuit and a corresponding pixel cell layout 2300 is shown. In the EVS pixel circuit, the EVS PD EPD1-4 is kept on the top chip ( Figure 2 , 210), but the corresponding EVS pixel circuit is moved to the bottom chip ( Figure 2 , 220). As shown in pixel cell layout 2300, this only requires the imaging pixel circuit transistors SEL, AMP, RST, and RST_Dummy to be located in the transistor layer in the top chip. This allows four EVS pixels to be retained in the pixel cell while still reducing the wiring complexity in the transistor layer of the top chip.

[0092] Figure 24 to Figure 25Another example of an imaging pixel circuit and corresponding pixel cell layout 2500 is shown. In the imaging pixel circuit, PD PD1-6 (time 2) remains on the top chip ( Figure 2 , 210), but the corresponding imaging pixel circuit is different from the EVS pixel circuit ( Figure 2 , 220) are moved to the bottom chip together. As shown in pixel cell layout 2500, this further simplifies the wiring of the transistor layer of the top chip and further reduces the potential impact of capacitive interactions between various wirings.

[0093] Fig.26 26 is a layout diagram showing another example of a pixel unit cell layout 2600 including an EVS pixel and an imaging pixel. Here, a dummy transmission gate E_TG is added for each EVS pixel. This produces a more uniform structure with higher EVS sensitivity while maintaining a relatively large PD area and controllable isolation of the EVS PD by the dummy TG.

[0094] FIG. 27A to FIG. 27C is shown in plan view as Figure 4A Schematic diagram of other examples of pixel unit cells 2702a to 2702c of alternative examples. Each pixel unit in pixel units 2702a-2702c includes sixteen sub-pixels arranged in a 4×4 two-dimensional matrix array (i.e., arranged in four rows and four columns), and pixel units 2702a-2702c again include four EVS sub-pixels and twelve imaging sub-pixels, individually labeled as R, G, and B. Again, within the unit cell, the sub-pixels may also be referred to as pixels, for example, EVS pixels and imaging pixels. Figure 4A and FIG. 27A to FIG. 27C The pattern in may be implemented in some or all pixel unit embodiments disclosed herein.

[0095] FIG. 28A to FIG. 28C 28 are diagrams of examples of pixel cell layouts 2800a - c that also include on-chip lens arrangements. Fig.28A An on-chip lens (OCL) 2802 is shown in a 1x1 configuration (ie, one OCL per pixel). This configuration is applicable to any instance of the pixel unit cell and for optimal performance of each pixel. Fig.28B and Fig.28C An OCL 2804 is shown in a 2x1 configuration and an OCL 2806 is shown in a 4x1 configuration. These examples also apply to any examples of pixel cells. They also apply to implementations using phase detection autofocus (PDAF).

[0096] Fig.29Another example of a pixel unit cell layout 2900 including EVS pixels and imaging pixels is shown. Here, these imaging pixels are rectangular in shape and have an area half the size of the previous example. The corresponding EVS pixel circuit and imaging pixel circuit are Fig. 6A and Fig.18 The transistor layer similarly includes both imaging pixel and EVS pixel transistors arranged along the boundary region. This pixel unit cell layout 2900 is also suitable for PDAF implementation.

[0097] FIG. 30A to FIG. 30B is a cross-sectional view illustrating an example of an RDTI structure for forming an RDTI boundary region. Fig. 30A The RDTI includes a (eg, epitaxial) silicon layer 3006 that extends along the PD region to form a PD separation boundary (eg, Figure 4B ). The inner polysilicon layer 3004 extends in the same direction and is separated from the epitaxial silicon layer 3006 by a dielectric layer 3002 (eg, oxide, nitride). Fig. 30B The RDTI also includes a silicon layer 3016 extending next to the PD region, an inner metal layer 3012 (eg, tungsten) extending in the same direction, and a passivation layer 3011 and a dielectric 3010 layer in between.

[0098] Figure 31 to Figure 32 3 is a timing diagram showing simultaneous EVS and imaging pixel readout processes 3100, 3200. The EVS pixel circuit (e.g., Fig. 6A ) is arranged to omit switch control so that event detection remains active throughout the entire time period. Imaging pixel circuits (e.g., Figure 6B ) are set so that the transmission gates are opened sequentially as part of the readout mode.

[0099] Fig.33 Schematic diagram showing implementation examples of imaging devices 12101, 12102, 12103, 12104, and 12105 located at locations such as the front nose, side mirrors, rear bumper, rear door, and upper side of the windshield of a vehicle 12100. Each of these imaging devices may implement one or more of the examples of image sensing, which includes a pixel array having an EVS and imaging pixels as previously described. A range 12111, 12112, 12113, and 1214 of imaging devices 12101 to 12104 facing outward are also shown. At least one of the imaging devices 12101 to 12105 may have a function of acquiring distance information. In addition, the imaging devices 12101 to 12105 include EVS pixels for performing event sensing. The corresponding computer system can coordinate with the imaging devices 12101 to 12105 to perform three-dimensional object detection, distance control, brake control, acceleration control, etc.

[0100] The examples described in this specification are merely examples and do not limit the disclosure herein, and other effects may be achieved.

[0101] For example, the present technology may have the following configurations.

[0102] (1) An image sensing device comprising:

[0103] A pixel array, the pixel array includes imaging pixels and event sensing pixels, the pixel array is a two-dimensional array, and the imaging pixels and the event sensing pixels are staggered in the pixel array;

[0104] imaging pixel circuitry configured to provide an image signal from the imaging pixel; and

[0105] The event sensing pixel circuit is configured to provide an event signal from the event sensing pixel.

[0106] (2) The image sensing device according to (1), further comprising:

[0107] Trench isolation surrounding each imaging pixel and event sensing pixel in the pixel array.

[0108] (3) The image sensing device according to (2), wherein, in a cross-sectional view, the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are each arranged under the trench isolation.

[0109] (4) The image sensing device according to (2), wherein the two-dimensional array extends in a horizontal direction and a vertical direction, and the trench isolation forms a first boundary region extending in the horizontal direction and a second boundary region extending in the vertical direction.

[0110] (5) The image sensing device according to (4), wherein, in a cross-sectional view, the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are each arranged below the first boundary region.

[0111] (6) An image sensing device according to (4), wherein, in a cross-sectional view, a first transistor in the imaging pixel circuit is arranged below a first boundary region, and, in a cross-sectional view, a second transistor in the event sensing pixel circuit is arranged below a second boundary region.

[0112] (7) An image sensing device according to (1), wherein the pixel array is formed on a first integrated circuit, and wherein the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are each arranged in the same transistor layer of the first integrated circuit.

[0113] (8) The image sensing device according to (1), wherein the image sensing device includes a stacked assembly, the stacked assembly includes a first portion, the first portion is bonded to a second portion, the first portion includes a first integrated circuit and the second portion includes a second integrated circuit.

[0114] (9) The image sensing device according to (8), wherein the third transistor in the event sensing pixel circuit is arranged in the second integrated circuit.

[0115] (10) The image sensing device according to (9), wherein the fourth transistor in the image sensing pixel circuit is arranged in the second integrated circuit.

[0116] (11) The image sensing device according to (1), wherein the event sensing pixels each include a photodiode, and the photodiode is connected in parallel with the event sensing pixel circuit to provide the event signal.

[0117] (12) The image sensing device according to (11), wherein the image sensing pixels each include a photodiode, and respective different color filters are provided for individual ones of the image sensing pixels.

[0118] (13) The image sensing device according to (12), wherein the imaging pixel circuit includes a transfer transistor, each of which is arranged for each photodiode of each image sensing pixel.

[0119] (14) The image sensing device according to (13), wherein the event signal of the event sensing pixel is connected for readout without switch gate control.

[0120] (15) The image sensing device according to (14), wherein image signals are sequentially read out from the respective imaging pixels using transfer transistors simultaneously with event signal readout.

[0121] Although the present disclosure includes references to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications to the described embodiments, as well as other embodiments obvious to those of ordinary skill in the art within the scope of the present disclosure, are considered to fall within the scope of the present disclosure, for example, as expressed in the following claims.

[0122] Some embodiments may be implemented as a circuit-based process, including possible implementation on a single integrated circuit.

[0123] Unless expressly stated otherwise, each numerical value and range should be interpreted as approximate as if the word "about" or "approximately" preceded the value or range.

[0124] It will be further understood that various changes in the details, materials and arrangements of components that have been described and illustrated to explain the nature and principles of the present disclosure may be made by those skilled in the relevant art without departing from the scope of the present disclosure, for example, as expressed in the following claims.

[0125] The use of figure numbers and / or figure reference signs (if any) in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use should not be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding drawings.

[0126] Even though elements in the following method claims, if any, are recited in a specific sequence with corresponding labels, those elements are not necessarily intended to be limited to being implemented in that specific sequence unless the claim recitation otherwise implies a specific sequence for implementing some or all of those elements.

[0127] References herein to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present disclosure. The appearances of the phrase "in one embodiment" in different places in this specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term "implementation."

[0128] Unless otherwise specified herein, the use of ordinal adjectives "first," "second," "third," etc. to refer to an object among a plurality of similar objects merely indicates that different examples of such similar objects are referred to, and is not intended to imply that the similar objects so referred to must be in a corresponding order or sequence in time, space, order, or in any other manner.

[0129] Unless otherwise specified herein, in addition to its plain meaning, the conjunction "if" may also or alternatively be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting", the construction of which may depend on the respective specific context. For example, the phrase "if it is determined" or "if [stated condition] is detected" may be interpreted to mean "upon determination" or "in response to determination" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]".

[0130] Throughout the detailed description, the drawings, which are not drawn to scale, are illustrative only and are used to explain rather than limit the present disclosure. The use of terms such as height, length, width, top, bottom is strictly for the convenience of describing the embodiments and is not intended to limit the embodiments to a particular direction. For example, height does not merely imply a vertical rise limit, but is used to identify one of the three dimensions of a three-dimensional structure as shown in the figure. Such a "height" would be vertical if the electrodes were horizontal, but would be horizontal if the electrodes were vertical, and so on. Similarly, although some of the drawings show different layers as horizontal layers, such orientation is only for descriptive purposes and should not be construed as limiting.

[0131] Also for the purposes of this specification, the terms "coupled," "coupled," "coupled," "connected," "connected," or "connected" refer to any means known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the insertion of one or more additional elements is contemplated, although not required. In contrast, the terms "directly coupled," "directly connected," and the like mean that there are no such additional elements. The same type of distinction applies to the use of the terms "attached" and "directly attached" as applied to the description of physical structures. For example, such "direct attachment" of two corresponding components in such a physical structure can be achieved using a relatively thin layer of an adhesive or other suitable adhesive.

[0132] The described embodiments are to be considered in all respects as illustrative only and not restrictive. Specifically, the scope of the present disclosure is indicated by the appended claims rather than by the description and drawings herein. All changes that fall within the meaning and range of equivalents of the claims are included within their scope.

[0133] The description and drawings illustrate only the principles of the present disclosure. Therefore, it should be understood that a person of ordinary skill in the art will be able to design various arrangements that, although not explicitly described or shown herein, embody the principles of the present disclosure and are included within the scope thereof. In addition, all examples cited herein are primarily and explicitly intended to be used only for educational purposes to help the reader understand the principles of the present disclosure and the concepts contributed by the inventors to promote the art, and are to be interpreted as not being limited to these specifically cited examples and conditions. In addition, all statements describing the principles, aspects, and embodiments of the present disclosure and specific examples thereof are intended to cover their equivalents.

[0134] The functions of the various elements shown in the drawings (including any functional blocks marked as "processors" and / or "controllers") can be provided by using dedicated hardware and hardware capable of executing software in association with appropriate software. When provided by a processor, the function can be provided by a single dedicated processor, by a single shared processor, or by multiple separate processors, some of which can be shared. In addition, the explicit use of the term "processor" or "controller" should not be interpreted as referring exclusively to hardware capable of executing software, and may implicitly include, but is not limited to, digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read-only memories (ROMs), random access memories (RAMs), and non-volatile memories for storing software. Conventional and / or customized other hardware may also be included. Similarly, any switches shown in the drawings are only conceptual. Their functions can be performed by the operation of program logic, by dedicated logic, by the interaction of program control and dedicated logic, or even manually, as more specifically understood from the context, and specific techniques may be selected by the implementer.

[0135] As used in this application, the term "circuitry" may refer to one or more or all of the following: (a) a hardware-only circuit implementation (e.g., an implementation solely in analog and / or digital circuits); (b) a combination of hardware circuitry and software, such as (as applicable): (i) a combination of analog and / or digital hardware circuitry and software / firmware and (ii) a hardware processor and software (including a digital signal processor), software, and any portion of memory that work together to enable a device such as a mobile phone or server to perform different functions; and (c) a hardware circuit and / or processor, such as a microprocessor or a portion of a microprocessor, that requires software (e.g., firmware) for operation, but the software may not be present when not required for operation. This definition of "circuitry" applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or a processor (or multiple processors) or a portion of a hardware circuit or a processor and its (or its) accompanying software and / or firmware. For example, and if applicable to the particular claim element, the term circuitry also covers a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in a server, cellular network device, or other computing or network device.

[0136] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.

Claims

1. An image sensing device, comprising: A pixel array, the pixel array comprising imaging pixels and event sensing pixels, the pixel array being a two-dimensional array, the imaging pixels and the event sensing pixels being staggered in the pixel array; imaging pixel circuitry configured to provide an image signal from the imaging pixel; as well as The event sensing pixel circuit is configured to provide an event signal from the event sensing pixel.

2. The image sensing device according to claim 1, further comprising: A trench isolation is formed around each of the imaging pixels and the event sensing pixels in the pixel array.

3. The image sensing device according to claim 2, wherein: In a cross-sectional view, a first transistor in the imaging pixel circuit and a second transistor in the event sensing pixel circuit are each arranged under the trench isolation.

4. The image sensing device according to claim 2, wherein: The two-dimensional array extends in a horizontal direction and a vertical direction, and the trench isolation forms a first boundary region extending in the horizontal direction and a second boundary region extending in the vertical direction.

5. The image sensing device according to claim 4, wherein: In a cross-sectional view, the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are each arranged below a first boundary region.

6. The image sensing device according to claim 4, wherein: In a cross-sectional view, a first transistor in the imaging pixel circuit is arranged below a first boundary region, and, in the cross-sectional view, a second transistor in the event sensing pixel circuit is arranged below a second boundary region.

7. The image sensing device according to claim 1, wherein: The pixel array is formed on a first integrated circuit, and wherein the first transistor in the imaging pixel circuit and the second transistor in the event sensing pixel circuit are each arranged in a same transistor layer of the first integrated circuit.

8. The image sensing device according to claim 1, wherein: The image sensing device includes a stacked assembly including a first portion joined to a second portion, the first portion including a first integrated circuit and the second portion including a second integrated circuit.

9. The image sensing device according to claim 8, wherein: The third transistor in the event sensing pixel circuit is arranged in the second integrated circuit.

10. The image sensing device according to claim 9, wherein: The fourth transistor in the image sensing pixel circuit is arranged in the second integrated circuit.

11. The image sensing device according to claim 1, wherein: The event sensing pixels each include a photodiode, and the photodiode is connected in parallel with the event sensing pixel circuit to provide the event signal.

12. The image sensing device according to claim 11, wherein: The image sensing pixels each include a photodiode, and respective different color filters are provided for individual ones of the image sensing pixels.

13. The image sensing device according to claim 12, wherein: The imaging pixel circuit includes a transfer transistor, each of which is arranged for each of the photodiodes of each of the image sensing pixels.

14. The image sensing device according to claim 13, wherein: The event signal of the event sensing pixel is connected for readout without switch gate control.

15. The image sensing device according to claim 14, wherein: Concurrently with the event signal readout, the image signal is sequentially read out from each of the imaging pixels using the transfer transistor.

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