Multi-layer memory devices having different width central stair regions in

Abstract

A memory device includes alternating stacks of insulating layers and conductive layers laterally spaced apart from each other along a second horizontal direction, extending laterally along a first horizontal direction through an inter-array region, a first memory array region, and a second memory array region, the second memory array region is laterally spaced apart from the first memory array region in the first horizontal direction by the inter-array region. Each conductive layer within the alternating stack has a respective bridging region within the inter-array region having a respective strip width along the second horizontal direction, and the strip width of the topmost conductive layer in the first layer alternating stack is less than the strip width of the topmost conductive layer in the second layer alternating stack overlying the first layer alternating stack.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 347,858, filed on July 6, 2023 in the U.S. Patent and Trademark Office and entitled “MULTI-TIER MEMORY DEVICEWITH DIFFERENT WIDTH CENTRAL STAIRCASE REGIONS IN DIFFERENT VERTICAL TIERSAND METHODS FOR FORMING THE SAME,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 378,534, filed on October 6, 2022. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and more particularly to a multi-layer memory device including central staircase regions of different widths in different vertical layers and a method of forming the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one embodiment of the present disclosure, a multi-layer memory device includes: a substrate; and a plurality of layer structures located at the multi-layer level, which are spaced apart from the substrate at different vertical spacings in the vertical direction. Each of the plurality of layer structures includes: a backside trench filling structure, which extends laterally through each of the plurality of layer structures along a first horizontal direction and is laterally spaced apart from each other along a second horizontal direction; alternating stacks of insulating layers and conductive layers, which are laterally spaced apart from each other along the second horizontal direction by the backside trench filling structure, and extend laterally through the inter-array region, the first memory array region, and the second memory array region along the first horizontal direction by the inter-array region; and a memory opening filling structure, which extends vertically through each of the plurality of layer structures, wherein each of the memory opening filling structures includes a vertical stack of memory elements located at the level of the conductive layer and a corresponding vertical semiconductor channel. Each alternating stack in the alternating stacks includes a stepped surface in the inter-array region; each conductive layer within the alternating stack has a corresponding bridging area having a corresponding stripe width along a second horizontal direction in the inter-array region, and has a corresponding uniform width along the second horizontal direction that is greater than the stripe width in the first memory array region, the second memory array region, and a portion of the inter-array region located outside the bridging area; and the stripe width of the topmost conductive layer in the first layer of alternating stacks is less than the stripe width of the topmost conductive layer in the second layer of alternating stacks covering the first layer of alternating stacks.

[0006] According to another aspect of the present disclosure, a method for forming a semiconductor device includes: forming a plurality of layer structures at a multi-layer level, the multi-layer levels being spaced apart from a substrate at different vertical spacings in a vertical direction. Each of the plurality of layer structures includes: alternating stacks of insulating layers and sacrificial material layers, the alternating stacks extending laterally along a first horizontal direction through an inter-array region, a first memory array region, and a second memory array region, the second memory array region being laterally spaced apart from the first memory array region along the first horizontal direction by the inter-array region; and memory opening filling structures extending vertically through each of the plurality of layer structures, wherein each of the memory opening filling structures includes a vertical stack of memory elements at a level of a corresponding vertical semiconductor channel and a sacrificial material layer. The method also includes: forming a back side trench through the alternating stack of insulating layers and sacrificial material layers; replacing the sacrificial material layer with a conductive layer passing through the back side trench to convert the alternating stack of insulating layers and sacrificial material layers into an alternating stack of insulating layers and conductive layers; and filling the back side trench with a back side trench filling structure, which extends laterally along a first horizontal direction through each of the multiple layer structures and is laterally spaced apart from each other along a second horizontal direction. The conductive layers are laterally spaced apart from each other along a second horizontal direction by a backside trench fill structure; each alternating stack of insulating layers and conductive layers includes a stepped surface in the inter-array region; each conductive layer within the alternating stack of insulating layers and conductive layers has a corresponding bridging region having a corresponding stripe width along the second horizontal direction in the inter-array region, and has a corresponding uniform width along the second horizontal direction that is greater than the stripe width in the first memory array region, the second memory array region, and a portion of the inter-array region located outside the bridging region; and the stripe width of the topmost conductive layer in the first alternating stack of insulating layers and conductive layers is less than the stripe width of the topmost conductive layer in the second alternating stack of insulating layers and conductive layers overlying the first alternating stack of insulating layers and conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a plan view of an exemplary semiconductor die configuration including multiple three-dimensional memory array regions according to one embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A Schematic perspective top view of the region M1 of FIG.

[0009] Figure 1C is along Figure 1B Schematic vertical cross-sectional view of a region of an exemplary semiconductor die along a vertical plane CC'.

[0010] Figure 1D is along Figure 1B Schematic vertical cross-sectional view of a region of an exemplary semiconductor die along a vertical plane DD′.

[0011] Figure 1E is along Figure 1B Schematic vertical cross-sectional view of a region of an exemplary semiconductor die along a vertical plane EE′.

[0012] Figure 2A is a schematic vertical cross-sectional view of an exemplary structure for forming a semiconductor die after forming an optional semiconductor device, an optional lower level dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, and a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer, and a first layer of backward stepped dielectric material portion according to an embodiment of the present disclosure.

[0013] Figure 2B is along Figure 2A Schematic vertical cross-sectional view of an exemplary structure along a vertical plane BB'.

[0014] Figure 2C yes Figure 2A and Figure 2B Another schematic vertical cross-sectional view of an exemplary structure of .

[0015] Figure 3A is a schematic vertical cross-sectional view of an exemplary structure after forming a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer and a second layer of rear stepped dielectric material portion according to one embodiment of the present disclosure.

[0016] Figure 3B is along Figure 3A Schematic vertical cross-sectional view of an exemplary structure along a vertical plane BB'.

[0017] Figure 3C yes Figure 3A and Figure 3B Another schematic vertical cross-sectional view of an exemplary structure of .

[0018] Figure 4A is a schematic vertical cross-sectional view of an exemplary structure after forming a third vertical alternating sequence of a third continuous insulating layer and a third continuous sacrificial material layer and a third layer of rear stepped dielectric material portion according to one embodiment of the present disclosure.

[0019] Figure 4B is along Figure 4A Schematic vertical cross-sectional view of an exemplary structure along a vertical plane BB'.

[0020] FIG. 5A to FIG. 5Eare vertical cross-sectional views of various configurations of an exemplary structure after forming a third layer structure according to an embodiment of the present disclosure.

[0021] FIG. 6A to FIG. 6C are sequential vertical cross-sectional views of an exemplary structure during formation of an inter-layer memory opening according to one embodiment of the present disclosure.

[0022] 7A to 7E Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to an embodiment of the present disclosure are illustrated.

[0023] Fig. 8A and Figure 8B is a schematic vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and backside trenches according to one embodiment of the present disclosure. Fig. 8A is along Fig. 8A Schematic vertical cross-sectional view of an exemplary structure along a vertical plane BB'.

[0024] Fig. 9 is a schematic vertical cross-sectional view of an exemplary structure after forming a backside recess according to one embodiment of the present disclosure.

[0025] Fig. 10A is a schematic vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0026] Fig. 10B yes Fig. 10A Another schematic vertical cross-sectional view of an exemplary structure of .

[0027] FIG. 11A to FIG. 11D yes Fig. 10A and Fig. 10B Schematic vertical cross-sectional views of various configurations of exemplary structures.

[0028] Fig.11E is a schematic vertical cross-sectional view of another exemplary structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] As discussed above, embodiments of the present disclosure relate to multi-layer memory devices and methods of forming the same in different width central staircase regions in different vertical layers, various aspects of which are now described in detail.

[0030] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is illustrated, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0031] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0032] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a first continuous structure. For example, a layer may be located between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0033] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0034] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the array of memory elements and a second horizontal plane including the bottommost surface of the array of memory elements. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0035] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material (i.e., providing a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0036] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for memory devices.

[0037] Various three-dimensional memory devices disclosed herein include single three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. Single three-dimensional NAND strings are positioned in a single three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0038] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded through, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0039] refer to Figures 1A to 1E, illustrates an exemplary semiconductor die 1000 according to an embodiment of the present disclosure. The exemplary semiconductor die 1000 includes a plurality of three-dimensional memory array regions and a plurality of inter-array regions. The exemplary semiconductor die 1000 may include a plurality of planes 300 (e.g., 300A, 300B), each plane including two memory array regions 100 laterally spaced apart by a corresponding inter-array region 200, such as a first memory array region 100A and a second memory array region 100B. In general, the semiconductor die 1000 may include a single plane 300 or a plurality of planes. The total number of planes in the semiconductor die 1000 may be selected based on the performance requirements for the semiconductor die 1000. A pair of memory array regions 100 within the plane 300 may be laterally spaced apart along a first horizontal direction hd1 (which may be a word line direction). The second horizontal direction hd2 (which may be a bit line direction) may be perpendicular to the first horizontal direction hd1.

[0040] According to one aspect of the present disclosure, within a given plane, the size of the first memory array region 100A may be different from the size of the second memory array region 100B. Specifically, the lateral extent of each of the first memory array region 100A and the second memory array region 100B may be the same along the second horizontal direction hd2 within the plane. However, the lateral extent of the first memory array region 100A within the plane 300 along the first horizontal direction hd1 may be greater than the lateral extent of the second memory array region 100B within the same plane 300. In one embodiment, each of the first memory array region 100A and the second memory array region 100B may have a corresponding rectangular area having the same width along the second horizontal direction hd2, and the lateral extent of the first memory array region 100A along the first horizontal direction hd1 may be greater than the lateral extent of the second memory array region 100B along the first horizontal direction hd1. Thus, the stepped regions 200 within each plane 300 may be positioned off-center from the corresponding plane 300 along the first horizontal direction hd1 (i.e., the stepped regions 200 are positioned closer to one end of the corresponding plane 300 than to the other end). For example, the stepped regions 200 in the left plane 300A may be shifted toward the left edge of the die 1000, while the stepped regions 200 in the right plane 300B may be shifted toward the right edge of the die 1000.

[0041] Each memory array region 100 includes a first layer alternating stack of a first insulating layer 132 and a first conductive layer 146 (which serves as a first word line), a second layer alternating stack of a second insulating layer 232 and a second conductive layer 246 (which serves as a second word line), and an optional third layer alternating stack of a third insulating layer 332 and a third conductive layer 346 (which serves as a third word line). Each second layer alternating stack (232, 246) overlies a corresponding first layer alternating stack (132, 146), and each third layer alternating stack (332, 346) (if present) overlies a corresponding second layer alternating stack (232, 246). Each combination of a first layer alternating stack (132, 146), an overlying second layer alternating stack (232, 246), and an optional overlying third layer alternating stack (332, 346) can be laterally separated from an adjacent combination of a corresponding first layer alternating stack (132, 146), an overlying corresponding second layer alternating stack (232, 246), and an overlying optional third layer alternating stack (332, 346) by a backside trench fill structure 76 extending laterally along a first horizontal direction (e.g., a word line direction) hd1.

[0042] As used herein, "first level" refers to the level closest to the substrate, "second level" refers to the level closest to the substrate among the levels overlying the first level, and "third level" refers to the level closest to the substrate among the levels overlying the second level, and so on. A "first level" element refers to an element located within the first level; a "second level" element refers to an element located within the second level; a "third level" element refers to an element located within the second level; and so on. Individual levels within a structure including multiple levels may be labeled as a first level, a second level, a third level, and so on. In this case, the first level may be any one of the multiple levels, the second level may be a level different from the first level, and so on.

[0043] The exemplary structure may include an optional semiconductor material layer 110, which includes a single crystal or polycrystalline semiconductor material, such as single crystal silicon or polycrystalline silicon. In one embodiment, the semiconductor material layer 110 can be a substrate. Optionally, a lower dielectric material layer can be provided below the semiconductor material layer 110. In this case, the lower dielectric material layer is referred to as a lower level dielectric material layer 760.

[0044] A first layer alternating stack of first insulating layers 132 and first conductive layers 146 is positioned above a substrate (which may include a semiconductor material layer 110 or another structure below the semiconductor material layer 110, such as a silicon wafer) between each adjacent pair of backside trench fill structures 76. A first layer of backward stepped dielectric material portion 165 covers and contacts a first stepped surface of the first layer of alternating stack (132, 146). A second layer of alternating stack of second insulating layers 232 and second conductive layers 246 covers over the first layer of alternating stack (132, 146) and over a horizontal plane including a flat top surface of the first layer of backward stepped dielectric material portion 165 between each adjacent pair of backside trench fill structures 76. A second layer of backward stepped dielectric material portion 265 covers and contacts a second stepped surface of the second layer of alternating stack (232, 246). The third layer alternating stack of third insulating layers 332 and third conductive layers 346 (if present) overlies the second layer alternating stack (232, 246) and overlies the horizontal plane including the flat top surface of the second layer backward stepped dielectric material portion 265 between each adjacent pair of backside trench filling structures 76. The third layer backward stepped dielectric material portion 365 overlies and contacts the third stepped surfaces (if present) of the third layer alternating stack (332, 346). The vertical steps S of the first stepped surface and the second stepped surface extend laterally along the second horizontal direction hd2 (e.g., the bit line direction).

[0045] The memory opening filling structure 58 may be positioned within each memory array region 100 (each memory array region includes a first memory array region 100A and a second memory array region 100B) between each adjacent pair of backside trench filling structures 76. The memory opening filling structure 58 may be positioned within memory openings that extend vertically through each of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346) positioned between respective adjacent pairs of backside trench filling structures 76.

[0046] In one embodiment, each of the memory opening filling structures 58 includes a vertical stack of memory elements (e.g., portions of a memory film or vertically separated discrete memory elements) at the level of a conductive layer (146, 246, 346) and a vertical semiconductor channel 60 electrically connected to a corresponding overlying metal interconnect structure (such as a bit line). In one embodiment, the inter-array region 200 is free of any memory stack structures that are in electrical contact with any metal interconnect structure (such as a bit line).

[0047] Each memory opening filling structure 58 includes a corresponding memory stacking structure, which includes a corresponding memory film and a corresponding vertical semiconductor channel. The memory opening and the memory opening filling structure 58 are formed in a region where each layer of the first layer alternating stack and each layer of the second layer alternating stack exist. For each region in which a continuous combination of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346) continuously extends laterally, the first memory stacking structure can be located in the corresponding first memory array region 100A, and the second memory stacking structure can be located in the corresponding second memory array region 100B. The second memory array region 100B can be connected to the first memory array region 100A through the corresponding inter-array region 200, and the first layer backward stepped dielectric material portion 165, the second layer backward stepped dielectric material portion 265, and the optional third layer backward stepped dielectric material portion 365 are located in the inter-array region.

[0048] A first layer backward stepped dielectric material portion 165 may be located between each adjacent pair of backside trench filling structures 76. Each first layer backward stepped dielectric material portion 165 is above a first stepped surface of a corresponding first layer alternating stack (132, 146). Each first layer backward stepped dielectric material portion 165 may have a sidewall extending laterally along a first horizontal direction hd1 and contacting a corresponding backside trench filling structure 76. The first stepped surface includes vertical steps of the first layer alternating stack (132, 146) that are laterally spaced apart along the first horizontal direction hd1 and vertically offset from each other.

[0049] The second layer backward stepped dielectric material portion 265 may be located between each adjacent pair of backside trench filling structures 76. Each second layer backward stepped dielectric material portion 265 is on the second stepped surface of the corresponding second layer alternating stack (232, 246). Each second layer backward stepped dielectric material portion 265 may have a sidewall extending laterally along the second horizontal direction hd1 and contacting the corresponding backside trench filling structure 76. The second stepped surface includes vertical steps of the second layer alternating stack (232, 246) that are laterally spaced apart and vertically offset from each other along the first horizontal direction hd1. In one embodiment, each second layer backward stepped dielectric material portion 265 covers a corresponding one of the first layer backward stepped dielectric material portions 165 and contacts the corresponding one of the first layer backward stepped dielectric material portions.

[0050] The third layer backward stepped dielectric material portion 365 may be located between each adjacent pair of back-side trench filling structures 76. Each third layer backward stepped dielectric material portion 365 covers the third stepped surface of the corresponding third layer alternating stack (332, 346). Each third layer backward stepped dielectric material portion 365 may have a sidewall extending laterally along the second horizontal direction hd2 and contacting the corresponding back-side trench filling structure 76. The third stepped surface includes vertical steps of the third layer alternating stack (332, 346) that are laterally spaced apart and vertically offset from each other along the second horizontal direction hd2. In one embodiment, each third layer backward stepped dielectric material portion 365 covers a corresponding second layer backward stepped dielectric material portion in the second layer backward stepped dielectric material portion 265 and contacts the corresponding second layer backward stepped dielectric material portion.

[0051] The backside trenches may extend laterally along a first horizontal direction hd1. Each backside trench may be filled with a backside trench filling structure 76, which may include a combination of a backside contact via structure and an insulating spacer laterally surrounding the backside contact via structure. Alternatively, each backside trench filling structure 76 may consist of an insulating filling structure. Each vertical stack of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346) may be located between adjacent pairs of backside trench filling structures 76.

[0052] For each vertical stack of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346), the corresponding first backside trench filling structure 761 extends laterally along the first horizontal direction hd1 (e.g., the word line direction) and may or may not contact the first sidewall of the first layer alternating stack (132, 146), the first sidewall of the second layer alternating stack (232, 246), and the first sidewall of the third layer alternating stack (332, 346) (if any); and the second backside trench filling structure 762 extends laterally along the first horizontal direction hd1 and may or may not contact the second sidewall of the first layer alternating stack (132, 146), the second sidewall of the second layer alternating stack (232, 246), and the second sidewall of the third layer alternating stack (332, 346) (if any), as Figure 1EAs illustrated. The first backside trench filling structure 761 and the second backside trench filling structure 762 are adjacent pairs of backside trench filling structures 76. Typically, at least one of the first backside trench filling structure 761 and the second backside trench filling structure 762 is in direct contact with each layer in the first layer alternating stack (132, 146); at least one of the first backside trench filling structure 761 and the second backside trench filling structure 762 is in direct contact with each layer in the second layer alternating stack (232, 246); and in the presence of a third layer alternating stack (332, 346), at least one of the first backside trench filling structure 761 and the second backside trench filling structure 762 is in direct contact with each layer in the third layer alternating stack (332, 346).

[0053] According to various embodiments, various configurations of exemplary structures are provided, wherein one or both of the first backside trench filling structure 761 and the second backside trench filling structure 762 are in direct contact with each layer within the first layer alternating stack (132, 146). In addition, one or both of the first backside trench filling structure 761 and the second backside trench filling structure 762 are in direct contact with each layer within the second layer alternating stack (232, 246). In addition, one or both of the first backside trench filling structure 761 and the second backside trench filling structure 762 are in direct contact with each layer within the third layer alternating stack (332, 346) (if present). Although Figures 1A to 1E A configuration is illustrated in which the first back side trench filling structure 761 is not in direct contact with the first layer alternating stack (132, 146), the second layer alternating stack (232, 246) or the third layer alternating stack (332, 346), and the second back side trench filling structure 762 is in direct contact with each layer within the first layer alternating stack (132, 146), each layer within the second layer alternating stack (232, 246) and each layer within the third layer alternating stack (332, 346), but embodiments of different combinations of the first back side trench filling structure 761 and the second back side trench filling structure 762 in contact with or not in contact with each of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246) and the third layer alternating stack (332, 346) are expressly contemplated herein.

[0054] In one embodiment, the first contact via structure 86A vertically extends through the second layer back stepped dielectric material portion 265 and the first layer back stepped dielectric material portion 165, and contacts a corresponding first conductive layer in the first conductive layers 146. The second contact via structure 86B vertically extends through the second layer back stepped dielectric material portion 265, and contacts a corresponding second conductive layer in the second conductive layers 246.

[0055] The inter-array region 200 includes strips of the first insulating layer 132, the first conductive layer 146, the second insulating layer 232, the second conductive layer 246, the third insulating layer 332, and the third conductive layer 346 located between each laterally adjacent pair of backside trench filling structures 76. Such strips are located in corresponding strip-shaped connection regions 240 (i.e., bridge regions) of the inter-array region 200, which are adjacent to corresponding first layer backward stepped dielectric material portions 165, corresponding second layer backward stepped dielectric material portions 265, or corresponding third layer backward stepped dielectric material portions 365. The strips have a narrower width along the second horizontal direction hd2 than portions of the strips located in the alternating stacks (132, 146, 232, 246, 332, 346) in the memory array region 100 and portions of the strips located in the remaining portion of the inter-array region 200 outside the corresponding strip-shaped connection regions 240.

[0056] For each vertical stack of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346), the first memory opening filling structure 58 may be located in the first memory array region 100A where each layer of the first layer alternating stack (132, 1446), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346) exists. The second memory opening filling structure 58 may be located in the second memory array region 100B, which is laterally offset from the first memory array region 100A along the first horizontal direction hd1 by the first layer backward stepped dielectric material portion 165, the second layer backward stepped dielectric material portion 265, and the optional third layer backward stepped dielectric material portion 365. Each of the first layer alternating stack (132, 1446), the second layer alternating stack (232, 246), and the optional third layer alternating stack (332, 346) is present in the second memory array region 100B. Each of the conductive layers (146, 246, 346) in the vertical stack can extend continuously from the first memory array region 100A to the second memory array region 100B through a strip-shaped connection region 240 (which is also called a bridge region). Each strip-shaped connection region 240 is located within the inter-array region 200 and may be located between the back-side trench filling structure 76 and the first layer backward stepped dielectric material portion 165 at the level of the first layer alternating stack (132, 146), or between the back-side trench filling structure 76 and the second layer backward stepped dielectric material portion 265 at the level of the second layer alternating stack (232, 246), or between the back-side trench filling structure 76 and the third layer backward stepped dielectric material portion 365 at the level of the third layer alternating stack (332, 346).

[0057] The stairs including the first stepped surface of the first layer of alternating stacks (132, 146), the second stepped surface of the second layer of alternating stacks (232, 246), and the third stepped surface of the optional third layer of alternating stacks (332, 346) can rise (i.e., rise) from the substrate along the first horizontal direction hd1 or along the direction opposite to the first horizontal direction hd1. In one embodiment, the rising direction of the stairs can be changed for every other pair of vertical stacks of the corresponding first layer of alternating stacks (132, 146), the corresponding second layer of alternating stacks (232, 246), and the corresponding third layer of alternating stacks (332, 346). In other words, the direction of rise is staggered in adjacent alternating stacks separated along the second horizontal direction. For example, when each vertical stack of the corresponding first layer alternating stack (132, 146), the corresponding second layer alternating stack (232, 246) and the corresponding third layer alternating stack (332, 346) is sequentially numbered with a positive integer N starting from 1, each (4N+1)th combination and each (4N+2)th vertical stack {(132, 146), (232, 246), (332, 246)} may have steps ascending along the first horizontal direction hd1, and each (4N+3)th combination and each (4N+4)th vertical stack {(132, 146), (232, 246), (332, 246)} may have steps ascending in a direction opposite to the first horizontal direction hd1. In this embodiment, the vertical distance between the first stepped surface and the substrate increases along the first horizontal direction hd1, the vertical distance between the second stepped surface and the substrate increases along the first horizontal direction hd1, the vertical distance between the additional first stepped surface and the substrate decreases along the first horizontal direction hd1, and the vertical distance between the additional second stepped surface and the substrate decreases along the first horizontal direction hd1.

[0058] In an alternative embodiment, for every other pair of combinations of the corresponding first layer alternating stacks (132, 146), the corresponding second layer alternating stacks (232, 246), and the corresponding third layer alternating stacks (332, 246), the ascending direction of the stairs does not change. In other words, the ascending direction is the same (i.e., non-staggered) in adjacent alternating stacks separated along the second horizontal direction.

[0059] Laterally isolated vertical interconnect structures (484, 486) may be formed through the inter-array region 200. Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure 486 and a tubular insulating spacer 484 that laterally surrounds the conductive via structure 486. Each through-memory level conductive via structure 486 may contact a lower level metal interconnect structure 780 located in a lower level dielectric material layer 760, such as Figure 1D and Figure 1EThe lower level metal interconnect structure 780 may be embedded in the lower level dielectric material layer 760, which is located between the first layer alternating stack (132, 146) and a substrate (not shown) that may be disposed below the lower level dielectric material layer 760. The laterally isolated vertical interconnect structures (484, 486) extend vertically through the strip portions of the first layer alternating stack (132, 146), the second layer alternating stack (232, 246), and the third layer alternating stack (332, 346), and contact a corresponding one of the lower level metal interconnect structures 780.

[0060] The drain contact via structures (not illustrated) may contact upper portions of the corresponding memory opening filling structures 58 (such as drain regions within the corresponding memory opening filling structures 58). Bit lines (not illustrated) may extend laterally along the second horizontal direction hd2 and may contact top surfaces of the corresponding subset of the drain contact via structures. Additional metal interconnect structures embedded in an overlying dielectric material layer (not shown) may be employed to provide electrical connections between various nodes of the three-dimensional memory device positioned in the semiconductor die 1000.

[0061] Each backside trench fill structure 76 includes an insulating material portion. In one embodiment, each insulating material portion may include an insulating spacer that laterally surrounds a contact via structure, such as a backside contact via structure (not explicitly shown). In another embodiment, each insulating material portion may include a dielectric wall structure that occupies the entire volume of the corresponding backside trench fill structure 76. In one embodiment, each sidewall of the first alternating stack (132, 146) may be contacted by a sidewall of the insulating material portion of the corresponding backside trench fill structure in the backside trench fill structures 76.

[0062] According to various embodiments of the present disclosure, various backward stepped dielectric material portions (165, 265, 365) may be formed in various configurations and may or may not contact adjacent backside trench filling structures 76. In one embodiment, when the backside trench filling structures 76 are sequentially numbered with positive integers along the second horizontal direction (e.g., the bit line direction) hd2, each odd-numbered backside trench filling structure 76 contacts a corresponding pair of first-layer backward stepped dielectric material portions 165, and each even-numbered backside trench filling structure 76 does not contact any one of the first-layer backward stepped dielectric material portions 165. Alternatively, the backside trench filling structure 76 may not contact any one of the first-layer backward stepped dielectric material portions 165, and the first-layer backward stepped dielectric material portions 165 may be laterally spaced apart from each adjacent pair of backside trench filling structures 76. For each configuration of the first-layer backward stepped dielectric material portion 165, each odd-numbered back-side trench-filling structure 76 may contact a corresponding pair of second-layer backward stepped dielectric material portions 265, and each even-numbered back-side trench-filling structure 76 does not contact any of the second-layer backward stepped dielectric material portions 265. Alternatively, each even-numbered back-side trench-filling structure 76 may contact a corresponding pair of second-layer backward stepped dielectric material portions 265, and each odd-numbered back-side trench-filling structure 76 does not contact any of the second-layer backward stepped dielectric material portions 265. Still alternatively, the backside trench filling structure 76 may not contact any of the second layer backward stepped dielectric material portions 265, and the second layer backward stepped dielectric material portions 265 may be laterally spaced apart from each adjacent pair of backside trench filling structures 76. For each configuration of the first layer backward stepped dielectric material portions 165 and each configuration of the second layer backward stepped dielectric material portions 265, each odd-numbered backside trench filling structure 76 may contact a corresponding pair of third layer backward stepped dielectric material portions 365, and each even-numbered backside trench filling structure 76 does not contact any of the third layer backward stepped dielectric material portions 365. Alternatively, each even-numbered backside trench-filling structure 76 may contact a corresponding pair of third-layer backward stepped dielectric material portions 365, and each odd-numbered backside trench-filling structure 76 may not contact any of the third-layer backward stepped dielectric material portions 365. Still alternatively, the backside trench-filling structure 76 may not contact any of the third-layer backward stepped dielectric material portions 365, and the third-layer backward stepped dielectric material portions 365 may be laterally spaced apart from each adjacent pair of backside trench-filling structures 76.

[0063] In one embodiment, each plane 300 within the exemplary semiconductor die 100 includes a three-dimensional memory device including alternating stacks of insulating layers (132, 232, 332) and conductive layers (146, 246, 346). Each of the alternating stacks {(132, 146), (232, 246), (332, 346)} extends laterally along a first horizontal direction hd1 through a first memory array region 100A and a second memory array region 100B that are laterally spaced apart by an inter-array region 200. Each of the alternating stacks {(132, 146), (232, 246), (332, 346)} includes a set of stepped surfaces (i.e., stairs) in the inter-array region 200. Each plane 300 within the exemplary semiconductor die 1000 includes a backward stepped dielectric material portion (165, 265, 365) overlying a corresponding set of stepped surfaces of the alternating stacks {(132, 146), (232, 246), (332, 346)}. Each plane 300 within the exemplary semiconductor die 1000 includes a cluster of memory stack structures located within the memory opening filling structure 58. Each of the memory stack structures extends vertically through a corresponding one of the alternating stacks {(132, 146), (232, 246), (332, 346)} and is located within the first memory array region 100A or the second memory array region 100B. Each memory stack structure may include a corresponding vertical semiconductor channel and a vertical stack of memory elements (e.g., memory films) located at the level of the conductive layer (146, 246, 346).

[0064] The three-dimensional memory device may include layer contact via structures (e.g., word line contact via structures) (86A, 86B, 86C) that extend vertically through a corresponding one of the backward stepped dielectric material portions (165, 265, 365) and contact a corresponding one of the conductive layers (146, 246, 346). In one embodiment, for each pair of conductive layers (146, 246, or 346) within the same alternating stack, the layer contact via structures (86A, 86B, 86C) that contact the overlying conductive layer are closer to the first memory array region 100A than the layer contact via structures that contact the underlying conductive layer are. In other words, the higher the bottom surface of the layer contact via structure (86A, 86B, 86C) is from the substrate (110, 760), the closer the layer contact via structure (86A, 86B, 86C) is to the first memory array region 100A. In other words, the steps generally rise (i.e., increase) in each plane 300 from the shorter second memory array region 100B toward the longer first memory array region 300.

[0065] The electrical connection between each layer contact via structure (86A, 86B, 86C) and a portion of each conductive layer (146, 246 or 346) within the second memory array region 100B is provided by a stripe portion of the conductive layer (146, 246 or 346) located in the bridge region 250, the stripe portion being adjacent to the corresponding rear stepped dielectric material portion (165, 265, 365) and laterally offset from the corresponding rear stepped dielectric material portion along the second horizontal direction. The stripe portion has a smaller width (i.e., a narrower width) than a portion of the conductive layer (146, 246 or 346) located in the first memory array region 100A or the second memory array region 100B. The portion of the conductive layer (146, 246 or 346) located in the first memory array region 100A or the second memory array region 100B has a width along the second horizontal direction hd2 that is the same as the lateral distance between adjacent pairs of backside trench fill structures 76.

[0066] In contrast, each strip portion of the conductive layer (146, 246 or 346) in the bridging region 240 has a width along the second horizontal direction hd2 that is the same as the difference between the lateral distance between adjacent pairs of back-side trench filling structures 76 and the width of the adjacent rear stepped dielectric material portion (165 or 265) along the second horizontal direction hd2. Each electrical connection between the layer contact via structures (86A, 86B, 86C) and the nearest side portion of the second memory array region 100B includes a narrow strip portion of the conductive layer (146, 246, 346) in the bridge region 240, while the electrical connection between the layer contact via structures (86A, 86B, 86C) and the nearest side portion of the first memory array region 100A does not include any narrow strip portion of the conductive layer (146, 246, 346) because the first memory array region 100A is not separated from the layer contact via structures (86A, 86B, 86C) by the bridge region 240.

[0067] In one embodiment, the alternating stacks {(132, 146), (232, 246), (332, 346)} are laterally spaced apart along a second horizontal direction hd2 by line trenches (such as backside trenches) extending laterally along a first horizontal direction hd1. The line trenches are filled with a backside trench fill structure 76 having a dielectric surface (such as a surface of an insulating spacer or a dielectric wall structure) contacting the sidewalls of the alternating stacks {(132, 146), (232, 246), (332, 346)}. In one embodiment, when the back side trench filling structures 76 are sequentially numbered with positive integers along the second horizontal direction hd2, the odd-numbered back side trench filling structures may contact a corresponding pair of backward stepped dielectric material portions (165, 265, 365) (which are located on either side of the corresponding odd-numbered back side trench filling structures 76), and the even-numbered back side trench filling structures do not contact any backward stepped dielectric material portion (165, 265, 365), or the even-numbered back side trench filling structures may contact a corresponding pair of backward stepped dielectric material portions (165, 265, 365), and the odd-numbered back side trench filling structures do not contact any backward stepped dielectric material portion (165, 265, 365).

[0068] In one embodiment, the stripe width of the first conductive layer 146 decreases with the corresponding vertical distance from the substrate (760, 110). The stripe width of the second conductive layer 246 decreases with the corresponding vertical distance from the substrate (760, 110). The stripe width of the third conductive layer 346 decreases with the corresponding vertical distance from the substrate (760, 110). The bottom-most second conductive layer 246 in the second layer alternating stack (232, 246) has a larger stripe width than the top-most first conductive layer 146 in the first layer alternating stack (132, 146). The bottom-most third conductive layer 346 in the third layer alternating stack (332, 346) has a larger stripe width than the top-most second conductive layer 246 in the second layer alternating stack (232, 246).

[0069] according to Figure 1E In one aspect of the present disclosure shown, a collection of a first layer of backward stepped dielectric material portion 165, a second layer of backward stepped dielectric material portion 265, and a third layer of backward stepped dielectric material portion 365 may be formed between adjacent pairs of backside trench filling structures 76, which are referred to herein as first backside trench filling structures 761 and second backside trench filling structures 762. The top surface of the first layer of backward stepped dielectric material portion 165 may have a first width D1 along the second horizontal direction hd2, which is less than the lateral spacing between adjacent pairs of backside trench filling structures (761, 762). The top surface of the second layer of backward stepped dielectric material portion 265 may have a second width D2 along the second horizontal direction hd2, which is less than the first width D1. The top surface of the third layer of backward stepped dielectric material portion 365 may have a third width D3 along the second horizontal direction hd2, which is less than the second width D1.

[0070] The width of each strip of the conductive layer (146, 246, 346) along the second horizontal direction in the bridge region 240 is referred to herein as the strip width or bridge width. In general, embedding the back-stepped dielectric material portions (165, 265, 365) in the alternating stack of the insulating layer (132, 232, 332) and the conductive layer (146, 246, 346) may cause cracking due to voids formed in the back-stepped dielectric material portions (165, 265, 365) and / or due to unbalanced conductive layer material filling causing the alternating stack to tilt into the backside trench.

[0071] According to one aspect of the present disclosure, the bridge width is different at different layer levels in the bridge region 240. For example, the stripe portion of the topmost first conductive layer 146 in each first layer alternating stack (132, 146) may have a first lateral extent (i.e., first width) E1 along the second horizontal direction hd2, the stripe portion of the topmost second conductive layer 246 in each second layer alternating stack (232, 242) may have a second lateral extent (i.e., second width) E2 along the second horizontal direction hd2, and the stripe portion of the topmost third conductive layer 346 in each third layer alternating stack (332, 342) may have a third lateral extent (i.e., third width) E3 along the second horizontal direction hd2. The first lateral extent E1 is smaller than the second lateral extent E2, and the second lateral extent E2 is smaller than the third lateral extent E3. In other words, the first width in the lower layer is smaller than the second width in the overlying second layer, and the second width is smaller than the third width in the overlying third layer (if present). Thus, due to the larger space between the strips in the lower layer in the bridging region 240, the formation of gaps in the rear stepped dielectric material portion (165, 265, 365) can be reduced or avoided, and / or due to the more balanced conductive layer material filling, the tilting of the alternating stacking into the backside trench can be reduced or avoided, as will be described below.

[0072] In addition, reference Figure 1C , for a three-layer memory device, the length of the bridging region 240 at the top of the first layer structure in the first horizontal direction hd1 may be L1, the length of the bridging region 240 at the top of the second layer structure in the first horizontal direction may be L2, and the length of the bridging region 240 at the top of the third layer structure in the first horizontal direction may be L3. In one embodiment, if L3 is equal to the length X, then L2=2 / 3X and L1=1 / 3X, and if E3 is equal to the width Y, then E2=2 / 3Y and E1=1 / 3Y. Similarly, for a two-layer memory device embodiment, if L2 is equal to the length X, then L1= 1 / 2, and if E2 is equal to width Y, then E1=1 / 2Y. In these embodiments, the resistance of the conductive layers (146, 246, 346) in the bridge region 240 in all three layers can be similar (e.g., differ by 10% or less) because in the same bridge region 240, the longer conductive layer 346 has a larger width than the shorter conductive layer 146.

[0073] In one embodiment, the first layer structure may be embedded in a first layer backward stepped dielectric material portion 165, the first layer backward stepped dielectric material portion having a first length along the first horizontal direction hd1 and a first width D1 along the second horizontal direction hd2. The second layer structure may be embedded in a second layer backward stepped dielectric material portion 265, the second layer backward stepped dielectric material portion having a second length greater than the first length along the first horizontal direction hd1 and having a second width D2 less than the first width D1 along the second horizontal direction hd2. The third layer structure may be embedded in a third layer backward stepped dielectric material portion 365, the third layer backward stepped dielectric material portion having a third length greater than the second length along the first horizontal direction hd1 and having a third width D3 less than the second width D2 along the second horizontal direction hd2. Therefore, the average bridging width (i.e., average stripe width) of the third conductive layer 346 along the second horizontal direction hd2 is greater than the average bridging width of the second conductive layer 246 along the second horizontal direction hd2, and the average bridging width of the second conductive layer along the second horizontal direction is greater than the average bridging width of the first conductive layer 146 along the second horizontal direction hd2.

[0074] In some embodiments, various layer structures can be constructed mirror-symmetrically with respect to a vertical plane extending through the backside trench filling structure 76 (such as the first backside trench filling structure 761) along the first horizontal direction. According to one aspect of the present disclosure, during the formation of the first layer of backward stepped dielectric material portions 165, conformal filling of the dielectric material in the backward stepped trenches can be facilitated by increasing the width of the backward stepped trenches along the second horizontal direction hd2, which is accompanied by an increase in the first width D1 of each first layer of backward stepped dielectric material portion 165. This reduces cracking and tilting while forming a symmetrical structure around each backside trench located between a pair of corresponding backward stepped dielectric material portions (165, 265, 365) stacks.

[0075] Although Figures 1A to 1E The illustrated configuration of the exemplary structure illustrated in employs three layer hierarchies, but embodiments employing two layer hierarchies or four or more layer hierarchies in alternative configurations are expressly contemplated herein.

[0076] A sequence of processing steps may be used to produce Figures 1A to 1E An exemplary semiconductor die 1000 is shown. FIG. 2A to FIG. 2C, illustrating a first vertical alternating sequence for forming a semiconductor device 720 on a substrate semiconductor layer 9 (which is disposed at least within an upper portion of a substrate 8), a lower level dielectric layer 760, a lower level metal interconnect structure 780 embedded in the lower level dielectric layer 760 (schematically represented by a dashed area including a physical implementation of the lower level metal interconnect structure), a semiconductor material layer 110, and a first insulating layer 132 and a first sacrificial material layer 142. Figures 1A to 1E The substrate semiconductor layer 9 may include a top portion (e.g., a doped well) of a substrate 8 (such as a silicon wafer) or a semiconductor layer positioned above a substrate (such as a silicon-on-insulator substrate or a semiconductor substrate). The semiconductor device 720 may include a field effect transistor formed above the top surface of the substrate 8. The lower level dielectric layer 760 may be an interconnect level dielectric material layer embedded in the lower level metal interconnect structure 780.

[0077] As used herein, a vertical alternating sequence refers to a sequence of multiple instances of a first element and multiple instances of a second element arranged such that an instance of the second element is positioned between each vertically adjacent pair of instances of the first element, and an instance of the first element is positioned between each vertically adjacent pair of instances of the second element.

[0078] The first insulating layer 132 may be composed of a first material, and the first sacrificial material layer 142 may be composed of a second material different from the first material. Each of the first insulating layers 132 is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the first sacrificial material layers 142 includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0079] The second material of the first sacrificial material layer 142 is a dielectric material that is a sacrificial material that is selectively removable with respect to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0080] The second material of the first sacrificial material layer 142 may then be replaced with a conductive electrode, which may be used, for example, as a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0081] Generally speaking, a vertical alternating sequence of unit layers is stacked on a substrate. Each unit layer stack in the unit layer stack includes a first insulating layer (such as the first insulating layer 132) and a first spacer material layer (such as the first sacrificial material layer 142). Typically, the first spacer material layer is formed as a first conductive layer, or is subsequently replaced by the first conductive layer. Although the present disclosure is described using an embodiment in which the first spacer material layer is formed as a first sacrificial material layer 142 that is subsequently replaced with the first conductive layer, an embodiment in which the first spacer material layer is formed as a first conductive layer is explicitly contemplated herein. In such an embodiment, the step of replacing the material of the first spacer material layer with a conductive material can be omitted.

[0082] The first stepped surface may be formed in the staircase region of the inter-array region 200, which will be filled with the first layer of backward stepped dielectric material portion 165. For example, a combination of a sacrificial hard mask layer and a trim mask layer may be used to form the first stepped surface. In one embodiment, a row of a plurality of first staircase regions may be formed in each region corresponding to a combination of a region of a laterally adjacent pair of first layer backward stepped dielectric material portions 165 and an intermediate region. In this case, the plurality of first staircase regions may be subsequently vertically offset to different depths by subsequently performing a regional recess etching process.

[0083] In the illustrated example, 2 M A first set of stepped surfaces may be formed in a combination of the regions of the first layer backward stepped dielectric material portions 165 and the intermediate regions of the laterally adjacent pairs. M may be an integer in the range of 1 to 8. Each first set of stepped stairs may include P steps such that the sidewalls of the P first continuous spacer material layers are physically exposed with a lateral offset. P may be an integer in the range of 2 to 64. The regional recess etching process may be performed M times such that each regional recess etching process causes P×2 iA set of first insulating layers 132 and first sacrificial material layers 142 are vertically recessed, where i is a different integer in the range of 0 to (M-1). For the first vertical alternating sequence of first insulating layers 132 and first sacrificial material layers 142, a total of up to 2 M ×P stepped surfaces. The total number of stepped surfaces within each continuous cavity covering the first stepped surface may be the same as the total number of first sacrificial material layers 142 in the first vertical alternating sequence (132, 142).

[0084] A first dielectric fill material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, may be deposited in each first continuous backward stepped cavity. The first dielectric fill material may be planarized to remove excess portions of the first dielectric fill material from above a horizontal plane including the topmost surface of the first vertical alternating sequence (132, 142). Each remaining portion of the first dielectric fill material filling the corresponding first continuous backward stepped cavity constitutes a first layer backward stepped dielectric material portion 165. Generally, the first layer backward stepped dielectric material portion 165 may be formed in an inter-array region 200 located between a corresponding first memory array region 100A and a corresponding second memory array region 100B that are laterally spaced apart along a first horizontal direction hd1.

[0085] Various first layer openings may be formed into the semiconductor material layer 110 through the first vertical alternating sequence (132, 142). A photoresist layer (not shown) may be applied over the first vertical alternating sequence (132, 142), and the photoresist layer may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the first vertical alternating sequence (132, 142) into the semiconductor material layer 110 through the first anisotropic etching process to simultaneously (i.e., during the first isotropic etching process) form various first layer openings. The various first layer openings may include first layer memory openings formed in the memory array region 100 and first layer support openings formed in the inter-array region 200. Each cluster of the first layer memory openings may be formed as a two-dimensional array of first layer memory openings. The first layer support openings are openings formed in the inter-array region 200 and are subsequently used to form support pillar structures. A subset of the first layer support openings may be formed through corresponding horizontal surfaces of the first stepped surface.

[0086] A sacrificial first layer opening filling portion may be formed in each first layer opening. For example, a sacrificial first layer filling material is deposited simultaneously in each first layer opening in the first layer opening. The sacrificial first layer filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142. In one embodiment, the sacrificial first layer filling material may include a semiconductor material, such as silicon (e.g., a-Si or polycrystalline silicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer filling material. The sacrificial first layer filling material may be formed by a non-conformal deposition or a conformal deposition method.

[0087] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the material of the first insulating layer 132. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 dilute hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0088] In yet another embodiment, the sacrificial first layer fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed for the material of the first vertical alternating sequence (132, 142).

[0089] Portions of the deposited sacrificial first layer fill material may be removed from above the topmost layer of the first vertical alternating sequence (132, 142), such as from above the topmost first insulating layer 132. For example, the sacrificial first layer fill material may be recessed to the top surface of the topmost first insulating layer 132 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the topmost first insulating layer 132 may be used as an etch stop layer or a planarization stop layer.

[0090] The remaining portion of the sacrificial first layer filling material includes a sacrificial first layer opening filling portion. Specifically, each remaining portion of the sacrificial first layer filling material in the first layer memory opening constitutes a sacrificial first layer memory opening filling portion 148. Each remaining portion of the sacrificial first layer filling material in the first layer support opening constitutes a sacrificial first layer support opening filling portion (not shown). The respective sacrificial first layer opening filling portions are formed simultaneously, that is, formed during the same set of processes, including a deposition process and a planarization process, the deposition process depositing the sacrificial first layer filling material, and the planarization process removing the first layer deposition process from above the first vertical alternating sequence (132, 142) (such as from above the top surface of the topmost first insulating layer 132). The top surface of the sacrificial first layer opening filling portion may be coplanar with the top surface of the topmost first insulating layer 132. Each of the sacrificial first layer opening filling portions may include or exclude a cavity therein. The collection of all structures positioned between the bottommost surface of the first vertical alternating sequence (132, 142) and the topmost surface of the first vertical alternating sequence (132, 142) or embedded within the first vertical alternating sequence (132, 142) constitutes a first layer structure.

[0091] refer to FIG. 3A to FIG. 3C , a second vertical alternating sequence of second insulating layers 232 and second sacrificial material layers 242 may be formed. Each of the second insulating layers 232 is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the second sacrificial material layers 242 includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. The second insulating layer 232 may have the same material composition and the same thickness as the first insulating layer 132. The second sacrificial material layer 242 may have the same material composition and the same thickness as the first sacrificial material layer 142.

[0092] In general, at least one additional vertical alternating sequence of additional insulating layers and additional sacrificial material layers may optionally be formed over the first vertical alternating sequence ( 132 , 142 ) and the first layer of backward stepped dielectric material portion 165 .

[0093] The second stepped surface may be formed in the staircase region of the inter-array region 200, which will be filled with the second layer of backward stepped dielectric material portion 265. For example, a combination of a sacrificial hard mask layer and a trim mask layer may be used to form the second stepped surface. In one embodiment, a row of a plurality of second staircase regions may be formed in each region corresponding to a combination of a region of a laterally adjacent pair of second layer backward stepped dielectric material portions 265 and an intermediate region. In this case, the plurality of second staircase regions may be subsequently vertically offset to different depths by subsequently performing a regional recess etching process.

[0094] In the illustrated example, 2 N A second set of stepped surfaces may be formed in a combination of the regions of the second layer backward stepped dielectric material portions 265 and the intermediate regions of the laterally adjacent pairs. N may be an integer in the range of 2 to 8. Each second set of stepped stairs may include P steps such that the sidewalls of Q second continuous spacer material layers are physically exposed with a lateral offset. Q may be an integer in the range of 2 to 64. The regional recess etching process may be performed M times such that each regional recess etching process causes Q×2 j A set of second insulating layers 232 and second sacrificial material layers 242 are vertically recessed, where j is a different integer in the range of 0 to (N-1). For the second vertical alternating sequence of second insulating layers 232 and second sacrificial material layers 242, a total of up to 2 N ×Q stepped surfaces. The total number of stepped surfaces within each continuous cavity covering the second stepped surface may be the same as the total number of second sacrificial material layers 242 in the second vertical alternating sequence (132, 242).

[0095] A second dielectric filling material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each second continuous backward stepped cavity. The second dielectric filling material may be planarized to remove excess portions of the second dielectric filling material above a horizontal plane including the topmost surface of the second vertical alternating sequence (232, 242). Each remaining portion of the second dielectric filling material filling the corresponding second continuous backward stepped cavity constitutes a second layer of backward stepped dielectric material portion 265.

[0096] Typically, a second layer structure is formed that includes a second vertical alternating sequence of second insulating layers 232 and second sacrificial material layers 242 and a second layer of back stepped dielectric material portion 265 overlying a second stepped surface of the second vertical alternating sequence in the inter-array region 200 .

[0097] Respective second layer openings may be formed through the second vertical alternating sequence (232, 242) and over the sacrificial first layer opening filling portions. A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232, 242) and the photoresist layer may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the second vertical alternating sequence (232, 242) to simultaneously (i.e., during the second isotropic etching process) form the respective second layer openings.

[0098] Each second layer opening may include a second layer memory opening formed in the memory array region 100 and a second layer support opening formed in the inter-array region 200. Each second layer opening may be formed in the region of a corresponding one of the sacrificial first layer opening filling portions. Therefore, the top surface of the sacrificial first layer opening filling portion may be physically exposed at the bottom of each second layer opening. Specifically, each second layer memory opening may be formed directly above the corresponding sacrificial first layer memory opening filling portion 148, and each second layer support opening may be formed directly above the corresponding sacrificial first layer support opening filling portion. Each cluster of the second layer memory openings may be formed as a two-dimensional array of second layer memory openings. The second layer support openings are openings formed in the inter-array region 200 and are subsequently used to form a support column structure. A subset of the second layer support openings may be formed through a corresponding horizontal surface of the second stepped surface.

[0099] A sacrificial second layer opening filling portion may be formed in each second layer opening. For example, a sacrificial first layer filling material is simultaneously deposited in each second layer opening in the second layer opening. The sacrificial second layer filling material may include any material that can be used for sacrificial first layer filling material. A portion of the deposited sacrificial second layer filling material may be removed from above the topmost layer of the second vertical alternating sequence (232, 242). The remaining portion of the sacrificial second layer filling material includes a sacrificial second layer opening filling portion. Specifically, each remaining portion of the sacrificial second layer filling material in the second layer memory opening constitutes a sacrificial second layer memory opening filling portion 248. Each remaining portion of the sacrificial second layer filling material in the first layer support opening constitutes a sacrificial second layer support opening filling portion (not illustrated). The top surface of the sacrificial second layer opening filling portion may be coplanar with the top surface of the topmost second insulating layer 232. Each sacrificial second layer opening filling portion in the sacrificial second layer opening filling portion may include or not include a cavity therein. The collection of all structures positioned between the bottommost surface of the second vertical alternating sequence (232, 242) and the topmost surface of the second vertical alternating sequence (232, 242) or embedded within the second vertical alternating sequence (232, 242) constitutes a second layer structure.

[0100] refer to Figure 4A and Figure 4B, a third vertical alternating sequence of third insulating layers 332 and third sacrificial material layers 342 may be formed. Each of the third insulating layers 332 is an insulating layer that extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. Each of the third sacrificial material layers 342 includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8, and may have a uniform thickness as a whole. The third insulating layer 332 may have the same material composition and the same thickness as the first insulating layer 132. The third sacrificial material layer 342 may have the same material composition and the same thickness as the first sacrificial material layer 142.

[0101] In general, at least one additional vertical alternating sequence of additional insulating layers and additional sacrificial material layers may optionally be formed over the first vertical alternating sequence ( 132 , 142 ) and the first layer of backward stepped dielectric material portion 165 .

[0102] The third stepped surface may be formed in the staircase region of the inter-array region 200, which will be filled with the third layer of backward stepped dielectric material portion 365. For example, a combination of a sacrificial hard mask layer and a trim mask layer may be used to form the third stepped surface. In one embodiment, a row of a plurality of third staircase regions may be formed in each region corresponding to a combination of a region and an intermediate region of a laterally adjacent pair of third layer backward stepped dielectric material portions 365. In this case, the plurality of third staircase regions may be subsequently vertically offset to different depths by subsequently performing a regional recess etching process.

[0103] A third dielectric filling material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each third continuous backward stepped cavity. The third dielectric filling material may be planarized to remove excess portions of the third dielectric filling material above a horizontal plane including the topmost surface of the third vertical alternating sequence (332, 342). Each remaining portion of the third dielectric filling material filling the corresponding third continuous backward stepped cavity constitutes a third layer of backward stepped dielectric material portion 365.

[0104] Typically, a third layer structure is formed that includes a third vertical alternating sequence of third insulating layers 332 and third sacrificial material layers 342 and a third layer of back stepped dielectric material portion 365 overlying a third stepped surface of the third vertical alternating sequence in the inter-array region 200 .

[0105] FIG. 5A to FIG. 5E are vertical cross-sectional views of various configurations of an exemplary structure after forming a third layer structure according to an embodiment of the present disclosure. FIG. 5A to FIG. 5EThe width of the vertical cross-sectional view illustrated in FIG corresponds to the lateral extent of three adjacent backside trench filling structures 76 that will be subsequently formed in various configurations of the exemplary structure along the second horizontal direction hd2. In other words, three adjacent backside trench filling structures 76 may be subsequently formed in the lateral extent of each of the illustrated regions of the various illustrated configurations of the exemplary structure.

[0106] FIG. 5A to FIG. 5D The configuration illustrated in FIG. 1 employs three layers, and Figure 5E The configuration illustrated in employs two layers. FIG. 5A to FIG. 5E Various exemplary configurations of the exemplary structures in the embodiment of the present invention employ optional layers that may or may not be formed over the respective vertical alternating sequences of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342). The optional layers are referred to herein as first insulating capping layer 170, second insulating capping layer 270, and third insulating capping layer 370. Each of the insulating capping layers (170, 270, 370) comprises an insulating material such as silicon oxide and may have a thickness in the range of 30 nm to 600 nm such as 60 nm to 300 nm, although lesser and greater thicknesses may also be employed.

[0107] refer to Figure 5A , illustrating a first configuration of an exemplary structure, which includes a stack of a first backward stepped dielectric material portion 165, a second backward stepped dielectric material portion 265 having a smaller lateral extent along a second horizontal direction hd2 than the first backward stepped dielectric material portion 165, and a third backward stepped dielectric material portion 365 having a smaller lateral extent along the second horizontal direction hd2 than the second backward stepped dielectric material portion 265.

[0108] refer to Figure 5B , illustrating a second configuration of the exemplary structure, which includes a stack of two first backward stepped dielectric material portions 165 laterally spaced apart from each other along a second horizontal direction hd2, a second backward stepped dielectric material portion 265 having a smaller lateral extent along the second horizontal direction hd2 than the two first backward stepped dielectric material portions 165, and a third backward stepped dielectric material portion 365 having a smaller lateral extent along the second horizontal direction hd2 than the second backward stepped dielectric material portion 265.

[0109] refer to Figure 5C, illustrating a third configuration of the exemplary structure, which includes a stack of a first backward stepped dielectric material portion 165, two second backward stepped dielectric material portions 265 and a third backward stepped dielectric material portion 365, wherein the third backward stepped dielectric material portion has a smaller lateral extent along the second horizontal direction hd2 than the two second backward stepped dielectric material portions 265.

[0110] refer to Figure 5D , illustrating a fourth configuration of the exemplary structure, which includes a stack of two first backward stepped dielectric material portions 165 laterally spaced apart from each other along a second horizontal direction hd2, two second backward stepped dielectric material portions 265 having a smaller lateral extent along the second horizontal direction hd2 than the two first backward stepped dielectric material portions 165, and a third backward stepped dielectric material portion 365 having a smaller lateral extent along the second horizontal direction hd2 than the two second backward stepped dielectric material portions 265.

[0111] refer to Figure 5E , illustrating a fifth configuration of the exemplary structure, which includes a stack of two first backward stepped dielectric material portions 165 laterally spaced apart from each other along a second horizontal direction hd2, and a second backward stepped dielectric material portion 265 having a smaller lateral extent than the two first backward stepped dielectric material portions 165 along the second horizontal direction hd2.

[0112] In one embodiment, a plurality of layered structures stacked vertically may be formed above the substrate 8. Each layer structure within the plurality of layer structures includes a respective vertical alternating sequence of continuous insulating layers (132, 232, 332) and continuous sacrificial material layers (142, 242, 342). Figure 5B , Figure 5D and Figure 5E As illustrated, a first layer structure of the plurality of layer structures may include a pair of first backward stepped dielectric material portions (such as first layer backward stepped dielectric material portions 165) overlying a first vertical alternating sequence of first continuous insulating layers (132, 232, 332) and first continuous sacrificial material layers (142, 242, 342). In addition, a second layer structure of the plurality of layer structures overlies the first layer level and includes second backward stepped dielectric material portions (265 and / or 365) having a partial area overlap with each of the pair of first backward stepped dielectric material portions 165 in a plan view along a vertical direction perpendicular to the top surface of the substrate 8, such as Figure 5B As illustrated in Figure 5F.

[0113] FIG. 6A to FIG. 6Care sequential vertical cross-sectional views of an exemplary structure during formation of an inter-layer memory opening 49 according to one embodiment of the present disclosure.

[0114] refer to Fig. 6A , in the corresponding Figure 4A and Figure 4B as well as FIG. 5A to FIG. 5E An exemplary structure is illustrated at the processing steps of the processing steps.

[0115] refer to Figure 6B , each third layer opening may be formed through the third vertical alternating sequence (332, 342) and over the sacrificial first layer opening filling portion. A photoresist layer (not shown) may be applied over the third vertical alternating sequence (332, 342), and the photoresist layer may be photolithographically patterned to form each opening therethrough. The pattern of the openings in the photoresist layer may be transferred through the third vertical alternating sequence (332, 342) to form each third layer opening simultaneously (i.e., during the third isotropic etching process).

[0116] Each third layer opening may include a third layer memory opening formed in the memory array region 100 and a third layer support opening formed in the inter-array region 200. Each third layer opening may be formed in the region of a corresponding one of the sacrificial second layer opening filling portions. Therefore, the top surface of the sacrificial second layer opening filling portion may be physically exposed at the bottom of each third layer opening. Specifically, each third layer memory opening 349 may be formed directly above the corresponding sacrificial second layer memory opening filling portion 248, and each third layer support opening may be formed directly above the corresponding sacrificial second layer support opening filling portion. Each cluster of the third layer memory openings 349 may be formed as a two-dimensional array of the third layer memory openings 349. The third layer support openings (not shown) are openings formed in the inter-array region 200 and are subsequently used to form a support column structure. A subset of the third layer support openings may be formed through a corresponding horizontal surface of the third stepped surface.

[0117] refer to Figure 6C, the sacrificial first layer filling material of the sacrificial second layer opening filling portion 248 and the sacrificial first layer opening filling portion 148 can be removed using an etching process that selectively etches the sacrificial second layer filling material and the sacrificial first layer filling material with respect to the materials of the insulating layer (132, 232, 332) and the sacrificial material layer (142, 242, 342). A memory opening (also referred to as an interlayer memory opening 49) is formed in each combination of the third layer memory opening 349 and the volume from which the sacrificial second layer memory opening filling portion 248 and the sacrificial first layer memory opening filling portion 148 are removed. A support opening (also referred to as an interlayer support opening (not shown)) is formed in each combination of the third layer support opening and the volume from which the sacrificial second layer support opening filling portion and the sacrificial first layer support opening filling portion are removed. The interlayer memory opening 49 extends through the third layer structure, the second layer structure, and the first layer structure. Generally, memory openings 49 may be formed in each memory array region 100 at each layer where there are first vertical alternating sequences (132, 142), second vertical alternating sequences (232, 242), and third vertical alternating sequences (332, 342).

[0118] 7A to 7E Illustrated are sequential vertical cross-sectional views of memory opening 49 during formation of memory opening filling structure 58 according to one embodiment of the present disclosure.

[0119] refer to Fig. 7A , exemplifies Figure 6C The inter-layer memory opening 49 at the processing step.

[0120] refer to Figure 7B, a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and an optional sacrificial cap layer 57 may be sequentially deposited in the interlayer memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or in addition, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0121] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242, 342) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242, 342) and the insulating layer (132, 232, 332) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242, 342) may be laterally recessed relative to the sidewalls of the insulating layer (132, 232, 332), and a combination of a deposition process and anisotropic etching process may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0122] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0123] The sacrificial capping layer 57 may include a sacrificial material that may be subsequently removed selectively to the material of the tunnel dielectric layer 56. For example, the sacrificial capping layer may include a semiconductor material (e.g., amorphous silicon), silicon oxide, or a carbon-based material (such as amorphous carbon or diamond-like carbon). The thickness of the sacrificial capping layer may be in the range of 1 nm to 10 nm, although lesser and greater thicknesses may also be employed.

[0124] refer to Figure 7C , an anisotropic etching process may be performed to remove horizontal portions of the sacrificial capping layer 57, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. During the anisotropic etching process, or by an isotropic etching process (such as a wet etching process) or by ashing, the remaining cylindrical portion of the sacrificial capping layer 57 may be removed selectively to the material of the tunneling dielectric layer 56. Alternatively, if the sacrificial capping layer 57 includes a semiconductor material (e.g., amorphous silicon), it may be retained.

[0125] refer to Fig.7D , the semiconductor channel material layer 60L may be deposited by a conformal deposition process. The semiconductor channel material layer 60L includes a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopant (such as boron atoms) is present at 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 (such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 ) in an atomic concentration in the range of 1.0×10 . In one embodiment, the semiconductor channel material layer 60L includes and / or consists essentially of boron-doped amorphous silicon or boron-doped polycrystalline silicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present in an atomic concentration in the range of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 (such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 ) range. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be used. A cavity 49' is formed in the volume of each interlayer memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0126] refer to Fig. 7E , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the top second insulating layer 232 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the topmost second insulating layer 232. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0127] refer to Figure 7F, a doped semiconductor material having a second conductivity type of doping may be deposited in a cavity overlying the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the topmost second insulating layer 232) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0128] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0129] Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0130] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the interlayer memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed through the memory array region 100 of the first vertical alternating sequence and the second vertical alternating sequence, wherein all layers of the first vertical alternating sequence and the second vertical alternating sequence are present. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the interlayer memory opening 49 constitutes a memory opening filling structure 58. Generally speaking, the memory opening filling structure 58 is formed within the memory opening 49. Each of the memory opening filling structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0131] In one embodiment, each of the memory stack structures 55 includes a vertical NAND string that includes a corresponding vertical stack of memory elements (including a portion of the charge storage layer 54 located at the level of the sacrificial material layer (142, 242, 342)) and a vertical semiconductor channel 60 extending vertically through the sacrificial material layer (142, 242, 342) adjacent to the corresponding vertical stack of memory elements.

[0132] refer to Fig. 8A and Figure 8B , exemplified in Figure 7F 4, after forming a memory opening filling structure 58 in the memory opening 49. In one embodiment, a support pillar structure (not shown) may be formed in the support opening. Generally, each of the memory opening filling structures 58 includes a respective vertical stack of memory elements at the level of the conductive layer (146, 246, 346) within the multiple layer structure, and also includes a respective vertical semiconductor channel 60 extending vertically through the multiple layer structure.

[0133] Subsequently, a backside trench 79 extending laterally through the plurality of layer structures along a first horizontal direction hd1 may be formed, such as Figure 8B The position of the back side groove 79 can be Figure 1A and Figure 1E The positions of the illustrated backside trench fill structures 76 are the same. Each of the vertical alternating sequences is divided into a corresponding set of alternating stacks {(132, 142), (232, 242), (332, 342)} of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342) that are laterally spaced apart along a second horizontal direction hd2.

[0134] In one embodiment, the first backside trench 79 divides each dielectric material portion (165, 265, 365) into a pair of backward stepped dielectric material portions (such as the first layer backward stepped dielectric material portion 265, the second layer backward stepped dielectric material portion 265 and / or the third layer backward stepped dielectric material portion 365). In general, a plurality of layer structures stacked vertically may be formed above the substrate 8. Each layer structure within the plurality of layer structures includes a corresponding alternating stacked set of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342). The first layer structure within the multiple layer structures includes a pair of first backward stepped dielectric material portions (such as the first layer backward stepped dielectric material portion 165) covering the corresponding first alternating stack of the first insulating layer 132 and the first sacrificial material layer 142, and the second layer structure covers the first layer level and includes a pair of second backward stepped dielectric material portions 265, which have a partial area overlap with the corresponding pair of first backward stepped dielectric material portions 165 in a plan view along the vertical direction perpendicular to the top surface of the substrate 8.

[0135] refer to Fig. 9 By supplying an isotropic etching liquid into the backside trench 79, the sacrificial material layer (142, 242, 342) can be selectively and isotropically etched with respect to the insulating layer (132, 232, 332), the first backward stepped dielectric material portion (such as the first layer backward stepped dielectric material portion 165 or the second layer backward stepped dielectric material portion 265), the second backward stepped dielectric material portion (such as the second layer backward stepped dielectric material portion 265 or the third layer backward stepped dielectric material portion 365), and any additional backward stepped dielectric material portions.

[0136] Typically, by supplying an isotropic etchant into the backside trench, the sacrificial material layer (142, 242, 342) can be isotropically etched selectively to the insulating layer (132, 232, 332), the back stepped dielectric material portion (165, 265, 365), and the semiconductor material layer 110. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242, 342) relative to the material of the insulating layer (132, 232, 332), the back stepped dielectric material portion (165, 265, 365), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242, 342) may include silicon nitride, and the insulating layer (132, 232, 332), the backward stepped dielectric material portion (165, 265, 365), and the outermost layer of the memory film 50 may include silicon oxide material.

[0137] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench in a vapor phase. For example, if the sacrificial material layer (142, 242, 342) includes silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0138] A backside recess (143, 243, 343) is formed in the volume from which the sacrificial material layer (142, 242, 342) is removed. The backside recess (143, 243, 343) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed, a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed, and a third backside recess 343 formed in the volume from which the third sacrificial material layer 342 is removed. Each of the backside recesses (143, 243, 343) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243, 343) can be greater than the height of the corresponding backside recess. A plurality of backside recesses (143, 243, 343) may be formed in the volume from which the material of the sacrificial material layer (142, 242, 342) is removed. Each of the backside recesses (143, 243, 343) may extend substantially parallel to the top surface of the semiconductor material layer 110. The backside recesses (143, 243, 343) may be vertically bounded by the top surface of the underlying insulating layer (132, 232, 332) and the bottom surface of the overlying insulating layer (132, 232, 332). In one embodiment, each of the backside recesses (143, 243, 343) may have a uniform height overall.

[0139] refer to Fig. 10A and Fig. 10B An optional backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses (143, 243, 343) and the backside trenches. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide (eg, aluminum oxide), silicon oxide, or a combination thereof.

[0140] The conductive layer (146, 246, 346) can be deposited in the remaining volume of the backside recess (143, 243, 343) by performing a conformal deposition process in which a precursor gas for the conductive material of the conductive layer (146, 246, 346) is supplied into the backside recess (143, 243, 343) through the backside trench 79. At least one conductive material can be deposited in the plurality of backside recesses (143, 243, 343), on the sidewalls of the backside trenches, and above the topmost layer structure. The at least one conductive material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0141] In one embodiment, at least one conductive material may include at least one metallic material, i.e., a conductive material containing at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the back recess (143, 243, 343) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filling material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, at least one conductive material used to fill the back recess (143, 243, 343) may be a combination of a titanium nitride layer and a tungsten filling material.

[0142] The conductive layer (146, 246, 346) may be formed by depositing at least one conductive material in the back side recess (143, 243, 343). A plurality of first conductive layers 146 may be formed in the plurality of first back side recesses 143, a plurality of second conductive layers 246 may be formed in the plurality of second back side recesses 243, a plurality of third conductive layers 346 may be formed in the plurality of third back side recesses 343, and a continuous metal material layer (not shown) may be formed on the sidewall of each back side trench and above the topmost layer structure. Each of the conductive layers (146, 246, 346) may include a corresponding conductive metal nitride liner and a corresponding conductive filling material. Therefore, the sacrificial material layer (142, 242, 342) may be replaced by the conductive layer (146, 246, 346), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246, and each third sacrificial material layer 342 may be replaced with an optional portion of the backside blocking dielectric layer and the third conductive layer 346. A backside cavity exists in a portion of each backside trench that is not filled with a continuous metal material layer.

[0143] During the formation of the conductive layer (146, 246, 346), a continuous layer of metallic material is formed at the perimeter region of the backside trench 79 and over the multiple layer structures.

[0144] The residual conductive material of the continuous metal material layer can be removed from inside the backside trench 79 and over the multiple layered structures. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each backside trench and from over the topmost layer structure, for example, by anisotropic or isotropic etching.

[0145] Each remaining portion of the deposited metallic material in the first backside recess constitutes a first conductive layer 146 .

[0146] Each remaining portion of the deposited metallic material in the second backside recess constitutes a second conductive layer 246 .

[0147] Each remaining portion of the deposited metal material in the third backside recess constitutes a third conductive layer 346. The sidewalls of the conductive layer (146, 246, 346) may be physically exposed to the corresponding backside trench 79.

[0148] Each conductive layer (146, 246, 346) may be a conductive sheet including openings therein. A first subset of openings through each conductive layer (146, 246, 346) may be filled with memory opening filling structure 58. A second subset of openings through each conductive layer (146, 246, 346) may be filled with support pillar structure 20.

[0149] A subset of the conductive layers (146, 246, 346) may include word lines for memory elements. The semiconductor devices in the semiconductor device 720 below may include word line switch devices (the word line switch devices are configured to control the bias voltage to the corresponding word lines) and / or bit line driver devices, such as sense amplifiers. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246, 332, 346) and a memory stack structure 55 vertically extending through at least one alternating stack (132, 146, 232, 246, 332, 346). Each of the memory stack structures 55 includes a vertical stack of memory elements at each level of the conductive layer (146, 246, 346).

[0150] FIG. 11A to FIG. 11D yes Fig. 10A and Fig. 10B Schematic vertical cross-sectional views of various configurations of exemplary structures. FIG. 11A to FIG. 11D , after removing the continuous metal material layer, a backside trench filling structure 76 is formed in the volume of the backside trench 79 .

[0151] A backside trench filling structure 76 may be formed in each backside trench 79. In one embodiment, an insulating liner layer comprising a dielectric material, such as silicon oxide, may be conformally deposited at the periphery of each backside trench and may be anisotropically etched to form insulating spacers within each backside trench. At least one conductive material may be deposited in the remaining volume of the backside trench, and excess portions of the at least one conductive material may be removed from above the topmost layer structure by a planarization process. Each remaining portion of the at least one conductive material that contacts the source region and is laterally surrounded by a corresponding insulating spacer constitutes a backside contact via structure that extends laterally along a first horizontal direction hd1. Each continuous combination of an insulating spacer and a backside contact via structure that fills the backside trench constitutes a backside trench filling structure 76.

[0152] Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited in the backside trenches by a conformal deposition process. Each portion of the deposited dielectric material that fills the backside trenches constitutes a backside trench fill structure 76. In this case, each backside trench fill structure may fill the entire volume of the backside trenches and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region may be omitted, and the horizontal source line (e.g., a direct stripe contact layer) may contact the side of the lower portion of the semiconductor channel 60.

[0153] Various contact via structures may then be formed. The various contact via structures may include drain contact via structures (not shown) formed on the top surface of the corresponding drain region 63 in the memory array region 100. The various contact via structures may include layer contact via structures (86A, 86B, 86C) formed in the inter-array region 200, such as Figures 1A to 1E The layer contact via structures ( 86A, 86B, 86C) may include a first contact via structure 86A contacting the corresponding first conductive layer 146 , a second contact via structure 86B contacting the corresponding second conductive layer 246 , and a third contact via structure 86C contacting the corresponding third conductive layer 346 .

[0154] Common Reference Fig. 11B , Fig.11D and Fig.11E , when forming the backside trenches, the first backward stepped dielectric material portion 165 is not physically exposed to any of the backside trenches 79. In some embodiments, during the formation of the backside trenches 79 from the first subset of the backside trenches, the second backward stepped dielectric material portion (such as the second layer backward stepped dielectric material portion 265 and / or the third layer backward stepped dielectric material portion 365) is cut through, and the cut portion of the second backward stepped dielectric material portion is physically exposed to the first subset of the backside trenches, but not physically exposed to the second subset of the backside trenches. Therefore, each cut portion of the second backward stepped dielectric material portion (such as the second layer backward stepped dielectric material portion 265 and / or the third layer backward stepped dielectric material portion 365) can be physically exposed only to the corresponding first backside trench, but not to any other backside trenches other than the corresponding first backside trench.

[0155] In one embodiment, each of the first layer backward stepped dielectric material portions 165 may have a first width D1 along the second horizontal direction hd2 at the topmost surface, each of the second layer backward stepped dielectric material portions 265 may have a second width D2 along the second horizontal direction hd2 at the topmost surface, and each of the third layer backward stepped dielectric material portions 365 may have a third width D3 along the second horizontal direction hd2 at the topmost surface. The first width D1 is greater than the second width D2, and the second width D2 is greater than the third width D3.

[0156] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a multilayer memory device includes a substrate 8; and a plurality of layer structures at a multilayer level, the multilayer levels being spaced apart from the substrate 8 by different vertical spacings in a vertical direction. Each of the plurality of layer structures includes a backside trench filling structure 76, which extends laterally through each of the plurality of layer structures along a first horizontal direction hd1 and is laterally spaced apart from each other along a second horizontal direction hd2. Each of the plurality of layer structures also includes alternating stacks of insulating layers (132, 232, 332) and conductive layers (146, 246, 346), which are laterally spaced apart from each other along a second horizontal direction hd2 by the backside trench filling structure 76, and extend laterally through an inter-array region 200, a first memory array region 100A, and a second memory array region 100B along the first horizontal direction hd1 by the inter-array region 200, the second memory array region being laterally spaced apart from the first memory array region 100A along the first horizontal direction hd1 by the inter-array region 200. Each of the plurality of layer structures further comprises a memory opening filling structure 58 extending vertically through each of the plurality of layer structures. Each of the memory opening filling structures 58 comprises a vertical stack of a memory element (e.g., a portion of a charge storage region 54 of a memory film) at the level of a respective vertical semiconductor channel 60 and a conductive layer (146, 246, 346).

[0157] Each of the alternating stacks includes a stepped surface in the inter-array region 200. Each conductive layer (146, 246, 346) within the alternating stack has a respective bridging region 240 having a respective stripe width (E1, E2, E3) along the second horizontal direction hd2 within the inter-array region 200, and has a respective uniform width along the second horizontal direction hd2 that is greater than the stripe width in the first memory array region 100A, the second memory array region 100B, and the portion of the inter-array region 200 located outside the bridging region 240. The stripe width E1 of the topmost conductive layer 146 in the first layer of alternating stacks (132, 146) is less than the stripe width E2 of the topmost conductive layer 246 in the second layer of alternating stacks (232, 246) overlying the first layer of alternating stacks (132, 146).

[0158] exist FIG. 11A to FIG. 11D In some embodiments shown in , the stripe width E2 of the topmost conductive layer 246 in the second layer alternating stack (232, 246) is smaller than the stripe width E3 of the topmost conductive layer 346 in the third layer alternating stack (332, 346) overlying the second layer alternating stack (232, 246).

[0159] In one embodiment, each of the backside trench filling structures 76 includes a dielectric material portion extending continuously from the top surface of the substrate to the topmost surface of the plurality of layer structures. In one embodiment, each of the plurality of layer structures further includes a corresponding backward stepped dielectric material portion (165, 265, 365) that contacts the corresponding alternatingly stacked stepped surfaces in the inter-array region 200.

[0160] exist Fig. 11B and Fig.11E In some embodiments shown in FIG. 1 , a pair of first backward stepped dielectric material portions 165 are located at a first layer level and include a corresponding pair of bottommost surfaces that are laterally spaced apart from a first backside trench filling structure 761 of the backside trench filling structure 76 along a second horizontal direction hd2. A pair of second backward stepped dielectric material portions 265 are located at a second layer level overlying the first layer level and include a corresponding pair of bottommost surfaces that contact corresponding longitudinal sidewalls of the first backside trench filling structure 761.

[0161] exist Fig. 11B and Fig.11E In the embodiment shown in , each of the conductive layers 146 within the first layer alternating stack (132, 146) has a corresponding first bridging region 240A and a corresponding second bridging region 240B, the first bridging region having a first portion of the corresponding strip width E1, and the second bridging region having a second portion of the corresponding strip width E1. For example, if E3 is equal to width Y, then E2=2 / 3Y, E1=1 / 3Y, and the first and second portions of E1 are equal to 1 / 6Y (in the case where the first and second portions have equal widths). The first bridging region 240A is located between the first backside trench filling structure 761 and the second backside trench filling structure 762 of the trench filling structure 76 along the second horizontal direction hd2. The first first backside stepped dielectric material portion of the pair of first backside stepped dielectric material portions 165 (e.g., the left first backside stepped dielectric material portion) is located between the first bridging region and the second bridging region (761, 762) along the second horizontal direction hd2. In contrast, each of the conductive layers 246 within the second layer alternating stack (232, 246) has a bridging region 240A having a respective stripe width E2 between the first and second backside trench fill structures (761, 762) along the second horizontal direction hd2.

[0162] exist Fig. 11CIn an alternative embodiment, the second layer of the alternatingly stacked conductive layer 246 has separate bridge regions 240A and 240B, while the first layer of the alternatingly stacked conductive layer and the third layer of the alternatingly stacked conductive layer (146, 346) have a single bridge region 240A.

[0163] exist Fig.11D In an alternative embodiment, the first and second layers of the alternatingly stacked conductive layers (146, 246) have separate bridge regions 240A and 240B, while the third layer of the alternatingly stacked conductive layers 346 has a single bridge region 240A.

[0164] exist Fig. 11B and Fig.11E , each of the pair of second backward stepped dielectric material portions 265 contacts a respective longitudinal sidewall of the first backside trench filling structure 761 between a horizontal plane including the bottommost surface of the pair of second backward stepped dielectric material portions and a horizontal plane including the topmost surface of the pair of second backward stepped dielectric material portions. In contrast, each of the pair of first backward stepped dielectric material portions 165 is laterally spaced apart from the first backside trench filling structure 761 and does not contact the first backside trench filling structure.

[0165] exist Fig. 11B and Fig.11E In the embodiment shown in , the backside trench filling structure 76 includes a second backside trench filling structure 762 and a third backside trench filling structure 763, and the second backside trench filling structure and the third backside trench filling structure are the nearest adjacent backside trench filling structures of the first backside trench filling structure 761. Each first backside stepped dielectric material portion in the pair of first backside stepped dielectric material portions 165 does not contact the second backside trench filling structure 762 and the third backside trench filling structure 763, and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction hd2. Each second backside stepped dielectric material portion in the pair of second backside stepped dielectric material portions 265 does not contact the second backside trench filling structure 762 and the third backside trench filling structure 763, and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction hd2.

[0166] In one embodiment, a width D1 of one of the pair of first backward stepped dielectric material portions 165 along the second horizontal direction h2 is greater than a width D2 of one of the pair of second backward stepped dielectric material portions 265 along the second horizontal direction hd2.

[0167] In one embodiment, a pair of third backward stepped dielectric material portions 365 of the backward stepped dielectric material portions are located at a third level overlying the second level and include a corresponding pair of bottommost surfaces that are in direct contact with the first backside trench fill structure 761 .

[0168] In one embodiment, the layer contact via structure 86A extends vertically through the rear stepped dielectric material portion ( 165 , 265 , 365 ) and contacts a corresponding one of the conductive layers 146 .

[0169] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". In the present disclosure, embodiments using specific structures and / or configurations are exemplified, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A multi-layer memory device, comprising: substrate; and a plurality of layer structures at a multi-layer level, the multi-layer level being spaced apart from the substrate in a vertical direction by different vertical spacings, wherein each layer structure of the plurality of layer structures comprises: a backside trench-fill structure extending laterally through each of the plurality of layer structures along a first horizontal direction and laterally spaced apart from one another along a second horizontal direction; an alternating stack of insulating layers and conductive layers, the alternating stacks being laterally spaced apart from each other along the second horizontal direction by the backside trench fill structure, extending laterally along the first horizontal direction through an inter-array region, a first memory array region, and a second memory array region, the second memory array region being laterally spaced apart from the first memory array region along the first horizontal direction by the inter-array region; and a memory opening filling structure extending vertically through each of the plurality of layer structures, wherein each of the memory opening filling structures comprises a respective vertical semiconductor channel and a vertical stack of memory elements at the level of the conductive layer, in: Each of the alternating stacks comprises a stepped surface in the inter-array region; each conductive layer within the alternating stack has a respective bridging region having a respective stripe width along the second horizontal direction within the inter-array region and a respective uniform width along the second horizontal direction that is greater than the stripe width in the first memory array region, the second memory array region, and a portion of the inter-array region that is located outside the bridging region; and The stripe width of the topmost conductive layer in a first alternating stack of layers is smaller than the stripe width of the topmost conductive layer in a second alternating stack of layers overlying the first alternating stack of layers.

2. The multi-layer memory device according to claim 1, wherein: The stripe width of the topmost conductive layer in the second alternating stack of layers is smaller than the stripe width of the topmost conductive layer in a third alternating stack of layers overlying the second alternating stack of layers; and Each of the backside trench-fill structures includes a dielectric material portion extending continuously from a top surface of the substrate to a topmost surface of the plurality of layer structures.

3. The multi-layer memory device of claim 1, wherein each of the plurality of layer structures further comprises a corresponding backward stepped dielectric material portion contacting the stepped surface in the inter-array region.

4. The multi-layer memory device according to claim 3, wherein: a pair of first ones of the backward stepped dielectric material portions are located at a first layer level and include a respective pair of bottom-most surfaces that are laterally spaced apart from a first one of the backside trench-fill structures along the second horizontal direction; and A pair of second ones of the backward stepped dielectric material portions are located at a second level overlying the first level and include a respective pair of bottommost surfaces contacting respective longitudinal sidewalls of the first backside trench fill structure.

5. The multi-layer memory device according to claim 4, wherein: Each of the conductive layers within the first layer alternating stack has a respective first bridging region having a first portion of the respective strip width and a respective second bridging region having a second portion of the respective strip width; The first bridging region is located between the first backside trench filling structure and the second backside trench filling structure of the trench filling structure along the second horizontal direction; A first one of the pair of first backward stepped dielectric material portions is located between the first bridge region and the second bridge region along the second horizontal direction; and Each of the conductive layers within the second layer alternating stack has a bridging region having the respective stripe width between the first backside trench fill structure and the second backside trench fill structure along the second horizontal direction.

6. The multi-layer memory device according to claim 4, wherein: each of the pair of second backward stepped dielectric material portions contacts the respective longitudinal sidewall of the first backside trench fill structure between a horizontal plane including a bottommost surface of the pair of second backward stepped dielectric material portions and a horizontal plane including a topmost surface of the pair of second backward stepped dielectric material portions; and Each first backward stepped dielectric material portion of the pair of first backward stepped dielectric material portions is laterally spaced apart from, and does not contact, the first backside trench fill structure.

7. The multi-layer memory device according to claim 6, wherein: The backside trench filling structure comprises a second backside trench filling structure and a third backside trench filling structure, the second backside trench filling structure and the third backside trench filling structure being the nearest adjacent backside trench filling structures of the first backside trench filling structure; each first backward stepped dielectric material portion of the pair of first backward stepped dielectric material portions is not in contact with the second backside trench filling structure and the third backside trench filling structure and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction; and Each second backward stepped dielectric material portion of the pair of second backward stepped dielectric material portions is not in contact with the second backside trench filling structure and the third backside trench filling structure and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction.

8. A multilayer memory device according to claim 4, wherein the width of one of the pair of first backward stepped dielectric material portions along the second horizontal direction is greater than the width of one of the pair of second backward stepped dielectric material portions along the second horizontal direction.

9. A multilayer memory device according to claim 4, wherein a pair of third backward stepped dielectric material portions of the backward stepped dielectric material portion are located at a third level overlying the second level and include a corresponding pair of bottommost surfaces, which are in direct contact with the first backside trench filling structure.

10. The multi-layer memory device of claim 3, further comprising a layer contact via structure extending vertically through the backward stepped dielectric material portion and contacting a corresponding one of the conductive layers.

11. A method for forming a semiconductor device, the method comprising: forming a plurality of layer structures at a multi-layer level, the multi-layer level being spaced apart from the substrate in a vertical direction by different vertical spacings, wherein each of the plurality of layer structures comprises: an alternating stack of insulating layers and sacrificial material layers, the alternating stack extending laterally along the first horizontal direction through an inter-array region, a first memory array region, and a second memory array region, the second memory array region being laterally spaced from the first memory array region along the first horizontal direction by the inter-array region; and a memory opening filling structure extending vertically through each of the plurality of layer structures, wherein each of the memory opening filling structures comprises a respective vertical semiconductor channel and a vertical stack of memory elements at the level of the sacrificial material layer; forming a backside trench through the alternating stack of insulating layers and sacrificial material layers; replacing the sacrificial material layer with a conductive layer passing through the backside trenches to convert the alternating stack of insulating layers and sacrificial material layers into an alternating stack of insulating layers and conductive layers; and filling the backside trench with a backside trench fill structure that extends laterally through each of the plurality of layer structures along a first horizontal direction and is laterally spaced apart from one another along a second horizontal direction; in: The conductive layers are laterally spaced apart from each other along the second horizontal direction by the backside trench filling structure; each of said alternating stacks of insulating layers and conductive layers comprises a stepped surface in said inter-array region; each conductive layer within the alternating stack of insulating and conductive layers has a respective bridging region having a respective stripe width along the second horizontal direction within the inter-array region and having a respective uniform width along the second horizontal direction that is greater than the stripe width in the first memory array region, the second memory array region, and a portion of the inter-array region that is located outside the bridging region; and The stripe width of the topmost conductive layer in a first alternating stack of insulating and conductive layers is smaller than the stripe width of the topmost conductive layer in a second alternating stack of insulating and conductive layers overlying the first alternating stack of insulating and conductive layers.

12. The method according to claim 11, wherein: The stripe width of the topmost conductive layer in the second alternating stack of layers is smaller than the stripe width of the topmost conductive layer in a third alternating stack of layers overlying the second alternating stack of layers; and Each of the backside trench-fill structures includes a dielectric material portion extending continuously from a top surface of the substrate to a topmost surface of the plurality of layer structures.

13. The method of claim 11, further comprising forming respective backward stepped dielectric material portions contacting the stepped surface in the inter-array region.

14. The method according to claim 13, wherein: a pair of first ones of the backward stepped dielectric material portions are located at a first layer level and include a respective pair of bottom-most surfaces that are laterally spaced apart from a first one of the backside trench-fill structures along the second horizontal direction; and A pair of second ones of the backward stepped dielectric material portions are located at a second level overlying the first level and include a respective pair of bottommost surfaces contacting respective longitudinal sidewalls of the first backside trench fill structure.

15. The method according to claim 14, wherein: Each of the conductive layers within the first layer alternating stack has a respective first bridging region having a first portion of the respective strip width and a respective second bridging region having a second portion of the respective strip width; The first bridging region is located between the first backside trench filling structure and the second backside trench filling structure of the trench filling structure along the second horizontal direction; A first one of the pair of first backward stepped dielectric material portions is located between the first bridge region and the second bridge region along the second horizontal direction; and Each of the conductive layers within the second layer alternating stack has a bridging region having the respective stripe width between the first backside trench fill structure and the second backside trench fill structure along the second horizontal direction.

16. The method of claim 14, wherein: each of the pair of second backward stepped dielectric material portions contacts the respective longitudinal sidewall of the first backside trench fill structure between a horizontal plane including a bottommost surface of the pair of second backward stepped dielectric material portions and a horizontal plane including a topmost surface of the pair of second backward stepped dielectric material portions; and Each first backward stepped dielectric material portion of the pair of first backward stepped dielectric material portions is laterally spaced apart from, and does not contact, the first backside trench fill structure.

17. The method of claim 16, wherein: The backside trench filling structure comprises a second backside trench filling structure and a third backside trench filling structure, the second backside trench filling structure and the third backside trench filling structure being the nearest adjacent backside trench filling structures of the first backside trench filling structure; each first backward stepped dielectric material portion of the pair of first backward stepped dielectric material portions is not in contact with the second backside trench filling structure and the third backside trench filling structure and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction; and Each second backward stepped dielectric material portion of the pair of second backward stepped dielectric material portions is not in contact with the second backside trench filling structure and the third backside trench filling structure and is laterally spaced apart from the second backside trench filling structure and the third backside trench filling structure along the second horizontal direction.

18. The method of claim 14, wherein a width of one of the pair of first backward stepped dielectric material portions along the second horizontal direction is greater than a width of one of the pair of second backward stepped dielectric material portions along the second horizontal direction.

19. The method of claim 14, wherein a pair of third backward stepped dielectric material portions of the backward stepped dielectric material portion are located at a third level overlying the second level and include a corresponding pair of bottommost surfaces that are in direct contact with the first backside trench fill structure.

20. The method of claim 13, further comprising forming a layer contact via structure that passes through the rear stepped dielectric material portion and contacts a corresponding one of the conductive layers.

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