A chip trimming function test method, device, equipment and medium

Abstract

The application discloses a chip trimming function test method, device, equipment and medium, and relates to the technical field of chip testing. The method is applied to an automatic test equipment, and comprises the following steps: a general input / output interface is configured for a chip to be tested; a chip test mode is executed according to a test signal in the general input / output interface, and serial data sent by the automatic test equipment is acquired; a data flow direction of the serial data is determined according to a preset data format, and the serial data is written into a trimming register based on the data flow direction. Through the technical scheme, the test method can be simplified, and the test time can be shortened.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip tuning function testing method, apparatus, equipment, and medium. Background Technology

[0002] With the rapid development of the integrated circuit industry, the requirements for chip testing are becoming increasingly stringent. How to complete chip testing more quickly and accurately is an issue that must be considered during testing. Currently, when performing Trim (trimming) related tests on ATE (Automatic Test Equipment) machines after chip fabrication, writing Trim data to the Trim register through various communication protocols is too cumbersome and increases the time cost of testing.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a chip tuning function testing method, apparatus, device, and medium, which can simplify the testing process and shorten the testing time. The specific solution is as follows:

[0005] In a first aspect, this application discloses a chip tuning function testing method, applied to automated testing equipment, comprising:

[0006] Configure a general-purpose input / output interface for the chip under test;

[0007] The chip test mode is executed according to the test signals in the general input / output interface, and the serial data sent by the automated test equipment is acquired.

[0008] The data flow direction of the serial data is determined according to a preset data format, and the serial data is written into the trim register based on the data flow direction.

[0009] Optionally, configuring a general-purpose input / output interface for the chip under test includes:

[0010] A first general-purpose input / output interface is configured for the chip under test; the first general-purpose input / output interface is used to provide a reference clock signal for the automated test equipment and the chip under test.

[0011] Configure a second general-purpose input / output interface for the chip under test; the second general-purpose input / output interface is used to provide test data signals;

[0012] A third general-purpose input / output interface is configured for the chip under test; the third general-purpose input / output interface is used to provide an enable signal for the chip's test mode.

[0013] Configure a fourth general-purpose input / output interface for the chip under test; the fourth general-purpose input / output interface is used to provide an indication signal to the tuning register as to whether to store data in memory.

[0014] Optionally, the step of executing the chip test mode based on the test signal in the general input / output interface includes:

[0015] If the enable signal corresponding to the third general-purpose input / output interface is detected to be high, the chip test mode is triggered.

[0016] Accordingly, after writing the serial data into the trimming register based on the data flow direction, the method further includes:

[0017] When the serial data is successfully written to the trim register, the enable signal corresponding to the third general-purpose input / output interface is pulled low.

[0018] Optionally, the chip tuning function test method further includes:

[0019] Set the flag bit for the first preset byte length, the data bits for the second preset byte length, and the address bits for the third preset byte length, respectively;

[0020] The preset data format is determined sequentially from the highest bit through the flag bit, the data bit, and the address bit.

[0021] Optionally, determining the data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction, includes:

[0022] The data flow direction of the serial data is determined according to a preset data format. When the value corresponding to the flag bit meets the preset condition, the serial data is written into the trim register based on the data flow direction.

[0023] Optionally, after determining the data flow direction of the serial data according to a preset data format and writing the serial data into the trimming register based on the data flow direction, the method further includes:

[0024] Determine whether there is a storage instruction that writes the data in the trim register into the memory;

[0025] When the storage instruction is present, the indicator signal corresponding to the fourth general-purpose input / output interface is pulled high.

[0026] Optionally, the chip tuning function test method further includes:

[0027] Monitor whether there are any trim registers pending operation;

[0028] If the trim register to be operated exists, then for the trim register to be operated, jump back to the step of executing the chip test mode according to the test signal in the general input / output interface, until all data is written to the trim register to be operated.

[0029] Secondly, this application discloses a chip tuning function testing device, applied to automated testing equipment, comprising:

[0030] The interface configuration module is used to configure general input / output interfaces for the chip under test.

[0031] The test execution module is used to execute the chip test mode according to the test signals in the general input / output interface, and to acquire the serial data sent by the automated test equipment;

[0032] The data storage module is used to determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction.

[0033] Thirdly, this application discloses an electronic device, which includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the chip tuning function test method as described above.

[0034] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the chip tuning function testing method as described above.

[0035] This application provides a chip tuning function testing method, applied to an automated testing device, comprising: configuring a general-purpose input / output interface for the chip under test; executing a chip test mode according to a test signal in the general-purpose input / output interface, and acquiring serial data sent by the automated testing device; determining the data flow direction of the serial data according to a preset data format, and writing the serial data into a tuning register based on the data flow direction.

[0036] The beneficial technical effects of this application are as follows: By configuring a general-purpose input / output interface through automated test equipment to generate corresponding input stimuli, the test data sent by the automated test equipment can be directly written into the corresponding register group of the chip, simplifying the write operation of the automated test equipment to the internal registers during testing. In addition, using a general-purpose input / output interface does not have strict requirements on clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0037] In addition, the chip tuning function testing apparatus, equipment and storage medium provided in this application correspond to the above-mentioned chip tuning function testing method and have the same effect. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is a flowchart of a chip tuning function testing method disclosed in this application;

[0040] Figure 2 This is a timing diagram of a testing process disclosed in this application;

[0041] Figure 3 This is a timing diagram of a testing process disclosed in this application;

[0042] Figure 4 This is a schematic diagram of a chip tuning function test architecture disclosed in this application;

[0043] Figure 5 This is a schematic diagram of a chip tuning function test process disclosed in this application;

[0044] Figure 6 This is a schematic diagram of the structure of a chip adjustment function testing device disclosed in this application;

[0045] Figure 7 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] After chip fabrication, during Trim testing on an ATE (Automatic Test Equipment) machine, the test data from the current GPIO (General-Purpose I / O ports) cannot be saved for use in the next ATE test. Therefore, the previous test data is written to the corresponding register. Current market solutions involve writing data to registers using various communication protocols, such as I2C (Integrated Circuit) protocol (a two-wire protocol using SCL (Serial Clock) and SDA (Serial Data) lines), and SPI (Serial Peripheral Interface) protocol (a four-wire protocol using SCLK clock line, CS (Chip Select), MOSI (Master Output / Slave Input), and MISO (Master Input / Slave Output) lines). Alternatively, data can be stored in memory using BIST (Built-in Self-Test) mode, and then loaded into the trim register via power-down and power-on cycles.

[0048] When writing to the trim register using a communication protocol, the ATE (Automatic Equipment) device needs to strictly adhere to the various requirements of the communication protocol itself to generate the correct stimuli, such as the conditions for starting and ending communication, and the timing requirements during communication. Clearly, writing to the trim register using I2C / SPI is somewhat complex for ATE devices.

[0049] For writing to the trim register using the BIST method, the ATE equipment needs to generate a test signal, and then the chip decodes the signal and stores the data in memory. Note that this is storing the data in memory, not directly writing it into the trim register. This requires powering down the chip and then powering it back on to load the data into the trim register, which is undoubtedly more cumbersome and increases the time cost of testing.

[0050] Therefore, this application provides a chip tuning function testing scheme that can simplify the testing process and shorten the testing time.

[0051] This invention discloses a chip tuning function testing method, see [link to relevant documentation]. Figure 1 As shown, applied to automated testing equipment, the method includes:

[0052] Step S11: Configure a general-purpose input / output interface for the chip under test.

[0053] In this embodiment, GPIO is configured on the ATE (Automatic Test Equipment) machine to generate corresponding input stimuli. In one specific implementation, four GPIO interfaces are configured and used. Specifically, these include:

[0054] A first general-purpose input / output interface is configured for the chip under test; the first general-purpose input / output interface is used to provide a reference clock signal for the automated test equipment and the chip under test.

[0055] Configure a second general-purpose input / output interface for the chip under test; the second general-purpose input / output interface is used to provide test data signals;

[0056] A third general-purpose input / output interface is configured for the chip under test; the third general-purpose input / output interface is used to provide an enable signal for the chip's test mode.

[0057] Configure a fourth general-purpose input / output interface for the chip under test; the fourth general-purpose input / output interface is used to provide an indication signal to the tuning register as to whether to store data in memory.

[0058] Table 1 shows the test signals and functional descriptions for the four GPIO interfaces:

[0059] Table 1

[0060]

[0061] Step S12: Execute the chip test mode according to the test signal in the general input / output interface, and acquire the serial data sent by the automated test equipment.

[0062] In this embodiment, when the ATE tester pulls Ten high, it enters the chip test mode. Specifically, if the enable signal corresponding to the third general-purpose input / output interface is detected to be high, the chip test mode is triggered. It should be noted that after entering the chip test mode, a Tclk reference clock signal is provided. The clock rate is not critical and can be arbitrarily selected.

[0063] For example, such as Figure 2 , Figure 3 The diagram shown is a timing illustration based on the GPIO interface. Specifically, in... Figure 2 In this context, `Data_in` and `addr_in` are the address and data to be input into the chip, which are converted to `Tdata`; `data_o` and `addr_o` are the data obtained after decoding by the chip. When `Ten` becomes 0, `R` is cleared, and the function will be reset. Figure 3 In the diagram, when unlock becomes 1, the data is automatically written to the memory. As shown in the diagram, during the period when the enable signal Ten is high, the test data signal Tdata transmits data based on the rising and falling edges provided by the reference clock signal Tclk, and there are no strict timing requirements.

[0064] Step S13: Determine the data flow direction of the serial data according to the preset data format, and write the serial data into the trimming register based on the data flow direction.

[0065] In this embodiment, the ATE transmits serial test data, which is transmitted according to the data flow direction. The data flow direction is determined based on a preset data format, and the ATE must adhere to this preset data format when transmitting serial data.

[0066] In one specific implementation, the process of determining the preset data format includes: setting a flag bit of a first preset byte length, a data bit of a second preset byte length, and an address bit of a third preset byte length; and determining the preset data format sequentially through the flag bit, the data bit, and the address bit, starting from the most significant bit.

[0067] Table 2 shows the preset data format, where the bits from the highest bit are 1 bit flag R, N bits data S, and M bits address T.

[0068] Table 2

[0069]

[0070] Here, the flag bit R is used to indicate the start of data transmission. It should be noted that after determining the data flow direction of the serial data according to the preset data format, the step of writing the serial data into the trim register based on the data flow direction can only be triggered if the value corresponding to the flag bit meets a preset condition. For example, the value of the R bit must be 1, representing the start of data transmission. For the receiver, when the highest bit of the register group receives this flag bit signal, the data will be locked until the Ten signal is invalidated and unlocked. That is, the data in the R bit represents the start (for ATE) / end (for the chip). In this way, the automatic locking of the R bit can effectively prevent data flow chaos.

[0071] The data bit S represents the data to be written to the trim register; the address bit T represents the address of the trim register.

[0072] Furthermore, when writing the serial data into the trim register based on the data flow direction, the data flow direction is: R->S most significant bit…->S least significant bit->T most significant bit…->T least significant bit. For example… Figure 4 The diagram shows the architecture of the ATE machine's write operation to the internal registers / memory during testing.

[0073] It should be noted that Ten is pulled low after the data is successfully written to the trim register. Specifically, when the serial data is successfully written to the trim register, the enable signal corresponding to the third general purpose input / output interface is pulled low.

[0074] In this embodiment, the aforementioned steps are repeated for all trim registers that need to be operated on until all trim registers that need to be operated on are written. Specifically, it is monitored whether there are trim registers to be operated on; if there are trim registers to be operated on, then for the trim registers to be operated on, the process jumps back to the step of executing the chip test mode according to the test signal in the general input / output interface until all trim registers to be operated on are written with data.

[0075] In another feasible implementation, if it is necessary to write the data in the trim register into memory, the unlock signal can be pulled high; otherwise, this step is not performed. Specifically, it is determined whether a storage instruction to write the data in the trim register into memory exists; if the storage instruction exists, the indicator signal corresponding to the fourth general-purpose input / output interface is pulled high. In this way, the memory write operation of the ATE equipment during testing can be simplified.

[0076] like Figure 5 The diagram illustrates the chip trimming function test steps. The process begins with ATM (Analog Test Mode) testing. Data from the ATM test mode is then directly written to the corresponding Trim registers via GPIO ports. During this process, all registers requiring operation are checked until all necessary Trim registers have been written. If it's necessary to write the data from the Trim registers to memory, the unlock button is pulled high; otherwise, this step is skipped. The process then ends.

[0077] This application provides a chip tuning function testing method, applied to an automated testing device, comprising: configuring a general-purpose input / output interface for the chip under test; executing a chip test mode according to a test signal in the general-purpose input / output interface, and acquiring serial data sent by the automated testing device; determining the data flow direction of the serial data according to a preset data format, and writing the serial data into a tuning register based on the data flow direction.

[0078] The beneficial technical effects of this application are as follows: By configuring a general-purpose input / output interface through automated test equipment to generate corresponding input stimuli, the test data sent by the automated test equipment can be directly written into the corresponding register group of the chip, simplifying the write operation of the automated test equipment to the internal registers during testing. In addition, using a general-purpose input / output interface does not have strict requirements on clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0079] Accordingly, this application also discloses a chip tuning function testing device, applied to automated testing equipment, see [link to relevant documentation]. Figure 6 As shown, the device includes:

[0080] Interface configuration module 11 is used to configure a general input / output interface for the chip under test;

[0081] The test execution module 12 is used to execute the chip test mode according to the test signals in the general input / output interface and to acquire the serial data sent by the automated test equipment;

[0082] The data storage module 13 is used to determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction.

[0083] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0084] Therefore, the above-described solution in this embodiment, when applied to an automated testing device, includes: configuring a general-purpose input / output interface for the chip under test; executing a chip testing mode according to the test signal in the general-purpose input / output interface, and acquiring serial data sent by the automated testing device; determining the data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction.

[0085] The beneficial technical effects of this application are as follows: By configuring a general-purpose input / output interface through automated test equipment to generate corresponding input stimuli, the test data sent by the automated test equipment can be directly written into the corresponding register group of the chip, simplifying the write operation of the automated test equipment to the internal registers during testing. In addition, using a general-purpose input / output interface does not have strict requirements on clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0086] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0087] Figure 7 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip tuning function testing method disclosed in any of the foregoing embodiments.

[0088] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0089] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it can include an operating system 221, computer programs 222, and data 223, etc. The data 223 can include various types of data. The storage method can be temporary storage or permanent storage.

[0090] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the chip tuning function test method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.

[0091] Furthermore, this application also discloses a computer-readable storage medium, which includes random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. The computer program, when executed by a processor, implements the aforementioned chip tuning function testing method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0092] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0093] The steps of the chip tuning function testing method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0094] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0095] The present invention has provided a detailed description of a chip tuning function testing method, apparatus, device, and medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for testing chip tuning functions, characterized in that, Applications in automated testing equipment, including: Configure a general-purpose input / output interface for the chip under test; The chip test mode is executed according to the test signals in the general input / output interface, and the serial data sent by the automated test equipment is acquired. The data flow direction of the serial data is determined according to a preset data format, and the serial data is written into the trimming register based on the data flow direction; The configuration of general-purpose input / output interfaces for the chip under test includes: A first general-purpose input / output interface is configured for the chip under test; the first general-purpose input / output interface is used to provide a reference clock signal for the automated test equipment and the chip under test. Configure a second general-purpose input / output interface for the chip under test; the second general-purpose input / output interface is used to provide test data signals; A third general-purpose input / output interface is configured for the chip under test; the third general-purpose input / output interface is used to provide an enable signal for the chip's test mode. A fourth general-purpose input / output interface is configured for the chip under test; the fourth general-purpose input / output interface is used to provide an indication signal to the tuning register as to whether to store data in memory; The step of executing the chip test mode based on the test signal in the general input / output interface includes: If the enable signal corresponding to the third general-purpose input / output interface is detected to be high, the chip test mode is triggered. Accordingly, after writing the serial data into the trim register based on the data flow direction, the method further includes: when the serial data is successfully written into the trim register, pulling the enable signal corresponding to the third general-purpose input / output interface low; The chip tuning function test method also includes: Set the flag bit for the first preset byte length, the data bits for the second preset byte length, and the address bits for the third preset byte length, respectively; The preset data format is determined sequentially from the highest bit through the flag bit, the data bit, and the address bit; Determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction, including: The data flow direction of the serial data is determined according to the preset data format. When the value corresponding to the flag bit meets the preset condition, the data starts to be sent. The serial data is written into the trim register based on the data flow direction. After the highest bit of the trim register receives the flag bit, it locks the data until the enable signal becomes invalid and unlocks it.

2. The chip tuning function testing method according to claim 1, characterized in that, After determining the data flow direction of the serial data according to a preset data format, and writing the serial data into the trimming register based on the data flow direction, the method further includes: Determine whether there is a storage instruction that writes the data in the trim register into the memory; When the storage instruction is present, the indicator signal corresponding to the fourth general-purpose input / output interface is pulled high.

3. The chip tuning function testing method according to claim 1 or 2, characterized in that, Also includes: Monitor whether there are any trim registers pending operation; If the trim register to be operated exists, then for the trim register to be operated, jump back to the step of executing the chip test mode according to the test signal in the general input / output interface, until all data is written to the trim register to be operated.

4. A chip adjustment function testing device, characterized in that, Applications in automated testing equipment, including: The interface configuration module is used to configure general input / output interfaces for the chip under test. The test execution module is used to execute the chip test mode according to the test signals in the general input / output interface, and to acquire the serial data sent by the automated test equipment; The data storage module is used to determine the data flow direction of the serial data according to a preset data format, and to write the serial data into the trimming register based on the data flow direction. The interface configuration module is specifically used for: A first general-purpose input / output interface is configured for the chip under test; the first general-purpose input / output interface is used to provide a reference clock signal for the automated test equipment and the chip under test. Configure a second general-purpose input / output interface for the chip under test; the second general-purpose input / output interface is used to provide test data signals; A third general-purpose input / output interface is configured for the chip under test; the third general-purpose input / output interface is used to provide an enable signal for the chip's test mode. A fourth general-purpose input / output interface is configured for the chip under test; the fourth general-purpose input / output interface is used to provide an indication signal to the tuning register as to whether to store data in memory; The test execution module is specifically used for: If the enable signal corresponding to the third general-purpose input / output interface is detected to be high, the chip test mode is triggered. Correspondingly, the chip trimming function testing device further includes: after writing the serial data into the trimming register based on the data flow direction, when the serial data is successfully written into the trimming register, pulling down the enable signal corresponding to the third general-purpose input / output interface; A flag bit of a first preset byte length, a data bit of a second preset byte length, and an address bit of a third preset byte length are set respectively; the preset data format is determined sequentially through the flag bit, the data bit, and the address bit, starting from the most significant bit; The data storage module is specifically used for: The data flow direction of the serial data is determined according to the preset data format. When the value corresponding to the flag bit meets the preset condition, the data starts to be sent. The serial data is written into the trim register based on the data flow direction. After the highest bit of the trim register receives the flag bit, it locks the data until the enable signal becomes invalid and unlocks it.

5. An electronic device, characterized in that, The electronic device includes a processor and a memory; wherein the memory is used to store a computer program, which is loaded and executed by the processor to implement the chip tuning function test method as described in any one of claims 1 to 3.

6. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein the computer program, when executed by a processor, implements the chip tuning function test method as described in any one of claims 1 to 3.

Images