Voltage configuration algorithm verification method, device and electronic equipment

Abstract

The present application discloses a method, device and electronic device for verifying a voltage configuration algorithm, the method comprising: obtaining multiple reference voltages of a voltage configuration algorithm deployed by a memory chip; determining a target voltage from the multiple reference voltages; adjusting a signal value corresponding to a portion of a time period in a first signal according to the target voltage and the multiple reference voltages to obtain a second signal; obtaining a standard voltage determined by the voltage configuration algorithm from the multiple reference voltages according to the second signal; obtaining a verification result according to the standard voltage and the target voltage, the verification result indicating whether the voltage configuration algorithm is accurate.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device and electronic device for verifying a voltage configuration algorithm. Background Art

[0002] At present, a voltage configuration algorithm can be used to select a suitable standard voltage for a memory chip from multiple candidate voltages. The standard voltage can be represented by VREF (Voltage reference). Memory chips can use the standard voltage to convert between analog signals and digital signals.

[0003] However, in a simulation environment, different reference voltages will not change the eye width of the signal fed back by the simulation model of the memory particle. Therefore, the voltage configuration algorithm in the simulation environment cannot obtain the eye width, and cannot select the standard voltage, and cannot verify the accuracy of the voltage configuration algorithm.

[0004] Therefore, at present we can only rely on the memory particle chip itself to verify whether the voltage configuration algorithm is accurate. Summary of the invention

[0005] In view of this, the present application provides a method, device and electronic device for verifying a voltage configuration algorithm, as follows:

[0006] A method for verifying a voltage configuration algorithm, comprising:

[0007] Obtain multiple reference voltages of a voltage configuration algorithm deployed by a memory chip;

[0008] determining a target voltage from among the plurality of reference voltages;

[0009] According to the target voltage and the multiple reference voltages, adjusting the signal value corresponding to a part of the time period in the first signal to obtain a second signal;

[0010] Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

[0011] A verification result is obtained according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate.

[0012] The above method preferably adjusts the signal value corresponding to a part of the time period in the first signal according to the target voltage and the multiple reference voltages to obtain the second signal, including:

[0013] Obtaining a voltage difference between each of the reference voltages and the target voltage;

[0014] According to the voltage difference, the signal value corresponding to a part of the time period in the first signal is adjusted to obtain the second signal.

[0015] The above method preferably adjusts the signal value corresponding to a part of the time period in the first signal according to the voltage difference, including:

[0016] Using the sampling coefficient corresponding to the memory particle, the absolute value corresponding to the voltage difference is processed to obtain a first time period;

[0017] The signal value corresponding to the first time period in the first signal is adjusted to a preset target value to obtain a second signal.

[0018] The above method preferably adjusts the signal value corresponding to a part of the time period in the first signal according to the target voltage and the multiple reference voltages to obtain the second signal, including:

[0019] Obtaining a voltage difference between each of the reference voltages and the target voltage;

[0020] Obtaining a third signal according to the voltage difference;

[0021] The third signal is bitwise ANDed with the first signal to obtain a second signal.

[0022] In the above method, preferably, the signal value corresponding to the second time period in the third signal is a preset target value;

[0023] The second period is obtained by:

[0024] The absolute value corresponding to the voltage difference is processed using the sampling coefficient corresponding to the memory particle to obtain a second time period.

[0025] The above method, preferably, obtains a verification result according to the standard voltage and the target voltage, including:

[0026] Comparing the standard voltage with the target voltage;

[0027] If the standard voltage is consistent with the target voltage, obtaining a verification result indicating that the voltage configuration algorithm is accurate;

[0028] If the standard voltage is inconsistent with the target voltage, a verification result indicating that the voltage configuration algorithm is inaccurate is obtained.

[0029] In the above method, preferably, the voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the multiple reference voltages according to the eye width parameter;

[0030] The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

[0031] The above method preferably obtains multiple reference voltages of the voltage configuration algorithm, including:

[0032] Through the backdoor method, at each rising edge of the clock signal, the voltage configuration parameters corresponding to the voltage configuration algorithm are read, and the voltage configuration parameters include the reference voltage corresponding to the rising edge.

[0033] A verification device for a voltage configuration algorithm, comprising:

[0034] A reference obtaining unit, used to obtain multiple reference voltages of a voltage configuration algorithm deployed by a memory particle;

[0035] a target determination unit, configured to determine a target voltage from among the plurality of reference voltages;

[0036] A signal obtaining unit, configured to adjust a signal value corresponding to a part of the time periods in the first signal according to the target voltage and the multiple reference voltages, so as to obtain a second signal;

[0037] a signal processing unit, configured to obtain a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

[0038] The algorithm verification unit is used to obtain a verification result according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate.

[0039] An electronic device, comprising:

[0040] A memory, used to store a computer program and data generated by the execution of the computer program;

[0041] A processor, configured to execute the computer program to implement:

[0042] Obtain multiple reference voltages of a voltage configuration algorithm deployed by a memory chip;

[0043] determining a target voltage from among the plurality of reference voltages;

[0044] According to the target voltage and the multiple reference voltages, adjusting the signal value corresponding to a part of the time period in the first signal to obtain a second signal;

[0045] Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

[0046] A verification result is obtained according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate.

[0047] A computer-readable storage medium stores a computer program / instruction, which implements the steps of the above-mentioned voltage configuration algorithm verification method when executed by a processor.

[0048] A computer program product comprises a computer program / instruction, which implements the steps of the verification method of the voltage configuration algorithm when executed by a processor.

[0049] It can be seen from the above technical scheme that in a voltage configuration algorithm verification method, device and electronic device disclosed in the present application, after obtaining multiple reference voltages of the voltage configuration algorithm deployed by the memory particles, the signal provided to the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltage and each other reference voltage. In this way, the signal used by the voltage configuration algorithm can be actively changed, and then the voltage configuration algorithm can select a standard voltage from the reference voltage according to these different signals, and then the verification result characterizing whether the voltage configuration algorithm is accurate can be obtained according to the standard voltage and the target voltage. This process does not rely on the memory particles themselves, but can perform algorithm verification in advance in the design stage of the memory particles, and promptly discover problems with the algorithm, thereby improving the reliability of the verification. Moreover, since the algorithm verification does not rely on the memory particles themselves, it will not be affected by the natural environment, thereby improving the accuracy of the verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0051] Figure 1 A flowchart of a method for verifying a voltage configuration algorithm provided in an embodiment of the present application;

[0052] Figure 2 This is an example diagram of determining a standard voltage by using a voltage configuration algorithm by generating a second signal in an embodiment of the present application;

[0053] Figure 3 Another example diagram of determining a standard voltage by using a voltage configuration algorithm by generating a second signal in an embodiment of the present application;

[0054] Figure 4 Another example diagram of determining a standard voltage by using a voltage configuration algorithm by generating a second signal in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of a verification device for a voltage configuration algorithm provided in an embodiment of the present application;

[0056] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0057] Figure 7 A flowchart for verifying the voltage configuration algorithm in the scenario where this application is applicable to LPDDR5;

[0058] Figure 8 This is an example diagram of adjusting the signal eye width in the scenario where the present application is applicable to LPDDR5. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] refer to Figure 1 As shown, it is a flow chart of the implementation of a verification method of a voltage configuration algorithm provided in an embodiment of the present application. The method can be applied to electronic devices that can be connected to the simulation model corresponding to the memory particles and can perform data processing, such as computers or servers, etc. The memory particles here can be low-power memory LPDDR5 (Low Power Double Data Rate 5) memory particles, which have a voltage configuration algorithm CBT training (command bus training), which can be applied to the selection of various VREFs, such as the VREF of the command bus CA (Command Address), namely CA VREF, and the VREF of the data bus DQ (Data Bus), namely DQ VREF. The technical solution in this embodiment is mainly used to improve the accuracy and reliability of verifying the voltage configuration algorithm without relying on the memory particles themselves.

[0061] Specifically, the method in this embodiment may include the following steps:

[0062] Step 101: Obtain multiple reference voltages of a voltage configuration algorithm deployed by a memory chip.

[0063] In this embodiment, a backdoor method such as backdoor can be used to read the voltage configuration parameters corresponding to the voltage configuration algorithm at each rising edge of the clock signal, and the voltage configuration parameters include the reference voltage corresponding to the rising edge. The reference voltage in the voltage configuration parameters is used by the voltage configuration algorithm to determine the standard voltage of CA or the standard voltage of DQ. For example, the voltage configuration algorithm can configure multiple reference voltages, and the voltage configuration algorithm selects a suitable reference voltage from the multiple reference voltages as the standard voltage.

[0064] Step 102: Determine a target voltage from a plurality of reference voltages.

[0065] The target voltage may be a voltage randomly selected from a plurality of reference voltages, or the target voltage may be an intermediate value selected from a plurality of reference voltages. The target voltage may be represented by GV or golden VREF, which stands for golden Voltage reference.

[0066] Step 103: According to the target voltage and a plurality of reference voltages, the signal value corresponding to a part of the time period in the first signal is adjusted to obtain a second signal.

[0067] The first signal refers to a CA signal or a DQ signal input to a memory chip.

[0068] It should be noted that, in this embodiment, for each reference voltage, according to the reference voltage and the target voltage, the signal value corresponding to a part of the time period in the first signal can be adjusted, so as to achieve the purpose of changing the signal eye width of the first signal multiple times, and then obtain multiple corresponding second signals. The obtained second signals correspond to each reference voltage different from the target voltage.

[0069] For example, Figure 2 As shown in , the voltage configuration algorithm can configure n reference voltages: V1 to Vn. In this embodiment, one is selected as the target voltage, such as V3 is selected as GV. Then, for each reference voltage from V1 to Vn, the signal value of a part of the time period in the first signal is adjusted respectively. In this way, based on different reference voltages, the signal eye widths of different second signals obtained are different, and then through these multiple second signals, the eye width change of the analog signal is changed.

[0070] Step 104: Obtain a standard voltage determined by a voltage configuration algorithm from a plurality of reference voltages according to the second signal.

[0071] In this embodiment, the second signal can be captured by a simulation model corresponding to the memory chip, and a voltage configuration algorithm can be used to determine a standard voltage from a plurality of reference voltages according to the second signal.

[0072] Specifically, in step 104, the second signal may be transmitted to a simulation model corresponding to the memory chip, and the simulation model is used to capture the second signal and determine the standard voltage from a plurality of reference voltages according to the second signal through a voltage configuration algorithm.

[0073] In one implementation, the simulation model can obtain the eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage through a voltage configuration algorithm, and determine the standard voltage from multiple reference voltages according to the eye width parameter. Figure 2 For example, in this embodiment, one is selected as the target voltage, such as V3 is selected as GV, and then, multiple second signals are obtained for each reference voltage from V1 to Vn, respectively. These second signals are adjusted based on different reference voltages, so the signal eye widths of these second signals are different. Therefore, these second signals are transmitted to the simulation model in sequence, thereby simulating the eye width changes of the signals to the simulation model. Based on this, the simulation model performs eye width detection on the second signals captured in sequence, and then obtains the eye width parameter (signal eye width) of each second signal, that is, the eye width parameter corresponding to each reference voltage. Therefore, the voltage configuration algorithm can select a standard voltage from these reference voltages according to the size of the signal eye width of the eye width parameter. The standard voltage may be V3 in the reference voltage, or it may be other voltages in the reference voltage.

[0074] The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters of the second signal corresponding to all the reference voltages.

[0075] Specifically, after capturing the second signal, the simulation model provides the second signal to the voltage configuration algorithm. The voltage configuration algorithm identifies the eye width parameter corresponding to the second signal, that is, the eye width parameter corresponding to the reference voltage corresponding to the second signal, specifically the signal eye width of the second signal. Therefore, each time the simulation model captures a second signal, the voltage configuration algorithm performs an eye width identification to obtain the eye width parameter corresponding to the second signal. Based on this, the voltage configuration algorithm determines the standard voltage from multiple reference voltages according to the eye width parameter identified for each second signal.

[0076] In one implementation, the voltage configuration algorithm may determine, from among a plurality of reference voltages, a reference voltage corresponding to the second signal having the largest signal eye width as the standard voltage.

[0077] For example, Figure 2 As shown in , the voltage configuration algorithm in the simulation model selects a reference voltage with the largest corresponding signal eye width from V1 to Vn, such as V2 or V3, and uses it as the standard voltage.

[0078] Step 105: Obtain a verification result based on the standard voltage and the target voltage, where the verification result indicates whether the voltage configuration algorithm is accurate.

[0079] In one implementation, in this embodiment, the standard voltage may be compared with the target voltage, and then a verification result may be obtained based on the comparison result.

[0080] Specifically, if the standard voltage is consistent with the target voltage, it indicates that the voltage configuration algorithm can accurately identify the signal eye width and select the standard voltage according to the signal eye width, then a verification result representing the accuracy of the voltage configuration algorithm can be obtained; if the standard voltage is inconsistent with the target voltage, it indicates that the voltage configuration algorithm cannot accurately identify the signal eye width or cannot accurately select the standard voltage according to the signal eye width, then a verification result representing the inaccuracy of the voltage configuration algorithm can be obtained.

[0081] For example, in this embodiment, the voltage difference between the reference voltage and the target voltage is used to change the signal value of the CA signal provided to the simulation model in a certain period of time, thereby changing the signal eye width of the CA signal, thereby simulating the eye width change process of the CA signal, thereby determining whether the voltage configuration algorithm CBT training can accurately determine the correct standard voltage based on whether the standard voltage determined by the voltage configuration algorithm CBT training is consistent with the target voltage, thereby realizing the verification of the voltage configuration algorithm CBT training, and this verification process does not rely on the LPDDR5 memory particles themselves. Figure 2 Taking the shown example, if the voltage configuration algorithm determines that V3 is the standard voltage, then it is consistent with GV, and it can be determined that the voltage configuration algorithm can accurately determine the correct standard voltage; if the voltage configuration algorithm determines that V2 is the standard voltage, then it is inconsistent with GV, and it can be determined that the voltage configuration algorithm cannot accurately determine the correct standard voltage.

[0082] It can be seen from the above technical solution that in a verification method of a voltage configuration algorithm provided in an embodiment of the present application, after obtaining multiple reference voltages of the voltage configuration algorithm deployed by the memory particles, the signal provided to the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltage and each other reference voltage. In this way, the signal used by the voltage configuration algorithm can be actively changed, and then the voltage configuration algorithm can select a standard voltage from the reference voltage according to these different signals, and then the verification result characterizing whether the voltage configuration algorithm is accurate can be obtained according to the standard voltage and the target voltage. This process does not rely on the memory particles themselves, but can perform algorithm verification in advance in the design stage of the memory particles, and promptly discover problems with the algorithm, thereby improving the reliability of the verification. Moreover, since the algorithm verification does not rely on the memory particles themselves, it will not be affected by the natural environment, thereby improving the accuracy of the verification.

[0083] In one implementation, in step 103, when adjusting the signal value corresponding to a part of the time period in the first signal according to the target voltage and the multiple reference voltages, it can be implemented in the following manner:

[0084] First, a voltage difference between each reference voltage and the target voltage is obtained, and then, according to the voltage difference, a signal value corresponding to a part of the time period in the first signal is adjusted to obtain a second signal.

[0085] The time period of the adjusted signal value in the first signal may be determined based on the voltage difference.

[0086] Specifically, in this embodiment, the sampling coefficient corresponding to the memory particle can be used to process the absolute value corresponding to the voltage difference to obtain the first time period. The sampling coefficient here can be an empirical value, but the sampling coefficient can be determined based on the frequency point and sampling mechanism of the memory particle. The sampling coefficient enables the memory particle to sample the signal; then, according to the first time period, the signal value corresponding to the first time period in the first signal is adjusted to a preset target value to obtain the second signal.

[0087] The preset target value can be represented by X, and the specific value can be set according to business requirements. The first time period represents the time period in the first signal during which the eye width needs to be adjusted to be narrower, which can be represented by T1. In this embodiment, the sampling coefficient can be multiplied by the absolute value corresponding to the voltage difference to obtain the first time period T1. Based on this, in this embodiment, the signal value of the first time period is adjusted to the target value to obtain the second signal.

[0088] It can be seen that in this embodiment, the signal value processing can be directly performed on the first signal based on the reference voltage and the target voltage to obtain the second signal with a changed eye width.

[0089] For example, Figure 3As shown in , in this embodiment, starting from V1, V1 and V3 are subtracted, and the signal value of the T1 period in the CA signal is adjusted to X according to the voltage difference, so as to obtain a second signal with a different eye width relative to the CA signal; then V2 and V3 are subtracted, and the signal value of the T1 period in the CA signal is adjusted to X according to the voltage difference, so as to obtain a second signal with different eye widths relative to the CA signal and the second signal corresponding to V1; then V3 and V3 are subtracted, and the signal value of the T1 period in the CA signal is adjusted to X according to the voltage difference (0), so as to obtain the second signal with different eye widths relative to the CA signal and the second signal corresponding to V1 and V2. The second signal with different eye widths is obtained by subtracting V4 from V3, and adjusting the signal value of the T1 period in the CA signal to X according to the voltage difference, so as to obtain a second signal with different eye widths relative to the CA signal and the second signals corresponding to V1, V2 and V3, and so on, until Vn is subtracted from V3, and adjusting the signal value of the T1 period in the CA signal to X according to the voltage difference, so as to obtain a second signal with different eye widths relative to the CA signal and each second signal obtained previously. Based on this, after these second signals are transmitted to the simulation model of the memory particle, the simulation model can capture the second signal with eye width changes, and then select the standard voltage from the reference voltages V1 to Vn according to the eye width parameters of these second signals through the voltage configuration algorithm, and compare it with the target voltage. If the standard voltage such as V3 is consistent with GV, it can be determined that the voltage configuration algorithm can accurately select the correct standard voltage. If the standard voltage such as V2 is inconsistent with GV, it can be determined that the voltage configuration algorithm cannot accurately select the correct standard voltage.

[0090] In another implementation, in step 103, when the signal value corresponding to a part of the time period in the first signal can be adjusted according to the target voltage and the multiple reference voltages, it can be implemented in the following manner:

[0091] First, a voltage difference between each reference voltage and the target voltage is obtained; then, a third signal is obtained according to the voltage difference, and a signal value in the third signal is related to the voltage difference; finally, the third signal is bitwise ANDed with the first signal to obtain a second signal.

[0092] For example, in this embodiment, a group of CA signals can be generated based on the voltage difference as the third signal, which can be called the lpddr5_if.ca_valid signal, and the signal value in the lpddr5_if.ca_valid signal is determined based on; then, the lpddr5_if.ca_valid signal and the first signal are bitwise ANDed to obtain a second signal that can be provided to the simulation model.

[0093] Specifically, in this embodiment, the sampling coefficient corresponding to the memory particle can be used to process the absolute value corresponding to the voltage difference to obtain the second time period, so that the signal value of the second time period in the third signal generated according to the second time period is a specific value, that is, a preset target value. Therefore, in this embodiment, the third signal is bitwise ANDed with the first signal to obtain the second signal.

[0094] It should be noted that the signal value corresponding to the second time period in the third signal is a preset target value, which can be represented by X, and the specific value can be set according to business needs. The second time period represents the time period when the eye width in the third signal becomes narrower, which can be represented by T2. In this embodiment, the sampling coefficient can be multiplied by the absolute value corresponding to the voltage difference to obtain the second time period T2. Based on this, the corresponding third signal is generated in this embodiment, and then bitwise ANDed with the first signal to obtain the second signal.

[0095] It can be seen that in this embodiment, the third signal can be generated based on the reference voltage and the target voltage, and then the third signal and the first signal are bitwise ANDed to obtain the second signal with a changed eye width.

[0096] For example, Figure 4As shown in , in this embodiment, starting from V1, V1 and V3 are subtracted, and a third signal whose signal value is X in the T2 period is generated according to the voltage difference. The third signal and the CA signal are bitwise ANDed, so as to obtain a second signal with a different eye width relative to the CA signal; then V2 and V3 are subtracted, and a third signal whose signal value is X in the T2 period is generated according to the voltage difference. The third signal and the CA signal are bitwise ANDed, so as to obtain a second signal with a different eye width relative to the CA signal and the second signal corresponding to V1; then V3 and V3 are subtracted, and a third signal whose signal value is X in the T2 period is generated according to the voltage difference (0), and the third signal and the CA signal are bitwise ANDed, so as to obtain a second signal with a different eye width relative to the CA signal and V1. and V2 respectively corresponding to the second signal (in other embodiments, the CA signal is not adjusted for the same reference voltage as GV); then V4 and V3 are subtracted, and a third signal whose signal value in the T2 period is X is generated according to the voltage difference, and the third signal is bitwise ANDed with the CA signal, so as to obtain a second signal whose eye width is different from that of the CA signal and the second signals respectively corresponding to V1, V2 and V3, and so on, until Vn and V3 are subtracted, and a third signal whose signal value in the T2 period is X is generated according to the voltage difference, and the third signal is bitwise ANDed with the CA signal, so as to obtain a second signal whose eye width is different from that of the CA signal and the second signals obtained previously. Based on this, after these second signals are transmitted to the simulation model of the memory particles, the simulation model can capture the second signals of the eye width change, and then select the standard voltage from the reference voltages V1 to Vn according to the eye width parameters of these second signals through the voltage configuration algorithm, and compare it with the target voltage. If the standard voltage such as V3 is consistent with GV, it can be determined that the voltage configuration algorithm can accurately select the correct standard voltage. If the standard voltage such as V2 is inconsistent with GV, it can be determined that the voltage configuration algorithm cannot accurately select the correct standard voltage.

[0097] refer to Figure 5 , is a schematic diagram of a structure of a voltage configuration algorithm verification device provided in an embodiment of the present application. The device can be deployed in an electronic device that can be connected to a simulation model corresponding to a memory particle and perform data processing, such as a computer or a server, etc. The memory particle here can be an LPDDR5 memory particle, which has a voltage configuration algorithm CBTtraining. The technical solution in this embodiment is mainly used to improve the reliability of verifying the voltage configuration algorithm.

[0098] Specifically, the device in this embodiment may include the following units:

[0099] A reference obtaining unit 501 is used to obtain a plurality of reference voltages of a voltage configuration algorithm deployed by a memory chip;

[0100] A target determination unit 502, configured to determine a target voltage from the plurality of reference voltages;

[0101] A signal obtaining unit 503, configured to adjust a signal value corresponding to a part of the time periods in the first signal according to the target voltage and the multiple reference voltages, so as to obtain a second signal;

[0102] A signal transmission unit 504, configured to obtain a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

[0103] The algorithm verification unit 505 is used to obtain a verification result according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate.

[0104] It can be seen from the above technical scheme that in a verification device for a voltage configuration algorithm provided in an embodiment of the present application, after obtaining multiple reference voltages of the voltage configuration algorithm deployed by the memory particles, the signal provided to the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltage and each other reference voltage. In this way, the signal used by the voltage configuration algorithm can be actively changed, and then the voltage configuration algorithm can select a standard voltage from the reference voltage according to these different signals, and then the verification result characterizing whether the voltage configuration algorithm is accurate can be obtained according to the standard voltage and the target voltage. This process does not rely on the memory particles themselves, but rather can perform algorithm verification in advance in the design stage of the memory particles, and promptly discover problems with the algorithm, thereby improving the reliability of the verification. Moreover, since the algorithm verification does not rely on the memory particles themselves, it will not be affected by the natural environment, thereby improving the accuracy of the verification.

[0105] In one implementation, the signal acquisition unit 503 is specifically used to: obtain the voltage difference between each of the reference voltages and the target voltage; and adjust the signal value corresponding to a portion of the time period in the first signal according to the voltage difference to obtain the second signal. For example, the absolute value corresponding to the voltage difference is processed using the sampling coefficient corresponding to the memory particle to obtain the first time period; and the signal value corresponding to the first time period in the first signal is adjusted to a preset target value to obtain the second signal.

[0106] In one implementation, the signal acquisition unit 503 is specifically used to: obtain a voltage difference between each reference voltage and the target voltage; obtain a third signal according to the voltage difference; and perform a bitwise AND operation on the third signal and the first signal to obtain a second signal.

[0107] Among them, the signal value corresponding to the second time period in the third signal is a preset target value; the signal acquisition unit 503 obtains the second time period in the following manner: using the sampling coefficient corresponding to the memory particle, the absolute value corresponding to the voltage difference is processed to obtain the second time period.

[0108] In one implementation, the algorithm verification unit 505 is specifically used to: compare the standard voltage with the target voltage; if the standard voltage is consistent with the target voltage, obtain a verification result indicating that the voltage configuration algorithm is accurate; if the standard voltage is inconsistent with the target voltage, obtain a verification result indicating that the voltage configuration algorithm is inaccurate.

[0109] In one implementation, the voltage configuration algorithm obtains an eye width parameter corresponding to each of the reference voltages according to the second signal corresponding to each of the reference voltages, and determines the standard voltage from the multiple reference voltages based on the eye width parameter; wherein the eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all of the reference voltages.

[0110] In one implementation, the reference obtaining unit 501 is specifically used to: read the voltage configuration parameters corresponding to the voltage configuration algorithm at each rising edge of the clock signal through a backdoor method, wherein the voltage configuration parameters include the reference voltage corresponding to the rising edge.

[0111] It should be noted that the specific implementation of each unit in this embodiment can refer to the corresponding content in the previous text and will not be described in detail here.

[0112] refer to Figure 6 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, and the electronic device may include the following structure:

[0113] Memory 601, used to store computer programs and data generated by the execution of the computer programs;

[0114] The processor 602 is configured to execute the computer program to implement:

[0115] Obtain multiple reference voltages of a voltage configuration algorithm deployed by a memory chip;

[0116] determining a target voltage from among the plurality of reference voltages;

[0117] According to the target voltage and the multiple reference voltages, adjusting the signal value corresponding to a part of the time period in the first signal to obtain a second signal;

[0118] Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal;

[0119] A verification result is obtained according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate.

[0120] It can be seen from the above technical solution that in an electronic device provided by an embodiment of the present application, after obtaining multiple reference voltages of the voltage configuration algorithm deployed by the memory particles, the signal provided to the voltage configuration algorithm can be adjusted according to the target voltage selected from the reference voltage and each other reference voltage. In this way, the signal used by the voltage configuration algorithm can be actively changed, and then the voltage configuration algorithm can select the standard voltage from the reference voltage according to these different signals, and then the verification result characterizing whether the voltage configuration algorithm is accurate can be obtained according to the standard voltage and the target voltage. This process does not rely on the memory particles themselves, but can perform algorithm verification in advance in the design stage of the memory particles, and timely discover problems with the algorithm, thereby improving the reliability of the verification. Moreover, since the algorithm verification does not rely on the memory particles themselves, it will not be affected by the natural environment, thereby improving the accuracy of the verification.

[0121] Taking the scenario where the voltage configuration algorithm CBT training used by LPDDR5 memory particles is verified as an example, the technical solution of this application is illustrated below:

[0122] First, the CBT training of LPDDR5 includes CA VREF training, the purpose of which is to find the most suitable VREF (CA). The CA VREF training algorithm written by the developer will try different VREF configurations, i.e. the reference voltage mentioned above, to find an optimal VREF (CA) configuration to maximize the eye width of the CA signal. However, in the simulation environment, configuring VREF (CA) to different values ​​does not really affect the eye width of the CA signal. How to simulate the eye width change of CA according to the configuration value of VREF (CA) through the simulation environment without relying on the memory particles themselves, and then verify the correctness of the training algorithm has become a difficult problem.

[0123] In view of the above problems, this application proposes the following technical solutions:

[0124] In the simulation environment, the CA signal of some time periods is assigned X according to the VREF value configured in CA VREF training to simulate the process of CA eye width change, thereby verifying the correctness of CA VREF training.

[0125] The following are the key points of the technical solution of this application:

[0126] 1. In the simulation environment, add a set of CA signals, such as lpddr5_if.ca_valid. This signal is bitwise ANDed with the CA signal output by LPDDR5PHY to obtain the second signal mentioned above, which is finally sent to the LPDDR5 particle (simulation model).

[0127] 2. In the simulation environment, first specify the golden VREF value, which is the target voltage mentioned above. This value is the VREF value that should be selected after executing the CA VREFtraining algorithm, that is, the VREF value corresponding to the maximum CA eye width, assuming it is 8'b01010001.

[0128] 3. After entering CA VREF training, read the voltage configuration parameters of VREF, i.e., the MR (Memory Register) register configuration, at each rising edge of the clock signal dfi clk. Taking CA VREF as an example, OP[6:0] of MR12 can be read through the backdoor method.

[0129] 4. Compare the currently configured VREF value (i.e., the reference voltage mentioned above) with the golden VREF value, and multiply it by a sampling coefficient (assuming that the value is step), as shown in formula (1), to determine the eye width that needs to be adjusted (that is, the value obtained after multiplying by the sampling coefficient determines the eye width change), assign the lpddr5_if.ca_valid signal value in this period to X, and simulate the process of CA signal eye width change.

[0130] t=|VREF-VREF_golden|×step (1)

[0131] Among them, VREF_golden is the golden VREF value, VREF is the currently configured VREF value (that is, the reference voltage in the previous text), and t is the eye width that needs to be adjusted, that is, the first time period or the second time period in the previous text.

[0132] 5. The LPDDR5 particle (simulation model) feeds back the received CA value to the CA VREF training through the pin. The algorithm will find which VREF value corresponds to the largest CA eye width.

[0133] 6. After running the algorithm, read the VREF result obtained by algorithm training and compare it with the golden VREF value. If they are equal, it means that the algorithm is correct.

[0134] like Figure 7 As shown in FIG. 1 , it is a flowchart of the algorithm verification of this application, and the specific process is as follows:

[0135] Step 701: specify the golden VREF value;

[0136] Step 702: Entering CA VREF training of CBT training. As the CA VREF training begins, in this embodiment, corresponding signals are provided for CA VREF training through steps 703 and 704, so that CA VREF training can train a CA VREF result value.

[0137] Step 703: read the MR configuration of VREF at each rising edge of dfi clk, and determine whether it is equal to the goldenVREF value. If not, execute step 704; if equal, provide the CA signal to CA VREF training, and execute step 705;

[0138] Step 704: Set the time period for narrowing the eye width to |VREF-VREF_golden|×step, obtain the second signal based on the set time period, and provide it to CA VREF training, and execute step 705;

[0139] Step 705: Determine whether the CA VREF training algorithm is finished, that is, the reference voltages in the MR configuration of VREF have been read and the corresponding second signal (that is, used to change the signal eye width provided to CA VREF training) is provided to CA VREF training accordingly. If not, then execute step 703. If it is finished, then execute step 706.

[0140] Step 706: Compare the VREF result value trained by the CA VREF training algorithm (i.e., the VREF result value determined according to the eye width of all signals) with the golden VREF value. If they are the same, execute step 707; if they are not the same, execute step 708;

[0141] Step 707: Obtaining a result that the algorithm has been verified (i.e., the algorithm is accurate);

[0142] Step 708: Obtain a result that the algorithm verification fails (ie, the algorithm is inaccurate).

[0143] Among them, Figure 8As shown in FIG. 7 , in step 704, after the reference voltage is read according to the rising edge of the clock signal CK, the signal value of the time period t (i.e., |VREF-VREF_golden|×step) during which the eye width in the CA signal becomes narrower is set to X according to the voltage difference between the reference voltage and the golden VREF, thereby obtaining the second signal CA_valid, thereby changing the signal eye width.

[0144] In summary, the technical solution of this application has the following advantages:

[0145] First, there is no need to wait until the chip comes back to verify the CA VREF training algorithm, so defects in the algorithm can be discovered in advance.

[0146] Secondly, the simulation environment is an ideal environment and is not affected by the outside world, so the CA eye width corresponding to different VREF values ​​will definitely change accurately according to the settings, which can reflect the impact of different VREF configuration values ​​on the CA eye width.

[0147] In addition, it is convenient to configure the signal eye width in the simulation environment, and the method of changing the signal eye width corresponding to each gear is more flexible.

[0148] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0149] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0150] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0151] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for verifying a voltage configuration algorithm, comprising: Obtain multiple reference voltages of a voltage configuration algorithm deployed in a memory chip; determining a target voltage from among the plurality of reference voltages; Obtaining a voltage difference between each of the reference voltages and the target voltage; According to the voltage difference, adjusting the signal value corresponding to a part of the time period in the first signal to obtain a second signal; wherein the signal eye width of the second signal is different from the signal eye width of the first signal, and the signal eye width of each second signal is different; Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal; Obtaining a verification result according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate; The voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the multiple reference voltages according to the eye width parameter; The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

2. The method according to claim 1, adjusting the signal value corresponding to a part of the time period in the first signal according to the voltage difference, comprises: Using the sampling coefficient corresponding to the memory particle, the absolute value corresponding to the voltage difference is processed to obtain a first time period; The signal value corresponding to the first time period in the first signal is adjusted to a preset target value to obtain a second signal.

3. The method according to claim 1, adjusting the signal value corresponding to a part of the time period in the first signal according to the voltage difference to obtain the second signal, comprising: Obtaining a third signal according to the voltage difference; The third signal is bitwise ANDed with the first signal to obtain a second signal.

4. The method according to claim 3, wherein the signal value corresponding to the second time period in the third signal is a preset target value; in, The second period is obtained by: The absolute value corresponding to the voltage difference is processed using the sampling coefficient corresponding to the memory particle to obtain a second time period.

5. The method according to claim 1 or 2, obtaining a verification result according to the standard voltage and the target voltage, comprising: Comparing the standard voltage with the target voltage; If the standard voltage is consistent with the target voltage, obtaining a verification result indicating that the voltage configuration algorithm is accurate; If the standard voltage is inconsistent with the target voltage, a verification result indicating that the voltage configuration algorithm is inaccurate is obtained.

6. The method according to claim 1 or 2, obtaining a plurality of reference voltages of a voltage configuration algorithm deployed in a memory cell, comprising: Through the backdoor method, at each rising edge of the clock signal, the voltage configuration parameters corresponding to the voltage configuration algorithm deployed by the memory particle are read, and the voltage configuration parameters include the reference voltage corresponding to the rising edge.

7. A verification device for a voltage configuration algorithm, comprising: A reference obtaining unit, used to obtain multiple reference voltages of a voltage configuration algorithm deployed in a memory particle; a target determination unit, configured to determine a target voltage from among the plurality of reference voltages; A signal acquisition unit, configured to obtain a voltage difference between each of the reference voltages and the target voltage; and according to the voltage difference, adjusting a signal value corresponding to a portion of a time period in the first signal to obtain a second signal; wherein a signal eye width of the second signal is different from a signal eye width of the first signal, and a signal eye width of each of the second signals is different; a signal processing unit, configured to obtain a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal; An algorithm verification unit, configured to obtain a verification result according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate; The voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the multiple reference voltages according to the eye width parameter; The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

8. An electronic device comprising: A memory, used to store a computer program and data generated by the execution of the computer program; A processor, configured to execute the computer program to implement: Obtain multiple reference voltages of a voltage configuration algorithm deployed in a memory chip; determining a target voltage from among the plurality of reference voltages; Obtaining a voltage difference between each of the reference voltages and the target voltage; According to the voltage difference, adjusting the signal value corresponding to a part of the time period in the first signal to obtain a second signal; wherein the signal eye width of the second signal is different from the signal eye width of the first signal, and the signal eye width of each second signal is different; Obtaining a standard voltage determined by the voltage configuration algorithm from the plurality of reference voltages according to the second signal; Obtaining a verification result according to the standard voltage and the target voltage, wherein the verification result indicates whether the voltage configuration algorithm is accurate; The voltage configuration algorithm obtains an eye width parameter corresponding to each reference voltage according to the second signal corresponding to each reference voltage, and determines the standard voltage from the multiple reference voltages according to the eye width parameter; The eye width parameter corresponding to the standard voltage is the largest among the eye width parameters corresponding to all the reference voltages.

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