Data reading method, selector-only memory and memory system

Abstract

Embodiments of the present application disclose a data reading method, a selector memory only, and a memory system. The data reading method comprises: raising a voltage of a selected word line to a first word line voltage, and detecting a first bit line voltage of a selected bit line; in response to the first bit line voltage of the selected bit line being less than a reference voltage, raising the voltage of the selected word line to a second word line voltage, and detecting a second bit line voltage of the selected bit line; and reading target data based on the second bit line voltage of the selected bit line. The second word line voltage is greater than the first word line voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a data reading method, a selector only memory and a memory system. BACKGROUND

[0002] In 3D XPoint memory (3D magnetic memory), a storage unit is composed of a selector (used as a switching element for cell selection) and a storage element (phase change memory PCM); that is, the 3D XPoint memory has a 1S1R configuration.

[0003] In a SOM (Selector Only Memory), a storage unit only includes a selector. Compared with the 3D XPoint memory, the SOM can adapt to a smaller processing size, and the high threshold voltage and low threshold voltage states in the SOM can be maintained even if the processing size is 15 nm; in addition, the write time of the SOM device is shorter, and the write time can basically remain consistent between the reset and set states; and the write cycle life of the SOM is also longer than that of the 1S1R configuration memory.

[0004] However, there is still a problem of read disturbance in the reading process of the SOM device, which can cause a decrease in Ea (activation energy) and thus cause a change in the threshold voltage of the device, adversely affecting the performance of the device. SUMMARY

[0005] Therefore, the embodiments of the present application provide a data reading method, a selector only memory and a memory system, which can reduce the problem of read disturbance and ensure the accuracy of the stored data.

[0006] The technical scheme of the embodiments of the present application is as follows:

[0007] The embodiments of the present application provide a data reading method applied to a selector only memory, including: raising the voltage of a selected word line to a first word line voltage, and detecting the first bit line voltage of a selected bit line; in response to the first bit line voltage of the selected bit line being less than a reference voltage, raising the voltage of the selected word line to a second word line voltage, and detecting the second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage; and reading target data based on the second bit line voltage of the selected bit line.

[0008] In some embodiments of the present application, the data reading method further includes: in response to the voltage of the selected word line being raised to the second word line voltage, raising the voltage of an unselected bit line to a compensation voltage.

[0009] In some embodiments of the present application, the compensation voltage is less than the first word line voltage and greater than a voltage of a ground terminal.

[0010] In some embodiments of the present application, the reading the target data based on the second bit line voltage of the selected bit line comprises: reading the target data as 1 in response to the second bit line voltage of the selected bit line being greater than the reference voltage; or reading the target data as 0 in response to the second bit line voltage of the selected bit line being less than the reference voltage.

[0011] In some embodiments of the present application, after the detecting the first bit line voltage of the selected bit line, the data reading method further comprises: reading the target data as 1 in response to the first bit line voltage of the selected bit line being greater than the reference voltage.

[0012] In some embodiments of the present application, before the raising the voltage of the selected word line to the first word line voltage, the data reading method further comprises: discharging the selected bit line to a starting bit line voltage; the starting bit line voltage is less than the reference voltage.

[0013] In some embodiments of the present application, after the reading the target data, the data reading method further comprises: grounding the selected word line and the selected bit line.

[0014] Embodiments of the present application also provide a selector-only memory, comprising: a storage unit array and a peripheral circuit; wherein the storage unit array comprises: a plurality of word lines and a plurality of bit lines, and a storage unit coupled between a word line and a bit line; the peripheral circuit is coupled to the plurality of word lines and the plurality of bit lines; the peripheral circuit is configured to raise a voltage of a selected word line to a first word line voltage, and detect a first bit line voltage of a selected bit line; and, in response to the first bit line voltage of the selected bit line being less than a reference voltage, raise the voltage of the selected word line to a second word line voltage, and detect a second bit line voltage of the selected bit line; and, based on the second bit line voltage of the selected bit line, read target data; wherein the second word line voltage is greater than the first word line voltage.

[0015] In some embodiments of the present application, the peripheral circuit is further configured to, in response to the voltage of the selected word line being raised to the second word line voltage, raise a voltage of an unselected bit line to a compensation voltage; wherein the compensation voltage is less than the first word line voltage and greater than a voltage of a ground terminal.

[0016] Embodiments of the present application also provide a memory system, comprising: one or more selector-only memories as described in the above solutions, and a memory controller; the memory controller is coupled to the selector-only memory; the memory controller controls the selector-only memory.

[0017] It can be understood that, in the reading process, the voltage of the selected word line is first raised to a smaller first word line voltage, and then, based on the first bit line voltage of the selected bit line, it is determined whether to raise the voltage of the selected word line to a larger second word line voltage. In this way, the stepped word line voltage is used in the reading process, avoiding the direct raising of the voltage of the selected word line to the larger second word line voltage, thereby reducing the voltage of the selected word line in the reading process, reducing the current on the SOM device in the reading process, and further reducing the read interference problem, thereby ensuring the accuracy of the stored data. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1A Figure 1 is a schematic diagram of a read interference problem in a SOM device;

[0019] Figure 1B Figure 2 is a schematic diagram of a read interference problem in a SOM device Figure 2 ;

[0020] Figure 1C Figure 3 is a schematic diagram of a read interference problem in a SOM device;

[0021] Figure 2 Figure 4 is a structural schematic diagram of a selector-only memory provided by an embodiment of the present application;

[0022] Figure 3A Figure 5 is an electrical parameter waveform schematic diagram of a writing process of a selector-only memory provided by an embodiment of the present application;

[0023] Figure 3B Figure 6 is an electrical parameter waveform schematic diagram of a writing process of a selector-only memory provided by an embodiment of the present application Figure 2 ;

[0024] Figure 4 Figure 7 is a schematic diagram of a reading process of a selector-only memory provided by an embodiment of the present application;

[0025] Figure 5 Figure 8 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present application;

[0026] Figure 6 Figure 9 is a schematic diagram of an implementation process of a data reading method provided by an embodiment of the present application Figure 2 ;

[0027] Figure 7 Figure 10 is an electrical parameter waveform schematic diagram of a data reading method provided by an embodiment of the present application;

[0028] Figure 8 Figure 11 is an electrical parameter waveform schematic diagram of a data reading method provided by an embodiment of the present application Figure 2 ;

[0029] Figure 9 This is a schematic diagram of the implementation process of the data reading method provided in this application embodiment;

[0030] Figure 10 This is a schematic diagram of the electrical parameter waveforms of the data reading method provided in this application embodiment;

[0031] Figure 11 This is a schematic diagram of the implementation flow of the data reading method provided in the embodiments of this application. Figure 4 ;

[0032] Figure 12 This is a schematic diagram of the implementation flow of the data reading method provided in the embodiments of this application. Figure 5 ;

[0033] Figure 13 This is a schematic diagram of the selector-only memory structure provided in the embodiments of this application. Figure 2 ;

[0034] Figure 14 This is a schematic diagram of the memory system provided in an embodiment of this application. Detailed Implementation

[0035] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected", or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0039] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] In order to enable more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present application.

[0042] In the related art, the increase in the number of read cycles in the SOM brings about a read disturbance problem. The read disturbance refers to the fact that, due to the increase in the number of read cycles, a large voltage difference is applied to both ends of the device multiple times, thereby causing the performance of the device to decrease (for example, Ea decreases, the threshold voltage changes), and in severe cases, the data stored in the device changes. For the SOM device, the read disturbance is manifested as an abnormal current in the read process.

[0043] Reference Figure 1A In the case where the SOM device stores data "1", as the number of read cycles increases, the current of the SOM device in the read process remains stable, that is, the read disturbance problem does not occur. In the case where the SOM device stores data "0", as the number of read cycles increases, the current of the SOM device in the read process is obviously abnormal, that is, the read disturbance problem occurs. Figure 1B In the case where the SOM device stores data "1", as the number of read cycles increases, the current of the SOM device in the read process remains stable, that is, the read disturbance problem does not occur. In the case where the SOM device stores data "0", as the number of read cycles increases, the current of the SOM device in the read process is obviously abnormal, that is, the read disturbance problem occurs.

[0044] Reference Figure 1C For condition 1, that is, in the case where the SOM device stores data "1", as the number of read cycles increases, the Ea of the SOM device remains stable. For condition 2, that is, in the case where the SOM device stores data "0", as the number of read cycles increases, the Ea of the SOM device obviously decreases, which causes the threshold voltage of the SOM device to change significantly and adversely affects the performance of the device.

[0045] In summary, for the SOM device, in the case where the SOM device stores data "1", the read disturbance problem does not occur; in the case where the SOM device stores data "0", the read disturbance problem is likely to occur.

[0046] Figure 2 is an optional structure diagram of the selector-only memory provided by the embodiments of the present application. Reference Figure 2 In the SOM, each OTS (bidirectional threshold switch selector) constitutes a memory cell, and both ends of each OTS are connected to a corresponding word line and bit line, respectively.

[0047] In combination with Figure 2 and Figure 3AWhen the set process is performed, the voltage of the selected word line WL is raised from the ground voltage VSS to the positive voltage Vp, and the voltage of the selected bit line BL is lowered from the ground voltage VSS to the negative voltage Vn, so that the phase change material in the target OTS can be converted from the amorphous state to the crystalline state, thereby writing data "1" to the target OTS.

[0048] In combination Figure 2 and Figure 3B When the reset process is performed, the voltage of the selected word line WL is lowered from the ground voltage VSS to the negative voltage Vn, and the voltage of the selected bit line BL is raised from the ground voltage VSS to the positive voltage Vp, so that the phase change material in the target OTS can be converted from the crystalline state to the amorphous state, thereby writing data "0" to the target OTS.

[0049] Figure 4 The read process of the SOM device is illustrated. As shown in Figure 4 , in the read process, the voltage of the selected word line WL is raised to a positive voltage, and the voltage of the selected bit line BL is detected, and the target data stored in the SOM device (i.e. Figure 2 , the target OTS) is determined according to the voltage of the selected bit line BL. The voltage drop between the selected bit line BL and the selected word line WL is determined by the resistance of the SOM device, that is, the target data stored in the SOM device is determined according to the resistance of the SOM device, wherein the resistance of the SOM device is determined by the state of the phase change material. In the read process, the current direction (i.e. the read direction) is from the selected word line WL to the selected bit line BL.

[0050] It should be noted that, referring to Figure 4 , since the read direction is from the selected word line WL to the selected bit line BL, the greater the voltage of the selected word line WL in the read process, the greater the current on the SOM device. Further, the greater the current on the SOM device in the read process, the more likely it is to occur read disturbance.

[0051] Figure 5 is an optional flowchart of a data reading method provided by the embodiments of the present application, which is applied to a selector-only memory. As shown in Figure 5 , the data reading method comprises steps S101-S103, which will be described in combination with the steps.

[0052] S101, raise the voltage of the selected word line to a first word line voltage, and detect the first bit line voltage of the selected bit line.

[0053] In the embodiments of the present application, referring to Figure 7During the reading process of the SOM device, the voltage of the selected word line WL can be increased to the first word line voltage VBN1, that is, the "WL ramping P1" stage is executed; and the voltage of the selected word line BL during the "WL ramping P1" stage (the first word line voltage of the selected word line BL) is detected.

[0054] S102. In response to the first line voltage of the selected position line being less than the reference voltage, the voltage of the selected word line is increased to the second word line voltage, and the second line voltage of the selected position line is detected; wherein, the second word line voltage is greater than the first word line voltage.

[0055] S103. Read the target data based on the second bit voltage of the selected positioning line.

[0056] In the embodiments of this application, such as Figure 7 In the example, the voltage of the selected word line BL during the "WL ramping P1" phase (the first word line voltage) remains at the initial word line voltage VNR1, which is less than the reference voltage Vref. Therefore, the voltage of the selected word line WL can be ramped from the first word line voltage VBN1 to the second word line voltage VBN2, i.e., the "WL ramping P2" phase is executed; and the voltage of the selected word line BL during the "WL ramping P2" phase (the second word line voltage of the selected word line BL) is detected. Furthermore, the target data to be read can be determined based on the second word line voltage of the selected word line BL.

[0057] In this embodiment, the second word line voltage VBN2 is greater than the first word line voltage VBN1; for example, the first word line voltage VBN1 can be 2-3V, and the second word line voltage VBN2 can be 4-5V. The second word line voltage VBN2 and the first word line voltage VBN1 can be provided by different power supplies preset in the SOM.

[0058] In some embodiments of this application, the first word line voltage VBN1 and the second word line voltage VBN2 can both be selected from multiple different voltage values ​​as needed. For example, one of three different voltage power supplies can be selected to provide the second word line voltage VBN2.

[0059] Understandably, during the read process, the voltage of the selected word line WL is first increased to a smaller first word line voltage. Then, based on the first word line voltage of the selected word line BL, it is determined whether to increase the voltage of the selected word line WL to a larger second word line voltage. This step-wise word line voltage approach avoids directly increasing the voltage of the selected word line WL to a larger second word line voltage, thereby reducing the voltage of the selected word line WL during the read process, reducing the current on the SOM device, and thus reducing read interference and ensuring the accuracy of the stored data.

[0060] In some embodiments of the present application, the reading of the target data can be implemented by Figure 6 The steps S201-S202 shown can be implemented by Figure 5 The step S103 shown will be described in combination with each step.

[0061] S201, in response to the second bit line voltage of the selected bit line being greater than the reference voltage, reading the target data as 1.

[0062] In the embodiments of the present application, the reference Figure 7 In the case where the voltage of the selected word line WL is raised to the second word line voltage VBN2 (i.e., in the "WL raised P2" phase), if the second bit line voltage of the selected bit line BL is raised to the voltage VNR2 (greater than the reference voltage Vref); it can be determined that the target OTS in Figure 2 is in a state of smaller resistance, i.e., it can be determined that the target data to be read is 1. Further, the "data latch" phase can be performed to latch the determined target data.

[0063] S202, in response to the second bit line voltage of the selected bit line being less than the reference voltage, reading the target data as 0.

[0064] In the embodiments of the present application, the reference Figure 7 In the case where the voltage of the selected word line WL is raised to the second word line voltage VBN2 (i.e., in the "WL raised P2" phase), if the second bit line voltage of the selected bit line BL remains the initial bit line voltage VNR1 (less than the reference voltage Vref); it can be determined that the target OTS in Figure 2 is in a state of larger resistance, i.e., it can be determined that the target data to be read is 0. Further, the "data latch" phase can be performed to latch the determined target data.

[0065] In some embodiments of the present application, Figure 5 After the step S101 shown, the data reading method further includes Figure 6 The step S203 shown will be described in combination with each step.

[0066] S203, in response to the first bit line voltage of the selected bit line being greater than the reference voltage, reading the target data as 1.

[0067] In the embodiments of the present application, the reference Figure 8, if the first bit line voltage of the selected bit line BL is raised to the voltage VNR3 (greater than the reference voltage Vref) when the voltage of the selected word line WL is raised to the first word line voltage VBN1 (i.e., in the "WL raised P1" stage), it can be determined that the target OTS in the SOM device is in a state of a smaller resistance, i.e., it can be determined that the target data to be read is 1. Further, the "data latch" stage can be performed to latch the determined target data. Figure 2

[0068] It can be understood that, if the first bit line voltage of the selected bit line BL is greater than the reference voltage Vref when the voltage of the selected word line WL is raised to the first word line voltage VBN1, the target data is directly determined to be 1; and if the first bit line voltage of the selected bit line BL is less than the reference voltage Vref, the voltage of the selected word line WL needs to be further raised to determine whether the target data is 0. In this way, for the SOM device storing the data "0", the stepped word line voltage is used in the reading process, so as to avoid directly raising the voltage of the selected word line WL to a larger second word line voltage, thereby being capable of specifically reducing the read disturbance problem, i.e., solving the problem that the SOM device in the "0" state is prone to read disturbance.

[0069] In some embodiments of the present application, Figure 5 After the step S102 shown, the data reading method further includes Figure 9 The step S104 shown will be described in combination with each step.

[0070] S104, in response to the voltage of the selected word line being raised to the second word line voltage, raising the voltage of the unselected bit line to a compensation voltage.

[0071] In the embodiments of the present application, the reference Figure 2 Since the selected word line WL is connected with a plurality of storage units (i.e., OTS), in the reading process, the voltage of the selected word line WL is raised, which not only affects the target OTS connected with the selected bit line BL, but also affects other OTS connected with the unselected bit line Usel BL. That is, the voltage of the selected word line WL is raised, which causes read disturbance to other OTS.

[0072] It should be noted that, in the writing process, a certain voltage difference needs to be applied across the OTS to change the state of the phase change material in the OTS, so as to write the corresponding data. In this regard, the reference Figure 3A In the process of writing the data "1", the word line WL applies a positive voltage Vp, and the bit line BL applies a negative voltage Vn; in this regard, the reference Figure 3B ​In the process of writing data "0", the word line WL applies a negative voltage Vn, and the bit line BL applies a positive voltage Vp. That is, the voltage difference across the OTS reaches a certain degree, which changes the stored data.

[0073] In combination Figure 2 and Figure 10 In the case that the voltage of the selected word line WL is raised to the second word line voltage VBN2, the voltage of the unselected bit line Usel BL is raised to the compensation voltage VC. In this way, the voltage difference between the unselected bit line Usel BL and the selected word line WL, i.e., the voltage difference across the other OTS connected to the unselected bit line Usel BL, is reduced, thereby offsetting the effect of the second word line voltage VBN2 on the other OTS and ensuring the accuracy of the data stored in the other OTS.

[0074] In some embodiments of the present application, the compensation voltage VC is less than the first word line voltage VBN1 and greater than the voltage VSS of the ground terminal. For example, the compensation voltage VC can be 1.2V.

[0075] It should be noted that the voltage of the unselected bit line Usel BL in the idle state remains the voltage VSS of the ground terminal, and therefore the compensation voltage VC needs to be greater than the voltage VSS of the ground terminal to take effect.

[0076] In addition, the compensation voltage VC should not be set too large. If the compensation voltage VC is too large, the voltage difference between the unselected bit line Usel BL and the selected bit line BL will be too large, which may result in leakage between the unselected bit line Usel BL and the selected bit line BL. Meanwhile, a large compensation voltage VC will also result in large power consumption.

[0077] In some embodiments of the present application, the data reading method further comprises Figure 11 The steps S301 and S302 are shown. The steps will be described in detail.

[0078] S301, discharging the selected bit line to a starting bit line voltage; the starting bit line voltage is less than a reference voltage.

[0079] In the embodiments of the present application, the reference Figure 7 and Figure 8 At the beginning of the reading process, the selected bit line BL needs to be discharged, i.e., the "BL discharge" phase is performed. In this way, the residual voltage on the selected bit line BL can be avoided to affect the reading result.

[0080] In the embodiments of the present application, the reference Figure 7 and Figure 8The selected bit line BL can be discharged to a starting bit line voltage VNR1; the starting bit line voltage VNR1 is less than the reference voltage Vref, and the starting bit line voltage VNR1 is also less than the ground voltage VSS.

[0081] S302, grounding the selected word line and the selected bit line.

[0082] In the embodiments of the present application, the reference Figure 7 and Figure 8 After the reading of the target data is completed, the voltages of the selected word line WL and the selected bit line BL need to be reset, that is, a "Weak Reset Back" stage is performed. In this way, the residual voltage on the selected word line WL and the selected bit line BL can be avoided from affecting other working processes of the memory.

[0083] In the embodiments of the present application, the reference Figure 7 and Figure 8 The selected word line WL and the selected bit line BL can be grounded, so that the voltages of the selected word line WL and the selected bit line BL are both reset to the ground voltage VSS.

[0084] Figure 12 is an optional flowchart of the data reading method provided by the embodiments of the present application, which is applied to a selector-only memory. As shown in Figure 12 , the data reading method comprises steps S401-S407, which will be described in combination with the steps.

[0085] S401, discharging the selected bit line BL to a starting bit line voltage VNR1.

[0086] In the embodiments of the present application, the reference Figure 7 and Figure 8 At the beginning of the reading process, the selected bit line BL needs to be discharged, that is, a "BL Discharge" stage is performed. The selected bit line BL can be discharged to a starting bit line voltage VNR1.

[0087] S402, raising the selected word line WL to a first word line voltage VBN1.

[0088] In the embodiments of the present application, the reference Figure 7 and Figure 8 The voltage of the selected word line WL can be raised to a first word line voltage VBN1 first, that is, a "WL Raise P1" stage is performed.

[0089] S403, raising the selected word line WL to a higher second word line voltage VBN2.

[0090] In the embodiments of the present application, the reference Figure 7After the voltage of the selected word line WL is raised to the first word line voltage VBN1, if the voltage (first bit line voltage) of the selected bit line BL is less than the reference voltage Vref, the voltage of the selected word line WL can be raised to a second word line voltage VBN2, that is, the "WL raise P2" stage is performed.

[0091] S404, the selected word line WL is kept at the first word line voltage VBN1.

[0092] In the embodiments of the present application, the reference voltage Vref is the voltage of the selected bit line BL when the selected word line WL is kept at the first word line voltage VBN1. Figure 8 After the voltage of the selected word line WL is raised to the first word line voltage VBN1, if the voltage (first bit line voltage) of the selected bit line BL is greater than the reference voltage Vref, the voltage of the selected word line WL can be kept at the first word line voltage VBN1. At this time, the target data can be read as 1.

[0093] S405, the unselected bit line Unsel BL is raised to the compensation voltage VC.

[0094] In the embodiments of the present application, the reference voltage Vref is the voltage of the selected bit line BL when the selected word line WL is kept at the first word line voltage VBN1. Figure 10 In the case that the voltage of the selected word line is raised to the second word line voltage VBN2, the voltage of the unselected bit line Usel BL is raised to the compensation voltage VC to reduce the voltage difference between the unselected bit line Usel BL and the selected word line WL.

[0095] S406, the selected word line WL is restored to the ground terminal voltage VSS.

[0096] In the embodiments of the present application, the reference voltage Vref is the voltage of the selected bit line BL when the selected word line WL is kept at the first word line voltage VBN1. Figure 7 and Figure 8 After the voltage of the selected word line is raised to the second word line voltage VBN2, the voltage of the selected bit line BL can be sensed, that is, the "data latch" stage is performed. At the same time, the selected word line WL can be restored to the ground terminal voltage VSS.

[0097] S407, the voltage of the selected bit line BL is restored to the ground terminal voltage VSS.

[0098] In the embodiments of the present application, the reference voltage Vref is the voltage of the selected bit line BL when the selected word line WL is kept at the first word line voltage VBN1. Figure 7 and Figure 8 After the reading of the target data is completed, the voltage of the selected bit line BL can be restored to the ground terminal voltage VSS, that is, the "weak reset" stage is performed.

[0099] It can be understood that, in the case that the voltage of the selected word line WL is raised to the first word line voltage VBN1, if the first bit line voltage of the selected bit line BL is greater than the reference voltage Vref, the target data is directly determined as 1; and if the first bit line voltage of the selected bit line BL is less than the reference voltage Vref, the voltage of the selected word line WL needs to be further raised to determine whether the target data is 0. In this way, for the condition that the data "0" is stored in the SOM device, the stepped word line voltage is used in the reading process, avoiding the direct raising of the voltage of the selected word line WL to the larger second word line voltage, so that the reading interference problem can be specifically reduced, that is, the problem of easy reading interference of the SOM device in the "0" state is solved.

[0100] Meanwhile, in the case that the voltage of the selected word line is raised to the second word line voltage VBN2, the voltage of the unselected bit line UselBL is raised to the compensation voltage VC. In this way, the voltage difference between the two ends of the other OTS connected to the unselected bit line UselBL is reduced, thereby offsetting the influence of the second word line voltage VBN2 on the other OTS, and ensuring the accuracy of the data stored in the other OTS.

[0101] Figure 13 An optional structure schematic diagram of only selector memory in the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the only selector memory 10 includes a peripheral circuit 110 and a storage unit array 120. Figure 13

[0102] In the embodiments of the present application, the storage unit array 120 includes a plurality of rows of word lines WL and a plurality of columns of bit lines BL, and storage units coupled between the word lines WL and the bit lines BL. The peripheral circuit 110 is coupled to the plurality of rows of word lines WL and the plurality of columns of bit lines BL. In combination with FIG. 1, the word lines WL and the bit lines BL extend in different directions, and the storage units (i.e., OTS) are coupled between the word lines WL and the bit lines BL. Figure 2

[0103] In the embodiments of the present application, the peripheral circuit 110 can perform operations to process data in the storage unit array 120. The peripheral circuit 110 can write data to the storage unit array 120 or read data from the storage unit array 120 based on a command CMD and an address ADDR.

[0104] In the embodiments of the present application, the peripheral circuit 110 is configured to raise the voltage of the selected word line to a first word line voltage, and detect a first bit line voltage of the selected bit line; and in response to the first bit line voltage of the selected bit line being less than a reference voltage, raise the voltage of the selected word line to a second word line voltage, and detect a second bit line voltage of the selected bit line; and read target data based on the second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage. ​​

[0105] In some embodiments of the application, the peripheral circuit 110 is further configured to, in response to the voltage of the selected word line rising to the second word line voltage, raise the voltage of the unselected bit line to a compensation voltage; wherein the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

[0106] In some embodiments of the application, the peripheral circuit 110 is further configured to, in response to the second bit line voltage of the selected bit line being greater than the reference voltage, read the target data as 1; or, in response to the second bit line voltage of the selected bit line being less than the reference voltage, read the target data as 0.

[0107] In some embodiments of the application, the peripheral circuit 110 is further configured to, in response to the first bit line voltage of the selected bit line being greater than the reference voltage, read the target data as 1.

[0108] In some embodiments of the application, the peripheral circuit 110 is further configured to discharge the selected bit line to a starting bit line voltage; wherein the starting bit line voltage is less than the reference voltage.

[0109] In some embodiments of the application, the peripheral circuit 110 is further configured to ground the selected word line and the selected bit line.

[0110] Figure 14 An optional structure of the memory system in embodiments of the application is shown in FIG. 3. As shown in FIG. 3, the memory system 30 includes one or more selector-only memories 10 and a memory controller 20. Figure 14 The memory controller 20 is coupled to the selector-only memories 10 and a host HOST, and is configured to control the selector-only memories 10. The host HOST can be a processor (CPU) or a graphics processing unit (GPU). The host HOST can be configured to send data to the selector-only memories 10, or receive data from the selector-only memories 10.

[0111] In embodiments of the application, the memory controller 20 can send data to and receive data from the host HOST, and send commands CMD and addresses ADDR to the selector-only memories 10. Figure 14 The memory controller 20 can manage data in the selector-only memories 10, and communicate with the host HOST. The memory controller 20 can be configured to control operations of the selector-only memories 10, such as read and write operations.

[0112] Continuing to refer to FIG. 3, the memory controller 20 can manage data in the selector-only memories 10, and communicate with the host HOST. The memory controller 20 can be configured to control operations of the selector-only memories 10, such as read and write operations. Figure 14 In embodiments of the application, the memory controller 20 can send data to and receive data from the host HOST, and send commands CMD and addresses ADDR to the selector-only memories 10.

[0113] Figure 14 In embodiments of the application, the memory controller 20 can send data to and receive data from the host HOST, and send commands CMD and addresses ADDR to the selector-only memories 10. ​

[0114] It should be noted that, in this document, the terms "comprising", "comprises" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0115] The above-mentioned embodiment numbers of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present application can be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present application can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A data reading method applied to a selector-only memory, characterized in that, The resistance of the storage unit storing data 1 is less than the resistance of the storage unit storing data 0. The data reading method comprises: raising the voltage of the selected word line to a first word line voltage, and detecting a first bit line voltage of the selected bit line; in response to the first bit line voltage of the selected bit line being greater than a reference voltage, reading the target data as 1; in response to the first bit line voltage of the selected bit line being less than the reference voltage, raising the voltage of the selected word line to a second word line voltage, and detecting a second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage; in response to the second bit line voltage of the selected bit line being greater than the reference voltage, reading the target data as 1; in response to the second bit line voltage of the selected bit line being less than the reference voltage, reading the target data as 0.

2. The data reading method according to claim 1, characterized by, The data reading method further comprises: in response to the voltage of the selected word line being raised to the second word line voltage, raising the voltage of the unselected bit line to a compensation voltage.

3. The data reading method according to claim 2, wherein: the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

4. The data reading method according to claim 1, characterized by, Before the voltage of the selected word line is raised to the first word line voltage, the data reading method further comprises: discharging the selected bit line to a starting bit line voltage; the starting bit line voltage is less than the reference voltage.

5. The data reading method according to any one of claims 1 to 4, characterized by, After reading the target data, the data reading method further comprises: grounding the selected word line and the selected bit line.

6. A select-only memory characterized by, Comprise: a storage unit array and a peripheral circuit; wherein the storage unit array comprises: a plurality of word lines and a plurality of bit lines, and a storage unit coupled between the word line and the bit line; wherein the resistance of the storage unit storing data 1 is less than the resistance of the storage unit storing data 0; the peripheral circuit is coupled to the plurality of word lines and the plurality of bit lines; the peripheral circuit is configured to raise the voltage of the selected word line to a first word line voltage, and detect a first bit line voltage of the selected bit line; in response to the first bit line voltage of the selected bit line being greater than a reference voltage, read the target data as 1; in response to the first bit line voltage of the selected bit line being less than the reference voltage, raise the voltage of the selected word line to a second word line voltage, and detect a second bit line voltage of the selected bit line; in response to the second bit line voltage of the selected bit line being greater than the reference voltage, read the target data as 1; in response to the second bit line voltage of the selected bit line being less than the reference voltage, read the target data as 0; wherein the second word line voltage is greater than the first word line voltage.

7. The selector-only memory according to claim 6, wherein: the peripheral circuit is further configured to, in response to the voltage of the selected word line being raised to the second word line voltage, raise the voltage of the unselected bit line to a compensation voltage; wherein the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

8. A memory system, comprising: Comprise: one or more selector-only memories according to claim 6 or 7, and a memory controller; The memory controller is coupled with the selectorless memory; the memory controller controls the selectorless memory.

Images