Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, wherein the preparation method comprises: providing a substrate, sequentially forming a buried power rail and a device structure on a first surface of the substrate. Forming a first dielectric layer on a second surface of the substrate, and performing an etching process on at least the first dielectric layer to form a through-hole structure and an opening structure, wherein the opening structure is located around the through-hole structure, and the through-hole structure exposes the buried power rail, wherein the first surface and the second surface are two surfaces of the substrate disposed opposite to each other. Performing a filling process to form a stress absorption structure in the opening structure and a conductive structure in the through-hole structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the continuous advancement of science and technology in recent years, the performance and preparation process of semiconductor structures have been greatly developed. In order to meet the normal use of semiconductor structures, a power supply structure is usually set in the semiconductor structure. It is understandable that the structural settings contained therein will have a certain impact on the performance of the semiconductor structure.

[0003] However, in conventional technologies, there are still many problems in the preparation method of semiconductor structures that need to be improved. Summary of the invention

[0004] The present disclosure provides a method for preparing a semiconductor structure, the method comprising:

[0005] Providing a substrate, and sequentially forming a buried power rail and a device structure on a first surface of the substrate;

[0006] A first dielectric layer is formed on the second surface of the substrate, and an etching process is performed on at least the first dielectric layer to form a through-hole structure and an opening structure, wherein the opening structure is located around the through-hole structure, and the through-hole structure exposes the buried power rail; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other;

[0007] A filling process is performed to form a stress absorbing structure in the opening structure and a conductive structure in the through-hole structure.

[0008] In some embodiments, providing a substrate comprises:

[0009] providing a substrate;

[0010] forming an etch stop layer on the substrate;

[0011] A semiconductor layer is formed on the etch stop layer.

[0012] In some embodiments, a buried power rail and a device structure are sequentially formed on the first surface of the substrate, including:

[0013] forming a second dielectric layer on the semiconductor layer;

[0014] forming a trench structure extending along a first direction in the second dielectric layer and the semiconductor layer, wherein the trench structure does not expose the etch stop layer;

[0015] performing a filling process to form the buried power rail in the trench structure;

[0016] The device structure is formed.

[0017] In some embodiments, before forming the first dielectric layer on the second surface of the substrate, the preparation method further includes:

[0018] thinning the substrate from the second surface to expose the etch stop layer;

[0019] The etch stop layer is removed.

[0020] In some embodiments, performing an etching process on at least the first dielectric layer to form a through-hole structure and an opening structure includes:

[0021] Performing an etching process on the first dielectric layer and the semiconductor layer to form the through-hole structure and the opening structure; wherein both the through-hole structure and the opening structure expose the buried power rail;

[0022] or,

[0023] An etching process is performed on the first dielectric layer and the semiconductor layer to form the through-hole structure and the opening structure; wherein the through-hole structure exposes the buried power rail, and the opening structure does not expose the buried power rail.

[0024] In some embodiments, performing a filling process to form the stress absorption structure in the opening structure and the conductive structure in the through-hole structure includes:

[0025] Filling the opening structure with a material having a preset thermal expansion coefficient to form the stress absorbing structure;

[0026] A conductive material is filled into the through-hole structure to form the conductive structure.

[0027] In some embodiments, after forming the stress absorption structure and the conductive structure, the preparation method further includes:

[0028] A metallization process is performed to form a metal line structure above the conductive structure, and an area formed by the intersection of the buried power rail and the orthographic projection of the metal line structure on the second surface of the substrate is defined as an intersection area, the conductive structure is located on part of the intersection area, and the stress absorption structure is located around the conductive structure.

[0029] In some embodiments, the intersection region includes a first region and a second region, the conductive structure is located on the first region, the stress absorption structure is located at least on the second region, and the conductive structure and the stress absorption structure are arranged at intervals along the extension direction of the metal wire structure.

[0030] In some embodiments, the intersection region includes a first region provided with the conductive structure and a second region not provided with the conductive structure, and along the direction in which the buried power rail extends, the stress absorption structure is at least located between the first region and the second region.

[0031] The present disclosure also provides a semiconductor structure, the semiconductor structure comprising:

[0032] substrate;

[0033] A buried power rail and device structure are arranged from bottom to top on the first surface of the substrate;

[0034] A first dielectric layer, located on the second surface of the substrate;

[0035] A stress absorption structure and a conductive structure, part of the conductive structure and at least part of the stress absorption structure are located in the first dielectric layer, and the stress absorption structure is located around the conductive structure; wherein the conductive structure penetrates the first dielectric layer and is connected to the buried power rail.

[0036] In some embodiments, the stress absorbing structure comprises a material having a predetermined coefficient of thermal expansion.

[0037] In some embodiments, along a direction from the first surface to the second surface, the stress absorption structure includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion have different thermal expansion coefficients;

[0038] and / or,

[0039] Along a direction parallel to the second surface, the stress absorption structure includes a first sub-layer and a second sub-layer from inside to outside, and the first sub-layer and the second sub-layer have different thermal expansion coefficients.

[0040] The present disclosure provides a method for preparing a semiconductor structure and a semiconductor structure, wherein the preparation method comprises: providing a substrate, sequentially forming a buried power rail and a device structure on the first surface of the substrate; forming a first dielectric layer on the second surface of the substrate, and performing an etching process on at least the first dielectric layer to form a through-hole structure and an opening structure, wherein the opening structure is located around the through-hole structure, and the through-hole structure exposes the buried power rail; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other; performing a filling process to form a stress absorption structure in the opening structure, and forming a conductive structure in the through-hole structure. Thus, in the present disclosure embodiment, the power supply structure (including but not limited to the conductive structure) originally arranged with the transistor is directly transferred to the back side of the transistor for rearrangement, which is beneficial to increase the transistor arrangement density per unit area, avoid signal interference between the transistor and the power supply structure, reduce wiring congestion at the back end of the line, provide power supply performance advantages, and enhance chip reliability. At the same time, it also helps to further shorten the process node. In addition, in the embodiment of the present disclosure, due to the provision of a stress absorption structure, during the process of forming the multiple structures included in the power supply structure, even if the process step of thinning the substrate is performed, the thermal stress generated by the above-mentioned multiple structures during the formation process will be effectively absorbed by the stress absorption structure, thereby reducing the occurrence of defects such as structural delamination, cracks, warping, etc. caused by poor heat dissipation and accumulation of thermal stress, which helps to improve the various performances of the semiconductor structure finally obtained.

[0041] Details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features and advantages of the present disclosure will become apparent from the specification and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A flowchart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 2 One of the process flow charts of the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0045] Figure 3 A second process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 4 A third process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0047] Figure 5 A fourth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0048] Figure 6 A fifth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0049] Figure 7 A sixth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Figure 8 A seventh process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Fig. 9 The eighth process flow chart of the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Fig.10 A ninth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Fig.11 A tenth process flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Fig.12 One of the process flow charts of the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0055] Fig.13 A structural schematic diagram of the positional relationship between a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure provided in one embodiment of the present disclosure;

[0056] Fig.14 A structural schematic diagram of the positional relationship between a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure provided in another embodiment of the present disclosure;

[0057] Fig.15 A schematic structural diagram of the cross-sectional shape of a stress absorbing structure provided in an embodiment of the present disclosure;

[0058] Fig.16 Schematic diagram of the structure of the stress absorption structure provided in different embodiments of the present disclosure. DETAILED DESCRIPTION

[0059] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0060] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0061] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0062] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0063] Spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0064] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] With the continuous advancement of science and technology in recent years, the performance and preparation process of semiconductor structures have been greatly developed. In order to meet the use requirements of semiconductor structures, a power supply structure is usually provided on the substrate of the semiconductor structure.

[0066] However, when the power supply structure and the device structure are both arranged on the front side of the substrate, there are usually phenomena such as large power loss and mutual interference of signals.

[0067] Based on this, the following technical solutions of the embodiments of the present disclosure are proposed:

[0068] The present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the preparation method includes the following steps:

[0069] Step S101: providing a substrate, and sequentially forming a buried power rail and a device structure on a first surface of the substrate;

[0070] Step S102: forming a first dielectric layer on the second surface of the substrate, and performing an etching process on at least the first dielectric layer to form a through-hole structure and an opening structure, wherein the opening structure is located around the through-hole structure, and the through-hole structure exposes the buried power rail; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other;

[0071] Step S103: performing a filling process to form a stress absorption structure in the opening structure and a conductive structure in the through-hole structure.

[0072] Thus, in the embodiment of the present disclosure, the power supply structure (including but not limited to the conductive structure) originally arranged together with the transistor is directly transferred to the back side of the transistor for rearrangement, which is beneficial to increase the arrangement density of the transistor per unit area while avoiding signal interference between the transistor and the power supply structure, reducing wiring congestion at the back end of the line and providing power supply performance advantages, thereby enhancing the reliability of the chip. At the same time, it also helps to further shorten the process node. In addition, in the embodiment of the present disclosure, due to the provision of the stress absorption structure, in the process of forming the multiple structures included in the power supply structure, even if the process step of thinning the substrate is performed, the thermal stress generated by the above multiple structures during the formation process will be effectively absorbed by the stress absorption structure, thereby reducing the occurrence of defects such as structural delamination, cracks, and warping caused by poor heat dissipation and accumulation of thermal stress, and helping to improve the various performances of the semiconductor structure finally obtained.

[0073] It should be understood that although Figure 1 The steps in the process are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0074] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure in detail, for the convenience of explanation, the schematic diagram will not be partially enlarged according to the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present disclosure.

[0075] Figures 2 to 12 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure; Fig.13 A structural schematic diagram of the positional relationship between a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure provided in one embodiment of the present disclosure; Fig.14 A structural schematic diagram of the positional relationship between a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure provided in another embodiment of the present disclosure; Fig.15 A schematic structural diagram of the cross-sectional shape of a stress absorbing structure provided in an embodiment of the present disclosure; Fig.16 Schematic diagram of the structure of the stress absorption structure provided in different embodiments of the present disclosure.

[0076] The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is further described in detail below with reference to the accompanying drawings.

[0077] First, execute step S101, such as Figures 2 to 5 As shown, a substrate 10 is provided, and a buried power rail 11 and a device structure 12 are sequentially formed on a first surface S1 of the substrate 10 .

[0078] In some embodiments, Figure 2 and Figure 3 As shown, providing a substrate 10 includes:

[0079] Providing a substrate 101;

[0080] forming an etch stop layer 102 on the substrate 101;

[0081] A semiconductor layer 103 is formed on the etch stop layer 102 .

[0082] Here, the substrate 101 may be a semiconductor material; specifically, it may include a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material or other semiconductor materials known in the art. In a specific embodiment, the substrate is a silicon material. In some embodiments, the substrate 101 may include a wafer.

[0083] In some embodiments, the material of the etch stop layer 102 may include any suitable material that can achieve an etch stop function during the thinning operation of the substrate 10 , including but not limited to a silicon germanium layer.

[0084] In some embodiments, the semiconductor layer may include, but is not limited to, at least one of silicon, germanium, etc., or a combination thereof.

[0085] In some embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10, but is not limited thereto. In some other embodiments, the first surface S1 of the substrate 10 may also be the back side of the substrate 10. This is not specifically limited and can be flexibly selected according to actual conditions.

[0086] In some embodiments, a buried power rail 11 and a device structure 12 are sequentially formed on a first surface S1 of a substrate 10, including:

[0087] forming a second dielectric layer L2 on the semiconductor layer 103;

[0088] A groove structure (not marked in the figure) extending along a first direction is formed in the second dielectric layer L2 and the semiconductor layer 103, and the groove structure (not marked in the figure) does not expose the etching stop layer 102; the first direction is parallel to the first surface S1 of the substrate 10;

[0089] Performing a filling process to form a buried power rail 11 in the trench structure (not shown);

[0090] A device structure 12 is formed.

[0091] Here, the material of the second dielectric layer L2 may include but is not limited to insulating materials such as oxide, nitride or oxynitride. In some specific embodiments, the material of the second dielectric layer L2 may include but is not limited to silicon oxide (SiO x )wait.

[0092] In some embodiments, the material of the buried power rail 11 may be a conductive material, specifically, may include but is not limited to metal materials, such as one or more of Cu, Co, W, Ni and Ru. By selecting these materials, the resistivity of the buried power rail 11 is low, which is beneficial to improve RC delay, improve chip processing speed and power supply efficiency.

[0093] In some embodiments, the device structure 12 may include but is not limited to a transistor, etc. The buried power rail 11 may be used to supply power to the device structure 12. A wider buried power rail 11 is beneficial to increasing the volume of the power rail, thereby reducing the resistance of the buried power rail 11, and correspondingly reducing the power supply resistance, thereby improving the power supply efficiency of the device structure 12 and improving the voltage drop.

[0094] In some embodiments, after forming the semiconductor layer 103 , a second dielectric layer L2 with a relatively thin thickness may be formed first, and then a process of forming a trench structure (not shown) is performed, and then a process of filling a material to form a buried power rail 11 is performed.

[0095] Next, after forming the buried power rail 11, the step of forming the device structure 12 can be continued. During, before or after the formation of the device structure 12, a process of forming a second dielectric layer L2 located between the device structures 12 can be performed again to achieve an electrical insulation effect between adjacent device structures 12.

[0096] In some embodiments, after forming the device structure 12 , the preparation method further includes forming a conductive metal line structure 15 . The material of the conductive metal line structure 15 may include: a conductive metal, such as tungsten.

[0097] Then, step S102 is performed, as shown in FIG. Figure 8 and Fig. 9 As shown, a first dielectric layer L1 is formed on the second surface S2 of the substrate 10, and an etching process is performed on at least the first dielectric layer L1 to form a through-hole structure T and an opening structure H, wherein the opening structure H is located around the through-hole structure T, and the through-hole structure T exposes the buried power rail 11; wherein the first surface S1 and the second surface S2 are two surfaces of the substrate 10 arranged opposite to each other.

[0098] In some embodiments, the material of the first dielectric layer L1 may include but is not limited to insulating materials such as oxide, nitride or oxynitride, etc. In some specific embodiments, the material of the first dielectric layer L1 may include but is not limited to silicon oxide, etc.

[0099] In some embodiments, the through hole structure T and the opening structure H can be formed in the same process step, but are not limited thereto, and can also be formed in different process steps to improve production efficiency. The design method of the opening structure H is compatible with the current fab process flow, has a simple structure, and has strong matching versatility.

[0100] In some embodiments, the through hole structure T and the opening structure H can be obtained by using a photolithography process and a reactive ion etching process.

[0101] In some embodiments, Figure 7 and Figure 8 As shown, before forming the first dielectric layer L1 on the second surface S2 of the substrate 10, the preparation method further includes:

[0102] Thinning the substrate 10 from the second surface S2 to expose the etch stop layer 102;

[0103] The etch stop layer 102 is removed.

[0104] In some embodiments, the second surface S2 of the substrate 10 may be the back side of the substrate 10, but is not limited thereto. In some other embodiments, the second surface S2 of the substrate 10 may also be the front side of the substrate 10. This is not specifically limited and can be flexibly selected according to actual conditions.

[0105] It should be noted that in the embodiment of the present disclosure, the first surface S1 and the second surface S2 are two surfaces arranged opposite to each other. For example, when the first surface S1 is the front side, the second surface S2 may be the back side. Conversely, when the first surface S1 is the back side, the second surface S2 may be the front side.

[0106] In some specific embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10 , and the second surface S2 of the substrate 10 may be the back side of the substrate 10 .

[0107] In some embodiments, Figure 6 As shown, before the substrate 10 is thinned from the second surface S2 to expose the etching stop layer 102, the preparation method further includes:

[0108] Bonding a surface of the substrate 10 provided with the device structure 12 to a carrier 20;

[0109] The semiconductor structure is flipped 180° so that the second surface S2 of the substrate 10 faces upward.

[0110] Here, before the semiconductor structure is flipped, an operation process is performed to bond the side of the substrate 10 where the device structure 12 is provided to the carrier 20. This is to ensure that during the subsequent process steps, the carrier 20 can play an effective supporting role and protect the structure located on the first surface S1 of the substrate 10 from being scratched or damaged.

[0111] In some embodiments, an etching process is performed on at least the first dielectric layer L1 to form a through hole structure T and an opening structure H, including:

[0112] The first dielectric layer L1 and the semiconductor layer 103 are etched to form a through hole structure T and an opening structure H; wherein the through hole structure T and the opening structure H both expose the buried power rail 11 (for details, please refer to Fig. 9 ).

[0113] or,

[0114] In some other embodiments, an etching process is performed on the first dielectric layer L1 and the semiconductor layer 103 to form a through-hole structure T and an opening structure H; wherein the through-hole structure H exposes the buried power rail 11 , and the opening structure H does not expose the buried power rail 11 .

[0115] In the embodiment of the present disclosure, the opening structure H may have various positions and forms, for example:

[0116] In some cases, the opening structure H may be located directly above the buried power rail 11, or part of the opening structure H in the same opening structure H may be located directly above the buried power rail 11, and the remaining opening structure H is located around the buried power rail 11. In structures at different positions, the opening structure H may have different depths. For example, when the opening structure H has a greater depth, the opening structure H will expose the buried power rail 11 located thereunder, and when the opening structure H has a smaller depth, the opening structure H may not expose the buried power rail 11 located thereunder. Specifically, the depth of the opening structure H and whether the buried power rail 11 structure needs to be exposed may be determined according to actual needs, and no specific limitation is made here.

[0117] In other cases, the relationship between the opening structure H and the buried power rail 11 may be other cases, for example, any part of the same opening structure H may not be located directly above the buried power rail 11, but may be located on the surrounding area of ​​the buried power rail 11. In this case, the size of the opening structure H on the second surface S2 perpendicular to the substrate 10 may not be limited to the distance between the surface of the buried power rail S1 and the top of the first dielectric layer, but may be within a range of a depth greater than this distance. That is, compared with the previous embodiment, this embodiment is conducive to better achieving the absorption effect of the stress absorption structure 13 on thermal stress. Specifically, the numerical range of the opening structure H may be flexibly selected according to actual conditions, and is not specifically limited here.

[0118] In some embodiments, in order to meet the requirement that the stress absorption structure 13 formed after the opening structure H is filled with material in the subsequent step S103 can better absorb thermal stress, these thermal stresses may include thermal stresses generated in the process of preparing the required structure on the second surface of the substrate 10 or in other process processes, the ratio of the size of the opening structure H in the direction perpendicular to the second surface S2 of the substrate 10 to the size of the through-hole structure T in the direction perpendicular to the second surface S2 of the substrate 10 can be greater than 0 and less than or equal to 1.

[0119] In some embodiments, the ratio of the size of the opening structure H in the direction parallel to the second surface S2 to the size of the through-hole structure T in the direction parallel to the second surface S2 may be greater than 0 and less than or equal to 1.

[0120] In conventional structures, through-hole structures, materials filled in through-hole structures, buried power rails and device structures are usually located on the same surface of the substrate. In this case, more area of ​​the substrate plane is occupied. Since these structures are close to each other, signal interference and other problems often occur. In addition, this layout method will also lead to wiring congestion in the subsequent process, increasing power loss.

[0121] In addition, since the above structures are all arranged on the same surface of the substrate, after the front-end process is completed, the operating space reserved for the back-end process is severely reduced, which is not conducive to the convenience of process operation and is not conducive to further shortening the process node.

[0122] In the embodiment of the present disclosure, the conductive structure obtained after the filling process of the subsequent step S103 is performed on the through-hole structure can be used as the power supply structure of the semiconductor structure. In this way, the power supply structure originally arranged on the same surface as the transistor is transferred to the back of the transistor for rearrangement, which is beneficial to increase the transistor arrangement density per unit area while avoiding signal interference between the transistor and the power supply structure, reducing wiring congestion at the back end of the line and providing power supply performance advantages, and enhancing chip reliability. At the same time, in the embodiment of the present disclosure, this structural layout can also free up more space for the implementation of the back-end process, reduce the area occupied by the interconnection line on the surface of the substrate where the device structure is arranged, and help to further shorten the process node.

[0123] It is understandable that in the process of preparing multiple structures located on the second surface S2 of the substrate 10, it is usually necessary to perform a process of thinning the substrate 10 (for example, in some structures, the substrate is thinned by 300nm, but not limited to this, and can also be other thicknesses) so that the final semiconductor structure has a lighter weight and a smaller volume. In addition, since these structures usually need to be made of materials involving different systems, such as but not limited to metal materials, semiconductor materials, and dielectric materials, and materials of different systems need to undergo different heat treatment conditions, the semiconductor structure will undergo a more complex heat treatment process during the preparation process, which will easily lead to the continuous accumulation of thermal stress in the structure, which will in turn affect the thermal stability of the structure and lead to a reduction in product yield.

[0124] In the embodiment of the present disclosure, since an opening structure H is provided around the through-hole structure T, the opening structure H will be filled with a material having a preset thermal expansion coefficient in the subsequent process step S103, so that the thermal stress generated during the preparation of multiple structures located on the back side of the substrate 10 can be effectively absorbed, thereby effectively reducing the occurrence of defects such as structural delamination, cracks, and warping, and helping to improve the various performances of the semiconductor structure finally obtained.

[0125] Finally, step S103 is executed. Fig.10 and Fig.11 As shown, a filling process is performed to form a stress absorption structure 13 in the opening structure H and a conductive structure 14 in the through-hole structure T.

[0126] Here, the conductive structure 14 may be a through silicon via (TSV) structure.

[0127] In some embodiments, a filling process is performed to form a stress absorption structure 13 in the opening structure H and a conductive structure 14 in the through-hole structure T, including:

[0128] Filling the opening structure H with a material having a preset thermal expansion coefficient to form a stress absorbing structure 13;

[0129] A conductive material is filled into the through-hole structure T to form a conductive structure 14 .

[0130] In some embodiments, the material used to form the stress absorption structure 13 may include but is not limited to a material with a relatively low thermal expansion coefficient. The material used to form the conductive structure 14 may include but is not limited to a conductive metal, such as tungsten.

[0131] In some specific embodiments, a chemical vapor deposition process may be used to deposit an organic polymer with high toughness and low thermal expansion coefficient, such as a high temperature resistant bismaleimide resin, in the opening structure H to obtain the stress absorption structure 13 .

[0132] In some embodiments, the predetermined thermal expansion coefficient of the material filled in the opening structure H is in a range greater than 0 and less than or equal to 3 ppm / K.

[0133] It can be understood that in the embodiment of the present disclosure, the through hole structure T and the opening structure H can be formed in the same process step to facilitate the improvement of production efficiency. At the same time, although the stress absorption structure 13 is added in the embodiment of the present disclosure, the structure can have good compatibility with the process of forming the conductive structure 14 during the formation process, that is, the design method provided by the embodiment of the present disclosure is compatible with the process flow of the current semiconductor structure preparation process, and the obtained stress absorption structure 13 has the characteristics of simple structure and strong matching versatility.

[0134] In some embodiments, in a direction parallel to the second surface S2 of the substrate 10 , the cross-sectional shape of the stress absorption structure 13 includes at least one of a circle, an ellipse, a triangle, a quadrilateral, a regular hexagon, a polygon and an irregular shape, or a combination thereof.

[0135] In some embodiments, step S103 may be performed in the order of first filling the opening structure H to form the stress absorption structure 13 and then filling the through-hole structure T to form the conductive structure 14, but not limited thereto. Step S103 may also be performed in the order of first filling the through-hole structure T to form the conductive structure 14 and then filling the opening structure H to form the stress absorption structure 13. Regardless of the order, due to the formation of the stress absorption structure 13, the thermal stress generated during the preparation process of the structure on the second surface S2 of the substrate 10 is effectively absorbed, which can effectively alleviate the occurrence of defects such as structural delamination, cracks, and warping.

[0136] It can be understood that, compared with other embodiments, in the embodiment in which step S103 can be performed in the order of first filling the opening structure H to form the stress absorption structure 13 and then filling the through-hole structure T to form the conductive structure, since a structure capable of absorbing thermal stress is pre-formed before forming the conductive structure 14, the thermal stress generated in the process of forming the conductive structure 14 can be effectively absorbed, thereby more effectively reducing the thermomechanical strain caused by the mismatch of the thermal expansion coefficient of the material, and more helpful to ultimately achieve the effect of improving wafer warping and reducing structural thermomechanical stress.

[0137] In some embodiments, Fig.12 and Fig.13 and Fig.14 As shown, after forming the stress absorption structure 13 and the conductive structure 14, the preparation method further includes:

[0138] A metallization process is performed to form a metal line structure 16 above the conductive structure. An area formed by the intersection of the orthographic projections of the buried power rail 11 and the metal line structure 16 on the second surface S2 of the substrate 10 is defined as an intersection area A. The conductive structure 14 is located on part of the intersection area A, and the stress absorption structure 13 is located around the conductive structure 14.

[0139] In some embodiments, the material of the metal line structure 16 may include any suitable conductive metal, such as copper, tungsten, etc.

[0140] In some embodiments, Fig.13 As shown, the intersection area A includes a first area A1 and a second area A2, the conductive structure 14 is located on the first area A1, the stress absorption structure 13 is at least located on the second area A2, and along the extension direction of the metal line structure 16, the conductive structure 14 and the stress absorption structure 13 are arranged alternately.

[0141] In other embodiments, Fig.14 As shown, the intersection area A includes a first area A1 provided with a conductive structure 14 and a second area A2 not provided with a conductive structure 14 . In the extending direction of the buried power rail 11 , the stress absorption structure 13 is at least located between the first area A1 and the second area A2 .

[0142] In some other embodiments, the stress absorption structure 13 may be located around the conductive structure 14, but not within the range defined by the orthographic projections of the buried power rail 11 and the metal line structure 16 on the substrate. Instead, at least part of the stress absorption structure is located outside the range defined by the orthographic projections of the buried power rail 11 and the metal line structure 16 on the substrate.

[0143] However, it is not limited thereto. In some embodiments, the position where the stress absorption structure 13 is arranged may also be a combination of at least two of the positions provided in any of the above embodiments. For example, the stress absorption structure 13 may include a structure located on the second region A2 of the intersection region A and a structure between the first region A1 and the second region A2 of the intersection region A; or, the stress absorption structure 13 may also include a structure located on the second region A2 of the intersection region A and a structure at least partially located outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate; or, the stress absorption structure 13 may also include a structure located between the first region A1 and the second region A2 of the intersection region A and a structure at least partially located outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate. Specifically, in actual operation, it may be flexibly selected according to actual conditions, and no specific limitation is made here.

[0144] In any of the above embodiments, the number of stress absorbing structures 13 located at the same position includes 1 or more, such as 2, 3, 4, 5 or even more, and the number of stress absorbing structures 13 located at different positions may be the same or different, and similarly, the sizes of stress absorbing structures 13 located at different positions parallel to (or perpendicular to) the second surface S2 of the substrate 10 may be the same or different. Specifically, whether the number of stress absorbing structures 13 at the position needs to be increased or decreased and whether the size of the stress absorbing structures 13 needs to be increased or decreased may be flexibly selected according to actual conditions, such as whether thermal stress accumulation is likely to occur, and no specific limitation is made herein.

[0145] It is understandable that in actual operation, the number and size of the stress absorbing structures can be flexibly selected according to the actual situation and the design manual to balance the relationship between thermal stress absorption and area occupancy.

[0146] The present disclosure also provides a semiconductor structure, such as Fig.12 As shown, the semiconductor structure includes:

[0147] Substrate 10;

[0148] The buried power rail 11 and the device structure 12 are arranged from bottom to top on the first surface S1 of the substrate 10;

[0149] A first dielectric layer L1 is located on the second surface S2 of the substrate 10;

[0150] The stress absorption structure 13 and the conductive structure 14 , part of the conductive structure 14 and at least part of the stress absorption structure 13 are located in the first dielectric layer L1 , and the stress absorption structure 13 is located around the conductive structure 14 ; wherein the conductive structure 14 penetrates the first dielectric layer L1 and is connected to the buried power rail 11 .

[0151] In the embodiment of the present disclosure, the first surface S1 and the second surface S2 are two surfaces arranged opposite to each other. For example, when the first surface S1 is the front side, the second surface S2 may be the back side. Conversely, when the first surface S1 is the back side, the second surface S2 may be the front side.

[0152] In some specific embodiments, the first surface S1 of the substrate 10 may be the front side of the substrate 10 , and the second surface S2 of the substrate 10 may be the back side of the substrate 10 .

[0153] Here, the conductive structure can be used as a power supply structure for the semiconductor structure.

[0154] In the embodiment of the present disclosure, the power supply structure originally arranged together with the transistor is directly transferred to the back side of the transistor for rearrangement, which is beneficial to increase the arrangement density of the transistors per unit area while avoiding signal interference between the transistors and the power supply structure, reducing wiring congestion at the back end of the line and providing power supply performance advantages, thereby enhancing the reliability of the chip. At the same time, it also helps to further shorten the process node. In addition, in the embodiment of the present disclosure, due to the provision of a stress absorption structure, in the process of forming the multiple structures included in the power supply structure, even if the process step of thinning the substrate is performed, the thermal stress generated by the above-mentioned multiple structures during the formation process will be effectively absorbed by the stress absorption structure, thereby reducing the occurrence of defects such as structural delamination, cracks, and warping caused by poor heat dissipation and accumulation of thermal stress, and helping to improve the various performances of the semiconductor structure finally obtained.

[0155] In some embodiments, the material used to form the conductive structure 14 may include, but is not limited to, conductive metals such as tungsten.

[0156] In some embodiments, the stress absorbing structure includes a material having a predetermined coefficient of thermal expansion.

[0157] In some embodiments, the predetermined thermal expansion coefficient of the material filled in the opening structure H is in a range greater than 0 and less than or equal to 3 ppm / K.

[0158] In some specific embodiments, a chemical vapor deposition process may be used to deposit an organic polymer with high toughness and low thermal expansion coefficient, such as a high temperature resistant bismaleimide resin, in the opening structure H to obtain the stress absorption structure 13 .

[0159] In some embodiments, Fig.15As shown, in a direction parallel to the second surface S2 of the substrate 10 , the cross-sectional shape of the stress absorption structure 13 includes at least one of a circle, an ellipse, a triangle, a quadrilateral, a regular hexagon, a polygon and an irregular shape, or a combination thereof.

[0160] In some embodiments, Fig.12 and Fig.16 As shown, along the direction from the first surface S1 to the second surface S2, the stress absorption structure 13 includes a first sub-portion 131 and a second sub-portion 132, and the thermal expansion coefficients of the first sub-portion 131 and the second sub-portion 132 are different (for details, please refer to Fig.16 (1) in Figure );

[0161] and / or,

[0162] Along the direction parallel to the second surface S2, the stress absorption structure 13 includes a first sublayer 13a and a second sublayer 13b from the inside to the outside, and the thermal expansion coefficients of the first sublayer 13a and the second sublayer 13b are different (for details, please refer to Fig.16 (Figure 2) in the figure).

[0163] It can be understood that when the stress absorption structure 13 is provided with a first sub-portion 131 and a second sub-portion with different thermal expansion coefficients, and / or a first sub-layer 13a and a second sub-layer 13b with different thermal expansion coefficients, it is equivalent to the effect of providing multiple stress absorption structures 13 at a single setting position, so that at this position, the stress absorption structures 13 located in different areas can achieve different thermal stress absorption effects, which helps designers to carry out targeted design according to the distribution of thermal stress, thereby meeting the demand for thermal stress absorption during the preparation process of the semiconductor structure, thereby reducing the thermomechanical strain caused by the mismatch of the thermal expansion coefficient of the material, and helping to ultimately achieve the effect of improving wafer warping and reducing structural thermomechanical stress.

[0164] In some embodiments, Fig.13 As shown, the intersection area A includes a first area A1 and a second area A2, the conductive structure 14 is located on the first area A1, the stress absorption structure 13 is at least located on the second area A2, and along the extension direction of the metal line structure 16, the conductive structure 14 and the stress absorption structure 13 are arranged alternately.

[0165] In other embodiments, Fig.14 As shown, the intersection area A includes a first area A1 provided with a conductive structure 14 and a second area A2 not provided with a conductive structure 14 . In the extending direction of the buried power rail 11 , the stress absorption structure 13 is at least located between the first area A1 and the second area A2 .

[0166] In some other embodiments, the stress absorption structure 13 may be located around the conductive structure 14, but not within the range defined by the orthographic projections of the buried power rail 11 and the metal line structure 16 on the substrate. Instead, at least part of the stress absorption structure is located outside the range defined by the orthographic projections of the buried power rail 11 and the metal line structure 16 on the substrate.

[0167] However, it is not limited thereto. In some embodiments, the position where the stress absorption structure 13 is arranged may also be a combination of at least two of the positions provided in any of the above embodiments. For example, the stress absorption structure 13 may include a structure located on the second region A2 of the intersection region A and a structure between the first region A1 and the second region A2 of the intersection region A; or, the stress absorption structure 13 may also include a structure located on the second region A2 of the intersection region A and a structure at least partially located outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate; or, the stress absorption structure 13 may also include a structure located between the first region A1 and the second region A2 of the intersection region A and a structure at least partially located outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate. Specifically, in actual operation, it may be flexibly selected according to actual conditions, and no specific limitation is made here.

[0168] In any of the above embodiments, the number of stress absorbing structures 13 located at the same position includes 1 or more, such as 2, 3, 4, 5 or even more, and the number of stress absorbing structures 13 located at different positions may be the same or different, and similarly, the sizes of stress absorbing structures 13 located at different positions parallel to (or perpendicular to) the second surface S2 of the substrate 10 may be the same or different. Specifically, whether the number of stress absorbing structures 13 at the position needs to be increased or decreased and whether the size of the stress absorbing structures 13 needs to be increased or decreased may be flexibly selected according to actual conditions, such as whether thermal stress accumulation is likely to occur, and no specific limitation is made herein.

[0169] It is understandable that in actual operation, the number and size of the stress absorbing structures can be flexibly selected according to the actual situation and the design manual to balance the relationship between thermal stress absorption and area occupancy.

[0170] It should be noted that the semiconductor structure and the method for manufacturing the same provided by the embodiments of the present disclosure can be applied to any semiconductor device including the structure, and no further limitation is given here. The embodiments of the method for manufacturing the semiconductor device provided by the present disclosure and the embodiments of the semiconductor device belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0171] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises: Providing a substrate, and sequentially forming a buried power rail and a device structure on a first surface of the substrate; A first dielectric layer is formed on the second surface of the substrate, and an etching process is performed on at least the first dielectric layer to form a through-hole structure and an opening structure, wherein the opening structure is located around the through-hole structure, and the through-hole structure exposes the buried power rail; wherein the first surface and the second surface are two surfaces of the substrate arranged opposite to each other; A filling process is performed to form a stress absorbing structure in the opening structure and a conductive structure in the through-hole structure.

2. The preparation method according to claim 1, characterized in that: Substrates include: providing a substrate; forming an etch stop layer on the substrate; A semiconductor layer is formed on the etch stop layer.

3. The preparation method according to claim 2, characterized in that: A buried power rail and a device structure are sequentially formed on the first surface of the substrate, including: forming a second dielectric layer on the semiconductor layer; forming a trench structure extending along a first direction in the second dielectric layer and the semiconductor layer, wherein the trench structure does not expose the etch stop layer; performing a filling process to form the buried power rail in the trench structure; The device structure is formed.

4. The preparation method according to claim 2, characterized in that: Before forming the first dielectric layer on the second surface of the substrate, the preparation method further includes: thinning the substrate from the second surface to expose the etch stop layer; The etch stop layer is removed.

5. The preparation method according to claim 4, characterized in that: Performing an etching process on at least the first dielectric layer to form a through-hole structure and an opening structure, comprising: Performing an etching process on the first dielectric layer and the semiconductor layer to form the through-hole structure and the opening structure; wherein both the through-hole structure and the opening structure expose the buried power rail; or, An etching process is performed on the first dielectric layer and the semiconductor layer to form the through-hole structure and the opening structure; wherein the through-hole structure exposes the buried power rail, and the opening structure does not expose the buried power rail.

6. The preparation method according to any one of claims 1 to 5, characterized in that: Performing a filling process to form the stress absorption structure in the opening structure and the conductive structure in the through-hole structure comprises: Filling the opening structure with a material having a preset thermal expansion coefficient to form the stress absorbing structure; A conductive material is filled into the through-hole structure to form the conductive structure.

7. The preparation method according to claim 1, characterized in that: After forming the stress absorption structure and the conductive structure, the preparation method further comprises: A metallization process is performed to form a metal line structure above the conductive structure, and an area formed by the intersection of the buried power rail and the orthographic projection of the metal line structure on the second surface of the substrate is defined as an intersection area, the conductive structure is located on part of the intersection area, and the stress absorption structure is located around the conductive structure.

8. The preparation method according to claim 7, characterized in that: The intersection region includes a first region and a second region, the conductive structure is located on the first region, the stress absorption structure is located at least on the second region, and the conductive structure and the stress absorption structure are arranged alternately along the extending direction of the metal wire structure.

9. The preparation method according to claim 7, characterized in that: The intersection region includes a first region provided with the conductive structure and a second region not provided with the conductive structure, and in the direction along which the buried power rail extends, the stress absorption structure is at least located between the first region and the second region.

10. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; A buried power rail and device structure are arranged from bottom to top on the first surface of the substrate; A first dielectric layer, located on the second surface of the substrate; A stress absorption structure and a conductive structure, part of the conductive structure and at least part of the stress absorption structure are located in the first dielectric layer, and the stress absorption structure is located around the conductive structure; wherein the conductive structure penetrates the first dielectric layer and is connected to the buried power rail.

11. The semiconductor structure according to claim 10, characterized in that: The stress absorbing structure includes a material having a predetermined coefficient of thermal expansion.

12. The semiconductor structure according to claim 10, characterized in that Along the direction from the first surface to the second surface, the stress absorbing structure includes a first sub-portion and a second sub-portion, and the first sub-portion and the second sub-portion have different thermal expansion coefficients; and / or, Along a direction parallel to the second surface, the stress absorption structure includes a first sub-layer and a second sub-layer from inside to outside, and the first sub-layer and the second sub-layer have different thermal expansion coefficients.

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