A high voltage power supply circuit for a test apparatus

Abstract

The application provides a high-voltage power supply circuit of a test device, which is independent of the test device, and can have N high-voltage output channels, and can be assembled according to the high-voltage power supply circuit, and a function board card can be designed according to user requirements, so that the cost problem caused by the integration of redundant functions of the function board card is avoided, and the production cost of the customized board card is reduced; meanwhile, the voltage and current of each high-voltage unit can be collected, and the channel selection and the working mode of each high-voltage unit can be independently controlled, so that the high-voltage output performance of the high-voltage unit is improved; in addition, N high-voltage unit multiplexing controllers, DAC modules, ADC modules, OPA modules and multiplexing selection circuits and the like are used to reduce the cost; the number of high-voltage units is multiple, and multiple devices to be tested can be tested in parallel, so that the test efficiency is improved.

Description

Technical Field

[0001] This invention belongs to the field of testing technology, and more specifically, relates to a high-voltage power supply circuit for a testing device. Background Technology

[0002] In the field of highly integrated and precise electronic product testing, the ability to withstand high voltage (HV) and perform simultaneous measurements (i.e., testing multiple units or parameters at the same time) is a key indicator for evaluating the performance of testing equipment. Currently, advanced testing machines such as the Magnum 2 and T5830 meet this need with their superior performance.

[0003] Taking the T5830 as an example, its built-in HV LVL DR module is a major highlight in the high-voltage testing field. This module consists of 48 independent units, each capable of outputting up to 30V and operating stably at a maximum current of 90mA. This design not only ensures testing accuracy but also achieves an impressive scalability of 288 high-voltage output channels through the flexibility of configuring each unit to six branches. Furthermore, the T5830 allows users to combine every two units into a Management Cell (MC) and flexibly configure it to VSIM (Virtual Simulation Mode) or MVM (Multi-Variable Measurement) mode according to testing needs, further enhancing testing flexibility and efficiency. The Magnum 2, with a similar structure to the T5830, also possesses these advanced features.

[0004] While high-end testing machines like the Magnum 2 and T5830 excel in high-voltage and high-volume measurements, their cost is a significant concern. For example, the Magnum 2's exorbitant price (approximately 7 to 8 million RMB) often deters many potential users. Even more regrettably, due to the modular design of these testing machines, users often cannot purchase the necessary HV modules separately and must bear the full cost of the entire machine, undoubtedly increasing testing costs and limiting the effective utilization of testing resources. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a high-voltage power supply circuit for a test device, which can be assembled independently of the test device according to requirements and reduce test costs.

[0006] This application discloses a high-voltage power supply circuit for a test device, the high-voltage power supply circuit being independent of the test device; the high-voltage power supply circuit includes: a controller, a DAC module, an OPA module, an ADC module, and M high-voltage output circuits; the high-voltage output circuits include: a multiplexing selection circuit, N high-voltage channel selection circuits, and N high-voltage units, the multiplexing selection circuits including: an ADC channel selection circuit, a VSIM channel selection circuit, and an MVM channel selection circuit; M is a positive integer, and N is an integer greater than 1; wherein:

[0007] The N high-voltage channel selection circuits and the N high-voltage units correspond one-to-one;

[0008] The first end of the controller is connected in sequence to one end of the high-voltage channel selection circuit through the DAC module, the OPA module, the high-voltage unit, and the DAC module.

[0009] The other end of the high-voltage channel selection circuit serves as an output terminal of the high-voltage power supply circuit and is connected to the device under test.

[0010] The second terminal of the controller is connected to the output terminal of the ADC module;

[0011] The four input terminals of the ADC module correspond one-to-one with the four output terminals of the ADC channel selection circuit; each input terminal of the ADC module is connected to each output terminal of the ADC channel selection module.

[0012] The two first input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is connected to each output terminal of the VSIM channel selection circuit.

[0013] The two second input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is connected to each output terminal of the MVM channel selection circuit.

[0014] The two input terminals of the VSIM channel selection circuit are connected to the positive and negative terminals of the current sampling terminal in the high-voltage unit, respectively.

[0015] The input terminal of the MVM channel selection circuit is connected to the voltage sampling terminal of the high-voltage unit;

[0016] The ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high-voltage unit, and the high-voltage channel selection circuit are all controlled by the controller.

[0017] Optionally, the OPA module includes: an in-phase adder and a follower;

[0018] The input terminal of the in-phase adder is connected to the output terminal of the DAC module;

[0019] The output of the in-phase adder is connected to the input of the follower;

[0020] The output terminal of the follower serves as the output terminal of the OPA module.

[0021] The positive power supply terminals of the in-phase adder and the follower are both connected to a 30V power supply.

[0022] The negative power supply terminals of the in-phase adder and the follower are both connected to a -5V power supply.

[0023] Optionally, the non-inverting adder includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, and a first capacitor;

[0024] One end of the third resistor serves as the input terminal of the in-phase adder;

[0025] The non-inverting input terminal of the first operational amplifier is connected to the other end of the third resistor, one end of the fourth resistor, and one end of the first capacitor, respectively.

[0026] The negative inverting input terminal of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor, respectively;

[0027] The output terminal of the first operational amplifier is connected to the other end of the second resistor, and the connection point serves as the output terminal of the non-inverting adder.

[0028] The positive and negative terminals of the first operational amplifier are respectively used as the positive and negative terminals of the non-inverting adder;

[0029] The other end of the fourth resistor is connected to a reference power supply; the other end of the first capacitor and the other end of the first resistor are grounded.

[0030] Optionally, the follower includes: two follower units; the connection point after the input terminals of the two follower units are connected serves as the input terminal of the follower; the output terminals of the two follower units serve as the output terminals of the follower.

[0031] The follower unit includes: a second operational amplifier, a fifth resistor, and a sixth resistor;

[0032] The non-inverting input terminal of the second operational amplifier serves as the input terminal of the follower unit;

[0033] The negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, one end of the fifth resistor, and one end of the sixth resistor, respectively.

[0034] The other end of the sixth resistor is grounded;

[0035] The other end of the fifth resistor serves as the output terminal of the follower unit;

[0036] The positive and negative terminals of the power supply of the second operational amplifier serve as the positive and negative terminals of the power supply of the follower unit.

[0037] Optionally, N is 16; the OPA module has 2 output terminals;

[0038] The input terminals of eight of the high-voltage units are connected to one output terminal of the OPA module;

[0039] The input terminals of the other eight high-voltage units are connected to another output terminal of the OPA module.

[0040] Optionally, the high-voltage unit includes: an HV operational amplifier circuit, a current sampling circuit, and a switching unit; the HV operational amplifier circuit includes: a high-voltage operational amplifier, a seventh resistor, an eighth resistor, and a ninth resistor; the current sampling circuit includes: a tenth resistor and a first switch; the switching unit includes: a second switch and a third switch.

[0041] The non-inverting input terminal of the high-voltage operational amplifier serves as the input terminal of the high-voltage unit.

[0042] The negative input terminal of the high-voltage operational amplifier is connected to one end of the seventh resistor;

[0043] The output terminal of the high-voltage operational amplifier is connected to one end of the eighth resistor and one end of the ninth resistor, respectively, and the connection point serves as the positive terminal of the current sampling terminal of the high-voltage unit.

[0044] The other end of the ninth resistor is connected to one end of the third switch, one end of the eighth resistor, and one end of the first switch, respectively, and the connection point serves as the negative terminal of the current sampling terminal of the high-voltage unit.

[0045] The other end of the seventh resistor is connected to the other end of the eighth resistor and one end of the second switch, respectively, and the connection point serves as the voltage sampling terminal of the high-voltage unit.

[0046] The other end of the first switch is connected to the other end of the tenth resistor;

[0047] The other end of the second switch serves as the first output terminal of the high-voltage unit;

[0048] The other end of the third switch serves as the second output terminal of the high-voltage unit.

[0049] Optionally, the high-voltage channel selection circuit includes: a first channel switch and a second channel switch;

[0050] One end of the first channel switch is connected to the first output terminal of the high-voltage unit;

[0051] One end of the second channel switch is connected to the second output terminal of the high-voltage unit;

[0052] The other end of the first channel switch is connected to the other end of the second channel switch, and the connection point serves as the output terminal of the high-voltage channel selection circuit.

[0053] Optionally, the ADC channel selection circuit includes: four MUX switches, four MUX operational amplifiers, and four MUX resistors;

[0054] One end of the first MUX switch serves as a first input terminal of the ADC channel selection circuit; the other end of the first MUX switch is connected to one end of the first MUX resistor and the positive input terminal of the first MUX operational amplifier; the other end of the first MUX resistor is grounded; the positive terminal of the power supply terminal of the first MUX operational amplifier is connected to a positive power supply; the negative terminal of the power supply terminal of the first MUX operational amplifier is connected to a negative power supply; the output terminal of the first MUX operational amplifier serves as the first output terminal of the ADC channel selection circuit.

[0055] One end of the second MUX switch serves as another first input terminal of the ADC channel selection circuit; the other end of the second MUX switch is connected to one end of the second MUX resistor and the positive input terminal of the second MUX operational amplifier; the other end of the second MUX resistor is grounded; the output terminal of the second MUX operational amplifier serves as the second output terminal of the ADC channel selection circuit.

[0056] One end of the third MUX switch serves as a second input terminal of the ADC channel selection circuit; the other end of the third MUX switch is connected to one end of the third MUX resistor and the positive input terminal of the third MUX operational amplifier; the other end of the third MUX resistor is grounded; the positive terminal of the power supply of the third MUX operational amplifier is connected to a positive power supply; the negative terminal of the power supply of the third MUX operational amplifier is connected to a negative power supply; the output terminal of the third MUX operational amplifier serves as the third output terminal of the ADC channel selection circuit.

[0057] One end of the fourth MUX switch serves as another second input terminal of the ADC channel selection circuit; the other end of the fourth MUX switch is connected to one end of the fourth MUX resistor and the positive input terminal of the fourth MUX operational amplifier respectively; the other end of the fourth MUX resistor is grounded; and the output terminal of the fourth MUX operational amplifier serves as the fourth output terminal of the ADC channel selection circuit.

[0058] Optionally, the VSIM channel selection circuit includes: two first multiplexing circuits; the first multiplexing circuit includes: a first multiplexing chip, a fifth MUX operational amplifier, a sixth MUX operational amplifier, a gain chip, and four multiplexing resistors;

[0059] The first multiplexing chip has its VDD pin connected to the positive power supply; its VSS pin connected to the negative power supply; and its EPAD and GND pins grounded.

[0060] The non-inverting input terminal of the fifth MUX operational amplifier is connected to the DA pin of the first multiplexer chip;

[0061] The negative input terminal of the fifth MUX operational amplifier is connected to the output terminal of the fifth MUX operational amplifier, one end of the first multiplexed resistor, and one end of the second multiplexed resistor;

[0062] The non-inverting input terminal of the sixth MUX operational amplifier is connected to the DB pin of the first multiplexer chip;

[0063] The other end of the first multiplexed resistor is connected to the -INA pin of the gain chip;

[0064] The negative input terminal of the sixth MUX operational amplifier is connected to the output terminal of the sixth MUX operational amplifier, one end of the third multiplexing resistor, and one end of the fourth multiplexing resistor;

[0065] The other end of the third multiplexing resistor is connected to the +INA pin of the gain chip;

[0066] The other end of the second multiplexed resistor, the other end of the fourth multiplexed resistor, and the REF pin of the gain chip are all grounded;

[0067] The positive power supply terminals of the fifth MUX operational amplifier, the sixth MUX operational amplifier, and the gain chip are connected to a positive power supply.

[0068] The negative power supply terminals of the fifth MUX operational amplifier, the sixth MUX operational amplifier, and the gain chip are connected to a negative power supply.

[0069] The OUT pin of the gain chip is connected to the anode of the first diode, and the connection point serves as the output terminal of the first multiplexing circuit.

[0070] The input terminal of the first multiplexing chip serves as the input terminal of the first multiplexing circuit;

[0071] The cathode of the first diode receives the first clamping voltage.

[0072] Optionally, the MVM channel selection circuit includes: two second multiplexing circuits, each of which includes: a second multiplexing chip and a seventh MUX operational amplifier;

[0073] The input terminal of the second multiplexing chip serves as the input terminal of the second multiplexing circuit;

[0074] The D pin of the second multiplexing chip is connected to one end of the fifth multiplexing resistor;

[0075] The other end of the fifth multiplexing resistor is connected to the non-inverting input terminal of the seventh MUX operational amplifier and one end of the sixth multiplexing resistor, respectively, and the other end of the sixth multiplexing resistor is grounded.

[0076] The negative inverting input terminal of the seventh MUX operational amplifier is connected to one end of the seventh multiplexed resistor and one end of the eighth multiplexed resistor, respectively.

[0077] The other end of the seventh multiplexing resistor receives a bias voltage;

[0078] The output terminal of the seventh MUX operational amplifier is connected to the other end of the eighth multiplexing resistor and the anode of the second diode, and the connection point serves as the output terminal of the second multiplexing circuit.

[0079] The cathode of the second diode receives the second clamping voltage.

[0080] As can be seen from the above technical solution, the high-voltage power supply circuit of the test equipment provided by the present invention is independent of the test equipment and can have N high-voltage output channels. It can be assembled based on the high-voltage power supply circuit, and functional boards can be customized according to user needs, avoiding the cost problems caused by redundant functions integrated into functional boards and reducing product production costs. Simultaneously, it can collect the voltage and current of each high-voltage unit and independently control the channel selection and operating mode of each high-voltage unit, improving the high-voltage output performance of the high-voltage units. Furthermore, the N high-voltage units reuse controllers, DAC modules, ADC modules, OPA modules, and multiplexing selection circuits, reducing costs. The multiple high-voltage units can support parallel testing of multiple devices under test, improving testing efficiency. Attached Figure Description

[0081] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0082] Figure 1This is a schematic diagram of a high-voltage power supply circuit for a testing device provided in an embodiment of the present invention;

[0083] Figure 2 This is a schematic diagram of the DAC module involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0084] Figure 3 This is a schematic diagram of the OPA module involved in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0085] Figure 4 This is a schematic diagram of the in-phase adder involved in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0086] Figure 5 This is a schematic diagram of a follower involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0087] Figure 6 This is a schematic diagram of the high-voltage output channel in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0088] Figure 7 This is a schematic diagram of the integrated module of the high-voltage unit involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0089] Figure 8 This is another schematic diagram of the integrated module of the high-voltage unit involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0090] Figure 9 This is a schematic diagram of the high-voltage unit involved in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0091] Figure 10 This is a schematic diagram of the high-voltage channel selection circuit involved in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0092] Figure 11 This is a schematic diagram of the sampling module involved in the high-voltage power supply circuit of a testing device provided in an embodiment of the present invention;

[0093] Figure 12 This is a schematic diagram of the VSIM channel selection circuit involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0094] Figure 13 This is a schematic diagram of the MVM channel selection circuit involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0095] Figure 14This is a schematic diagram of the ADC channel selection circuit involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention;

[0096] Figure 15 This is a schematic diagram of the ADC module involved in the high-voltage power supply circuit of a test device provided in an embodiment of the present invention. Detailed Implementation

[0097] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0098] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Furthermore, the terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data used can be interchanged where appropriate so that embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein.

[0099] This application provides a high-voltage power supply circuit for a testing device, which addresses the problem that in the modular design of existing testing machines, users often cannot purchase the required HV modules separately and must bear the entire cost of the machine, which undoubtedly increases testing costs and limits the effective utilization of testing resources.

[0100] The high-voltage power supply circuit is independent of the test equipment. This means that users can purchase the high-voltage power supply circuit separately and then assemble it to obtain the test equipment they need. This assembly method allows for more personalized configuration and avoids the cost issues caused by integrating redundant functions.

[0101] See Figure 1 The high-voltage power supply circuit includes: a controller, a DAC module, an OPA module, an ADC module, and M high-voltage output circuits.

[0102] A DAC module, or Digital-to-Analog Converter, is an electronic component that converts digital signals into analog signals. Its main components include a digital signal processing module, a digital-to-analog conversion module, a digital signal output module, and an analog signal processing module. The DAC module receives digital signals, processes and converts them internally, and ultimately outputs analog signals. This conversion is widely used in various fields such as audio, video, and communications. For example, in an audio system, a DAC module can convert digital audio signals into analog audio signals for playback through speakers.

[0103] Performance metrics for a DAC module include resolution and refresh rate. Resolution determines the accuracy of the analog signals the DAC can generate, while the refresh rate determines the speed at which the DAC can process digital signals. DAC modules with high resolution and fast refresh rates can provide higher quality analog signal output.

[0104] An OPA module, typically referring to an operational amplifier, is a circuit unit with very high amplification. An operational amplifier contains multiple stages of amplification circuitry, enabling the amplification and processing of weak signals. Operational amplifiers have various applications, such as signal amplification, filtering, and comparison. In electronic systems, operational amplifiers are often used as the core component of signal conditioning circuits to improve the system's signal processing capabilities and accuracy.

[0105] The main parameters of an operational amplifier include input offset voltage, open-loop voltage gain, and closed-loop bandwidth. These parameters determine the performance of the operational amplifier. For example, the smaller the input offset voltage, the higher the accuracy of the operational amplifier; the larger the open-loop voltage gain, the stronger the amplification capability of the operational amplifier.

[0106] An ADC module, or Analog-to-Digital Converter, is an electronic component that converts analog signals into digital signals. The main components of an ADC module include an analog signal sampling module, an analog signal processing module, an analog-to-digital conversion module, and a digital signal processing module. The ADC module acquires analog signals, processes and converts them internally, and finally outputs digital signals. This conversion is widely used in many fields such as digital signal processing and control systems.

[0107] The performance metrics of an ADC module include resolution and sampling rate. Resolution determines the accuracy of the analog signals the ADC can recognize, while the sampling rate determines the speed at which the ADC can acquire analog signals. ADC modules with high resolution and high sampling rate can provide more accurate digital signal output.

[0108] The number of high-voltage output circuits can be multiple or one; for example, the number of high-voltage output circuits is 8, that is, M=8. It depends on the actual situation, and all are within the protection scope of this application.

[0109] The high-voltage output circuit includes: a multiplexing selection circuit, N high-voltage channel selection circuits, and N high-voltage units (HVunits). The multiplexing selection circuit includes: an ADC channel selection circuit, a VSIM channel selection circuit, and an MVM channel selection circuit.

[0110] It should be noted that, as Figure 1 As shown, FPGA is for control; DAC is for DAC module; OPA is for OPA module; HV unit is for high voltage unit; HV channel selection is for high voltage channel selection circuit; HV-ADC channel selection is for ADC channel selection circuit; HV-VSIM channel selection is for VSIM channel selection circuit; HV-MVM channel selection is for MVM channel selection circuit; V1, V2, and V3 are the voltages of each node.

[0111] M is a positive integer, and N is an integer greater than 1.

[0112] There are N high-voltage channel selection circuits and N high-voltage units (HV units) in a one-to-one correspondence. That is, each high-voltage unit (HV unit) is used as a high-voltage output channel, and the high-voltage channel selection circuit can select the state of each high-voltage output channel, that is, select the operating mode of the high-voltage unit (HV unit).

[0113] The multiplexing selection circuit can collect electrical signals from each high-voltage output channel, such as current and voltage, and feed these electrical signals back to the controller through the ADC module. The controller then controls the working state of the multiplexing selection circuit according to the signal corresponding to the high-voltage output channel, thereby realizing the working mode control of the high-voltage unit (HV unit).

[0114] The first end of the controller is connected to one end of the high-voltage channel selection circuit in sequence through the DAC module, OPA module, and high-voltage unit (HV unit).

[0115] Specifically, the first terminal of the controller is connected to the input terminal of the DAC module, the output terminal of the DAC module is connected to the input terminal of the OPA module; the output terminal of the OPA is connected to the input terminal of the high voltage unit (HV unit), and the output terminal of the high voltage input unit is connected to the input terminal of the channel-to-selection circuit.

[0116] It should be noted that the number of N can be multiple or one, for example, N=16; this will not be elaborated further here, and can be determined according to the actual situation, all of which are within the scope of protection of this application.

[0117] The number of high-voltage output channels in this high-voltage power supply circuit is N*M; that is, when M=1 and N is 16, the number of high-voltage output channels in this high-voltage power supply circuit is 16; when M=8 and N is 16, the number of high-voltage output channels in this high-voltage power supply circuit is 128; other values ​​will not be elaborated here.

[0118] The other end of the high-voltage channel selection circuit serves as an output terminal of the high-voltage power supply circuit, which is connected to the device under test.

[0119] The other end of each high-voltage channel selection circuit can also serve as an output terminal of a high-voltage power supply circuit, meaning that the high-voltage power supply circuit can connect to N*M devices under test. Therefore, this application can improve testing efficiency by configuring a larger number of high-voltage output circuits and high-voltage units (HVunits) to enable simultaneous testing of multiple devices under test.

[0120] The second terminal of the controller is connected to the output terminal of the ADC module.

[0121] In other words, the controller receives the signal fed back by the ADC module.

[0122] The four input terminals of the ADC module correspond one-to-one with the four output terminals of the ADC channel selection module; each input terminal of the ADC module is connected to each output terminal of the ADC channel selection module.

[0123] Specifically, the first input terminal of the ADC is connected to the first output terminal of the ADC channel selection module; the second input terminal of the ADC is connected to the second output terminal of the ADC channel selection module; the third input terminal of the ADC is connected to the third output terminal of the ADC channel selection module; and the fourth input terminal of the ADC is connected to the fourth output terminal of the ADC channel selection module.

[0124] The two first input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is connected to each corresponding output terminal of the VSIM channel selection circuit. Specifically, one first input terminal of the ADC channel selection module is connected to one output terminal of the VSIM channel selection circuit; the other first input terminal of the ADC channel selection module is connected to the other output terminal of the VSIM channel selection circuit.

[0125] The two second input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is connected to each corresponding output terminal of the MVM channel selection circuit. Specifically, one second input terminal of the ADC channel selection module is connected to one output terminal of the MVM channel selection circuit; the other second input terminal of the ADC channel selection module is connected to the other output terminal of the MVM channel selection circuit.

[0126] The two input terminals of the VSIM channel selection circuit are connected to the positive and negative terminals of the current sampling terminal in the high-voltage unit HV unit, respectively. Specifically, one input terminal of the VSIM channel selection circuit is connected to the positive terminal of the current sampling terminal in the high-voltage unit HV unit, and the other input terminal of the VSIM channel selection circuit is connected to the negative terminal of the current sampling terminal in the high-voltage unit HV unit. The current signal of the high-voltage unit HV unit is received by the VSIM channel selection circuit.

[0127] The input terminal of the MVM channel selection circuit is connected to the voltage sampling terminal of the high-voltage unit (HV unit).

[0128] In other words, the MVM channel selection circuit receives the voltage signal from the high-voltage unit (HV unit).

[0129] The ADC channel selection circuit, VSIM channel selection circuit, MVM channel selection circuit, high voltage unit (HV unit), and high voltage channel selection circuit are all controlled by the controller.

[0130] Specifically, the controller controls the paths in the ADC channel selection circuit, VSIM channel selection circuit, and MVM channel selection circuit to achieve current and voltage sampling of the corresponding high-voltage unit (HV unit); at the same time, it controls the working state of the high-voltage output path by controlling the working state of the high-voltage channel selection circuit.

[0131] It should be noted that this high-voltage power supply circuit is one of the high-voltage functional modules in the general functions of ATE testers. Different companies have different strategies and different integration and distribution methods for functional modules. They can use a single board with multiple functional modules, or a single board with one function, and multiple boards with different functions, to meet the various functional requirements of the tester. These different strategies determine the configuration functions of the tester, and thus its cost.

[0132] Currently, existing products on the market have fixed configuration methods, while customer needs are diverse. Some customers require more than necessary functions, and the cost exceeds their budget.

[0133] This application describes a design scheme in which a single module of a high-voltage power supply circuit can have 16 high-voltage output channels, thereby designing functional boards according to customer needs and reducing product manufacturing costs through customized boards.

[0134] In this embodiment, N high-voltage channel selection circuits and N high-voltage units correspond one-to-one; the first terminal of the controller is connected to one terminal of the high-voltage channel selection circuit via the DAC module, OPA module, and high-voltage unit in sequence; the other terminal of the high-voltage channel selection circuit serves as an output terminal of the high-voltage power supply circuit, connected to the device under test; the second terminal of the controller is connected to the output terminal of the ADC module; the four input terminals of the ADC module correspond one-to-one with the four output terminals of the ADC channel selection module; each input terminal of the ADC module is connected to each output terminal of the ADC channel selection module; the two first input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the VSIM channel selection circuit; each first input terminal of the ADC channel selection module is connected to each output terminal of the VSIM channel selection circuit; the two second input terminals of the ADC channel selection module correspond one-to-one with the two output terminals of the MVM channel selection circuit; each second input terminal of the ADC channel selection module is connected to each output terminal of the MVM channel selection circuit; the VSIM channel selection... The two input terminals of the selection circuit are connected to the positive and negative terminals of the current sampling terminal in the high-voltage unit, respectively. The input terminal of the MVM channel selection circuit is connected to the voltage sampling terminal of the high-voltage unit. The ADC channel selection circuit, VSIM channel selection circuit, MVM channel selection circuit, high-voltage unit, and high-voltage channel selection circuit are all controlled by the controller. In other words, this high-voltage power supply circuit is independent of the test equipment and can have N high-voltage output channels. Therefore, it can be assembled based on the high-voltage power supply circuit, and functional boards can be customized according to user needs to avoid the cost problems caused by redundant functions integrated on the functional boards and reduce the cost of customized boards and product production. At the same time, it can collect the voltage and current of each high-voltage unit and independently control the channel selection and working mode of each high-voltage unit to improve the high-voltage output performance of the high-voltage unit. In addition, the N high-voltage units reuse the controller, DAC module, ADC module, OPA module, and multiplexing selection circuit, etc., to reduce costs. The number of high-voltage units is multiple, which can support the parallel testing of multiple devices under test and improve testing efficiency.

[0135] Optional, such as Figure 2 As shown, a DAC module can be implemented using a DAC chip and peripheral components; specifically, such as... Figure 2 As shown, this DAC module can use the 16-bit high-precision DAC chip AD5761R to achieve digital-to-analog conversion.

[0136] The VDD and VSS pins of the DAC chip are connected to ±15V power supplies, its DVCC pin is connected to VCC_3.3V power supply, and the VREFIN pin is the input pin for the 2.5V reference voltage, which serves as the reference voltage for digital-to-analog conversion.

[0137] In other words, this DAC chip integrates a sophisticated power management design. The VDD pin is connected to a +15V power supply as the positive power input (VDD), while the VSS pin is connected to a -15V power supply as the negative power input (VSS). This bipolar power supply configuration ensures stable and efficient operation of the DAC chip. Furthermore, the DVCC pin is specifically designed to receive the VCC_3.3V power supply, which is dedicated to powering the digital logic section, ensuring the stability and reliability of the SPI communication interface.

[0138] To provide an accurate digital-to-analog conversion reference, the VREFIN pin is configured to receive a 2.5V reference voltage input. This stable reference voltage is crucial for ensuring the accuracy of the DAC output signal, serving as the reference point for all analog output conversions.

[0139] LED4 is a DAC fault alarm light. When the temperature of the DAC chip exceeds 150°C, the output is short-circuited. When the DAC chip is undervoltage, this pin is pulled low and the light illuminates as an alarm.

[0140] In other words, the system is also equipped with a fault monitoring and alarm mechanism, specifically implemented through LED4 fault alarm lights. When the DAC chip encounters an abnormal situation, such as the temperature exceeding the safety threshold of 150°C, a short circuit at the output terminal, or an undervoltage condition, the LED4 pin will be pulled low, thereby illuminating the alarm light and promptly notifying maintenance personnel for handling.

[0141] The DAC chip communicates with the FPGA (controller) via an SPI serial bus. The FPGA controls the AD5761R to output voltage VOUT V1 via corresponding pins using SPI serial communication. The output voltage VOUT V1 can range from -10V to 10V. This range does not meet the high-voltage output range of -5V to 30V, therefore an OPA (bias amplifier) ​​module is needed to adjust the voltage.

[0142] In other words, regarding communication, the DAC chip seamlessly connects to the FPGA controller via the SPI (Serial Peripheral Interface) bus. The FPGA, acting as the master control unit, precisely controls the analog voltage V1 (VOUT) required by the AD5761R chip output through the SPI communication protocol. It's worth noting that while the DAC chip supports an output range of -10V to 10V, this is insufficient to meet the high-voltage requirements of -5V to 30V in some applications.

[0143] To address this, an OPA (Opposition over Amplifier) ​​module was introduced as a crucial processing step after the DAC module output. This module enables bias adjustment and amplification of the DAC output signal, successfully extending the voltage range to -5V to 30V, thus meeting the needs of a wider range of high-voltage applications. This design not only enhances the system's flexibility and adaptability but also ensures the accuracy and stability of the output signal.

[0144] Optional, such as Figure 3 As shown, the OPA module includes: an in-phase adder and a follower.

[0145] The input terminal of the non-inverting adder is connected to the output terminal of the DAC module; the output terminal of the non-inverting adder is connected to the input terminal of the follower; the output terminal of the follower serves as the output terminal of the OPA module; the positive terminals of the power supply of both the non-inverting adder and the follower are connected to a 30V power supply; the negative terminals of both the power supply of both the non-inverting adder and the follower are connected to a -5V power supply.

[0146] The in-phase adder, a crucial link in the signal processing chain, has its input directly connected to the output of the DAC module. This ensures that the analog voltage signal generated by the DAC module (such as a DAC chip) can be transmitted to the in-phase adder for processing without loss. The in-phase adder acts as the summation device, adding the DAC module's output signal to any other possible signal source (such as a reference power supply), achieving in-phase superposition of the signals. This other signal source can be a reference power supply, with a voltage of 5V, although other possibilities exist, which will not be elaborated upon here.

[0147] A signal follower, as a type of buffer amplifier with high input impedance and low output impedance, can effectively isolate the influence of subsequent circuits on preceding circuits while maintaining signal integrity and driving subsequent circuits. In this way, the signal processed by the in-phase adder can be stably transmitted to the signal follower.

[0148] In other words, the in-phase adder enables bias amplification and adjustment of the DAC module's output voltage, while the voltage follower enables isolation and driving of the DAC's output voltage.

[0149] As the core of voltage regulation, the OPA module is responsible for further amplifying and adjusting the signal output by the follower to the required voltage range, i.e., -5V to 30V, to meet the needs of high-voltage applications.

[0150] In terms of power supply, both the in-phase adder and the follower employ a bipolar power supply to ensure circuit stability and performance. Specifically, the positive terminals of the in-phase adder and the follower are connected to a 30V power supply, providing a positive bias voltage for the circuit; while their negative terminals are simultaneously connected to a -5V power supply, providing a negative bias voltage for the circuit. This symmetrical power supply configuration helps reduce the impact of power supply noise on circuit performance and improves the overall stability and reliability of the circuit.

[0151] Optional, such as Figure 4 The in-phase adder shown includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, and a first capacitor.

[0152] One end of the third resistor serves as the input of the non-inverting adder and is connected to the output of the DAC module. The precise analog signal generated by the DAC module can flow into the non-inverting adder without obstruction for subsequent signal processing.

[0153] The non-inverting input of the first operational amplifier is connected to the other end of the third resistor, one end of the fourth resistor, and one end of the first capacitor. This connection method not only achieves signal convergence but also filters the signal to a certain extent through the addition of capacitors, reducing high-frequency noise interference.

[0154] The negative input terminal of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor. In other words, the negative input terminal of the first operational amplifier forms a feedback network with one end of the first resistor and the other end of the second resistor. This feedback mechanism is crucial for maintaining the operational amplifier in the linear amplification region, ensuring that the non-inverting adder can accurately perform voltage amplification and signal addition operations.

[0155] The output of the first operational amplifier is connected to the other end of the second resistor, and the connection point serves as the output of the non-inverting adder and is connected to the input of the second operational amplifier.

[0156] The positive and negative terminals of the first operational amplifier are used as the positive and negative terminals of the non-inverting adder, respectively; that is, the positive terminal of the first operational amplifier is connected to a 30V power supply, and its negative terminal is connected to a -5V power supply.

[0157] The other end of the fourth resistor is connected to the reference power supply; the other ends of the first capacitor and the first resistor are grounded.

[0158] In terms of power supply, the first operational amplifier adopts a bipolar power supply method, with its positive and negative terminals directly serving as the positive and negative power supply terminals for the non-inverting adder. Specifically, the positive terminal is connected to a stable 30V power supply to provide forward bias for the circuit, while the negative terminal is connected to a -5V power supply to provide negative bias. This symmetrical power supply configuration not only ensures the stable operation of the operational amplifier but also reduces the impact of power fluctuations on circuit performance.

[0159] Furthermore, the other end of the fourth resistor is carefully connected to a reference power supply, providing the circuit with a certain bias current or voltage. The other ends of both the first capacitor and the first resistor are grounded, which not only provides a stable reference potential for the circuit but also helps reduce interference and noise in the circuit.

[0160] The voltage range is biased and amplified to -5V to 30V by using a non-inverting adder circuit.

[0161] The formula for the in-phase adder is as follows:

[0162]

[0163]

[0164] Wherein, V1: -10V to 10V (output voltage of the DAC module); V2 = 5V (reference voltage).

[0165] Therefore, V is calculated according to the above formula. OUT The range is -10V to 30V, but because the negative power supply VSS of the first operational amplifier is -5V, the negative voltage range is clamped by the power supply, and the output voltage range is -5V to 30V.

[0166] Optionally, the follower includes: two follower units; the connection point after the input terminals of the two follower units are connected serves as the input terminal of the follower; the output terminals of the two follower units serve as the output terminals of the follower.

[0167] The follower unit includes: a second operational amplifier.

[0168] The non-inverting input of the second operational amplifier serves as the input of the follower unit and is connected to the output of the non-inverting adder. The negative input of the second operational amplifier is connected to its output, with the connection point serving as the output of the follower unit. The positive and negative terminals of the second operational amplifier's power supply also serve as the positive and negative terminals of the follower unit's power supply.

[0169] Specifically, the follower unit can also be equipped with a fifth resistor and a sixth resistor.

[0170] The non-inverting input of the second operational amplifier serves as the input of the follower unit and is connected to the output of the non-inverting adder. The negative input of the second operational amplifier is connected to its output, one end of the fifth resistor, and one end of the sixth resistor, with the other end of the sixth resistor grounded. The other end of the fifth resistor serves as the output of the follower unit, and the positive and negative terminals of the second operational amplifier's power supply serve as the positive and negative terminals of the follower unit's power supply.

[0171] like Figure 5 As shown, in the first follower unit: the non-inverting input of the second operational amplifier U28A serves as the input of the first follower unit and is connected to the output of the non-inverting adder. The negative input of the second operational amplifier U28A is connected to its output, one end of the fifth resistor R302, and one end of the sixth resistor R303, with the other end of the sixth resistor R303 grounded. The other end of the fifth resistor R302 serves as the output of the first follower unit. The positive and negative terminals of the power supply of the second operational amplifier U28A serve as the positive and negative terminals of the power supply of the first follower unit. The positive terminal of the power supply of the second operational amplifier U28A is connected to the VDD_30V power supply; the negative terminal of the power supply of the second operational amplifier U28A is connected to the VSS_-5V power supply.

[0172] In the second follower unit: the non-inverting input of the second operational amplifier U28B serves as the input of the second follower unit and is connected to the output of the non-inverting adder. The negative input of the second operational amplifier U28B is connected to its output, one end of the fifth resistor R304, and one end of the sixth resistor R305, with the other end of the sixth resistor R305 grounded. The other end of the fifth resistor R305 serves as the output of the second follower unit. The positive and negative terminals of the power supply of the second operational amplifier U28B serve as the positive and negative terminals of the power supply of the second follower unit.

[0173] The second operational amplifier can be implemented using the OPA2196 chip.

[0174] The bias amplified voltage is isolated from the subsequent circuit by the first and second follower units, ensuring the purity and stability of the signal.

[0175] The first and second follower units precisely isolate and convert the voltage HV_OUT output from the in-phase adder into two independent output voltages: HV_OPA1 and HV_OPA2. This conversion process not only maintains signal integrity but also significantly improves signal processing efficiency and speed through dual-channel parallel processing.

[0176] Optional, such as Figure 6 As shown, N is 16; the OPA module has 2 output terminals.

[0177] The input terminals of eight high-voltage units (HV units) are connected to one output terminal of the OPA module; the input terminals of the other eight high-voltage units (HV units) are connected to the other output terminal of the OPA module.

[0178] Figure 6 In this context, VISM / MVM mode refers to two modes used by the customer, encompassing all 16 high-voltage units. Both modes can be used for testing with VSIM and MVM functions. VSIM stands for Voltage Source Current Measurement, where the tester measures current while supplying voltage. MVM stands for Measure Voltage Mode, where the tester measures voltage while supplying voltage, or it can measure voltage from an external source. "Probercard side (example)" refers to the tester's external connection side. Externally connected components are called prober cards.

[0179] Specifically, high-voltage units HVunit0-unit7 are connected to the first output terminal (HV_OPA1) of the OPA module; high-voltage units HV unit8-unit16 are connected to the second output terminal (HV_OPA2) of the OPA module. The current of each high-voltage unit HVunit can be 2mA. HV_OPA1 and HV_OPA2 are the output settings of the OPA module.

[0180] Each high-voltage unit (HV unit) corresponds to one channel, and each HV unit is built using operational amplifiers and discrete components, eliminating the need for expensive integrated chips and thus reducing costs. Compared to the T5830, where every two units form one MC, and each MC can be independently configured in VSIM or MVM mode, this application allows each HV unit to be independently configured in either VSIM or MVM mode.

[0181] Each group of eight channels is equipped with a set voltage provided by one operational amplifier in the OPA module, which can meet the current requirements for the output setting of 64 channels for the Datong measurement scheme. Two operational amplifiers provide the input set voltage for 128 channels.

[0182] Due to the requirements of large-scale measurement, the size of the single board is also limited. Multiplexers and analog switches can be used to reduce the size, allowing for integrated configuration of each high-voltage unit (HV unit). Simultaneously, two high-voltage units (HV units, such as...) can be integrated... Figure 7 (As shown) integrated together; Figure 7The two high-voltage units (HV units) and the high-voltage channel selection circuit are integrated together, and this integrated unit is named VMON CBB. The high-voltage channel selection circuit can use a corresponding chip, thus enabling one chip to select the channels of the two high-voltage units (HV units).

[0183] Figure 7 In the diagram: VDD_30V pin of VMON CBB is connected to the VDD_30V power supply; VL_5V pin of VMON CBB is connected to the VCC_5V power supply; VSS_-5V pin of VMON CBB is connected to the VSS_-5V power supply; GND pin of VMON CBB is grounded to GND.

[0184] For PER: The power supply section provides power to the operational amplifiers and switching devices; the HV_IN pin of VMON CBB receives the output voltage of the OPA module. Figure 7 (The example shown is VMON CBB).

[0185] For the DUT SEL section: Channel selection input, independent enable for DUT0 and DUT1 can be configured; VMON CBB's DUTa_b_SW_IN1, DUTa_b_SW_IN2, DUTa_b_SW_IN3, and DUTa_b_SW_IN4 receive signals DUT0_1_SW_IN1, DUT0_1_SW_IN2, DUT0_1_SW_IN3, and DUT0_1_SW_IN4 respectively through corresponding resistors (R388, R389, R390, R391).

[0186] For the DUT0 section: DUTa_SW_IN1, DUTa_SW_IN2, DUTa_SW_IN3, and DUTa_SW_IN4 pins receive signals DUT0_SW_IN1, DUT0_SW_IN2, DUT0_SW_IN3, and DUT0_SW_IN4 respectively through corresponding resistors (R392, R393, R394, R395). The DUTa_RANGE_SEL pin receives signal DUT0_RANGE_SEL through resistor R398; the VSIM_Ha pin serves as the positive terminal (VSIM0_H0) for the current sampling of high-voltage unit HV unit0; the VSIM_La pin serves as the negative terminal (VSIM0_L0) for the current sampling of high-voltage unit HV unit0; and the MVM_a pin serves as the voltage sampling terminal (MVM0_V0) for high-voltage unit HV unit0. OUTa_A pin is connected to TP1; OUTa_B pin is connected to TP2; HV_POGO_a pin serves as the output terminal (HV_POGO_0) of the high-voltage unit HVunit0; that is, it includes the switching control of DUT0, range selection, VSIM0 interface output, MVM0 interface output, OUT0 test point, and DUT0 connection to HV_POGO_0.

[0187] For the DUT1 section: pins DUTb_SW_IN1, DUTb_SW_IN2, DUTb_SW_IN3, and DUTb_SW_IN4 receive signals DUT1_SW_IN1, DUT1_SW_IN2, DUT1_SW_IN3, and DUT1_SW_IN4 respectively through corresponding resistors (R403, R404, R405, R406). Pin DUTb_RANGE_SEL receives signal DUT1_RANGE_SEL through resistor R415; pin VSIM_Hb serves as the positive terminal (VSIM0_H1) for current sampling of high-voltage unit HV unit1; pin VSIM_Lb serves as the negative terminal (VSIM0_L1) for current sampling of high-voltage unit HV unit1; and pin MVM_b serves as the voltage sampling terminal (MVM0_V1) for high-voltage unit HV unit1. OUTb_A pin connects to TP3; OUTb_B pin connects to TP4; HV_POGO_b pin serves as the output terminal (HV_POGO_1) of the high-voltage unit HVunit1; that is, it includes the switching control of DUT1, range selection, VSIM1 interface output, MVM1 interface output, OUT1 test point, and DUT1 connection to HV_POGO_1.

[0188] It should be noted that HVUnit1 = DUT0, and HVUnit2 = DUT1. HVUnit1 and HVUnit2 are both high-voltage units (HVunit); OR / 0402 are the specific parameters of the resistor.

[0189] like Figure 8 As shown, it illustrates the expanded diagram of VMON CBB; where HVOUTa and HVOUTb are both high-voltage units (HVunits), and POGO_SW is a channel selection chip (including two high-voltage channel selection circuits); it enables two high-voltage units (HVunits) to reuse one channel selection chip; that is, VMON CBB consists of 2 HVOUT CBBs and 1 POGO SW.

[0190] In HVOUTa: The HV_IN pin receives the output signal of the OPA module; SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTa_SW_IN1, DUTa_SW_IN2, DUTa_SW_IN3, and DUTa_SW_IN4 pins respectively; the Set_Range pin is connected to the DUTa_RANGE_SEL pin; the VSS pin is connected to the VSS_-5V pin; the VDD pin is connected to the VDD_30V pin; the GDN pin is grounded; the VSIM_H pin is connected to the VSIM_Ha pin; the VSIM_L pin is connected to the VSIM_La pin; the OUT_A pin is connected to the OUTa_A pin; the OUT_B pin is connected to the OUTa_B pin; and the MVM pin is connected to the MVM_a pin.

[0191] In HVOUTb: The HV_IN pin receives the output signal from the OPA module; SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTb_SW_IN1, DUTb_SW_IN2, DUTb_SW_IN3, and DUTb_SW_IN4 pins respectively; the Set_Range pin is connected to the DUTb_RANGE_SEL pin; the VSS pin is connected to the VSS_-5V pin; the VDD pin is connected to the VDD_30V pin; the GDN pin is grounded; the VSIM_H pin is connected to the VSIM_Hb pin; the VSIM_L pin is connected to the VSIM_Lb pin; the OUT_A pin is connected to the OUTb_A pin; the OUT_B pin is connected to the OUTb_B pin; and the MVM pin is connected to the MVM_b pin.

[0192] In POGO_SW: SW1_IN1, SW1_IN2, SW1_IN3, and SW1_IN4 pins are connected to DUTa_b_SW_IN1, DUTa_b_SW_IN2, DUTa_b_SW_IN3, and DUTa_b_SW_IN4 pins respectively; VSS pin is connected to VSS_-5V pin; VDD pin is connected to VDD_30V pin; GDN pin is grounded; VL pin is connected to VL_5V pin; HV_DUT1 pin is connected to HV_POGO_a_ pin; HV_DUT2 pin is connected to HV_POGO_b_ pin.

[0193] The DUTA pin of HVOUTa is connected to the DUTB_1 pin in POGO_SW; the DUTB pin of HVOUTa is connected to the DUTA_1 pin in POGO_SW; the DUTA pin of HVOUTb is connected to the DUTA_2 pin in POGO_SW; and the DUTB pin of HVOUTb is connected to the DUTB_2 pin in POGO_SW.

[0194] Optional, the high-voltage unit (HV unit) includes: an HV operational amplifier circuit, a current sampling circuit, and a switching unit.

[0195] See Figure 9 The HV operational amplifier circuit includes: a high-voltage operational amplifier HV, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. The current sampling circuit includes: a tenth resistor R10 and a first switch SPST1. The switching unit includes: a second switch SPST2 and a third switch SPST3; the switching unit may also include: a fourth switch SPST4 and a fifth switch SPST5.

[0196] The non-inverting input of the high-voltage operational amplifier HV serves as the input of the high-voltage unit HV unit, receiving the voltage signal HV_OPA1 or HV_OPA2 output from the OPA module.

[0197] The negative input terminal of the high-voltage operational amplifier HV is connected to one end of the seventh resistor R7.

[0198] The output of the high-voltage operational amplifier HV is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9, respectively. The connection point serves as the positive terminal of the current sampling terminal of the high-voltage unit HV and is connected to one of the input terminals of the VSIM channel selection circuit.

[0199] The other end of the ninth resistor R9 is connected to one end of the third switch SPST3, one end of the eighth resistor R8, and one end of the first switch SPST1. The connection point serves as the negative terminal of the current sampling terminal of the high-voltage unit HV unit and is connected to the other input terminal of the VSIM channel selection circuit.

[0200] It should be noted that the positive and negative terminals of the current sampling terminal of the high-voltage unit (HV unit) can also be connected to the VSIM channel selection circuit through buffers, respectively.

[0201] The other end of the seventh resistor R7 is connected to the other end of the eighth resistor R8 and one end of the second switch SPST2. The connection point serves as the voltage sampling terminal (MVM) of the high-voltage unit HV unit and is connected to the input terminal of the MVM channel selection circuit.

[0202] The voltage sampling terminal can measure the output voltage of the high-voltage unit (HV unit) and can also be used to measure the high voltage value of the DUT at the output terminal HV_POGO of the high-voltage channel selection circuit. This voltage sampling terminal can be connected to the input terminal of the MVM channel selection circuit after being isolated by a buffer.

[0203] The other end of the first switch SPST1 is connected to the other end of the tenth resistor R10.

[0204] The other end of the second switch SPST2 is connected to one end of the fourth switch SPST4. The connection point serves as the first output terminal of the high-voltage unit HVunit and is connected to one input terminal of the high-voltage channel selection circuit.

[0205] The other end of the fourth switch SPST4 serves as the OUTA interface for the high-voltage unit HV unit.

[0206] The other end of the third switch SPST3 is connected to one end of the fifth switch SPST5. The connection point serves as the second output terminal of the high-voltage unit HVunit and is connected to the other input terminal of the high-voltage channel selection circuit.

[0207] The other end of the fifth switch SPST5 serves as the OUTB interface for the high-voltage unit HV unit.

[0208] The OUTA and OUTB interfaces are reserved interfaces that can be used to measure the voltage across the feedback resistor and to measure the feedback current.

[0209] In other words, by configuring the pins of the controller FPGA to turn the first switch SPST1 on and off, the parallel connection and disconnection of the ninth resistor R9 and the tenth resistor R10 are realized, thereby changing the output resistance value of the HV op-amp to change the output current range.

[0210] By controlling the on / off state of each switch in the switching unit, the various modes of the high-voltage unit (HV unit) can be switched.

[0211] Optionally, the high-voltage channel selection circuit includes: a first channel switch and a second channel switch.

[0212] One end of the first channel switch is connected to the first output terminal of the high-voltage unit (HV unit).

[0213] One end of the second channel switch is connected to the second output terminal of the high-voltage unit (HV unit).

[0214] The other end of the first channel switch is connected to the other end of the second channel switch, and the connection point serves as the output terminal of the high-voltage channel selection circuit.

[0215] It should be noted that the high-voltage selection circuits corresponding to the two high-voltage units HVunit can be integrated together.

[0216] like Figure 10 As shown:

[0217] One end of the first channel switch U72B is connected to the first output terminal of the high-voltage unit HV unit1, and the other end of the first channel switch U72B receives the DUTA1 signal.

[0218] One end of the second channel switch U72E is connected to the second output terminal of the high-voltage unit HV unit1, and the other end of the second channel switch receives the DUTB1 signal.

[0219] The other end of the first channel switch U72B is connected to the other end of the second channel switch U72E. The connection point serves as the output terminal of the first high-voltage channel selection circuit, for example, outputting the HV_DUT1 signal.

[0220] One end of the first channel switch U72C is connected to the first output terminal of the high-voltage unit HV unit2, and the other end of the first channel switch U72C receives the DUTA2 signal.

[0221] One end of the second channel switch U72D is connected to the second output terminal of the high-voltage unit HV unit2, and the other end of the second channel switch receives the DUTB2 signal.

[0222] The other end of the first channel switch U72C is connected to the other end of the second channel switch U72D. The connection point serves as the output terminal of the second high-voltage channel selection circuit, for example, outputting the HV_DUT2 signal.

[0223] The connection between DUTA1 or DUTB1 and HV_DUT1 can be established via a switch. Similarly, the connection between DUTA2 or DUTB2 and HV_DUT2 can be established.

[0224] like Figure 11 As shown, it illustrates the connection relationship between one ADC channel selection circuit and four RC low-pass filter circuits, two VSIM channel selection circuits and one MVM channel selection circuit.

[0225] Specifically as follows:

[0226] Two VSIM channel selection circuits:

[0227] The left side of the VSIM channel selection circuit contains input signals, which are control signals from the FPGA, including enable (EN) and channel control signals A0, A1, A2, etc. There are also voltages VSIM_H0 / 15 and VSIM_L0 / 15 from the sampling resistors of the 16 HV units.

[0228] The right side of the VSIM channel selection circuit is the output signal. The output terminals VSIM_OUT_1 and VSIM_OUT_2 of the two VSIM channel selection circuits are respectively connected to the ADC channel selection circuit.

[0229] In other words, the VSIM channel selection module is used to perform voltage-to-current conversion across the current sampling resistor and to achieve 2-to-16 channel selection. The signal definitions are as follows:

[0230] MUX Enable: EN. MUX Channel Control: A0, A1, A2. MUX Channel 16 to 2: S1-8A corresponds to sampling the voltage at the L end of the sampling resistor. S1-8B corresponds to sampling the voltage at the H end of the sampling resistor. VSIM Output: The differential voltage passes through a 16:2 MUX to select 1 from 8 channels for VSIM function sampling. The current value is converted to a voltage value by a current-sensing amplifier and output through VSIM_OUT1 and VSIM_OUT_2.

[0231] One MVM channel selection circuit:

[0232] The left side of the MVM channel selection circuit contains input signals, which are control signals from the FPGA, including enable (EN) and channel control signals A0, A1, A2, etc. There are also output voltage sampling signals MVM0_V0-7 and MVM1_V8-15 from the 16 HV units.

[0233] The right side of the MVM channel selection circuit is the output signal. The output terminals MVM_OUT1 and MVM_OUT2 of the MVM channel selection circuit are respectively connected to the ADC channel selection circuit.

[0234] In other words, the MVM channel selection circuit is used to perform high-voltage reduction biasing of the HV output voltage / DUT sampling voltage and to achieve 2-to-16 channel selection. The signal definitions are as follows:

[0235] MUX Enable: EN. MUX Channel Control: A0a, A1a, A2a correspond to DUTTa; A0b, A1b, A2b correspond to DUTb. MUX Channel 16 to 2 Selection: S1-8a corresponds to voltage sampling at DUT output terminals 0-7. S1-8b corresponds to voltage sampling at DUT output terminals 8-15. MVM Output: The DUT output voltage is generated by two 8:1 MUXs, enabling selection of 2 channels from 16 channels for MVM sampling. After voltage bias amplification, the signal is output through MVM_OUT.

[0236] One HV_ADC channel selection circuit + four RC low-pass filters:

[0237] The left side of the ADC channel selection circuit contains four input signals from the VSIM and MVM channel selection circuits, as well as MUX control signals from the FPGA, including channel controls IN1, IN2, IN3, and IN4.

[0238] The right side of the ADC channel selection circuit has four switch-path output signals: VSIM_MUX_OUT1, VSIM_MUX_OUT2, MVM_MUX_OUT1, and MVM_MUX_OUT2. These four signals pass through their respective corresponding RC low-pass filter circuits before entering channels AIN0, AIN7, BIN0, and BIN7 of the ADC module. In other words, the four RC low-pass filter circuits correspond one-to-one with the four output terminals of the ADC channel selection circuit; each RC low-pass filter circuit is positioned between its corresponding output terminal of the ADC channel selection circuit and the ADC module. The ADC module can have multiple channels, such as 16. Figure 11 As shown, this only applies to 4 channels.

[0239] In other words, the ADC channel selection circuit is equipped with 4 MUX channels to achieve switching control of 2 HV_VSIM channels and 2 HV_MVM channels.

[0240] The analog voltage selected by the SIM and MVM channels is filtered and then enters the ADC sampling channel.

[0241] Optional, such as Figure 12 As shown, the VSIM channel selection circuit includes: two first multiplexing circuits; each first multiplexing circuit includes: a first multiplexing chip U77, a fifth MUX operational amplifier U76A, a sixth MUX operational amplifier U76B, a gain chip GAIN, and four multiplexing resistors (including, for example,...). Figure 12(R739-R742 shown). The multiplexed resistor R742 is a 10kΩ / 0402 resistor; the multiplexed resistor R741 is a 33Ω / 0402 resistor; the multiplexed resistor R740 is a 10kΩ / 0402 resistor; and the multiplexed resistor R739 is a 33Ω / 0402 resistor.

[0242] The VDD pin of the first multiplexer chip U77 is connected to the positive power supply VDD; its VSS pin is connected to the negative power supply VSS. Its EPAD and GND pins are both grounded to GND. The first multiplexer chip U77 can be an ADG5207 chip.

[0243] The non-inverting input terminal +INA of the fifth MUX operational amplifier U76A is connected to the DA pin of the first multiplexer chip U77.

[0244] The negative input terminal -INA of the fifth MUX operational amplifier U76A is connected to the output terminal OUTA of the fifth MUX operational amplifier U76A, one end of the first multiplexed resistor R739, and one end of the second multiplexed resistor R740.

[0245] The non-inverting input terminal +INB of the sixth MUX operational amplifier U76B is connected to the DB pin of the first multiplexer chip U77.

[0246] The other end of the first multiplexed resistor R739 is connected to the -INA pin of the gain chip GAIN.

[0247] The negative input terminal -INB of the sixth MUX operational amplifier U76B is connected to the output terminal OUTB of the sixth MUX operational amplifier U76B, one end of the third multiplexed resistor R741, and one end of the quadruple multiplexed resistor R742.

[0248] The other end of the third multiplexing resistor R741 is connected to the +INA pin of the gain chip GAIN.

[0249] The other end of the second multiplexing resistor R740, the other end of the fourth multiplexing resistor R742, and the REF pin of the gain chip GAIN are all grounded.

[0250] The positive power supply terminal of the fifth MUX operational amplifier U76A, the positive power supply terminal of the sixth MUX operational amplifier U76B, and the positive power supply terminal V+ of the gain chip GAIN are connected to the positive power supply VDD.

[0251] The negative power supply terminal of the fifth MUX operational amplifier U76A, the negative power supply terminal of the sixth MUX operational amplifier U76B, and the negative power supply terminal V- of the gain chip GAIN are connected to the negative power supply VSS.

[0252] The fifth MUX operational amplifier U76A and the sixth MUX operational amplifier U76B can use the OPA2196 chip, or other chips, which will not be elaborated here.

[0253] The OUT pin of the gain chip GAIN is connected to the anode of the first diode D10, and the connection point serves as the output terminal of the first multiplexing circuit. The gain chip GAIN can be a 10-gain chip, or other gain chips, which will not be elaborated here.

[0254] The input terminals of the first multiplexer chip U77 (e.g.) Figure 12 S1B-S8B and S1A-S8A shown are used as the input terminals of the first multiplexing circuit.

[0255] The EN pin of the first multiplexer chip U77 receives the EN signal; its A0, A1 and A2 pins receive the A0, A1 and A2 signals respectively; its NC1-NC7 are all pins.

[0256] In the gain chip GAIN, +INB, +INC, -INB, -INC, and / SHDN are all pins. The gain chip GAIN can be the LT1997-1 chip.

[0257] The cathode of the first diode D10 receives the first clamping voltage V_CLAMP_VSIM; the first clamping voltage V_CLAMP_VSIM can be 15V.

[0258] The first diode D10 can be a DFLS140-7 diode.

[0259] It should be noted that the first multiplexer chip U77 is a 16-to-2 multiplexer. It takes the voltage across the current feedback resistor, passes it through the DA and DB converters, and then isolates it via the U76 voltage follower (including U76A and U76B) before inputting it to the U78 current sense amplifier to achieve current-to-voltage conversion. This operational amplifier has a gain of 10, and the voltage range across the feedback resistor is approximately -0.5V to 1V (I*R). After amplification, the voltage range is -5V to 10V. The actual ADC sampling range meets the requirement of -12V to 12V.

[0260] Optionally, the MVM channel selection circuit includes: two second multiplexing circuits, each including: a second multiplexing chip and a seventh MUX operational amplifier.

[0261] The input terminal of the second multiplexing chip serves as the input terminal of the second multiplexing circuit.

[0262] The D pin of the second multiplexing chip is connected to one end of the fifth multiplexing resistor.

[0263] The other end of the fifth multiplexing resistor is connected to the non-inverting input of the seventh MUX operational amplifier and one end of the sixth multiplexing resistor, while the other end of the sixth multiplexing resistor is grounded.

[0264] The negative inverting input of the seventh MUX operational amplifier is connected to one end of the seventh multiplexed resistor and one end of the eighth multiplexed resistor, respectively.

[0265] The other end of the seventh multiplex resistor receives the bias voltage.

[0266] The output of the seventh MUX operational amplifier is connected to the other end of the eighth multiplexing resistor and the anode of the second diode, and the connection point serves as the output of the second multiplexing circuit.

[0267] The cathode of the second diode receives the second clamping voltage V_CLAMP_MVM; the second clamping voltage V_CLAMP_MVM can be 15V.

[0268] like Figure 13 As shown, in the first second multiplexing circuit: the input terminal of the second multiplexing chip U88 serves as the input terminal of the first second multiplexing circuit. The D pin of the second multiplexing chip U88 is connected to one end of the fifth multiplexing resistor R753. The other end of the fifth multiplexing resistor R753 is connected to the non-inverting input terminal of the seventh MUX operational amplifier U85A and one end of the sixth multiplexing resistor R754, with the other end of the sixth multiplexing resistor R754 grounded. The negative inverting input terminal of the seventh MUX operational amplifier U85A is connected to one end of the seventh multiplexing resistor R751 and one end of the eighth multiplexing resistor R752. The other end of the seventh multiplexing resistor R751 receives the bias voltage VBIAS. The output terminal of the seventh MUX operational amplifier U85A is connected to the other end of the eighth multiplexing resistor R752 and the anode of the second diode D12; this connection point serves as the output terminal MVM_OUTa of the first second multiplexing circuit. The cathode of the second diode D12 receives the second clamping voltage V_CLAMP_MVM.

[0269] In the second secondary multiplexing circuit: the input terminal of the second multiplexing chip U87 serves as the input terminal of the second secondary multiplexing circuit. The D pin of the second multiplexing chip U87 is connected to one end of the fifth multiplexing resistor R757. The other end of the fifth multiplexing resistor R757 is connected to the non-inverting input terminal of the seventh MUX operational amplifier U85B and one end of the sixth multiplexing resistor R758, with the other end of the sixth multiplexing resistor R758 grounded. The negative inverting input terminal of the seventh MUX operational amplifier U85B is connected to one end of the seventh multiplexing resistor R755 and one end of the eighth multiplexing resistor R756. The other end of the seventh multiplexing resistor R755 receives the bias voltage VBIAS. The output terminal of the seventh MUX operational amplifier U85B is connected to the other end of the eighth multiplexing resistor R756 and the anode of the second diode D13; this connection point serves as the output terminal MVM_OUTb of the first secondary multiplexing circuit. The cathode of the second diode D13 receives the second clamping voltage V_CLAMP_MVM.

[0270] The first multiplexer chip U86 and the second multiplexer chip U87 both use the ADG5408 chip. Operational amplifiers U85B / A both use the OPA2196 chip.

[0271] Resistors R751, R753, R755, and R757 are all 30kΩ / 0603 resistors; resistors R752, R754, R756, and R758 are all 7.5kΩ / 0603 resistors.

[0272] Figures 1-15 In the diagram: +INA and +INB are both non-inverting input terminals of the operational amplifier; -INA and -INB are both non-inverting input terminals of the operational amplifier; OUTA and OUTB are both output terminals of the operational amplifier.

[0273] In U87 and U88, S1-S8, EN, A0, A1, A2, VDD, VSS, and GND respectively receive corresponding signals, such as S1a-S8a signals / S1b-S8b signals, ENa / b signals, A0a-A2a signals / A0b-A2b signals, VDD signals, VSS signals, and GND signals.

[0274] The second multiplexer chip, U86, is an 8-to-1 multiplexer. The voltage is biased and amplified by a non-inverting adder, with a bias voltage VBIAS = 10V, as shown in the following formula:

[0275] V out =(V in -10V) / 4;

[0276] The MVM sampling voltage range is -5V to 30V, which is amplified and biased to -1.25V to 5V. Within the ADC's maximum sampling voltage range, it is -12V to 12V.

[0277] Optional, such as Figure 14 As shown, the ADC channel selection circuit includes: four MUX switches, four MUX operational amplifiers, and four MUX resistors.

[0278] One end of the first MUX switch U83B serves as a first input terminal of the ADC channel selection circuit; the other end of the first MUX switch U83B is connected to one end of the first MUX resistor R747 and the positive input terminal of the first MUX operational amplifier U82A respectively; the other end of the first MUX resistor R747 is grounded; the positive terminal of the power supply of the first MUX operational amplifier U82A is connected to the positive power supply VDD; the negative terminal of the power supply of the first MUX operational amplifier U82A is connected to the negative power supply VSS; the output terminal of the first MUX operational amplifier U82A serves as the first output terminal VSIM_MUX_OUT1 of the ADC channel selection circuit.

[0279] One end of the second MUX switch U83C serves as the other first input terminal of the ADC channel selection circuit; the other end of the second MUX switch U83C is connected to one end of the second MUX resistor R748 and the positive input terminal of the second MUX operational amplifier U82B respectively; the other end of the second MUX resistor R748 is grounded; the output terminal of the second MUX operational amplifier U82B serves as the second output terminal VSIM_MUX_OUT2 of the ADC channel selection circuit.

[0280] One end of the third MUX switch U83D serves as a second input terminal of the ADC channel selection circuit; the other end of the third MUX switch U83D is connected to one end of the third MUX resistor R749 and the positive input terminal of the third MUX operational amplifier U84A respectively; the other end of the third MUX resistor R749 is grounded; the positive terminal of the power supply of the third MUX operational amplifier U84A is connected to the positive power supply VDD; the negative terminal of the power supply of the third MUX operational amplifier U84A is connected to the negative power supply VSS; the output terminal of the third MUX operational amplifier U84A serves as the third output terminal MVM_MUX_OUT3 of the ADC channel selection circuit.

[0281] One end of the fourth MUX switch U83E serves as the other second input terminal of the ADC channel selection circuit; the other end of the fourth MUX switch U83E is connected to one end of the fourth MUX resistor R750 and the positive input terminal of the fourth MUX operational amplifier U84B respectively; the other end of the fourth MUX resistor R750 is grounded; the output terminal of the fourth MUX operational amplifier U84B serves as the fourth output terminal MVM_MUX_OUT4 of the ADC channel selection circuit.

[0282] The MUX switches U83B\C\D\E are 4-channel analog switches, and the sampling channels of VSIM and MVM can be controlled by an FPGA. Each channel is independently controlled. After passing through an operational amplifier stage, a voltage follower provides isolation protection between the preceding and following stages.

[0283] The ADC channel selection circuit may also include: a MUX switch U83A; its IN1-IN4 pins receive SW_IN1-SW_IN4 signals respectively; its VL, VDD, VSS, and GND pins receive VL, VDD, VSS, and GND signals respectively.

[0284] Resistors R747, R748, R749, and R750 are all 10mA / 0603 resistors. MUX switches U83A, U83B, U83C, U83, and U83E are all ADG411 switches. Operational amplifiers U84A, U84B, U84C, and U84D all use the OPA2196 chip.

[0285] like Figure 15 The diagram shown illustrates the circuit diagram of an ADC module. The ADC module includes an ADC chip.

[0286] This ADC chip can be a high-precision 16-bit, 16-channel ADC chip, including 8 A channels and 8 B channels.

[0287] Power supply for the ADC chip: AVDD analog voltage is powered by VCC_5V, and DVDD digital voltage is powered by VCC_3V3. REFIO is the external reference source voltage for the ADC, which is VCC_2V5.

[0288] The ADC chip has 16 input channels in total; this application uses 4 channels for both VSIM and MVM. Figure 11 and Figure 1 The numbers AIN0, AIN7, BIN0, and BIN7 are shown.

[0289] 128DUTs multi-channel solution: By using MUX multiplexing and switching, 16 DUTs can share a single ADC channel in a single mode, thus achieving a multi-channel solution of 16*8=128DUTs.

[0290] ADC chip configuration: Configure the various functions of the ADC through the GPIO pins of the FPGA.

[0291] ADC chip communication: After the ADC configuration is selected, it communicates with the FPGA through the hardware serial interface SPI. At the same time, additional software serial parallel interface and hardware parallel interface are reserved.

[0292] In this embodiment, each high-voltage unit is independent, and this application can meet the requirement of 128 high-voltage output channels, utilizing the remaining ADC pins to reach peak performance. Devices in every 8 channels are multiplexed using switch control, forming a minimum subset that can be configured according to the required number of simultaneous measurements. By increasing the number of ADC channels, the final number of simultaneous measurements can be increased, depending on board size limitations.

[0293] The features described in the various embodiments of this specification can be substituted for or combined with each other. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0294] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0295] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high voltage power supply circuit for a test apparatus, characterized by, The high-voltage power supply circuit is independent of the test equipment; The high-voltage power supply circuit comprises a controller, a DAC module, an OPA module, an ADC module and M high-voltage output circuits; the high-voltage output circuit comprises a multiplexing selection circuit, N high-voltage channel selection circuits and N high-voltage units, the multiplexing selection circuit comprises an ADC channel selection circuit, a VSIM channel selection circuit and an MVM channel selection circuit; M is a positive integer, and N is an integer greater than 1; wherein: The N high-voltage channel selection circuits and the N high-voltage units correspond to each other one by one; One end of the high-voltage channel selection circuit is connected to the other end of the high-voltage unit through the DAC module and the OPA module in sequence. The other end of the high-voltage channel selection circuit serves as an output end of the high-voltage power supply circuit and is connected to the device under test; The second end of the controller is connected to the output end of the ADC module; The four input ends of the ADC module correspond to the four output ends of the ADC channel selection circuit one by one; each input end of the ADC module is connected to each output end of the ADC channel selection module in correspondence; The two first input ends of the ADC channel selection module correspond to the two output ends of the VSIM channel selection circuit one by one; each first input end of the ADC channel selection module is connected to each output end of the VSIM channel selection circuit in correspondence; The two second input ends of the ADC channel selection module correspond to the two output ends of the MVM channel selection circuit one by one; each second input end of the ADC channel selection module is connected to each output end of the MVM channel selection circuit in correspondence; The two input ends of the VSIM channel selection circuit are connected to the positive and negative poles of the current sampling end in the high-voltage unit in correspondence; The input end of the MVM channel selection circuit is connected to the voltage sampling end of the high-voltage unit; The ADC channel selection circuit, the VSIM channel selection circuit, the MVM channel selection circuit, the high-voltage unit and the high-voltage channel selection circuit are all controlled by the controller.

2. The high voltage power supply circuit for a test apparatus according to claim 1, characterized by, The OPA module comprises a same-phase adder and a follower; The input end of the same-phase adder is connected to the output end of the DAC module; The output end of the same-phase adder is connected to the input end of the follower; The output end of the follower serves as the output end of the OPA module; The positive power supply end of the same-phase adder and the positive power supply end of the follower are both connected to a 30V power supply; The negative power supply end of the same-phase adder and the negative power supply end of the follower are both connected to a -5V power supply.

3. The high voltage power supply circuit for a test apparatus according to claim 2, wherein The same-phase adder comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier and a first capacitor; One end of the third resistor serves as the input end of the same-phase adder; The positive-phase input end of the first operational amplifier is connected to the other end of the third resistor, one end of the fourth resistor and one end of the first capacitor, respectively; The negative-phase input end of the first operational amplifier is connected to one end of the first resistor and the other end of the second resistor, respectively; An output end of the first operational amplifier is connected with another end of the second resistor, and a connecting point is an output end of the non-inverting adder; Positive and negative supply ends of the first operational amplifier are positive and negative supply ends of the non-inverting adder; Another end of the fourth resistor is connected with a reference power supply, and another end of the first capacitor and another end of the first resistor are grounded.

4. The high voltage power supply circuit for a test apparatus according to claim 2, wherein The follower comprises two follower units, a connecting point after the input ends of the two follower units is an input end of the follower, and output ends of the two follower units are output ends of the follower respectively; The follower unit comprises a second operational amplifier, a fifth resistor and a sixth resistor; A positive input end of the second operational amplifier is an input end of the follower unit; A negative input end of the second operational amplifier is connected with an output end of the second operational amplifier, one end of the fifth resistor and one end of the sixth resistor respectively; Another end of the sixth resistor is grounded; Another end of the fifth resistor is an output end of the follower unit; Positive and negative supply ends of the second operational amplifier are positive and negative supply ends of the follower unit.

5. The high voltage power supply circuit for a test apparatus according to claim 1, wherein N is 16, and the OPA module has two output ends; Input ends of eight high-voltage units are connected with one output end of the OPA module; Input ends of the other eight high-voltage units are connected with the other output end of the OPA module.

6. The high voltage power supply circuit for a test apparatus according to claim 1, wherein The high-voltage unit comprises an HV operational amplifier circuit, a current sampling circuit and a switching unit, the HV operational amplifier circuit comprises a high-voltage operational amplifier, a seventh resistor, an eighth resistor and a ninth resistor, the current sampling circuit comprises a tenth resistor and a first switch, and the switching unit comprises a second switch and a third switch; A positive input end of the high-voltage operational amplifier is an input end of the high-voltage unit; A negative input end of the high-voltage operational amplifier is connected with one end of the seventh resistor; An output end of the high-voltage operational amplifier is connected with one end of the eighth resistor and one end of the ninth resistor respectively, and a connecting point is a positive pole of a current sampling end of the high-voltage unit; Another end of the ninth resistor is connected with one end of the third switch, one end of the eighth resistor and one end of the first switch respectively, and a connecting point is a negative pole of the current sampling end of the high-voltage unit; Another end of the seventh resistor is connected with another end of the eighth resistor and one end of the second switch respectively, and a connecting point is a voltage sampling end of the high-voltage unit; Another end of the first switch is connected with another end of the tenth resistor; Another end of the second switch is a first output end of the high-voltage unit; Another end of the third switch is a second output end of the high-voltage unit.

7. The high voltage power supply circuit for a test apparatus according to claim 1, wherein The high-voltage channel selection circuit comprises a first channel switch and a second channel switch; One end of the first channel switch is connected with the first output end of the high-voltage unit; One end of the second channel switch is connected with the second output end of the high-voltage unit; Another end of the first channel switch and another end of the second channel switch are connected, and a connecting point is an output end of the high-voltage channel selection circuit.

8. The high voltage power supply circuit for a test apparatus according to claim 1, wherein The ADC channel selection circuit comprises four MUX switches, four MUX operational amplifiers and four MUX resistors. One end of the first MUX switch is a first input end of the ADC channel selection circuit; the other end of the first MUX switch is connected with one end of the first MUX resistor and the positive input end of the first MUX operational amplifier respectively; the other end of the first MUX resistor is grounded; the positive power supply end of the first MUX operational amplifier is connected with the positive power supply; the negative power supply end of the first MUX operational amplifier is connected with the negative power supply; and the output end of the first MUX operational amplifier is a first output end of the ADC channel selection circuit. One end of the second MUX switch is another first input end of the ADC channel selection circuit; the other end of the second MUX switch is connected with one end of the second MUX resistor and the positive input end of the second MUX operational amplifier respectively; the other end of the second MUX resistor is grounded; and the output end of the second MUX operational amplifier is a second output end of the ADC channel selection circuit. One end of the third MUX switch is a second input end of the ADC channel selection circuit; the other end of the third MUX switch is connected with one end of the third MUX resistor and the positive input end of the third MUX operational amplifier respectively; the other end of the third MUX resistor is grounded; the positive power supply end of the third MUX operational amplifier is connected with the positive power supply; the negative power supply end of the third MUX operational amplifier is connected with the negative power supply; and the output end of the third MUX operational amplifier is a third output end of the ADC channel selection circuit. One end of the fourth MUX switch is another second input end of the ADC channel selection circuit; the other end of the fourth MUX switch is connected with one end of the fourth MUX resistor and the positive input end of the fourth MUX operational amplifier respectively; the other end of the fourth MUX resistor is grounded; and the output end of the fourth MUX operational amplifier is a fourth output end of the ADC channel selection circuit.

9. The high voltage power supply circuit for a test apparatus according to claim 1, wherein The VSIM channel selection circuit comprises two first multiplexing circuits; each first multiplexing circuit comprises a first multiplexing chip, a fifth MUX operational amplifier, a sixth MUX operational amplifier, a gain chip and four multiplexing resistors. The VDD pin of the first multiplexing chip is connected with the positive power supply; the VSS pin of the first multiplexing chip is connected with the negative power supply; the EPAD pin and the GND pin of the first multiplexing chip are grounded. The non-inverting input end of the fifth MUX operational amplifier is connected with the DA pin of the first multiplexing chip. The negative input end of the fifth MUX operational amplifier is connected with the output end of the fifth MUX operational amplifier, one end of the first multiplexing resistor and one end of the second multiplexing resistor. The non-inverting input end of the sixth MUX operational amplifier is connected with the DB pin of the first multiplexing chip. The other end of the first multiplexing resistor is connected with the -INA pin of the gain chip. The negative input end of the sixth MUX operational amplifier is connected with the output end of the sixth MUX operational amplifier, one end of the third multiplexing resistor and one end of the fourth multiplexing resistor; The other end of the third multiplexing resistor is connected with the +INA pin of the gain chip; The other end of the second multiplexing resistor, the other end of the fourth multiplexing resistor and the REF pin of the gain chip are grounded; The positive power supply end of the fifth MUX operational amplifier, the positive power supply end of the sixth MUX operational amplifier and the positive power supply end of the gain chip are connected with a positive power supply; The negative power supply end of the fifth MUX operational amplifier, the negative power supply end of the sixth MUX operational amplifier and the negative power supply end of the gain chip are connected with a negative power supply; The OUT pin of the gain chip is connected with the anode of the first diode, and the connection point is used as the output end of the first multiplexing circuit; The input end of the first multiplexing chip is used as the input end of the first multiplexing circuit; The cathode of the first diode receives a first clamping voltage.

10. The high voltage power supply circuit for a test apparatus according to claim 1, wherein The MVM channel selection circuit comprises two second multiplexing circuits, and each second multiplexing circuit comprises a second multiplexing chip and a seventh MUX operational amplifier; The input end of the second multiplexing chip is used as the input end of the second multiplexing circuit; The D pin of the second multiplexing chip is connected with one end of a fifth multiplexing resistor; The other end of the fifth multiplexing resistor is connected with the positive-phase input end of the seventh MUX operational amplifier and one end of a sixth multiplexing resistor respectively, and the other end of the sixth multiplexing resistor is grounded; The negative-phase input end of the seventh MUX operational amplifier is connected with one end of a seventh multiplexing resistor and one end of an eighth multiplexing resistor respectively; The other end of the seventh multiplexing resistor receives a bias voltage; The output end of the seventh MUX operational amplifier is connected with the other end of the eighth multiplexing resistor and the anode of a second diode respectively, and the connection point is used as the output end of the second multiplexing circuit; The cathode of the second diode receives a second clamping voltage.

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