Three-level inverter circuit and its control method

Abstract

This application relates to the field of three-level inverter technology, and provides a three-level inverter circuit and its control method. The circuit includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit, and a controller. The controller is used to acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector forming a reference voltage vector. Between adjacent first and second vectors, a first zero vector and a second zero vector are inserted to form a vector sequence in which the first and second vectors are switched via zero vectors. Based on this vector sequence, the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit is controlled. The three-level inverter circuit provided in this application can reduce losses on switching devices while maintaining neutral point voltage balance.

Description

Technical Field

[0001] This application relates to the field of three-level inverter technology, specifically to a three-level inverter circuit and its control method. Background Technology

[0002] With the increasing DC voltage and power levels, and the rising frequency requirements of high-speed drivers, three-level inverters are now commonly used to meet the demands of high-voltage, high-power applications. In these applications, SVPWM vector modulation is employed to determine the synthesized voltage vectors and corresponding switching devices used in the three-level inverter. From these synthesized voltage vectors, a reference voltage vector is derived to form a switching sequence for controlling the inverter's operation. However, the switching sequence in existing technologies results in significant losses on the switching devices of the three-level inverter. Therefore, reducing these losses to improve the overall efficiency of the three-level inverter circuit is a pressing issue that needs to be addressed. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems existing in the related art. To this end, this application proposes a control method for a three-level inverter circuit, which can reduce the losses of switching devices while maintaining the balance of the midpoint voltage.

[0004] This application also proposes a three-level inverter circuit, which can reduce the cost of existing solutions. Furthermore, when using the control method proposed in this application, dead time can be eliminated, further improving efficiency.

[0005] This application also proposes a control device for a three-level inverter circuit.

[0006] This application also proposes an electronic device.

[0007] The three-level inverter circuit according to the first aspect of this application includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit, and a controller.

[0008] One end of the first half-bridge circuit is connected to one end of the second half-bridge circuit, the other end of the first half-bridge circuit is connected to one end of the first capacitor, the other end of the second half-bridge circuit is connected to one end of the second capacitor, the first capacitor and the second capacitor are connected in series, and one end of the first half-bridge circuit is connected to the midpoint between the first capacitor and the second capacitor.

[0009] The three-phase inverter circuit includes a first half-bridge, a second half-bridge, and a third half-bridge, which are connected in parallel. One end of the first half-bridge is connected to the midpoint of the first half-bridge circuit, and the other end of the first half-bridge is connected to the midpoint of the second half-bridge circuit.

[0010] The controller is used to acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector that form a reference voltage vector, and to insert a first zero vector and a second zero vector between adjacent first and second vectors to form a vector sequence in which the first vector and the second vector are switched by the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit according to the vector sequence.

[0011] Wherein, the first vector and the second vector are vectors that cause the change in the midpoint current between the first capacitor and the second capacitor;

[0012] The zero vector includes a first zero vector or a second zero vector. The first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit. The first vector and the adjacent zero vector are connected to the same switching device in the three-phase inverter circuit, and the second vector and the adjacent zero vector are connected to the same switching device in the three-phase inverter circuit.

[0013] According to one embodiment of this application, the controller is specifically used for:

[0014] Sort the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors. Then, insert the first zero vector and the second zero vector sequentially between the first vector and the second vector, and insert the second zero vector and the first zero vector sequentially between the second vector and the first vector to obtain the vector sequence; or,

[0015] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is located between the two second vectors;

[0016] Between the second vector and the first vector, the second zero vector and the first zero vector are inserted sequentially, and between the first vector and the second vector, the first zero vector and the second zero vector are inserted sequentially to obtain the vector sequence.

[0017] According to one embodiment of this application, the control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0018] The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0019] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0020] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0021] According to one embodiment of this application, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on.

[0022] The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0023] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0024] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0025] According to one embodiment of this application, the control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0026] The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0027] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0028] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0029] According to one embodiment of this application, the control strategy corresponding to the first vector includes the lower bridge arm of the first half-bridge circuit being turned on, the lower bridge arm of the second half-bridge circuit being turned on, the upper bridge arm of the first half-bridge being turned on, and the lower bridge arms of the second half-bridge and the third half-bridge being turned on.

[0030] The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0031] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0032] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0033] According to one embodiment of this application, the first half-bridge circuit includes a first switching device and a second switching device, and the second half-bridge circuit includes a third switching device and a fourth switching device.

[0034] The first switching device, the second switching device, the third switching device, and the fourth switching device are connected in series, and one end of the second switching device connected to the third switching device is connected to the midpoint between the first capacitor and the second capacitor.

[0035] The second and third switching devices are passive power devices.

[0036] The control method for a three-level inverter circuit according to the second aspect of this application, applied to a three-level inverter circuit as described in any of the above embodiments, includes:

[0037] Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector;

[0038] Between adjacent first and second vectors, a first zero vector and a second zero vector are inserted to form a vector sequence that switches between the first and second vectors via the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit according to the vector sequence.

[0039] A control device for a three-level inverter circuit according to a third aspect embodiment of this application, applied to a three-level inverter circuit as described in any of the above embodiments, includes:

[0040] The vector acquisition module is used to acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector that form the reference voltage vector.

[0041] The on / off control module is used to insert a first zero vector and a second zero vector between adjacent first and second vectors to form a vector sequence in which the first vector and the second vector are switched through the zero vector, so as to control the on / off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0042] An electronic device according to a fourth aspect of this application includes a processor and a memory storing a computer program, wherein the processor executes the computer program to implement the control method of the three-level inverter circuit described in any of the above embodiments.

[0043] A computer-readable storage medium according to a fifth aspect of this application stores a computer program thereon, which, when executed by a processor, implements the control method of the three-level inverter circuit described in any of the above embodiments.

[0044] A vehicle according to a fifth aspect of this application includes a three-level inverter circuit as described in the first aspect, or an electronic device as described in the fourth aspect.

[0045] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects:

[0046] By acquiring at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first and second vectors, a vector sequence is formed in which the first and second vectors are switched via the zero vector. Based on this vector sequence, the switching on and off of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit is controlled. Since the switching between the first and second vectors is via the zero vector, and the voltage is zero at the zero vector, there are no switching losses during the control of the switching on and off of each device. Therefore, the losses to the switching devices can be effectively reduced, the operating efficiency of the entire three-level inverter circuit can be improved, and the balance of the midpoint voltage can be maintained. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 This is a first structural schematic diagram of the three-level inverter circuit provided in the embodiments of this application;

[0049] Figure 2 This is a schematic diagram of the second structure of the three-level inverter circuit provided in the embodiments of this application;

[0050] Figure 3 This is a schematic diagram of the control method for the three-level inverter circuit provided in the embodiments of this application;

[0051] Figure 4 This is a schematic diagram of the control device for the three-level inverter circuit provided in the embodiments of this application;

[0052] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] With the increasing DC voltage and power levels, and the rising frequency requirements of high-speed drivers, three-level inverters are now commonly used to meet the demands of high-voltage, high-power applications. In these applications, SVPWM vector modulation is employed to determine the composite voltage vector used by the three-level inverter and the corresponding switching devices. From these composite voltage vectors, the first vector, second vector, and zero vector that form the reference voltage vector are obtained to create a switching sequence for controlling the three-level inverter. The first and second vectors are the vectors that change the midpoint voltage of the three-level inverter.

[0055] However, the switching sequence formed in the existing technology causes significant losses to the switching devices of the three-level inverter. Therefore, how to reduce the losses to the switching devices and improve the overall efficiency of the three-level inverter circuit is an urgent problem to be solved.

[0056] To address the aforementioned problems, embodiments of this application provide a three-level inverter circuit, such as... Figure 1 As shown, the three-level inverter circuit includes a first half-bridge circuit 10, a second half-bridge circuit 20, a first capacitor C1, a second capacitor C2, a three-phase inverter circuit 30, and a controller.

[0057] One end of the first half-bridge circuit 10 is connected to one end of the second half-bridge circuit 20, the other end of the first half-bridge circuit 10 is connected to one end of the first capacitor C1, the other end of the second half-bridge circuit 20 is connected to one end of the second capacitor C2, the first capacitor C1 and the second capacitor C2 are connected in series, and one end of the first half-bridge circuit 10 is connected to the midpoint between the first capacitor C1 and the second capacitor C2.

[0058] The three-phase inverter circuit 30 includes a first half-bridge, a second half-bridge, and a third half-bridge, which are connected in parallel. One end of the first half-bridge is connected to the midpoint of the first half-bridge circuit 10, and the other end of the first half-bridge is connected to the midpoint of the second half-bridge circuit 20.

[0059] The controller is used to acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector that form a reference voltage vector, and to insert a first zero vector and a second zero vector between adjacent first and second vectors to form a vector sequence that switches between the first and second vectors through the zero vector, so as to control the on / off state of each device in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 according to the vector sequence.

[0060] Wherein, the first vector and the second vector are vectors that cause the change in the midpoint current between the first capacitor C1 and the second capacitor C2;

[0061] The zero vector includes a first zero vector or a second zero vector. The first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit 30. The first vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit 30. The second vector and the adjacent zero vector have the same switching device turned on in the three-phase inverter circuit 30.

[0062] In some embodiments, the first half-bridge circuit 10 includes a first switching device sp and a second switching device dp, and the second half-bridge circuit 20 includes a third switching device dn and a fourth switching device sn.

[0063] A first switching device sp, a second switching device dp, a third switching device dn, and a fourth switching device sn are connected in series. One end of the first switching device sp is connected to one end of the first capacitor C1, and one end of the fourth switching device sn is connected to one end of the second capacitor C2. The end of the third switching device dn connected to the fourth switching device sn is connected to the midpoint between the first capacitor C1 and the second capacitor C2. All of the first switching device sp, the second switching device dp, the third switching device dn, and the fourth switching device sn can be active switching devices, such as IGBT (Insulated Gate Bipolar Transistor) modules.

[0064] One end of the first capacitor C1 can be connected to the positive terminal of the power supply, and one end of the second capacitor C2 can be connected to the negative terminal of the power supply. The first capacitor C1 and the second capacitor C2 can be the same capacitor.

[0065] The three-phase inverter circuit 30 includes a first half-bridge, a second half-bridge, and a third half-bridge. The upper arm of the first half-bridge includes a first switch sa1, and the lower arm includes a second switch sa2. The upper arm of the second half-bridge includes a third switch sb1, and the lower arm includes a fourth switch sb2. The upper arm of the third half-bridge includes a fifth switch sc1, and the lower arm includes a sixth switch sc2. All switches sa1, sa2, sb1, sb2, sc1, and sc2 can be active switching devices, such as IGBT modules. Switches sa1 and sa2 are interlocked, as are sb1 and sb2, and sc1 and sc2. The three-phase inverter circuit 30 can be connected to a three-phase circuit. For example, it can be connected to a three-phase motor, such as the first, second, and third half-bridges being connected to phases A, B, and C of the motor, respectively.

[0066] According to SVPWM modulation theory, each phase of a three-level inverter circuit can have three states, resulting in a total of 27 switching states and 27 synthesized voltage vectors. These 27 synthesized voltage vectors include a large vector (lv), a small vector (sv), and a zero vector (zv). The large vector (lv) and the zero vector (zv) have no effect on the midpoint voltage between the first capacitor C1 and the second capacitor C2, while the polarity of the small vector (sv) does affect the midpoint voltage. The synthesized voltage vectors can form a reference voltage vector, which is the voltage vector used to synthesize the desired output voltage in three-level SVPWM modulation; that is, the voltage vector of the desired output voltage obtained by the three-level inverter circuit through SVPWM modulation. Therefore, the corresponding synthesized voltage vectors can be formed to output the reference voltage vector by controlling the switching devices of the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30.

[0067] Since the large vector lv has no effect on the midpoint voltage, the reference voltage vector can be composed of multiple small vectors sv and zero vector zv. For example, the reference voltage vector can be composed of small vectors and zero vectors. The controller can store the small vectors sv and zero vectors zv that make up a certain reference voltage vector, as well as the control strategy of the three-phase inverter circuit 30 corresponding to any small vector sv and the control strategy of the three-phase inverter circuit 30 corresponding to any zero vector zv.

[0068] For example, the vector set forming a reference voltage vector may include two identical small vectors, another small vector, a zero vector identical to the two identical small vectors in the switching device that is turned on in the three-phase inverter circuit 30, and a zero vector identical to the other small vector in the switching device that is turned on in the three-phase inverter circuit 30. After determining the reference voltage vector, the controller can determine the sector in which the reference voltage vector is located based on the phase angle and modulation ratio of the reference voltage vector, and determine the vector set that makes up the reference voltage vector based on the sector, so that the two identical small vectors in the vector set are determined as the first vector and the other small vector is determined as the second vector, or the two identical small vectors are determined as the second vector and the other small vector is determined as the first vector. At the same time, the zero vector identical to the first vector in the switching device that is turned on in the three-phase inverter circuit 30 is determined as the first zero vector, and the zero vector identical to the second vector in the switching device that is turned on in the three-phase inverter circuit 30 is determined as the second zero vector.

[0069] After obtaining at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form the reference voltage vector, the first vector and the second vector can be alternately sorted, and then the first zero vector and the second zero vector can be inserted between adjacent first vectors and second vectors to form a vector sequence, so that the first vector and the second vector can be switched through the zero vector.

[0070] After obtaining the vector sequence, the devices in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 can be controlled according to the vector sequence. For example, if the vector sequence is first vector - first zero vector - second zero vector - second vector - second zero vector - first zero vector - first vector, then the devices in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 can be controlled first according to the control strategy corresponding to the first vector, and then the devices in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 can be controlled according to the control strategy corresponding to the first zero vector, and so on, so as to form a reference voltage vector through the three-level inverter circuit.

[0071] By acquiring at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first and second vectors, a vector sequence is formed in which the first and second vectors are switched via the zero vector. Based on this vector sequence, the switching on and off of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit is controlled. Since the switching between the first and second vectors is via the zero vector, and the voltage is zero at the zero vector, there are no switching losses during the control of the switching on and off of each device. Therefore, the losses to the switching devices can be effectively reduced, and the operating efficiency of the entire three-level inverter circuit can be improved. The polarity of the midpoint current of the second vector can be selected, thus maintaining the balance of the midpoint voltage.

[0072] In some embodiments, the controller is specifically used for:

[0073] Sort the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors. Then, insert the first zero vector and the second zero vector sequentially between the first vector and the second vector, and insert the second zero vector and the first zero vector sequentially between the second vector and the first vector to obtain the vector sequence; or,

[0074] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is located between the two second vectors;

[0075] Between the second vector and the first vector, the second zero vector and the first zero vector are inserted sequentially, and between the first vector and the second vector, the first zero vector and the second zero vector are inserted sequentially to obtain the vector sequence.

[0076] As one possible implementation, the vector set forming the reference voltage vector may include two first vectors svi, a second vector svj, a first zero vector zvi, and a second zero vector zvj. After inserting the second vector svj between the two first vectors svi to obtain a first initial sequence svi–svj–svi, the first vector svi and the second zero vector zvj are sequentially inserted between the first vector svi and the second vector svj. Then, the second zero vector zvj and the first zero vector svi are sequentially inserted between the second vector svj and the first vector svi to obtain the vector sequence: svi–zvi–zvj–svj–zvj–zvi–svi.

[0077] As another possible implementation, the vector set forming the reference voltage vector may include a first vector svi, two second vectors svj, a first zero vector zvi, and a second zero vector zvj. After inserting the first vector svi between the two second vectors svj to obtain the second initial sequence svj–svi–svj, the second zero vector zvj and the first zero vector svi are sequentially inserted between the second vectors svj and the first vector svi. Then, the first vector svi and the second zero vector zvj are sequentially inserted between the first vector svi and the second vector svj to obtain the vector sequence: svj-zvj–zvi–svi–zvi–zvj–svj.

[0078] At this time, when the vector sequence is used to control the on and off of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30, there are a total of 6 switching actions. Since the voltage is zero when the zero vector is used, there is no switching loss in the process of controlling the on and off of each device. Therefore, when the vector sequence obtained in the above way controls the on and off of each device, there are only 4 switching losses, thereby further reducing the switching loss of the three-level inverter circuit.

[0079] In some embodiments, the first vector can be denoted as sv1p, the second vector as sv2n, the first zero vector as zv1, and the second zero vector as zv2. The control strategy corresponding to sv1p includes the following: the upper arm of the first half-bridge circuit 10 is turned on; the upper arm of the second half-bridge circuit 20 is turned on; the upper arm of the first half-bridge is turned on; and the lower arms of the second and third half-bridges are turned on. That is, the first switching device sp is turned on; the third switching device dn is turned on; the first switch sa1 is turned on; the fourth switch sb2 is turned on; and the sixth switch sc2 is turned on. The control strategy corresponding to sv2n includes the following: the lower arm of the first half-bridge circuit 10 is turned on; the lower arm of the second half-bridge circuit 20 is turned on; the upper arms of the first and second half-bridges are turned on; and the lower arm of the third half-bridge is turned on. That is, the second switching device dp and the fourth switching device sn are turned on; the first switch sa1 is turned on; the third switch sb1 is turned on; and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arm of the first half-bridge, and turning on the lower arms of the second and third half-bridges; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the fourth switch sb2, and turning on the sixth switch sc2. The control strategy corresponding to zv2 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arms of the first and second half-bridges, and turning on the lower arm of the third half-bridge; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the third switch sb1, and turning on the sixth switch sc2.

[0080] The vector sequence obtained by the controller is:

[0081] sv1 p-zv1-zv2-sv2n-zv2-zv1-sv1 p;

[0082] or sv2n-zv2-zv1-sv1 p-zv1-zv2-sv2n

[0083] At this point, the on / off states of each device in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 can be controlled sequentially using the aforementioned vector sequence and control strategy.

[0084] In some embodiments, the first vector can be denoted as sv1n, the second vector can be denoted as sv2p, the first zero vector can be denoted as zv1, and the second zero vector can be denoted as zv2. The control strategy corresponding to sv1n includes the conduction of the lower arm of the second half-bridge circuit 20, the conduction of the upper arm of the first half-bridge, and the conduction of the lower arms of the second and third half-bridges; that is, the conduction of the second switching device dp, the conduction of the fourth switching device sn, the conduction of the first switch sa1, the conduction of the fourth switch sb2, and the conduction of the sixth switch sc2. The control strategy corresponding to sv2p includes the conduction of the upper arm of the first half-bridge circuit 10, the conduction of the upper arm of the second half-bridge circuit 20, the conduction of the upper arms of the first and second half-bridges, and the conduction of the lower arm of the third half-bridge; that is, the conduction of the first switching device sp and the third switching device dn, the conduction of the first switch sa1, the conduction of the third switch sb1, and the conduction of the sixth switch sc2. The control strategy corresponding to zv1 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arm of the first half-bridge, and turning on the lower arms of the second and third half-bridges; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the fourth switch sb2, and turning on the sixth switch sc2. The control strategy corresponding to zv2 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arms of the first and second half-bridges, and turning on the lower arm of the third half-bridge; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the third switch sb1, and turning on the sixth switch sc2.

[0085] The vector sequence obtained by the controller is:

[0086] sv1 n-zv1-zv2-sv2p-zv2-zv1-sv1 n;

[0087] or sv2p-zv2-zv1-sv1 n-zv1-zv2-sv2p

[0088] At this point, the on / off states of each device in the first half-bridge circuit 10, the second half-bridge circuit 20, and the three-phase inverter circuit 30 can be controlled sequentially using the aforementioned vector sequence and control strategy.

[0089] However, considering that the duty cycle of the first zero vector and the second zero vector is determined when using the control strategy corresponding to the above vector sequence to control the on / off state of the device, the on / off control using the control strategy corresponding to the above vector sequence cannot balance the midpoint voltage between the first capacitor C1 and the second capacitor C2.

[0090] Therefore, in some embodiments, the first vector can be denoted as sv1p, the second vector as sv2p, the first zero vector as zv1, and the second zero vector as zv2. The control strategy corresponding to sv1p includes the conduction of the upper arm of the first half-bridge circuit 10, the upper arm of the second half-bridge circuit 20, the upper arm of the first half-bridge, and the lower arms of the second and third half-bridges; that is, the conduction of the first switching device sp, the third switching device dn, the first switch sa1, the fourth switch sb2, and the sixth switch sc2. The control strategy corresponding to sv2p includes the conduction of the upper arm of the first half-bridge circuit 10, the upper arm of the second half-bridge circuit 20, the upper arms of the first and second half-bridges, and the lower arm of the third half-bridge; that is, the conduction of the first switching device sp and the third switching device dn, the conduction of the first switch sa1, the third switch sb1, and the sixth switch sc2. The control strategy corresponding to zv1 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arm of the first half-bridge, and turning on the lower arms of the second and third half-bridges; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the fourth switch sb2, and turning on the sixth switch sc2. The control strategy corresponding to zv2 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arms of the first and second half-bridges, and turning on the lower arm of the third half-bridge; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the third switch sb1, and turning on the sixth switch sc2.

[0091] The vector sequence obtained by the controller is:

[0092] sv1 p-zv1-zv2-sv2p-zv2-zv1-sv1 p;

[0093] Or sv2p-zv2-zv1-sv1p-zv1-zv2-sv2p

[0094] Since the polarity of the first or second vector is changed at this time, when the control strategy corresponding to the above vector sequence is used to control the on / off state of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30 in sequence, the polarity of the first or second vector can be used to balance the midpoint voltage.

[0095] Alternatively, in some embodiments, the first vector can be denoted as sv1n, the second vector as sv2n, the first zero vector as zv1, and the second zero vector as zv2. The control strategy corresponding to sv1n includes the following: the lower arm of the first half-bridge circuit 10 is turned on; the lower arm of the second half-bridge circuit 20 is turned on; the upper arm of the first half-bridge is turned on; and the lower arms of the second and third half-bridges are turned on. That is, the second switching device dp is turned on; the fourth switching device sn is turned on; the first switch sa1 is turned on; the fourth switch sb2 is turned on; and the sixth switch sc2 is turned on. The control strategy corresponding to sv2n includes the following: the lower arm of the first half-bridge circuit 10 is turned on; the lower arm of the second half-bridge circuit 20 is turned on; the upper arms of the first and second half-bridges are turned on; and the lower arm of the third half-bridge is turned on. That is, the second switching device dp and the fourth switching device sn are turned on; the first switch sa1 is turned on; the third switch sb1 is turned on; and the sixth switch sc2 is turned on. The control strategy corresponding to zv1 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arm of the first half-bridge, and turning on the lower arms of the second and third half-bridges; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the fourth switch sb2, and turning on the sixth switch sc2. The control strategy corresponding to zv2 includes short-circuiting the first half-bridge circuit 10 and the second half-bridge circuit 20, turning on the upper arms of the first and second half-bridges, and turning on the lower arm of the third half-bridge; that is, turning on the second switching device dp and the third switching device dn, turning on the first switch sa1, turning on the third switch sb1, and turning on the sixth switch sc2.

[0096] The vector sequence obtained by the controller is:

[0097] sv1 n-zv1-zv2-sv2n-zv2-zv1-sv1 n;

[0098] or sv2n-zv2-zv1-sv1 n-zv1-zv2-sv2n

[0099] Since the polarity of the first or second vector is changed at this time, when the control strategy corresponding to the above vector sequence is used to control the on / off state of each device in the first half-bridge circuit 10, the second half-bridge circuit 20 and the three-phase inverter circuit 30 in sequence, the polarity of the first or second vector can be used to balance the midpoint voltage.

[0100] Considering that the first switching device sp, the second switching device dp, the third switching device dn, and the fourth switching device sn are all active switching devices, a dead time needs to be forcibly inserted to prevent short circuits and burnouts caused by the simultaneous conduction of the first switching device sp and the second switching device dp, or by the simultaneous conduction of the third switching device dn and the fourth switching device sn. Therefore, in some embodiments, such as... Figure 2As shown, the second switching device dp and the third switching device dn are passive power devices. For example, the second switching device dp and the third switching device dn can be diodes. Since the second switching device dp and the third switching device dn are not short-circuited, there is no need to insert a dead time. With no dead time in the first half-bridge circuit 10 and the second half-bridge circuit 20, only the dead time needs to be set for the three-phase inverter circuit 30. However, when performing on / off control based on the vector sequence proposed above, the devices in the three-phase inverter circuit 30 are in a ZVS state during switching, and no dead time is needed. Therefore, there is no need to set a dead time, further improving the operating efficiency of the three-level inverter circuit.

[0101] Figure 3 A flowchart illustrating a control method for a three-level inverter circuit according to an embodiment of this application is shown. This control method for the three-level inverter circuit is applied to the three-level inverter circuit in any of the above embodiments; specifically, it can be applied to the controller in any of the above embodiments.

[0102] In some embodiments, the control method for the three-level inverter circuit includes:

[0103] Step 101: Obtain at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form the reference voltage vector;

[0104] Step 102: Insert a first zero vector and a second zero vector between adjacent first and second vectors to form a vector sequence in which the first and second vectors are switched by the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0105] By acquiring at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector, and inserting the first zero vector and the second zero vector between adjacent first and second vectors, a vector sequence is formed in which the first and second vectors are switched via the zero vector. Based on this vector sequence, the switching on and off of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit is controlled. Since the switching between the first and second vectors is via the zero vector, and the voltage is zero at the zero vector, there are no switching losses during the control of the switching on and off of each device. Therefore, the losses to the switching devices can be effectively reduced, and the overall efficiency of the three-level inverter circuit can be improved.

[0106] In some embodiments, a first zero vector and a second zero vector are inserted between adjacent first and second vectors to form a vector sequence in which the first and second vectors are switched via zero vectors, including:

[0107] Sort the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors. Then, insert the first zero vector and the second zero vector sequentially between the first vector and the second vector, and insert the second zero vector and the first zero vector sequentially between the second vector and the first vector to obtain the vector sequence; or,

[0108] Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is located between the two second vectors;

[0109] Between the second vector and the first vector, the second zero vector and the first zero vector are inserted sequentially, and between the first vector and the second vector, the first zero vector and the second zero vector are inserted sequentially to obtain the vector sequence.

[0110] In some embodiments, the control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0111] The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0112] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0113] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0114] In some embodiments, the control strategy corresponding to the first vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0115] The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0116] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0117] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0118] In some embodiments, the control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0119] The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0120] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0121] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0122] In some embodiments, the control strategy corresponding to the first vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on.

[0123] The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on.

[0124] The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge.

[0125] The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

[0126] Figure 4This illustration shows a schematic structural block diagram of a control device for a three-level inverter circuit according to an embodiment of this application. It should be understood that this device is related to... Figure 3 The method embodiments described above correspond to the methods described in the previous embodiments, and the device is capable of performing the steps involved in the aforementioned methods. The specific functions of the device can be found in the description above; to avoid repetition, detailed descriptions are omitted here. The device includes at least one software functional module that can be stored in memory or embedded in the device's operating system (OS) in the form of software or firmware. Specifically, the device can be applied to the charging control subsystem in any of the above embodiments.

[0127] In one embodiment, such as Figure 4 As shown, a control device for a three-level inverter circuit is provided, comprising:

[0128] Vector acquisition module 210 is used to acquire at least one first vector, at least one second vector, a first zero vector and a second zero vector that form a reference voltage vector;

[0129] The on / off control module 220 is used to insert a first zero vector and a second zero vector between adjacent first vectors and second vectors to form a vector sequence in which the first vector and the second vector are switched through the zero vector, so as to control the on / off of each device in the first half-bridge circuit, the second half-bridge circuit and the three-phase inverter circuit according to the vector sequence.

[0130] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 81, a communication interface 82, a memory 83, and a communication bus 840, wherein the processor 81, the communication interface 82, and the memory 83 communicate with each other via the communication bus 840. The processor 81 can call a computer program in the memory 83 to execute a control method for the three-level inverter circuit, such as including:

[0131] Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector;

[0132] Between adjacent first and second vectors, a first zero vector and a second zero vector are inserted to form a vector sequence that switches between the first and second vectors via the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit according to the vector sequence.

[0133] Furthermore, the logical instructions in the aforementioned memory 83 can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] On the other hand, this application also provides a storage medium, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the control method of the three-level inverter circuit provided in the above embodiments.

[0135] On the other hand, embodiments of this application also provide a vehicle, including the three-level inverter circuit of any of the above embodiments, or the electronic device of the above embodiments.

[0136] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A three-level inverter circuit, characterized in that, It includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor, a second capacitor, a three-phase inverter circuit, and a controller; One end of the first half-bridge circuit is connected to one end of the second half-bridge circuit, the other end of the first half-bridge circuit is connected to one end of the first capacitor, the other end of the second half-bridge circuit is connected to one end of the second capacitor, the first capacitor and the second capacitor are connected in series, and one end of the first half-bridge circuit is connected to the midpoint between the first capacitor and the second capacitor. The three-phase inverter circuit includes a first half-bridge, a second half-bridge, and a third half-bridge, which are connected in parallel. One end of the first half-bridge is connected to the midpoint of the first half-bridge circuit, and the other end of the first half-bridge is connected to the midpoint of the second half-bridge circuit. The controller is used to acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector that form a reference voltage vector, and to insert a first zero vector and a second zero vector between adjacent first and second vectors to form a vector sequence in which the first vector and the second vector are switched by the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit according to the vector sequence. Wherein, the first vector and the second vector are vectors that cause the change in the midpoint current between the first capacitor and the second capacitor; The zero vector includes a first zero vector or a second zero vector. The first zero vector and the second zero vector correspond to different control strategies of the three-phase inverter circuit. The first vector and the adjacent zero vector are connected to the same switching device in the three-phase inverter circuit. The second vector and the adjacent zero vector are connected to the same switching device in the three-phase inverter circuit. The controller is specifically used for: Sort the two first vectors and the second vector to obtain a first initial sequence in which the second vector is located between the two first vectors. Then, insert the first zero vector and the second zero vector sequentially between the first vector and the second vector, and insert the second zero vector and the first zero vector sequentially between the second vector and the first vector to obtain the vector sequence; or, Sort the two second vectors and the first vector to obtain a second initial sequence in which the first vector is located between the two second vectors; Between the second vector and the first vector, the second zero vector and the first zero vector are inserted sequentially, and between the first vector and the second vector, the first zero vector and the second zero vector are inserted sequentially to obtain the vector sequence.

2. The three-level inverter circuit according to claim 1, characterized in that, The control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on. The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on. The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge. The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

3. The three-level inverter circuit according to claim 1, characterized in that, The control strategy corresponding to the first vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on. The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on. The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge. The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

4. The three-level inverter circuit according to claim 1, characterized in that, The control strategy corresponding to the first vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on. The control strategy corresponding to the second vector includes the upper arm of the first half-bridge circuit being turned on, the upper arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on. The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge. The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

5. The three-level inverter circuit according to claim 1, characterized in that, The control strategy corresponding to the first vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arm of the first half-bridge being turned on, and the lower arms of the second half-bridge and the third half-bridge being turned on. The control strategy corresponding to the second vector includes the lower arm of the first half-bridge circuit being turned on, the lower arm of the second half-bridge circuit being turned on, the upper arms of the first half-bridge and the second half-bridge being turned on, and the lower arm of the third half-bridge being turned on. The control strategy corresponding to the first zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge, and turning on the lower bridge arms of the second half-bridge and the third half-bridge. The control strategy corresponding to the second zero vector includes short-circuiting the first half-bridge circuit and the second half-bridge circuit, turning on the upper bridge arm of the first half-bridge and the second half-bridge, and turning on the lower bridge arm of the third half-bridge.

6. The three-level inverter circuit according to any one of claims 1-5, characterized in that, The first half-bridge circuit includes a first switching device and a second switching device, and the second half-bridge circuit includes a third switching device and a fourth switching device; The first switching device, the second switching device, the third switching device, and the fourth switching device are connected in series, and one end of the second switching device connected to the third switching device is connected to the midpoint between the first capacitor and the second capacitor. The second and third switching devices are passive power devices.

7. A control method for a three-level inverter circuit, characterized in that, The method, applied to the three-level inverter circuit as described in any one of claims 1-6, comprises: Acquire at least one first vector, at least one second vector, a first zero vector, and a second zero vector to form a reference voltage vector; Between adjacent first and second vectors, a first zero vector and a second zero vector are inserted to form a vector sequence that switches between the first and second vectors via the zero vector, so as to control the on / off state of each device in the first half-bridge circuit, the second half-bridge circuit, and the three-phase inverter circuit according to the vector sequence.

8. An electronic device comprising a processor and a memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the control method for the three-level inverter circuit as described in claim 7.

9. A vehicle, characterized in that, This includes the three-level inverter circuit as described in any one of claims 1-6, or the electronic device as described in claim 8.

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