Multi-module parallel inverter zero common mode modulation method based on unified voltage modulation

Abstract

The invention discloses a multi-module parallel inverter zero common mode modulation method based on unified voltage modulation. The method comprises the steps that effective time offsets of SPWM, SVPWM and DPWM of different clamps are calculated according to a modulation mode and a control period; according to amplitudes and phases of voltages of two sets of windings of the six-phase permanent magnet synchronous motor with 60-degree phase shift and Y-type connection, a relation between virtual conduction time of the UVW phase voltage and virtual conduction time of the ABC phase voltage is calculated; calculating the actual conduction time of a UVW winding switch tube and an ABC three-phase switch tube according to the relationship between the virtual conduction time of a UVW phase voltage and the virtual conduction time of an ABC phase voltage and the effective time offset, and inverting the conduction and turn-off states of the UVW winding switch tube and the conduction and turn-off states of the ABC three-phase switch tube; according to the method, common-mode voltage elimination of a parallel three-phase inverter driving phase shift 60-degree Y-type connection six-phase permanent magnet synchronous motor system is realized, the common-mode voltage can be effectively eliminated, the conducted electromagnetic interference of the system is reduced, and meanwhile, the cost is relatively low.

Description

Technical Field

[0001] The invention belongs to the technical field of motor drive, and relates to a zero common mode modulation method of a multi-module parallel inverter based on unified voltage modulation. Background Art

[0002] With the vigorous development of power electronics technology, it has been widely used in industrial products. In the motor drive system, power electronic switching devices have significantly improved the freedom of the control level, and the application of pulse width modulation technology has greatly improved the driving performance of the system, freeing the system from the constraints of industrial frequency drive, but it has led to the emergence of common-mode voltage problems. The common-mode voltage has high-frequency characteristics and can excite common-mode currents with higher frequencies, causing serious common-mode electromagnetic interference within a certain frequency range, affecting the reliability of the electric drive system itself and the normal operation of other sensitive equipment. In addition, the common-mode voltage can also cause damage to the insulation of the motor, and the common-mode current it excites will also bring additional losses to the electric drive system; reduce the life of the motor bearings; and increase the system operation and maintenance costs. Therefore, it is very necessary to study the suppression strategy of the common-mode voltage of the electric drive system. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a zero common-mode modulation method for multi-module parallel inverters based on unified voltage modulation, which can effectively eliminate common-mode voltage and reduce the conducted electromagnetic interference of the system while having low cost.

[0004] To achieve the above object, the zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation described in the present invention includes:

[0005] 1) Collect the phase voltage and DC side voltage of the six-phase permanent magnet synchronous motor with a phase shift of 60° Y-type connection;

[0006] 2) Compare the instantaneous value of each phase voltage with the amplitude of the DC side voltage to obtain the virtual on-time of the switch tube;

[0007] 3) According to the modulation mode and control period, the effective time offset of SPWM, SVPWM and DPWM with different clamping positions is calculated;

[0008] 4) According to the amplitude and phase of the two sets of winding voltages of the six-phase permanent magnet synchronous motor with a phase shift of 60° Y-type connection, the relationship between the virtual conduction time of the UVW phase voltage and the ABC phase voltage is calculated;

[0009] 5) According to the relationship between the virtual on-time of the UVW phase voltage and the ABC phase voltage and the effective time offset, the actual on-time of the UVW winding switch tube and the ABC three-phase switch tube is calculated, and the on-and-off states of the UVW winding switch tube and the on-and-off states of the ABC three-phase switch tube are reversed to achieve the common-mode voltage elimination of the parallel three-phase inverter driving the phase-shifted 60° Y-type connected six-phase permanent magnet synchronous motor system.

[0010] Furthermore, the virtual on-time T of the switch tube calculated in step 2) is as 、T bs and T cs for:

[0011]

[0012] Among them, U as * , U bs * and U cs * is the instantaneous value of the three-phase sine wave, U D is the DC bus voltage, T s is the carrier period.

[0013] Furthermore, the effective time offset of SPWM is:

[0014]

[0015] Among them, T s is the sampling period of space vector modulation.

[0016] Furthermore, the effective time offset of SVPWM is:

[0017]

[0018] Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

[0019] Furthermore, the effective time offset of the 60° clamped DPWM is:

[0020] if T min +T max ≥0→T offset =T s -Tmax

[0021] if T min +T max <0→T offset =-T min

[0022] Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

[0023] Furthermore, the effective time offset of the 30° clamped DPWM is:

[0024] if T min +T max ≥0→T offset =-T min

[0025] if T min +T max <0→T offset =T s -T max

[0026] Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

[0027] Furthermore, the effective time offset of the DPWM with 120° clamping at the positive peak of the voltage is:

[0028] T offset =T s -T max

[0029] Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ).

[0030] Furthermore, the effective time offset of the DPWM clamped at 120° at the negative peak of the voltage is:

[0031] T offset =-T min

[0032] Among them, T min =min(T as ,T bs ,T cs ).

[0033] Furthermore, the relationship between the virtual on-time of the UVW phase voltage and the ABC phase voltage is:

[0034]

[0035] in, Tas , Tas and Tbs is the virtual conduction time of the ABC phase voltage, Tus , Tvs and Tws is the virtual on-time of UVW phase voltage.

[0036] The present invention has the following beneficial effects:

[0037] In specific operation, the zero common-mode modulation method of the multi-module parallel inverter based on unified voltage modulation described in the present invention calculates the actual on-time of the UVW winding switch tube and the ABC three-phase switch tube according to the relationship between the virtual on-time of the UVW phase voltage and the ABC phase voltage and the effective time offset, and reverses the on- and off-states of the UVW winding switch tube and the on- and off-states of the ABC three-phase switch tube. While effectively eliminating the common-mode voltage and reducing the conducted electromagnetic interference of the system, uninterrupted switching of different modulation modes including SPWM, SVPWM, and DPWM with different clamps is achieved, which is suitable for a variety of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0039] Figure 1 The structure diagram of the system is a parallel three-phase inverter driving a 60° phase-shifted Y-type six-phase permanent magnet synchronous motor;

[0040] Figure 2 This is a common mode current conduction path diagram of a parallel three-phase inverter driving a 60° phase-shifted Y-type connected six-phase permanent magnet synchronous motor system;

[0041] Figure 3It is a schematic diagram of the common mode voltage of the seven-segment SVPWM;

[0042] Figure 4a It is a graph showing the relationship between the effective time of unified voltage modulation and the output voltage;

[0043] Figure 4b Schematic diagram of actual switch generation time for uniform voltage modulation;

[0044] Figure 5 It is a schematic diagram of Toffset.min and Toffset.max curves;

[0045] Figure 6 This is a schematic diagram of zero common mode modulation;

[0046] Figure 7 A schematic diagram of a control module for uniform voltage modulation;

[0047] Figure 8 A schematic diagram of a switching module for a modulation mode;

[0048] Fig. 9 It is the simulation waveform diagram of the unified voltage modulation module;

[0049] Fig.10 This is a detailed diagram of the simulation waveform of the unified voltage modulation module;

[0050] Fig.11 This is the simulation result diagram of the motor current;

[0051] Fig.12 The simulation result diagram of motor speed, electrical angle and electromagnetic torque;

[0052] Fig.13 This is the simulation result diagram of six-phase PWM wave;

[0053] Fig.14 This is the common mode voltage simulation result diagram;

[0054] Fig.15 This is the DC side common-mode conducted EMI simulation result diagram. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0057] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0058] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0059] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0060] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0062] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0063] The zero common mode modulation method of a multi-module parallel inverter based on unified voltage modulation of the present invention comprises the following steps:

[0064] like Figure 1 As shown, the phase-shifted 60° Y-type connected six-phase permanent magnet synchronous motor is composed of six-phase windings ABCUVW, where the ABC three-phase voltage is:

[0065]

[0066] UVW three-phase voltage is:

[0067]

[0068] Among them, U ref is the fundamental amplitude of the phase voltage, the angular frequency is ω=2πf, and f is the fundamental voltage frequency.

[0069] Comparing equations (1) and (2), we can obtain the relationship between the voltages of the three phases UVW and ABC:

[0070]

[0071] Taking the midpoint of the DC side as the reference point for calculating the common mode voltage, the common mode voltage V cm for:

[0072]

[0073] Among them, Sa, Sb, Sc, Su, Sv and Sw are the switching binary functions of the three-phase bridge arm. When the upper tube is turned on, it is 1, and when the lower tube is turned on, it is -1. The conduction path of the common-mode current caused by the common-mode voltage is as follows: Figure 2 shown.

[0074] At present, most motor drive systems adopt the traditional voltage space vector PWM modulation, namely SVPWM modulation technology. The six voltage vectors corresponding to the instantaneous values ​​of the three-phase sinusoidal AC voltage at θ = ωt = 0°, 60°, 120°, 180°, 240°, and 300° are: The 360° interval is divided into six sectors, each sector is 60°. The instantaneous value of each phase voltage required to be output at each moment The voltage vectors on both sides of the sector where this value is located can be used Add a zero vector The synthesis is performed, and its duration is T0 T1 T2 respectively.

[0075] in:

[0076]

[0077] Among them, T s is the sampling period of space vector modulation, m is the modulation degree of reference voltage vector, θ is the angle of reference voltage vector relative to α axis, and σ is the angle of reference voltage vector relative to the sector vector.

[0078] On this basis, by determining the sector where the reference vector is located, the non-zero vector and The action time T1 and T2 of the zero vector and the action time T0 of the zero vector are used to arrange the wave generation sequence to achieve the synthesis of the target voltage vector.

[0079] At present, SVPWM technology often adopts a seven-segment wave sequence, that is, zero vector (000)— Vector - Vector—Zero Vector (111)— Vector - Vector—zero vector (000), the corresponding action times are:

[0080] T0 / 4—T1 / 2(T2 / 2)—T2 / 2(T1 / 2)—T0 / 2—T2 / 2(T1 / 2)—T1 / 2(T2 / 2)—T0 / 4

[0081] Under this time allocation, we can get Figure 3The bridge arm voltage and common-mode voltage of each phase of the 60° Y-type connected permanent magnet synchronous motor system are shown. The common-mode voltage of the system presents a seven-stage step-type change between the four amplitudes of Vdc / 2, Vdc / 6, -Vdc / 6 and -Vdc / 2, and it can never be zero or maintained at a constant value. Therefore, if you want to eliminate the common-mode voltage, you need to optimize and improve the modulation strategy.

[0082] In a switching cycle, the synthesis of the reference vector is the result of the action of different voltage vectors, and the action time of different vectors is also different. The flow of energy is completed within the duration of the non-zero vector. In the present invention, the duration of the non-zero vector is defined as the effective time. Since the output voltage of the inverter is determined by the effective time, if the effective time can be reasonably arranged, the common mode voltage can be eliminated in the parallel three-phase inverter driving the phase shift 60° Y-type connection six-phase permanent magnet synchronous motor system.

[0083] Since the 60° phase-shifted Y-type connected six-phase permanent magnet synchronous motor can be equivalently replaced by two sets of three-phase windings with a phase difference of 60°, the three-phase system can be used as an example for equivalent analysis. In a three-phase system, when the switching state of one phase changes from 0 to 1, an effective time acts on the load. In the figure, U as * ,U bs * ,U cs * is the instantaneous value of the three-phase sine wave, U D is the DC bus voltage, T eff is the effective time, T s is the carrier period, then Figure 4a The proportional relationship shown is:

[0084]

[0085] Since the instantaneous value of voltage can be positive or negative, T as , T bs , T cs It can be positive or negative. In the present invention, this time is assumed to be virtual time. Assume that the effective time T eff is the difference between the maximum and minimum values ​​in virtual time, that is:

[0086] T eff =T max -T min (7)

[0087] Among them, T max =max(T as ,T bs ,T cs )T min =min(Tas ,T bs ,T cs ).

[0088] For different PWM algorithms, when obtaining the action signal of the switching device, the position of the effective time in the entire sampling period can be changed, thereby producing different effects. Therefore, the actual action time of each phase bridge arm T ga , T gb , T gc for:

[0089]

[0090] To generate a symmetrical PWM signal, such as Figure 4b As shown, we have:

[0091]

[0092] Among them, T offset is the offset of the effective time position. For different PWM methods, there are different T offset , at the effective time T eff If T offset This will cause the position of the effective time to shift, thereby changing the distribution position and action time of the zero vector and the effective vector, causing the generated PWM wave to change accordingly, resulting in different control effects.

[0093] To ensure that the actual on-off time is within the sampling period T s Within, formula (8) must also satisfy T ga T gb T gc All between 0 and T s Between, that is, satisfying: 0≤T min +T offset ,T max +T offset ≤T s .

[0094] Then we have:

[0095] T offset.min ≤T offset ≤T offset.max (10)

[0096] Among them, T offset.min =-T min , T offset.max =T s -T max .

[0097] Figure 5 T corresponding to the three-phase voltage offset.minWith T offset.max , the area between the two lines is T offset When the modulation index m=1.15, T offset.min With T offset.max The lines will cross, which is exactly what happens when the modulation is maximum.

[0098] In order to achieve uninterrupted switching of different modulation modes, the offset T of the effective time position under different modulation modes is offset The derivation is as follows:

[0099] 11) SPWM modulation;

[0100] For the widely used traditional carrier modulation, the phase voltage With pole voltage There is no difference between them. According to the proportional relationship of similar triangles, we have:

[0101]

[0102] Right now:

[0103]

[0104] Comparing equation (11) with equation (12), the zero vector offset of SPWM is obtained as:

[0105]

[0106] 12) SVPWM modulation;

[0107] SVPWM is based on the average voltage vector within a sampling period. When the reference voltage vector U* is given, the actual on-off time of each phase bridge arm. In SVPWM, the zero vector is symmetrically distributed at T s The beginning and end of

[0108]

[0109] 13) DPWM modulation;

[0110] In DPWM, 30° clamping, 60° clamping, and 120° clamping have always been the most popular. DPWM, like SVPWM, can achieve the maximum modulation degree. Although this modulation method brings a larger harmonic component compared to SVPWM, because each phase is clamped for a period of time, it can effectively reduce the switching frequency and reduce switching losses. However, since the waveform is no longer continuous, the current harmonics are also larger.

[0111] 13a) DPWM modulation with 60° clamping;

[0112] If the A-phase reference voltage reaches the maximum positive or negative value, the A-phase switch state is clamped at 1 or 0. That is, in the case of 60° clamping, there are:

[0113]

[0114] Thus, the time offset T is obtained offset The values ​​are:

[0115]

[0116] 13b) DPWM modulation with 30° clamping;

[0117] The switching loss of the 30° clamped DPWM does not depend on the phase angle. This is because the 30° clamped period is evenly distributed within a sampling period. Among various DPWMs, the current harmonics of the 30° clamped current are the smallest. This switching mode is exactly opposite to the 60° clamped current, so its time offset is:

[0118]

[0119] 13c) DPWM modulation with 120° clamping;

[0120] In a cycle, 120° clamping does not break for one third of the time, so the switching loss of 120° clamping is the smallest among these discontinuous modulation methods. The time offset of 120° clamping is divided into two cases:

[0121] 13c1) Clamping at the positive peak voltage is:

[0122] T offset =T s -T max (18)

[0123] 13c2) Clamping at the negative peak of voltage is:

[0124] T offset =-T min (19)

[0125] On this basis, in order to achieve zero common-mode voltage, it is necessary to ensure that at any time, 3 bridge arms are turned on and 3 bridge arms are turned off, so that the sum of the system PWM wave is 0, that is, the common-mode voltage is 0.

[0126] Since the voltage phases of the UVW phases are opposite to those of the BCA phases, the relationship between the virtual time of the ABC phases and the UVW phases is:

[0127]

[0128] Since the time period when all the switches are turned on and off is the time of zero vector action, the on and off periods of the switches are swapped while ensuring that the effective time length remains unchanged, without affecting the synthesis of the target voltage vector. Therefore, in one switching cycle, the present invention reverses the on and off sequence of the UVW phases compared to ABC, and configures the virtual time according to formula (20), so that 3 switches are turned on and 3 switches are turned off at any time, thereby achieving the sum of the system PWM wave to be 0. The waveform of this modulation strategy in timing is as follows: Figure 6 As shown. And by configuring the offset T of the effective time position offset , it can realize uninterrupted switching of different modulation modes, and achieve zero common-mode voltage under SPWM, SVPWM, and DPWM with different clamps, which is suitable for a variety of application scenarios. So far, the zero common-mode modulation strategy based on unified voltage modulation for the parallel three-phase inverter driving the phase-shifted 60° Y-type connected six-phase permanent magnet synchronous motor system has been fully realized.

[0129] Embodiment 1

[0130] by Figure 1 Taking the electric drive system shown in FIG. 1 as an example, the present invention is used to perform simulation verification in the Matlab / Simulink platform, wherein the control module of the unified voltage modulation and the switching module of the modulation mode are respectively as shown in FIG. Figure 7 and Figure 8 The main simulation parameters are shown in Table 1:

[0131] Table 1

[0132]

[0133] The simulation results are as follows Figures 9 to 15 shown.

[0134] Fig. 9 and Fig.10 It is the simulation waveform of the unified voltage modulation module. Fig. 9 and Fig.10 As shown, the constructed unified modulation module can realize uninterrupted switching of different modulation modes.

[0135] Fig.11 This is the current waveform of the motor. The simulation result has good sinusoidal properties. The ABC phase current differs from the UVW phase current by 60°. The direct-axis currents of the two sets of windings follow the reference value 0 well. The quadrature-axis currents are the same, and the total quadrature-axis current fits the reference value.

[0136] Fig.12The simulation results of motor speed, electrical angle and electromagnetic torque are as follows. The motor speed follows the reference value 2000rad / min well. After the load is applied at t=0.3s, the electromagnetic torque of the motor is close to the load torque of 9.5N*m. After the common mode voltage suppression algorithm is applied at t=0.4s, the electromagnetic torque oscillates briefly and then re-fits the reference value.

[0137] Fig.13 This is a six-phase PWM wave simulation result diagram. The PWM waves of the UVW three-phases are opposite to the PWM waves of the CAB three-phases.

[0138] Fig.14 It is a common-mode voltage waveform diagram. The simulation results show that, under the condition of considering the stray parameters, before the common-mode voltage suppression algorithm is put into use, the common-mode voltage shows a step-like change from -Vdc / 2 to Vdc / 2 according to the switching cycle. After the common-mode voltage suppression algorithm is put into use at t=0.4s, the amplitude of the common-mode voltage does not exceed 0.1V. Compared with the DC voltage of 270V, the common-mode voltage is close to 0, which verifies the effectiveness of the present invention.

[0139] Fig.15 This is the DC side common mode conducted EMI simulation result diagram. Fig.15 It can be seen that after adopting the zero common-mode modulation strategy, the DC side common-mode conducted EMI is reduced by about 20dBμA within 400kHz, by about 60dBμA around 450kHz, and by about 10dBμA in the range of 3-20MHz.

[0140] Embodiment 2

[0141] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the zero common mode modulation method of a multi-module parallel inverter based on unified voltage modulation are implemented. The memory may include a memory, such as a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk memory, etc. The processor, the network interface, and the memory are interconnected through an internal bus. The internal bus may be an industrial standard architecture bus, a peripheral component interconnection standard bus, an extended industrial standard structure bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory is used to store programs. Specifically, the program may include a program code, and the program code includes computer operation instructions. The memory may include a memory and a non-volatile memory, and provide instructions and data to the processor.

[0142] Embodiment 3

[0143] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the zero common mode modulation method of a multi-module parallel inverter based on uniform voltage modulation are implemented. Specifically, the computer-readable storage medium includes, but is not limited to, for example, a volatile memory and / or a non-volatile memory. The volatile memory may include a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include a read-only memory (ROM), a hard disk, a flash memory, an optical disk, a magnetic disk, etc.

[0144] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0145] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0146] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0147] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0148] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and disclosure of the invention. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0149] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

[0150] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent structural change made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A zero common mode modulation method for multi-module parallel inverters based on unified voltage modulation, characterized in that: include: 1) Collect the phase voltage and DC side voltage of the six-phase permanent magnet synchronous motor with a phase shift of 60° Y-type connection; 2) Compare the instantaneous value of each phase voltage with the amplitude of the DC side voltage to obtain the virtual on-time of the switch tube; 3) According to the modulation mode and control period, the effective time offset of SPWM, SVPWM and DPWM with different clamping positions is calculated; 4) According to the amplitude and phase of the two winding voltages of the six-phase permanent magnet synchronous motor with a phase shift of 60° Y-type connection, the relationship between the virtual conduction time of the UVW phase voltage and the ABC phase voltage is calculated; 5) According to the relationship between the virtual on-time of the UVW phase voltage and the ABC phase voltage and the effective time offset, the actual on-time of the UVW winding switch tube and the ABC three-phase switch tube is calculated, and the on-and-off states of the UVW winding switch tube and the on-and-off states of the ABC three-phase switch tube are reversed to achieve the common-mode voltage elimination of the parallel three-phase inverter driving the phase-shifted 60° Y-type connected six-phase permanent magnet synchronous motor system.

2. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The virtual on-time T of the switch tube calculated in step 2) as , T bs and T cs for: Among them, U as * , U bs * and U cs * is the instantaneous value of the three-phase sine wave, U D is the DC bus voltage, T s is the carrier period.

3. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of SPWM is: Among them, T s is the sampling period of space vector modulation.

4. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of SVPWM is: Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

5. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of the 60° clamped DPWM is: if T min +T max ≥0→T offset =T s -T max if T min +T max <0→T offset =-T min Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

6. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of the DPWM with 30° clamping is: if T min +T max ≥0→T offset =-T min if T min +T max <0→T offset =T s -T max Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ), T min =min(T as ,T bs ,T cs ).

7. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of the DPWM with 120° clamping at the positive peak of the voltage is: T offset =T s -T max Among them, T s is the sampling period of space vector modulation, T max =max(T as ,T bs ,T cs ).

8. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The effective time offset of the DPWM with 120° clamping at the negative peak of the voltage is: T offset =-T min Among them, T min =min(T as ,T bs ,T cs ).

9. The zero common mode modulation method of multi-module parallel inverter based on unified voltage modulation according to claim 1, characterized in that: The relationship between the virtual on-time of the UVW phase voltage and the ABC phase voltage is: Among them, T as , T as and T bs is the virtual conduction time of phase ABC voltage, T us , T vs and T ws is the virtual on-time of UVW phase voltage.

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