Data storage, check node data update, and LDPC decoding method and system

Abstract

The present invention relates to a data storage, check node data update, and LDPC decoding method and system, belonging to the field of wireless communication technology. The data storage method includes constructing a check matrix H with M rows and N columns, dividing it into a plurality of submatrices with m rows and n columns; using a plurality of dual-port RAMs to store element 1 in the check matrix H, wherein the storage rule includes storing element 1 in the same position in a source submatrix and its corresponding submatrix in the same dual-port RAM; grouping elements 1 in each row of the check matrix H into twos and storing them in different dual-port RAMs; furthermore, grouping the source submatrix and its corresponding submatrix into twos, storing the elements 1 therein in the same dual-port RAM; and if the number of rows in the submatrix is ​​odd, grouping elements 1 in the remaining rows of the submatrix into twos and storing them in different dual-port RAMs. The present invention improves data access speed during information node data updates and check node data updates.

Description

Technical Field

[0001] The present invention belongs to the field of wireless communication technology, and in particular relates to a data storage, check node data update and LDPC decoding method and system. Background Art

[0002] LDPC (Low-Density Parity-Check) codes are block error-correcting codes with a sparse parity check matrix, proposed by Robert Gallager of MIT in his 1963 doctoral dissertation. Applicable to nearly all channels, they have become a research hotspot in the coding community in recent years. Their performance approaches the Shannon limit, and their simple description and implementation make them amenable to theoretical analysis and research. Decoding is straightforward and can be performed in parallel, making them suitable for hardware implementation.

[0003] There are three main types of LDPC decoders: fully parallel decoder, partially parallel decoder, and serial decoder.

[0004] A fully parallel architecture can achieve excellent performance and high data throughput with simple control logic. However, when the codeword is long (greater than 1000), this architecture leads to complex implementation and routing, as well as significant wiring overhead. Furthermore, a fully parallel architecture increases area consumption, and the randomized connections between check nodes and information nodes can cause routing congestion. If synchronous circuits are used to ensure signal synchronization, a large number of registers must be added to store data during the iteration process, further increasing resource consumption. Another disadvantage of the parallel architecture is that it is fixed and can only be used for LDPC codes with a specific check matrix, resulting in limited flexibility.

[0005] The shortcoming of the partially parallel structure is that it has certain requirements on the regularity of the check matrix, especially the regularity of the positions of non-zero elements. Many existing partially parallel LDPC decoder designs in the industry are accompanied by corresponding check matrices constructed by special rules. Without the support of this specially constructed check matrix, its application scope is very limited.

[0006] The disadvantages of the serial structure are slow decoding rate and low data throughput, and it cannot be applied to high-speed data interaction systems. Summary of the Invention

[0007] The purpose of the present invention is to provide a data storage, check node data update and LDPC decoding method and system, which partially solves or alleviates the above-mentioned deficiencies in the prior art, achieves a balance between decoder area, speed, power consumption and performance in the case of long code length, and realizes information exchange between nodes quickly and efficiently.

[0008] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions:

[0009] A data storage method is applied to update data storage of information nodes and / or check nodes in LDPC decoding, comprising:

[0010] Constructing a check matrix H with M rows and N columns, where N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, where element 1 indicates that the information node and the check node have a connection relationship, and element 0 indicates that the information node and the check node have no connection relationship;

[0011] Divide the check matrix H into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns. Where m is the column weight of the check matrix H, and n is the row weight of the check matrix H.

[0012] Use several dual-port RAMs to store element 1 in the check matrix H. The storage rules include:

[0013] The element 1 at the same position in the source submatrix and its corresponding submatrix should be stored in the same dual-port RAM;

[0014] The elements 1 of each row of the check matrix H are grouped into two pairs and stored in different dual-port RAMs respectively;

[0015] Furthermore, the source submatrix and its corresponding submatrix are grouped into groups of two rows each, and the element 1s therein are stored in the same dual-port RAM. If the number of rows of the submatrix is ​​odd, the element 1s in the remaining rows of the submatrix are grouped into groups of two and stored in different dual-port RAMs respectively.

[0016] The present invention also provides a verification node data updating method, comprising:

[0017] Read n information node data from the information node data storage module;

[0018] Input the data of n information nodes into the CNU computing unit (check node update computing unit) for calculation;

[0019] The result calculated by the CNU computing unit is stored in the verification node data storage module;

[0020] The information node data storage module and / or the check node data storage module adopts the above-mentioned data storage method to perform data storage.

[0021] As an improvement, the calculation steps of the CNU calculation unit include:

[0022] Perform cumulative multiplication on the highest sign bit of the information node data;

[0023] Obtain the minimum and second minimum values ​​of the remaining bits in the information node data except the highest sign bit.

[0024] As an improvement, the step of obtaining the minimum value and the second minimum value of the remaining bits excluding the highest sign bit in the information node data includes:

[0025] S321 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register;

[0026] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local next minimum value, and the local next minimum value is stored in the register of the next level;

[0027] If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0028] Use pointers to indicate the storage location of the local minimum in the register;

[0029] Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

[0030] The present invention also provides an LDPC decoding method, comprising:

[0031] Reading external soft information input values ​​and storing them in the initial soft information memory;

[0032] Reading external soft information from the initial soft information memory and storing it in the information storage node data memory;

[0033] Using the above-mentioned verification node data updating method to update the verification node data;

[0034] Update information node data;

[0035] Repeat the check node data update and the information node data update until the set number of iterations is reached, and store the last information node data update result in the decoding result memory.

[0036] As an improvement, the step of updating the information node data includes:

[0037] Read m check node data from the check node data storage module;

[0038] Input the m check node data into the VNU calculation unit (information node update calculation unit) for calculation;

[0039] The result calculated by the VNU calculation unit is stored in the information node data storage module;

[0040] The information node data storage module and / or the check node data storage module adopts the above-mentioned data storage method to perform data storage.

[0041] The present invention also provides a verification node data update system, comprising:

[0042] A check node data storage module, configured to store check node data using the above data storage method;

[0043] The CNU calculation unit is used to read n information node data from the information node data storage module and perform verification node data update calculation.

[0044] As an improvement, the CNU computing unit includes:

[0045] A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data;

[0046] The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including:

[0047] S11 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register;

[0048] S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level;

[0049] If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0050] Use pointers to indicate the storage location of the local minimum in the register;

[0051] Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

[0052] The present invention also provides an LDPC decoding system, comprising:

[0053] An initial soft information memory, used for reading and storing external soft information input values;

[0054] A check node data update system includes a check node data storage module for storing check node data using the above data storage method; and a CNU calculation unit for reading n information node data from the information node data storage module and performing check node data update calculations;

[0055] An information node data update system includes an information node data storage module for storing information node data using the above data storage method; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation;

[0056] The decoding result memory is used to store the last information node data update result when the set number of iterations is reached.

[0057] As an improvement, the CNU computing unit includes:

[0058] A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data;

[0059] The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including:

[0060] S321 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register;

[0061] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local next minimum value, and the local next minimum value is stored in the register of the next level;

[0062] If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0063] Use pointers to indicate the storage location of the local minimum in the register;

[0064] Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

[0065] The present invention is beneficial in that:

[0066] 1. Data storage method

[0067] (1) When updating a check node, a clock can read 12 numbers through the dual ports of the RAM, calculate 12 results, and then store the 12 numbers. Reading and writing can be done in address order, and the parallelism of the information node update is 2. This shortens the update delay of the check node by half, and the control logic and address generation logic are very simple.

[0068] (2) During initialization and information node update, since the three source sub-matrices and their respective corresponding sub-matrices are stored in the same RAM in sequence, and due to the principle of relative position invariance, as long as the address that needs to be read and written when the information node corresponding to "1" in the source sub-matrix is ​​updated is known, it can be used as the starting address and increased in sequence to complete the update of the information nodes of all corresponding sub-matrices.

[0069] The data storage method provided by the present invention utilizes the highly structured quasi-cyclic structure of the check matrix H, greatly simplifies the control logic and read / write address generation logic at the cost of a small number of registers and data selectors, and reduces decoding delay, which is beneficial to hardware implementation and brings great convenience to programmers.

[0070] 2. Pointer-based method for finding the minimum and second minimum values.

[0071] For the same six-input case, the pointer-based algorithm uses fewer registers to store intermediate variables than the classic algorithm, resulting in lower resource usage. However, the difference in resource usage between the two algorithms' FPGA implementations becomes even greater as the number of inputs and outputs increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the embodiments or the description of the prior art. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the various elements or parts are not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without inventive work.

[0073] Figure 1Schematic diagram of the check matrix H in the present invention;

[0074] Figure 2 Schematic diagram of the segmentation of the neutron matrix of the present invention;

[0075] Figure 3 This is a schematic diagram of the numbering of element 1 in the check matrix H matrix of the existing data storage method;

[0076] Figure 4 A schematic diagram of data storage in an existing data storage method;

[0077] Figure 5 Schematic diagram of the numbering of element 1 in the check matrix H matrix of the present invention;

[0078] Figure 6 This is a schematic diagram of data storage in the present invention;

[0079] Figure 7 This is the "pointer-based" algorithm for finding the minimum value and the second minimum value in the present invention;

[0080] Figure 8 Schematic diagram of the structure of the CNU in the present invention;

[0081] Figure 9 This is a schematic diagram of the LDPC decoding system structure in the present invention. DETAILED DESCRIPTION

[0082] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0083] Herein, suffixes such as "module," "component," or "unit" used to represent elements are only used to facilitate description of the present invention and have no specific meaning. Therefore, "module," "component," or "unit" may be used interchangeably.

[0084] As used herein, terms such as "upper," "lower," "inner," "outer," "front," "back," "one end," and "the other end" indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate and simplify the description of the present invention and are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0085] As used herein, unless otherwise expressly specified or limited, the terms "installed," "provided with," and "connected" should be understood broadly. For example, "connected" may refer to a fixed connection, a detachable connection, or an integral connection; it may refer to a mechanical connection, a direct connection, an indirect connection via an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention on a case-by-case basis.

[0086] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0087] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0088] Definition of noun:

[0089] LDPC decoding: Low-Density Parity-Check decoding.

[0090] CNU: Check Node Unit, check node update calculation unit.

[0091] VNU: Variable Node Unit, information node update calculation unit.

[0092] Example 1

[0093] Prior art Chinese patent application CN200710118461.9 discloses an efficient LDPC code decoder device and decoding method, which first analyzes the check matrix of the LDPC code to find the comparative relationship between row weight and column weight; then, based on the above comparative relationship, determines the degree of reuse of the check node update unit and the variable node update unit, and groups them to form a unified node update unit, and uses the unified node update unit to process the check node update operation and the variable node update operation.

[0094] The above-mentioned existing technologies do not change the data storage method, and cannot achieve the effect of fully parallel reading when reading data. They focus on controlling logical computing resources and storage resources, and their operating efficiency is unsatisfactory.

[0095] In order to solve the above technical problems, the present invention provides a data storage method applied to update data of information nodes and / or check nodes in LDPC decoding, comprising:

[0096] S101 constructs a check matrix H with M rows and N columns, where N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, where element 1 indicates that the information node and the check node have a connection relationship, and element 0 indicates that the information node and the check node have no connection relationship.

[0097] The LDPC decoding algorithm is based on the structure of the parity check matrix H. To simplify the algorithm's implementation, the structure of the H matrix must be studied. A highly structured quasi-cyclic structure can be used. Furthermore, since physical parameters such as the number of read / write ports in the memory cannot be changed, the data storage method can be modified to achieve the goal of reading as much valid data as possible using relatively simple logic control.

[0098] The parity check matrix H is a sparse matrix that defines the parity check rules for codewords. It has M rows and N columns, where the M rows correspond to the length of the parity check code of the LDPC codeword, meaning there are M check nodes. The N rows correspond to the code length of the LDPC codeword, meaning there are N information nodes. The elements in the parity check matrix can be either 1 or 0. When an element is 1, it indicates that the parity check node and the information node are connected, requiring a calculation. When an element is 0, it indicates that the parity check node and the information node are not connected, and no calculation is required.

[0099] S102 divides the check matrix H into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; where m is the column weight of the check matrix H, and n is the row weight of the check matrix H.

[0100] Row weight refers to the number of 1 elements in each row of the check matrix H. Assuming the row weight of the check matrix is ​​y, when a check node is updated, each check node is associated with y information nodes. Y check node update calculations are performed using the data of y information nodes, thereby updating y storage spaces associated with that check node.

[0101] Column weight refers to the number of 1 elements in each column of the check matrix H. Assuming the column weight of the check matrix is ​​x, when an information node is updated, each information node is associated with x check nodes. Therefore, x check node data must be used to perform x information node update calculations, thereby updating the x storage spaces associated with the information node.

[0102] Based on the above problems, the present invention provides a data storage method that can have certain regularity in the three steps of LDPC decoding (i.e., initialization, check node update, and information node update), so as to simplify the logic, maximize the use of memory resources, and reduce latency.

[0103] Specifically, the check matrix H in the present invention is divided into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns row by row; where m is the column weight of the check matrix H, and n is the row weight of the check matrix H.

[0104] like Figure 1 As shown, the check matrix H with 9 rows and 18 columns has a row weight of 6 and a column weight of 3. It is divided into 9 sub-matrices with 3 rows and 3 columns, and each sub-matrix has 3 rows and 6 columns.

[0105] like Figure 2 As shown in the figure, H0, H1, and H2 in the first row are the source submatrices, and the submatrices in the remaining rows are obtained by shifting the source submatrices right by 6 columns. For example, in the second row, the three submatrices are ordered as H2, H0, and H1; in the third row, the three submatrices are ordered as H1, H2, and H0, and so on.

[0106] Therefore, the structure of the entire parity check matrix H can be derived by simply recording the positions of the "1"s in the source submatrices H0, H1, and H2. Specifically, the "1"s in the last six rows are obtained by cyclically shifting the "1"s in the first three rows by 6 positions to the right. If the "1"s in the first three rows are numbered in order of appearance, and the "1"s in the last six rows, which are obtained by cyclically shifting the 18 "1"s in the first three rows, are the same number, it is easy to observe that numbers with the same number have similar reading and writing rules, because their relative positions in the columns of their respective submatrices remain unchanged.

[0107] Existing storage methods such as Figure 3 、 Figure 4 As shown in the figure, the 6 columns of elements 1 after regularization are stored in the order of arrangement through 3 dual-port RAMs. The so-called dual-port RAM refers to a RAM that can read two data at a time. Under the existing storage method, since the 6 1s in the same row are stored in groups of two in 3 dual-port RAMs, the data of 6 information nodes can be read at once when the check node is updated, and the parallelism is guaranteed. However, when updating the information node, if it is necessary to read S 00 、S 10 、S 20 The elements 1 at the three positions are all stored in the same RAM, and the RAM can only read 2 data at a time, so it needs to be read twice to complete, which greatly reduces the running speed.

[0108] As can be seen, during the LDPC decoding process, the check node update process (related to row weights) is highly regular, the storage space is easily partitioned, and the control logic is simple. However, this storage method is not conducive to the read and write data and control logic for initialization and information node updates (related to column weights). This is because the storage method described above is completely irregular with respect to these two processes, making the control logic extremely complex and difficult to implement, while also causing significant delays, wasted resources, and even timing disruptions.

[0109] In order to meet the parallel processing requirements of check node update and information node update, the storage method of the present invention is as follows.

[0110] S103 uses a plurality of dual-port RAMs to store element 1 in the check matrix H. The term "storing element 1" as used in the present invention actually refers to storing information at a position corresponding to element 1 in the check matrix H. For ease of description, this is simplified to "storing element 1." Please note this.

[0111] Specifically, the storage rules include:

[0112] (1) The element 1 at the same position in the source submatrix and its corresponding submatrix must be stored in the same dual-port RAM;

[0113] (2) Group the elements 1 of each row of the check matrix H into two pairs and store them in different dual-port RAMs;

[0114] (3) Furthermore, the source submatrix and its corresponding submatrix are grouped into two rows, and the element 1 therein is stored in the same dual-port RAM; if the number of rows of the submatrix is ​​odd, the element 1 in the remaining rows of the submatrix is ​​grouped into twos and stored in different dual-port RAMs.

[0115] Likewise, Figures 1 to 3 Take the check matrix shown as an example.

[0116] like Figure 5 、 Figure 6 As shown in rule (1), elements 1 at the same position in submatrix H0 need to be stored in the same dual-port RAM, elements 1 at the same position in submatrix H1 need to be stored in the same dual-port RAM, and similarly, elements 1 at the same position in submatrix H2 need to be stored in the same dual-port RAM. For example, S00 in the first row of submatrix H0 and S32 in the second row of submatrix H0 have the same position within the submatrix, so they need to be stored in the same dual-port RAM, RAM0.

[0117] The purpose of setting rule (1) is to ensure that the elements 1 in the same column of the check matrix H are not completely in one RAM, because the elements 1 in the source submatrix and its corresponding submatrix are definitely staggered.

[0118] In rule (2), S 00 、S 01 One group is stored in RAM0, S 02 、S 03 One group is stored in RAM1, S 04 、S 05 One group is stored in RAM 2. It is easy to understand that the above storage is for the purpose of reading out the data of the required 6 information nodes at one time when the verification node is updated.

[0119] In rule (3), the first row and the second row of the source submatrix H0 of the first row are grouped together, the first row and the second row of the source submatrix H0 of the second row are grouped together, and the first row and the second row of the source submatrix H0 of the third row are grouped together. 00 、S 01 、S 10 、S 11 、S 30 、S 31 、S 40 、S 41 、S 60 、S 61 、S 70 、S 71 All are stored in RAM0.

[0120] Similarly, the first row and the second row of the source sub-matrix H1 of the first row are grouped together, the first row and the second row of the source sub-matrix H1 of the second row are grouped together, and the first row and the second row of the source sub-matrix H1 of the third row are grouped together. 02 、S 03 、S 12 、S 13 、S 32 、S 33 、S 42 、S 43 、S 62 、S 63 、S 72 、S 73 All are stored in RAM1.

[0121] The first row and the second row of the source sub-matrix H2 of the first row are grouped together, the first row and the second row of the source sub-matrix H2 of the second row are grouped together, and the first row and the second row of the source sub-matrix H2 of the third row are grouped together. The element 1 in the above group, i.e. S 04 、S 05 、S 14 、S 15 、S 34 、S 35 、S 44 、S45 、S 64 、S 65 、S 74 、S 75 All are stored in RAM2.

[0122] Since the number of rows in the submatrix is ​​odd, the three submatrices H0, H1, and H2 in each row have a third row left, so there are three rows of elements 1 that are not allocated for storage. The remaining three rows of elements 1 are stored in a RAM in pairs per row, that is, the S of the third row of the check matrix 20 、S 21 、S in the sixth row 55 、S 50 、S in the ninth row 84 、S 85 Stored in RAM3; S in the third row 22 、S 23 、S in the sixth row 51 、S 52 、S in the ninth row 80 、S 81 Stored in RAM4; S in the third row 24 、S 25 、S in the sixth row 53 、S 54 、S in the ninth row 82 、S 83 Stored in RAM5.

[0123] After such storage, the three elements 1 in the same column must be stored in two different dual-port RAMs respectively and can be read out at one time, thus avoiding repeated reading.

[0124] It should be noted that Figure 5 This shows that a large portion of RAM3, RAM4, and RAM5 is unused because it only stores the information corresponding to the missing "1" in a submatrix row. However, in practice, since the check matrix H has 18 rows, it can be divided into nine groups of two rows each, and the corresponding information for each group is stored in the same RAM.

[0125] Example 2

[0126] Based on the construction of the check matrix H and the data storage method described above, the present invention also provides a check node data update method, comprising:

[0127] S31 reads n information node data from the information node data storage module.

[0128] The row weight of the check matrix H is n, indicating that when a check node is updated, data from n information nodes is associated with the update. Therefore, data from n information nodes must be read from the information node data storage module. According to the data storage method of Example 1, n is 6 and is stored in three dual-port RAMs. Therefore, the required data for all six information nodes can be read simultaneously.

[0129] S32 inputs the n information node data into the CNU computing unit for calculation.

[0130] During the iterative calculations of the LDPC decoding algorithm, the most computationally intensive and complex part is the check node information update calculation. Each check node is associated with n information nodes, so updating a check node requires calculating n correlation values. Specifically, this calculation involves two steps: the first step is to multiply the most significant sign bit of the information node data, and the second step is to find the minimum and next-smallest values ​​of the remaining bits in the information node data, excluding the most significant sign bit.

[0131] The first part, which multiplies the highest sign bit of the information node data, can be implemented using an exclusive-OR gate. The second part, which finds the minimum absolute value of the n-1 information nodes, is the minimum absolute value of the n information nodes associated with each check node. For the n information nodes associated with each check node, the minimum absolute value of the n-1 information nodes other than that information node needs to be found. Analyzing its characteristics, a more intuitive explanation is to find the minimum and next-smallest absolute value of the information values ​​of these n information nodes. Except for the information node with the smallest absolute value, whose result after this step is the next-smallest absolute value of the n information nodes, the results of this step for the other n nodes are the minimum absolute values. How to implement this calculation process with the least resources is one of the key considerations in this invention.

[0132] Existing algorithms typically use a pipeline approach when implemented in FPGAs or ASICs. This algorithm's advantages include simple and intuitive control and structure, facilitating pipeline implementation and achieving high speed. Excluding input registers, this architecture consumes at least 34 6-bit registers and 12 comparators. Because each stage of calculation must store not only all comparison results but also all input values, registers are largely wasted to maintain consistent timing within the pipeline structure. When the degree of parallelism in the check node calculation is high or the row weight n of the check matrix is ​​large, the register resource usage in this area increases significantly.

[0133] To address the above issues, the present invention provides a method for searching for minimum and next-to-minimum values. Since the check node's process for updating the minimum value actually only outputs two values: the minimum and next-to-minimum value among all input numbers, if the minimum and next-to-minimum values ​​of all input numbers are found and indicated by "pointers," all output data is determined. Therefore, this solution is called a "pointer-based" minimum and next-to-minimum algorithm.

[0134] Specific as Figure 7 The example is shown in the figure. The six inputs are compared and searched through three steps (it is understandable that the more inputs, the more search steps are required) to find the minimum and next-to-minimum values ​​of the six inputs (in actual applications, the next-to-minimum value is used as the output value corresponding to the minimum input, and the minimum value is used as the output value corresponding to the other inputs). The specific steps are as follows:

[0135] S321 compares the input information node data in groups of two to obtain the local minimum value between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum value in the register.

[0136] like Figure 7 As shown in the example, the input values ​​are data1 to data6. For ease of description, in this example, data1 to data6 are assigned values ​​1 to 6 to search for the minimum and second-minimum values.

[0137] In this step, 1 and 2 form a group, 3 and 4 form a group, and 5 and 6 form a group. It's easy to understand that after comparing the three groups D1_1 through D1_3, 1, 3, and 5 in the registers are local minima, indicated by the pointer. In this step, all data is retained, meaning data1 through data6 are stored in registers as data1_1 through data1_6.

[0138] This round of comparison can be completed through 3 comparison gates.

[0139] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, where the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the next level register; the information node data of the four information nodes that are compared with the local minimum value in the same group at the previous level are compared with the failure value again, where the smaller one is the local second minimum value, and the local second minimum value is stored in the next level register; if the local minimum value obtained in the previous level comparison is odd, the odd local minimum value and the information node data in the same group are directly stored in the next level register; the pointer is used to indicate the storage location of the local minimum value in the register; repeat this step until the minimum value and the second minimum value in the input information node data are obtained.

[0140] Continuing with the previous example, the two local minimum values ​​1 and 3 are compared D2_1. 1 once again enters the next-level register as the local minimum and is indicated by a pointer (since 1 and 3 are both "winners" of the previous-level comparison, 1 is actually the local minimum among the four values). 3 is the losing value and is compared again with 2, the previous-level comparator of 1, D2_2. It is easy to understand that 2 enters the next-level register as the local second minimum of the four values.

[0141] This round of comparison can be completed through two comparators and two selectors.

[0142] Since 5 is alone and has no comparison object in this comparison, it enters the next level register together with the previous level comparison object 6.

[0143] This level of registers includes data2_1~data2_4, namely 1, 2, 5, and 6.

[0144] Repeat this step, comparing the two local minimum values ​​1 and 5 (D3_3), with 1 being the minimum. Then compare 5 with 2, with 2 being the next minimum. The entire search process ends with the minimum (Min) being 1 and the next minimum (2nd_Min) being 2.

[0145] Similarly, this round of comparison can be completed through two comparators and two selectors.

[0146] That is to say, ignoring the input register, the implementation of the above minimum value algorithm uses 18 6-bit registers to store data, 6 3-bit registers to store pointers, 3 comparison selectors, 4 2-way selectors and 4 comparators.

[0147] Table 1 Comparison of the structure and resource usage of the existing algorithm and the pointer-based algorithm of the present invention

[0148]

[0149] Using a Xilinx FPGA, we synthesized the compiled VHDL source code for the existing algorithm and the pointer-based algorithm. Table 1 shows the results. For the same six-input implementation, the pointer-based algorithm requires fewer registers for storing intermediate variables than the classic algorithm, resulting in lower resource usage. The difference in resource usage between the two FPGA implementations becomes even greater when the number of inputs and outputs increases.

[0150] S33 stores the result calculated by the CNU calculation unit in the check node data storage module.

[0151] After the calculation is completed, the calculation results are stored in the verification node data storage module.

[0152] The information node data storage module and / or the check node data storage module performs data storage using the data storage method described in Example 1. The specific steps of data storage are described in Example 1 of the present invention and will not be repeated here.

[0153] Example 3

[0154] Based on the data storage method provided in Example 1 and the check node data update method provided in Example 2, the present invention further provides an LDPC decoding method, including:

[0155] S1 reads the external soft information input value and stores it in the initial soft information memory.

[0156] The external soft information input value is stored in the initial soft information memory MEM for Yn1 or MEM for Yn1 according to the ping-pong rule.

[0157] S2 reads the external soft information from the initial soft information memory and stores it in the information storage node data memory.

[0158] Start the LDPC decoding initialization process. Read the initial soft information from the initial soft information memory and store it in the corresponding information node data memory. The specific data storage method is shown in Example 1 and will not be repeated here.

[0159] S3 updates the verification node data.

[0160] The specific update steps are shown in Example 2 and will not be repeated here.

[0161] S4 updates the information node data. The specific steps include:

[0162] S41 reads m check node data from the check node data storage module.

[0163] The column weight of the check matrix H is m, indicating that when an information node is updated, m check node data are related. Therefore, m check node data must be read from the check node data storage module. According to the data storage method of Example 1, m is 3 and is stored in two dual-port RAMs, so the required three check node data can be read in parallel at one time.

[0164] S42 inputs the m check node data into the VNU calculation unit for calculation.

[0165] The calculation of information node updates itself is not technically difficult; the challenge lies in accessing the data. The data storage method in Example 1 solves this problem. Therefore, the information node update calculation module consists of a large number of multiplexers and a four-input adder (for binary numbers, this can be implemented using XOR gates).

[0166] S43 stores the result calculated by the VNU calculation unit in the information node data storage module; wherein the information node data storage module and / or the check node data storage module adopts the data storage method of embodiment 1 for data storage.

[0167] S5 repeats the check node data update and the information node data update until the set number of iterations is reached, and stores the last information node data update result in the decoding result memory.

[0168] Example 4

[0169] The present invention also provides a verification node data update system, comprising:

[0170] A check node data storage module, configured to store check node data using the data storage method of the first embodiment;

[0171] The CNU calculation unit is used to read n information node data from the information node data storage module and perform verification node data update calculation; Figure 8 As shown, specifically including:

[0172] A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data;

[0173] The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including:

[0174] S11 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register;

[0175] S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level;

[0176] If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0177] Use pointers to indicate the storage location of the local minimum in the register;

[0178] Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

[0179] Figure 8 In the CNU computing unit shown, the input control signals include an enable signal "EN," a reset signal "RESET," and a clock signal "CLK." Six 7-bit inputs, S1 (6 down to 0) through S6 (6 down to 0), are fed into the sign accumulation module. The highest sign bit of each input, SIGN_S1 through SIGN_S6, is fed into the sign accumulation module, while the remaining 6 bits, S1 (5 down to 0) through S6 (5 down to 0), are fed into the pointer-based minimum sub-minimum module. The outputs of the sign accumulation module, SIGN_S1_OUT through SIGN_S6_OUT, and the outputs of the pointer-based minimum sub-minimum module, S1_OUT through S6_OUT, are combined to form the six 7-bit outputs, S1_OUT (6 down to 0) through S6_OUT (6 down to 0), of the entire CHU computing unit.

[0180] Example 5

[0181] like Figure 9 As shown, the present invention also provides an LDPC decoding system, comprising:

[0182] The initial soft information memory is used to read and store external soft information input values. In this embodiment, there are two parallel initial soft information memories, namely MEM for Yn1 or MEM for Yn2.

[0183] The check node data update system includes a check node data storage module for storing check node data using the data storage method of the first embodiment; and a CNU calculation unit for reading n information node data from the information node data storage module and performing check node data update calculation.

[0184] The specific structure of the CNU computing unit is as follows Figure 8 As shown, specifically including:

[0185] A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data;

[0186] The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including:

[0187] S321 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register;

[0188] S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local next minimum value, and the local next minimum value is stored in the register of the next level;

[0189] If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register;

[0190] Use pointers to indicate the storage location of the local minimum in the register;

[0191] Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

[0192] The information node data update system includes an information node data storage module for storing information node data using the data storage method of the first embodiment; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation.

[0193] The decoding result memory is used to store the last information node data update result when the set number of iterations is reached, and finally output the LDPC decoding result Decode Data output.

[0194] The control module is used to send instructions to the above modules, including the enable signal "EN", the reset signal "RESET", the clock signal "CLK", the ready signal "READY", and the addressing signal "addr".

[0195] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0196] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a computer terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present invention.

[0197] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A data storage method for updating data of information nodes and / or check nodes in LDPC decoding, characterized in that include: Constructing a check matrix H with M rows and N columns, where N is the number of information nodes and M is the number of check nodes; the elements in the check matrix H include 1 and 0, where element 1 indicates that the information node and the check node have a connection relationship, and element 0 indicates that the information node and the check node have no connection relationship; Divide the check matrix H into several sub-matrices with m rows and n columns, where the sub-matrix in the first row is the source sub-matrix, and the sub-matrices in the remaining rows are obtained by cyclically shifting the corresponding source sub-matrix to the right by n columns. Where m is the column weight of the check matrix H, and n is the row weight of the check matrix H. Use several dual-port RAMs to store element 1 in the check matrix H. The storage rules include: The element 1 at the same position in the source submatrix and its corresponding submatrix should be stored in the same dual-port RAM; The elements 1 of each row of the check matrix H are grouped into two pairs and stored in different dual-port RAMs respectively; Furthermore, the source submatrix and its corresponding submatrix are grouped into groups of two rows each, and the element 1s therein are stored in the same dual-port RAM. If the number of rows of the submatrix is ​​odd, the element 1s in the remaining rows of the submatrix are grouped into groups of two and stored in different dual-port RAMs respectively.

2. A verification node data update method, characterized in that include: Read n information node data from the information node data storage module; Input the data of n information nodes into the CNU computing unit for calculation; The result calculated by the CNU computing unit is stored in the verification node data storage module; Wherein, the information node data storage module and / or the check node data storage module adopts the data storage method according to claim 1 to perform data storage.

3. A check node data updating method according to claim 2, characterized in that The calculation steps of the CNU calculation unit include: Perform cumulative multiplication on the highest sign bit of the information node data; Obtain the minimum and second minimum values ​​of the remaining bits in the information node data except the highest sign bit.

4. A check node data updating method according to claim 3, characterized in that The steps of obtaining the minimum value and the second minimum value of the remaining bits excluding the highest sign bit in the information node data include: S321 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register; S322 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local next minimum value, and the local next minimum value is stored in the register of the next level; If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register; Use pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

5. An LDPC decoding method, characterized in that include: Reading external soft information input values ​​and storing them in the initial soft information memory; Reading external soft information from the initial soft information memory and storing it in the information storage node data memory; Using the check node data updating method according to any one of claims 2 to 4 to update the check node data; Update information node data; Repeat the check node data update and the information node data update until the set number of iterations is reached, and store the last information node data update result in the decoding result memory.

6. The LDPC decoding method according to claim 5, characterized in that The step of updating the information node data includes: Read m check node data from the check node data storage module; Input the m check node data into the VNU computing unit for calculation; The result calculated by the VNU calculation unit is stored in the information node data storage module; Wherein, the information node data storage module and / or the check node data storage module adopts the data storage method according to claim 1 to perform data storage.

7. A verification node data update system, characterized in that include: A check node data storage module, configured to store check node data using the data storage method according to claim 1; The CNU calculation unit is used to read n information node data from the information node data storage module and perform update calculations on the check node data.

8. A check node data update system according to claim 7, characterized in that The CNU computing unit includes: A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data; The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including: S11 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register; S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level; If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register; Use pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

9. An LDPC decoding system, characterized in that include: An initial soft information memory, used for reading and storing external soft information input values; A check node data update system comprising a check node data storage module for storing check node data using the data storage method of claim 1; and a CNU computing unit for reading n information node data from the information node data storage module and performing update calculations on the check node data; An information node data updating system comprising an information node data storage module for storing information node data using the data storage method according to claim 1; and a VNU calculation unit for reading m check node data from the check node data storage module and performing information node data update calculation; The decoding result memory is used to store the last information node data update result when the set number of iterations is reached.

10. An LDPC decoding system according to claim 9, characterized in that The CNU computing unit includes: A symbol accumulation module is used to accumulate and multiply the highest sign bit of the information node data; The pointer-based minimum and sub-minimum value module is used to find the minimum and sub-minimum values ​​of N information node data, specifically including: S11 compares the input information node data in groups of two to obtain the local minimum between each pair; stores the information node data in the next level register, and uses a pointer to indicate the storage location of the local minimum in the register; S12 compares the two local minimum values ​​in the two groups of information node data in the previous level comparison, wherein the smaller information node data is the local minimum value among the four information node data, and the larger one is the failure value, and the local minimum value is stored in the register of the next level; the information node data of the four information nodes that are compared with the local minimum value in the same group in the previous level are compared with the failure value, wherein the smaller one is the local second minimum value, and the local second minimum value is stored in the register of the next level; If the number of local minimum values ​​obtained in the previous level comparison is odd, the single local minimum value and the information node data of the same group are directly stored in the next level register; Use pointers to indicate the storage location of the local minimum in the register; Repeat this step until the minimum and second minimum values ​​of the input information node data are obtained.

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