A semiconductor device and its manufacturing method

Abstract

This invention provides a semiconductor device and its manufacturing method, applicable to the field of semiconductor technology. In this invention, by changing the width of the spacing between adjacent bit line structures, the width of the connecting pad structures formed between different adjacent bit line structures varies in the horizontal direction, thereby causing a partial positional shift of the second isolation structure, achieving the purpose of connecting some adjacent connecting pad structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, comprising an array area consisting of multiple memory cells and a peripheral area consisting of control circuitry. Each memory cell consists of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage and release of charge in the capacitor to store data. The control circuitry addresses each memory cell and controls data access by using word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to limitations in manufacturing technology, existing DRAMs still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and its fabrication method to improve the reliability and performance of the semiconductor device.

[0004] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a semiconductor device, which may include at least:

[0005] Base;

[0006] Multiple bit line structures, including a first bit line structure and a second bit line structure disposed on the substrate separately from each other;

[0007] Multiple connecting pad structures are disposed between adjacent bit line structures;

[0008] Multiple isolation structures are disposed between adjacent connecting pad structures, the isolation structures including:

[0009] The first isolation structure is in direct contact with the first bit line structure and the connecting pad structure;

[0010] The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connecting pad structure.

[0011] Optionally, the first interval between adjacent first bit line structures may be smaller than the second interval between adjacent first bit line structures and second bit line structures.

[0012] Optionally, the connecting pad structure may further include:

[0013] A first connecting pad structure is disposed between adjacent first bit line structures;

[0014] The second connecting pad structure is disposed between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connecting pad structure.

[0015] Optionally, the second connecting pad structure is connected to the first connecting pad structure adjacent to it.

[0016] Optionally, the second isolation structure can be isolated from both the first bit line structure and the second bit line structure.

[0017] Optionally, there is a first spacing between adjacent first isolation structures, and a second spacing between adjacent first isolation structures and second isolation structures, wherein the first spacing is smaller than the second spacing.

[0018] Optionally, the semiconductor device may further include:

[0019] Multiple contact structures are disposed under the connecting pad structure, and the width of the contact structure located under the first connecting pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connecting pad structure in the horizontal direction.

[0020] Optionally, the width of the first bit line structure in the horizontal direction may be smaller than the width of the second bit line structure in the horizontal direction.

[0021] Optionally, the semiconductor device may further include:

[0022] The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connecting pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

[0023] Optionally, the third bit line structure may include semiconductor layers and metal layers stacked sequentially from bottom to top, with the connection pad structure in direct contact with the metal layer.

[0024] Secondly, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising at least:

[0025] Provide a base;

[0026] Multiple bit line structures are formed, the bit line structures including a first bit line structure and a second bit line structure disposed on the substrate and separated from each other;

[0027] Multiple connection pad structures are formed, and the connection pad structures are disposed between adjacent bit line structures;

[0028] Multiple isolation structures are formed and disposed between adjacent connecting pad structures. The isolation structure includes a first isolation structure that is in direct contact with the first bit line structure and the connecting pad structure, and a second isolation structure located between the first bit line structure and the second bit line structure, wherein the bottom surface of the second isolation structure is completely covered by the connecting pad structure.

[0029] Optionally, the first interval between adjacent first bit line structures may be smaller than the second interval between adjacent first bit line structures and second bit line structures.

[0030] Optionally, the connection pad structure may include:

[0031] A first connecting pad structure is disposed between adjacent first bit line structures;

[0032] The second connecting pad structure is disposed between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connecting pad structure.

[0033] Optionally, the second connecting pad structure is connected to the first connecting pad structure adjacent to it.

[0034] Optionally, the second isolation structure can be isolated from both the first bit line structure and the second bit line structure.

[0035] Optionally, the method for manufacturing the semiconductor device may further include:

[0036] Multiple contact structures are formed, the contact structures are disposed under the connecting pad structure, and the width of the contact structure located under the first connecting pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connecting pad structure in the horizontal direction.

[0037] Optionally, the bit line structure may further include:

[0038] The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connecting pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

[0039] Optionally, the third bit line structure includes semiconductor layers and metal layers stacked sequentially from bottom to top, and the connection pad structure is in direct contact with the metal layer.

[0040] In this invention, by setting the interval between adjacent first line structures and second line structures to be larger than the interval between adjacent first line structures, the width of the connecting pad structure formed between two adjacent first line structures in the horizontal direction is smaller than the width of the connecting pad structure formed between adjacent first line structures and second line structures in the horizontal direction. This causes the second isolation structure within the connecting pad structure formed between adjacent first line structures and second line structures to shift in the direction closer to the second line structure, thereby achieving the purpose of allowing the connecting pad structure located between adjacent first line structures and second line structures to communicate with the connecting pad structure adjacent to it and located between adjacent first line structures. Attached Figure Description

[0041] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0042] Figures 1-5 and Figure 7 The semiconductor device provided in the first embodiment of the present invention is manufactured along the following process: Figure 6 The diagram shows the structure of a portion of the area along the AA' tangent in the top view.

[0043] Figure 6 The semiconductor device provided in the first embodiment of the present invention Figure 5 The top view of the structure shown.

[0044] Figures 8-12 and Figure 14 The semiconductor device provided in the second embodiment of the present invention is manufactured along the process of... Figure 13 The diagram shows the structure of a portion of the area along the AA' tangent in the top view.

[0045] Figure 13 The semiconductor device provided in the second embodiment of the present invention Figure 12 The top view of the structure shown.

[0046] The attached figures are labeled as follows:

[0047] 100 - Substrate, 110 - Trench isolation, 120 - Insulating layer, 130 - Bit line material layer, 131 - Semiconductor layer, 132 - Barrier layer, 133 - Metal layer, 134 - Cap layer, BL - Bit line structure, BL1 - First bit line structure, BL2 - Second bit line structure, BL3 - Third bit line structure, SP1 - First spacer, SP2 - Second spacer, SP3 - Third spacer, SP4 - Fourth spacer, 140 - Sidewall structure, 141 - First sidewall, 142 - Second sidewall, 150 - Contact structure, 160 - Silicate layer, 170 - Connector pad structure, 170.1 - First connector pad layer, 170.2 - Second connector pad layer, 171 - First connector pad structure, 172 - Second connector pad structure, 180 - Isolation structure, 181 - First isolation structure, 182 - Second isolation structure, d1 - First pitch, d2 - Second pitch.

[0048] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0049] The semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0050] Please refer to Figure 5 and Figure 6 , Figure 6 The drawing shows a partial top view of the semiconductor device according to the first embodiment of the present invention. Figure 5 The illustration shows a semiconductor device according to a first embodiment of the present invention. Figure 6 The diagram shows a cross-sectional view of a portion of the tangent line AA'. The semiconductor device of this invention can be used to manufacture dynamic random access memory (DRAM), and without departing from the spirit of this invention, it can also be applied to other types of memory.

[0051] like Figure 5As shown, the semiconductor device includes a substrate 100, multiple bit line structures BL, multiple connection pad structures 170, and multiple isolation structures 180. The substrate 100 can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe), a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. In one embodiment, a plurality of trench isolations 110 (e.g., including silicon oxide) may be further provided within the substrate 100 to define a plurality of active regions (not shown) extending in the same direction (not shown) within the substrate 100. For example, the trench isolations 110 in this embodiment may be elongated. Furthermore, an insulating layer 120 is also provided on the substrate 100. Specifically, the insulating layer 120 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, but is not limited thereto. For example, the insulating layer 120 in this embodiment is a single-layer structure (e.g., including a silicon nitride layer).

[0052] In this embodiment, a bitline structure BL is disposed on a substrate 100, and includes a plurality of first bitline structures BL1 and a second bitline structure BL2 that are separated from each other and have different widths and intervals. Specifically, the plurality of first bitline structures BL1 are arranged sequentially along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the second bitline structure BL2 is located on one side outside the plurality of first bitline structures BL1; specifically, if the width of the first bitline structure BL1 in the horizontal direction is a first width, and the width of the second bitline structure BL2 in the horizontal direction is a second width, then the first width is smaller than the second width; if the interval between adjacent first bitline structures BL1 is a first interval SP1, and the interval between adjacent first bitline structures BL1 and second bitline structures BL2 is a second interval SP2, then the first interval SP1 is smaller than the second interval SP2. In one embodiment, the first bit line structure BL1 and the second bit line structure BL2 have the same multilayer bit line material layers, such as a bit line material layer 130 composed of a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a capping layer 134 stacked sequentially from bottom to top. The semiconductor layer 131 may be made of crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The barrier layer 132 may be made of metal, metal silicide, or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but is not limited thereto. The metal layer 133 may be made of tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but is not limited thereto. The capping layer 134 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto. For example, the semiconductor layer 131 is made of polycrystalline silicon, the barrier layer 132 is made of cobalt silicide (CoSi), the metal layer 133 is made of tungsten (W), and the capping layer 134 is made of silicon nitride (SiN).

[0053] Furthermore, in this embodiment, both the first bit line structure BL1 and the second bit line structure BL2 may be provided with sidewall structures 140. The sidewall structures 140 may also have a multi-layered structure, for example... Figure 5The first sidewall 141 and the second sidewall 142 are shown stacked sequentially in a horizontal direction, with the first sidewall 141 in direct contact with the sidewall of the first bit line structure BL1 or the second bit line structure BL2. Specifically, the first sidewall 141 and the second sidewall 142 may each comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but are not limited thereto. For example, the material of the first sidewall 141 is silicon oxide (SiO2), and the material of the second sidewall 142 is silicon nitride (SiN).

[0054] Continue to refer to Figure 5 As shown, the semiconductor device in this embodiment may further include multiple contact structures 150 and silicide layers 160. A contact structure 150 and a silicide layer 160 are respectively formed within a first interval SP1 between adjacent first bit line structures BL1 and a second interval SP2 between the first bit line structure BL1 and the second bit line structure BL2. The two sides of the contact structure 150 are separated from the bit line structures BL by sidewall structures 140 and do not directly contact each other. The contact structure 150 extends vertically within the substrate 100 between adjacent bit line structures BL in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) to electrically connect with the substrate 100. In one embodiment, the material of the contact structure 150 may include crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon-germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. For example, the material of the contact structure 150 is phosphorus-doped silicon (SiP).

[0055] Furthermore, in this embodiment, the connecting pad structure 170 is specifically disposed between adjacent bit line structures BL and conformally covers the top surface of the silicide layer 160, the top surface of the sidewall structure 140, and the top surface of the bit line structure BL, while the isolation structure 180 is specifically disposed between adjacent connecting pad structures 170. In one embodiment, the connecting pad structure 170 may include a first connecting pad layer 170.1 and a second connecting pad layer 170.2 stacked sequentially from bottom to top; wherein, the material of the first connecting pad layer 170.1 may include titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN) and other conductive barrier materials, and is preferably titanium nitride (TiN), but is not limited thereto; the material of the second connecting pad layer 170.2 may include metals, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, and is preferably tungsten (W), but is not limited thereto.

[0056] In this embodiment, since the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different (i.e., first interval SP1 < second interval SP2), the widths of the connecting pad structure 170 between adjacent first bit line structures BL1 and the connecting pad structure 170 between adjacent first bit line structures BL1 and second bit line structures BL2, as well as the silicide layer 160 and contact structure 150 below them, are also different in the horizontal direction. For ease of distinction, this embodiment names the connecting pad structure between adjacent first bit line structures BL1 as the first connecting pad structure 171 and the connecting pad structure between adjacent first bit line structures BL1 and second bit line structures BL2 as the second connecting pad structure 172 (e.g., ...). Figure 4 (As shown). Therefore, in this embodiment of the invention, the width of the second connecting pad structure 172 in the horizontal direction is greater than the width of the first connecting pad structure 171 in the horizontal direction, and the width of the contact structure 150 located below the first connecting pad structure 171 in the horizontal direction is also smaller than the width of the contact structure 150 located below the second connecting pad structure 172 in the horizontal direction.

[0057] Under this configuration, the isolation structure 180 in this embodiment can also be divided into a first isolation structure 181 and a second isolation structure 182 due to the difference between the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2, such as... Figure 5As shown; specifically, the first isolation structure 181 passes vertically through the first connecting pad structure 171 and directly contacts the first bit line structure BL1, and the second isolation structure 182 passes vertically through the second connecting pad structure 172 and its bottom surface is completely covered by the second connecting pad structure 172, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 located on both sides of the second connecting pad structure 172 through which it passes; in other words, if the distance between adjacent first isolation structures 181 is a first distance d1, and the distance between adjacent first isolation structures 181 and second isolation structures 182 is a second distance d2, then the first distance d1 is smaller than the second distance d2. In one embodiment, the materials of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) may be the same and may specifically include nitrides, such as silicon nitride, or oxides, such as silicon oxide, and are preferably silicon nitride, but are not limited thereto.

[0058] In the prior art, adjacent first connecting pad structure 171 and second connecting pad structure 172 are usually isolated by a second isolation structure 182 to prevent short circuits of the two contact structures 150 located below the adjacent first connecting pad structure 171 and second connecting pad structure 172. However, since the first bit line structure BL1 located at the edge and the adjacent second bit line structure BL2 are often used as dummy structures to adjust the pattern density of semiconductor devices in practical applications, in this embodiment of the invention, the second isolation structure 182 located in the second interval SP2 between the adjacent first bit line structure BL1 and second bit line structure BL2 is offset in the horizontal direction close to the second bit line structure BL2, so that the first connecting pad structure 171 and the second connecting pad structure 172 located above the adjacent first bit line structure BL1 and second bit line structure BL2 are connected. This avoids the technical problem that some contact structures are stripped during photolithography and other processes due to differences in pattern density, thereby improving the reliability and performance of semiconductor devices.

[0059] In addition, please refer to Figure 7 As shown, the semiconductor device in this embodiment may further include a capacitor structure CAP disposed on a first connection pad structure 171 adjacent to the first bit line structure BL1, wherein the capacitor structure CAP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0060] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0061] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of this invention may have other forms and is not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.

[0062] Please refer to Figure 12 and Figure 13 , Figure 13 The drawing shows a partial top view of a semiconductor device according to a second embodiment of the present invention. Figure 12 The illustration shows a semiconductor device according to a second embodiment of the present invention. Figure 13 The diagram shows a cross-sectional view of a portion of the AA' tangent. The structure of the semiconductor device in this embodiment is largely the same as that in the first embodiment described above. For example, the semiconductor device also includes multiple first bit line structures BL1 arranged horizontally and mutually separated on the substrate 100, and second bit line structures BL2 located on the outer side of one side of the multiple first bit line structures BL1, multiple contact structures 150, etc. The similarities will not be repeated here. The main difference between the semiconductor device in this embodiment and the first embodiment described above is that at least one third bit line structure BL3 is also provided in the multiple bit line structures BL of the semiconductor device, and the top surface of the third bit line structure BL3 is located at a different horizontal height from the top surfaces of the first bit line structure BL1 and the second bit line structure BL2, so that the second isolation structure 182 located on the top surface of the third bit line structure BL3 is also different.

[0063] Specifically, such as Figure 12As shown, in this embodiment, the semiconductor device has a third bit line structure BL3 disposed between adjacent first bit line structures BL1 and second bit line structures BL2, such that multiple first bit line structures BL1, one third bit line structure BL3, and one second bit line structure BL2 are horizontally spaced apart, and the top surface of the third bit line structure BL3 is lower than the top surfaces of the first bit line structures BL1 and the second bit line structures BL2. In one embodiment, the third bit line structure BL3 has the same multilayer bit line material layers, such as the semiconductor layer 131 (e.g., polysilicon), the barrier layer 132 (e.g., cobalt silicide), and the metal layer 133 (e.g., tungsten) stacked sequentially from bottom to top; the third spacing SP3 between the third bit line structure BL3 and the adjacent first bit line structure BL1 may be the same as the first spacing SP1 between adjacent first bit line structures BL1, and the fourth spacing SP4 between the third bit line structure BL3 and the adjacent second bit line structure BL2 may be smaller than the third spacing SP3.

[0064] It should be noted that the connecting pad structure 170 in this embodiment is still divided into a first connecting pad structure 171 and a second connecting pad structure, and the isolation structure 180 is also still divided into a first isolation structure 181 and a second isolation structure 182. Since the multilayer bit line material layer of the third bit line structure BL3 does not include the cover layer 134, the connecting pad structure 170 located in the adjacent first bit line structure BL1 and second bit line structure BL2 in this embodiment changes from one in the aforementioned first embodiment to two in this embodiment. That is, a second connecting pad structure 172 located on the top surface of the third bit line structure BL3 and in the third interval SP3 between it and the adjacent first bit line structure BL1 (at this time, the first connecting pad layer 170.1 in the second connecting pad structure 172 is in direct contact with the metal layer 134 of the third bit line structure BL3), and a second connecting pad structure 172 located in the fourth interval SP4 between the third bit line structure BL3 and the adjacent second bit line structure BL2 and on the top surface of the second bit line structure BL2.

[0065] In this configuration, the isolation structure 180 located between the first bit line structure BL1 and the second bit line structure BL2 in this embodiment is changed from a second isolation structure 182 whose bottom is completely covered by the second connecting pad structure 172 in the aforementioned first embodiment to a second isolation structure 182 located above the third bit line structure BL3 and isolated from the third bit line structure BL3 and the bit line structures BL on both sides, and a second isolation structure 182 located above the second bit line structure BL2 and in direct contact with the second bit line structure BL2.

[0066] Obviously, in this embodiment, the second isolation structure 182 located above the third bit line structure BL3 undergoes a process offset, so that the two adjacent second connection pad structures 172 located above the third bit line structure BL3 are connected. This avoids the technical problem of some contact structures being stripped off during photolithography and other processes due to large differences in pattern density, thereby improving the reliability and performance of semiconductor devices.

[0067] Furthermore, based on the same inventive concept, this embodiment of the invention also provides a method for manufacturing the semiconductor device, which may specifically include the following steps:

[0068] Step S100: Provide substrate 100;

[0069] Step S200: A plurality of bit line structures BL are formed, wherein the bit line structure BL includes a first bit line structure BL1 and a second bit line structure BL2 that are disposed on the substrate 100 separately from each other.

[0070] Step S300: A plurality of connecting pad structures 170 are formed, wherein the connecting pad structures 170 are disposed between adjacent bit line structures BL;

[0071] In step S400, a plurality of isolation structures 180 are formed and disposed between adjacent connecting pad structures 170. Each isolation structure 180 includes a first isolation structure 181 that is in direct contact with the first bit line structure BL1 and the connecting pad structure 170, and a second isolation structure 182 located between the first bit line structure BL1 and the second bit line structure BL2, wherein the bottom surface of the second isolation structure 182 is completely covered by the connecting pad structure 170.

[0072] In order to enable those skilled in the art to easily understand the manufacturing method of the semiconductor device in the embodiments of the present invention, the manufacturing method of the semiconductor device proposed in the present invention will be further described below with reference to the various structural schematic diagrams in the preparation process of the manufacturing method.

[0073] Please refer to Figures 1 to 7 As shown, Figures 1 to 7 This is a schematic diagram of the structure of the semiconductor device manufacturing method provided in the first embodiment of the present invention during the preparation process.

[0074] Please refer to Figure 1The steps S100 and S200 described above are performed as follows: a substrate 100 is provided, and multiple trenches are formed within the substrate 100 using an etching process. Then, an insulating material (such as silicon oxide, silicon nitride, etc.) is filled into the multiple trenches using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, or atomic layer deposition, to form multiple trench isolations 110. These multiple trench isolations 110 define multiple active regions within the substrate 100. Next, an insulating layer 120 (such as a silicon oxide layer or a silicon nitride layer) and a multilayer bit line material layer located on the insulating layer 120 are formed on the substrate 100. Specifically, forming the multilayer bit line material layer may include forming a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a capping layer 134 sequentially from bottom to top on the substrate 100. For example, the semiconductor layer 131 is made of polycrystalline silicon, the barrier layer 132 is made of cobalt silicide (CoSi), the metal layer 133 is made of tungsten (W), and the capping layer 134 is made of silicon nitride (SiN). Subsequently, an etching process is used to sequentially etch the multilayer structure of the bit line material layer along the vertical direction, thereby forming multiple mutually separated bit line structures BL within it; specifically, the bit line structure BL includes multiple first bit line structures BL1 and a second bit line structure BL2. The multiple first bit line structures BL1 are arranged sequentially along the horizontal direction, and the second bit line structure BL2 is located on one side outside the multiple first bit line structures BL1. The width of the first bit line structure BL1 in the horizontal direction is smaller than the width of the second bit line structure BL2 in the horizontal direction, and the first interval SP1 between adjacent first bit line structures BL1 is smaller than the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2.

[0075] Please refer to Figure 2 Following step S200 above, sidewall structures 140, which are self-aligned to the sidewalls of the first bit line structure BL1 and the second bit line structure BL2, are formed on both sides of the plurality of first bit line structures BL1 and the second bit line structure BL2, respectively. In one embodiment, the sidewall structure 140 has a multilayer structure, for example, a first sidewall 141 (such as silicon oxide) and a second sidewall 142 (such as silicon nitride) are stacked sequentially in the horizontal direction.

[0076] Please refer to Figure 3Following step S200: using an etching process, etching is performed downwards along the vertical direction to form a memory node contact trench (not shown) on the outside of the sidewall structure 140 after removing the insulating layer 120 and part of the substrate 100. Then, a contact material layer (not shown) is formed to completely cover the substrate 100 and fill the memory node contact trench. Next, an etching or planarization process is used to remove the contact material layer outside the memory node contact trench until the top surfaces of the bit line structure BL and the sidewall structure 140 are exposed, thereby obtaining contact structures 150 located in the memory node contact trenches. The contact material layer can be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Then, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 are silicided to allow the top of the contact structure 150, which is made of a silicon-containing semiconductor material such as phosphorus-doped silicon, to react with the metal material layer to form a silicide layer 160, resulting in... Figure 3 The structure is shown. At this time, since the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different (i.e., first interval SP1 < second interval SP2), the width in the horizontal direction of the contact structure 150 and the silicide layer 160 located between adjacent first bit line structures BL1 is also different from the width in the horizontal direction of the contact structure 150 and the silicide layer 160 located between adjacent first bit line structures BL1 and second bit line structures BL2. That is, the width in the horizontal direction of the contact structure 150 and the silicide layer 160 located between adjacent first bit line structures BL1 is smaller than the width in the horizontal direction of the contact structure 150 located between adjacent first bit line structures BL1 and second bit line structures BL2.

[0077] Please refer to Figure 4Perform the above step S300: using a deposition process, deposit a first connection pad material layer (e.g., titanium nitride) and a second connection pad material layer (e.g., tungsten metal) of the connection pad structure 170 on the substrate 100, and etch them to form a first connection pad layer 170.1 that wraps around the surface of the silicide layer 160, the first bit line structure BL1 and the second bit line structure BL2, and a second connection pad layer 170.2 that fills the gap between adjacent first bit line structures BL1 and second bit line structures BL2 and whose top surface is higher than the top surface of the first bit line structure BL1, thereby forming a connection pad structure 170 including the first connection pad layer 170.1 and the second connection pad layer 170.2 arranged sequentially from bottom to top. Similarly, due to the difference between the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2, the multiple connecting pad structures 170 in this embodiment can be specifically divided into a first connecting pad structure 171 and a second connecting pad structure 172 according to their different widths in the horizontal direction. The first connecting pad structure 171 is located between adjacent first bit line structures BL1, and the second connecting pad structure 172 is located between adjacent first bit line structures BL1 and second bit line structures BL2. The width of the first connecting pad structure 171 in the horizontal direction is smaller than the width of the second connecting pad structure 172 in the horizontal direction.

[0078] Please refer to Figure 5 The above step S400 is performed: a mask layer (not shown) is formed on the connecting pad structure 180, wherein the mask layer has an isolation structure pattern, and using the mask layer as a mask, multiple isolation structures 180 are formed along the vertical direction on the connecting pad structure 170 and part of the bit line structure BL on one side of the bit line structure BL using an etching process. Specifically, the isolation structure 180 includes a first isolation structure 181 and a second isolation structure 182 that are separated from each other and arranged sequentially along the horizontal direction. The first isolation structure 181 passes through the first connecting pad structure 171 and its bottom surface extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1. The second isolation structure 182 passes through the second connecting pad structure 172 and its bottom surface is completely covered by the second connecting pad structure 172, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 located on both sides of the second connecting pad structure 172 through which it passes. In one embodiment, the materials of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) may be the same and may specifically include nitrides, such as silicon nitride, or oxides, such as silicon oxide, and are preferably silicon nitride, but are not limited thereto.

[0079] Please refer to Figure 7Following step S400 above: a capacitor structure CAP can then be formed on the first connection pad structure 171 between adjacent first bit line structures BL1, wherein the capacitor structure CAP includes a lower electrode BE, a dielectric layer DL, and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0080] It should be noted that, since the embodiments of the present invention are based on the fact that the first bit line structure BL1 located at the edge of the cell area and the second bit line structure BL2 located on the peripheral area are often used as dummy structures for adjusting the pattern density of the cell area in practical applications, the second isolation structure 182 located in the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 is offset in the horizontal direction close to the second bit line structure BL2, so that the first connecting pad structure 171 and the second connecting pad structure 172 located above adjacent first bit line structures BL1 and second bit line structures BL2 are connected, therefore, when the isolation structure 180 is formed using the above step S400, When the manufacturing process of this invention forms an isolation trench (not shown, but in the same position as the isolation structure) in the first connecting pad structure 171 and the second connecting pad structure 172, the isolation trench located in the second connecting pad structure 172 needs to be offset along the horizontal direction close to the second bit line structure BL2. Then, after filling the isolation trench with insulating material (e.g., silicon nitride) using a deposition process, the entire bottom surface of the second isolation structure 182 formed is covered by the second connecting pad structure 172, that is, the first connecting pad structure 171 and the second connecting pad structure 172 located above the adjacent first bit line structure BL1 and second bit line structure BL2 are connected.

[0081] Please refer to Figures 8 to 14 As shown, Figures 8 to 14 This is a schematic diagram of the structure of the semiconductor device manufacturing method provided in the second embodiment of the present invention during the preparation process.

[0082] The structure of the semiconductor device in this embodiment is largely the same as the manufacturing method of the semiconductor device in the first embodiment described above, and the similarities will not be repeated here. The main difference between the manufacturing method of the semiconductor device in this embodiment and the manufacturing method of the first embodiment described above is that: after performing the above step S200 to form a plurality of first bit line structures BL1 and a second bit line structure BL2 arranged sequentially and spaced apart in the horizontal direction, the capping layer 134 of a first bit line structure BL1 adjacent to the second bit line structure BL2 can be further removed using an etching process such as a dry etching process, so as to form a third bit line structure BL3 between the adjacent first bit line structures BL1 and the second bit line structure BL2, such as... Figure 8 As shown; it should be understood that in other embodiments, the sidewall structure 140 may also be formed on the sidewalls of the first bit line structure BL1 and the second bit line structure BL2, and then an etching process may be used to form the structure as shown. Figure 9 The structures described herein, but not limited thereto.

[0083] In summary, in this invention, by setting the interval between adjacent first line structures and second line structures to be larger than the interval between adjacent first line structures, the width of the connecting pad structure formed between two adjacent first line structures in the horizontal direction is smaller than the width of the connecting pad structure formed between adjacent first line structures and second line structures in the horizontal direction. This causes the second isolation structure within the connecting pad structure formed between adjacent first line structures and second line structures to shift in the direction closer to the second line structure, thereby achieving the purpose of allowing the connecting pad structure located between adjacent first line structures and second line structures to communicate with the connecting pad structure adjacent to it and located between adjacent first line structures.

[0084] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0085] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Base; Multiple bit line structures, including a first bit line structure and a second bit line structure disposed on a substrate and spaced apart from each other, wherein the first bit line structure adjacent to the second bit line structure is located at the edge of the cell region and the second bit line structure is located in the peripheral region; Multiple connecting pad structures are disposed between adjacent bit line structures; Multiple isolation structures are disposed between adjacent connecting pad structures, the isolation structures including: The first isolation structure is in direct contact with the first bit line structure and the connecting pad structure; The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connecting pad structure.

2. The semiconductor device as claimed in claim 1, characterized in that, The first interval between adjacent first bit line structures is smaller than the second interval between adjacent first bit line structures and second bit line structures.

3. The semiconductor device as described in claim 2, characterized in that, The connecting pad structure includes: a first connecting pad structure disposed between adjacent first bit line structures; The second connecting pad structure is disposed between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connecting pad structure.

4. The semiconductor device as described in claim 3, characterized in that, The second connecting pad structure is connected to the first connecting pad structure adjacent to it.

5. The semiconductor device as claimed in claim 1, characterized in that, The second isolation structure is isolated from both the first bit line structure and the second bit line structure.

6. The semiconductor device as claimed in claim 1, characterized in that, There is a first spacing between adjacent first isolation structures, and a second spacing between adjacent first isolation structures and second isolation structures, wherein the first spacing is smaller than the second spacing.

7. The semiconductor device as claimed in claim 3, characterized in that, Also includes: Multiple contact structures are disposed under the connecting pad structure, and the width of the contact structure located under the first connecting pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connecting pad structure in the horizontal direction.

8. The semiconductor device as claimed in claim 1, characterized in that, The width of the first bit line structure in the horizontal direction is smaller than the width of the second bit line structure in the horizontal direction.

9. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connecting pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

10. The semiconductor device as claimed in claim 9, characterized in that, The third bit line structure includes semiconductor layers and metal layers stacked sequentially from bottom to top, and the connection pad structure is in direct contact with the metal layer.

11. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; Multiple bit line structures are formed, including a first bit line structure and a second bit line structure disposed on the substrate separately from each other. The first bit line structure adjacent to the second bit line structure is located at the edge of the cell region, and the second bit line structure is located in the peripheral region. Multiple connection pad structures are formed, and the connection pad structures are disposed between adjacent bit line structures; Multiple isolation structures are formed and disposed between adjacent connecting pad structures. The isolation structure includes a first isolation structure that is in direct contact with the first bit line structure and the connecting pad structure, and a second isolation structure located between the first bit line structure and the second bit line structure, wherein the bottom surface of the second isolation structure is completely covered by the connecting pad structure.

12. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, The first interval between adjacent first bit line structures is smaller than the second interval between adjacent first bit line structures and second bit line structures.

13. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, The connecting pad structure includes: A first connecting pad structure is disposed between adjacent first bit line structures; The second connecting pad structure is disposed between the adjacent first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connecting pad structure.

14. The method for manufacturing a semiconductor device as described in claim 13, characterized in that, The second connecting pad structure is connected to the first connecting pad structure adjacent to it.

15. The method for manufacturing a semiconductor device as described in claim 11, characterized in that, The second isolation structure is isolated from both the first bit line structure and the second bit line structure.

16. The method for manufacturing a semiconductor device as described in claim 13, characterized in that, Also includes: Multiple contact structures are formed, the contact structures are disposed under the connecting pad structure, and the width of the contact structure located under the first connecting pad structure in the horizontal direction is smaller than the width of the contact structure located under the second connecting pad structure in the horizontal direction.

17. The method for manufacturing a semiconductor device as claimed in claim 11, characterized in that, The bitline structure also includes: The third bit line structure is located between the adjacent first bit line structure and the second bit line structure, and at least one of the connecting pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

18. The method for manufacturing a semiconductor device as described in claim 17, characterized in that, The third bit line structure includes semiconductor layers and metal layers stacked sequentially from bottom to top, and the connection pad structure is in direct contact with the metal layer.

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