Semiconductor device, method of manufacturing the same, and electronic system

Abstract

The invention discloses a semiconductor device, an electronic system including the semiconductor device, and a manufacturing method of the semiconductor device. The semiconductor device includes a gate stack structure, a channel structure, and a horizontal conductive layer. The gate stack structure may include a plurality of gate electrodes and a plurality of insulating layers alternately stacked. The channel structure may be provided with an inner portion extending into the gate stack structure and a protruding portion protruding from one surface of the gate stack structure. The horizontal conductive layer may be connected to the protruding portion of the channel structure. In this case, the channel structure may include a semiconductor layer. The semiconductor layer may include a polycrystalline region at least in the protruding portion and including a polycrystalline semiconductor material, and a channel region in the inner portion and having a crystal structure different from that of the polycrystalline region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and an electronic system. Background Art

[0002] In electronic systems implementing data storage, semiconductor devices can store high-capacity data. Therefore, methods for increasing the data storage capacity of semiconductor devices are being studied. As a method for increasing the data storage capacity of semiconductor devices, semiconductor devices including three-dimensionally arranged memory cells rather than two-dimensionally arranged memory cells have been proposed. Summary of the invention

[0003] Some embodiments may provide a semiconductor device, a method of manufacturing the same, and an electronic system having improved reliability and performance.

[0004] A semiconductor device according to an embodiment includes a gate stack structure, a channel structure and a horizontal conductive layer. The gate stack structure may include a plurality of gate electrodes and a plurality of insulating layers stacked alternately. The channel structure may be provided with an inner portion extending into the gate stack structure and a protruding portion protruding from one surface of the gate stack structure. The horizontal conductive layer may be connected to the protruding portion of the channel structure. In this case, the channel structure may include a semiconductor layer. The semiconductor layer may include a polycrystalline region and a channel region, the polycrystalline region being at least in the protruding portion and including a polycrystalline semiconductor material, and the channel region being in the inner portion and having a crystal structure different from the crystal structure of the polycrystalline region.

[0005] An electronic system according to an embodiment includes a main substrate, the above-mentioned semiconductor device on the main substrate, and a controller on the main substrate electrically connected to the semiconductor device.

[0006] The manufacturing method of the semiconductor device according to the embodiment includes forming a stacking structure, forming a preliminary channel structure, forming a semiconductor layer and forming a plurality of gate electrodes. In the formation of the stacking structure, a stacking structure including a plurality of sacrificial insulating layers and a plurality of insulating layers alternately stacked on a substrate can be formed. In the formation of the preliminary channel structure, a penetration portion extending into the stacking structure can be formed, and a preliminary channel structure including a preliminary semiconductor layer can be formed in the penetration portion, the preliminary semiconductor layer including an amorphous semiconductor material. In the formation of the semiconductor layer, a heat treatment process can be performed for crystallization of the preliminary semiconductor layer. In this case, the first region of the preliminary semiconductor layer can be crystallized to have a polycrystalline structure, and the second region of the preliminary semiconductor layer can be crystallized to have a single crystal structure or a quasi-single crystal structure. In the formation of multiple gate electrodes, the multiple sacrificial insulating layers can be replaced with multiple gate electrodes.

[0007] According to an embodiment, damage or defects in the channel structure can be reduced or prevented by a semiconductor layer including a polycrystalline region having a polycrystalline semiconductor material. In addition, by including a semiconductor layer having a channel region having a crystal structure different from the crystal structure of the polycrystalline region, a cell current can be increased. Therefore, the reliability and performance of the semiconductor device can be improved.

[0008] According to embodiments, semiconductor devices with improved reliability and performance may be formed by processes of reasonable complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments.

[0010] Figure 2 yes Figure 1 An enlarged cross-sectional view of portion A of FIG.

[0011] Figure 3 yes Figure 2 An enlarged cross-sectional view of portion B.

[0012] Figure 4 is an enlarged cross-sectional view of a portion of a semiconductor device according to a modified embodiment.

[0013] FIG. 5A to FIG. 5H is a partial cross-sectional view of a semiconductor manufacturing method according to some embodiments.

[0014] Figure 6 An electronic system including a semiconductor device according to some embodiments is schematically illustrated.

[0015] Figure 7 An electronic system including a semiconductor device according to some embodiments is schematically illustrated.

[0016] Figure 8 is a schematic cross-sectional view of a semiconductor package according to some embodiments. DETAILED DESCRIPTION

[0017] Embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily implement the present disclosure. The present disclosure may be implemented in any of a variety of different forms, without being limited to the embodiments provided herein. In the accompanying drawings, the same reference numerals are used for the same components, and their repeated descriptions are omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. Note that aspects described with respect to an embodiment may be incorporated into different embodiments, although not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment may be combined in any manner and / or combination.

[0018] In order to clearly describe the present disclosure, parts not related to the description are omitted. In addition, since the sizes and thicknesses of the parts, regions, components, units, layers, films, etc. shown in the drawings can be arbitrarily displayed for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. The thicknesses of some parts, regions, components, units, layers, films, etc. may be enlarged in the drawings to improve clarity. In addition, for ease of explanation, in the drawings, the thicknesses of parts, regions, components, units, layers, films, etc. may be exaggerated.

[0019] It will be understood that when a component such as a layer, film, region, or substrate is referred to as being "on" another component, it can be directly on the other component, or intervening components may also be present. In contrast, when a component is referred to as being "directly on" another component, there are no intervening components. Furthermore, when a component is referred to as being "on" or "over" a reference component, the component may be located on the reference component, e.g., above or below the reference component, and may not necessarily be "on" or "over" the reference component in an opposite direction of gravity.

[0020] In addition, unless explicitly described to the contrary, the words “comprise,” “include,” or “contain,” and variations such as “comprising,” “including,” or “containing,” will be understood to imply the inclusion of other components rather than the exclusion of any other components.

[0021] In addition, throughout the specification, the phrases "on a plane", "in a plane", "on a plan view" or "in a plan view" may mean observing a part from above or from the top, and the phrases "on a cross section" or "in a cross section" may mean observing a cross section taken in a vertical direction from the side.

[0022] In the following, refer to Figures 1 to 4 and FIG. 5A to FIG. 5H , a semiconductor device according to an embodiment and a modified embodiment, and a method of manufacturing the same will be described in detail.

[0023] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments, Figure 2 yes Figure 1 An enlarged cross-sectional view of portion A of FIG.

[0024] Reference Figure 1 and Figure 2According to some embodiments, the semiconductor device 10 may include a cell region 100 provided with a memory cell structure and a circuit region 200 provided with a peripheral circuit structure for controlling the memory cell structure. In this case, the cell region 100 and the circuit region 200 may be a bonded semiconductor device of a chip-to-chip (C2C) structure bonded by a wafer bonding method (e.g., hybrid bonding). For example, the circuit region 200 and the cell region 100 may correspond to the circuit region 200 included in the cell region 100. Figure 6 The first structure 1100F and the second structure 1100S of the semiconductor device 1100 in the electronic system 1000 are shown as corresponding parts. For example, the circuit area 200 and the unit area 100 may include Figure 8 Corresponding portions of the first structure 1100F and the second structure 1100S of the semiconductor chip 2200 are shown.

[0025] Here, the circuit region 200 may include a peripheral circuit structure on a first substrate 210, and the cell region 100 may include a gate stack structure 120 and a channel structure CH as a memory cell structure. The circuit region 200 may include a first wiring portion 230 electrically connected to the peripheral circuit structure, and the cell region 100 may include a second wiring portion 180 electrically connected to the memory cell structure.

[0026] In an embodiment, the cell region 100 may be disposed on the circuit region 200. Therefore, there is no need to secure an area corresponding to the circuit region 200 separately from the cell region 100, and thus the area of ​​the semiconductor device 10 may be reduced. However, the embodiment is not limited thereto, and many variations are applicable.

[0027] The circuit region 200 may include a first substrate 210, a circuit element 220 and a first wiring portion 230 on the first substrate 210, and a first bonding structure 240 on the circuit element 220 and the first wiring portion 230 at a surface opposite to the cell region 100. In addition, the circuit region 200 may further include a first insulating layer 250 covering the first substrate 210, the circuit element 220, the first wiring portion 230, and the like.

[0028] The first substrate 210 may be a semiconductor substrate including a semiconductor material. For example, the first substrate 210 may be a semiconductor substrate formed of a semiconductor material, and may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the first substrate 210 may be formed of single crystal silicon or polycrystalline silicon, epitaxial silicon, germanium, silicon germanium, silicon on insulator (SOI) and / or germanium on insulator (GOI), etc.

[0029] The circuit element 220 on the first substrate 210 may include any of various circuit elements that control the operation of the memory cell structure provided in the cell region 100. For example, the circuit element 220 may form a peripheral circuit structure such as a decoder circuit (see Figure 6 1110 in), page buffer (refer to Figure 6 1120 in), logic circuit (refer to Figure 6 1130 in ), etc. The circuit element 220 may include, for example, a transistor, but this is not restrictive. For example, the circuit element 220 may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, inductors, etc.

[0030] The first wiring portion 230 disposed on the first substrate 210 may electrically connect the circuit element 220 and the first bonding structure 240. In an embodiment, the first wiring portion 230 may include a plurality of wiring layers 236, the plurality of wiring layers 236 are spaced apart and the first insulating layer 250 is therebetween, and the plurality of wiring layers 236 are connected by contact paths 234 to form a preferred path. The wiring layers 236 or the contact paths 234 may include any of various conductive materials, and the first insulating layer 250 may include any of various insulating materials, such as silicon oxide, silicon nitride, etc. The first insulating layer 250 may be formed of one or more insulating layers.

[0031] The cell region 100 may include a cell array region 102 and a connection region 104. The gate stack structure 120 and the channel structure CH may be disposed on the horizontal conductive layer 110 in the cell array region 102. The connection region 104 may be disposed at the periphery of the cell array region 102. A structure for connecting the gate stack structure 120 and / or the channel structure CH to an external circuit or a circuit region 200 formed in the cell array region 102 may be in the connection region 104.

[0032] In this specification, unless otherwise specified, the upper part or the lower part may mean the upper part or the lower part in the manufacturing process. For example, unless otherwise specified, for the gate stack structure 120, the channel structure CH, etc., the upper part may mean a part located away from the horizontal conductive layer 110 or a part located close to the circuit area 200, and the lower part may mean a part located close to the horizontal conductive layer 110 or a part located away from the circuit area 200. Unless otherwise specified, for the horizontal conductive layer 110, the upper part may mean a part located away from the circuit area 200, as Figure 1 and Figure 2 The upper part and the lower part may refer to the part located close to the circuit area 200. Figure 1 and Figure 2 The lower part of the.

[0033] In an embodiment, the semiconductor layer disposed on one surface 120p of the gate stack structure 120 may be removed. Figure 5A 110s in the figure) and then form a horizontal conductive layer 110. This will be described in more detail later. Here, one surface 120p of the gate stack structure 120 may be the bottom surface of the gate stack structure 120 during the manufacturing process, and / or may be Figure 1 and Figure 2 The gate stack structure 120 has an upper surface on which the horizontal conductive layer 110 is disposed.

[0034] The gate stack structure 120 may be disposed on the horizontal conductive layer 110. The gate stack structure 120 may include a plurality of unit insulating layers 132 and a plurality of gate electrodes 130 that are alternately stacked.

[0035] The unit insulating layer 132 may include an interlayer insulating layer 132m, upper insulating layers 132a and 132b, and a bottom insulating layer 132l. The interlayer insulating layer 132m may be between two adjacent gate electrodes 130 in the gate stack structure 120. The upper insulating layers 132a and 132b may be on the upper side ( Figure 1 The bottom insulating layer 1321 may be between a gate electrode adjacent to one surface 120p of the gate stack structure 120 among the plurality of gate electrodes 130 and the horizontal conductive layer 110. The bottom insulating layer 1321 may be adjacent to one surface of the gate stack structure 120 or may form one surface 120p of the gate stack structure 120. For simplicity of description, Figure 1 , it is shown that the cell insulating layer 132 is provided without a border in the connection region 104 except for a portion where the connection line 190a is disposed. However, the cell insulating layer 132 in the connection region 104 may have any of various structures including one or more insulating layers, and embodiments are not limited thereto.

[0036] The gate electrode 130 may include any of a variety of conductive materials. For example, the gate electrode 130 may include a metal material (such as tungsten (W), copper (Cu), aluminum (Al), etc.), polysilicon, a metal nitride (such as titanium nitride (TiN), tantalum nitride (TaN), etc.), or a combination thereof. Figure 2 As shown in the enlarged view of FIG. 1 , a barrier layer 156 (e.g., a first barrier layer 156a) formed of an insulating material may be disposed on the outer side of the gate electrode 130. The cell insulating layer 132 may include any of various insulating materials. For example, the cell insulating layer 132 may include silicon oxide, silicon nitride, silicon oxynitride, a low dielectric constant material having a lower dielectric constant than silicon oxide, or a combination thereof.

[0037] A channel structure CH extending into the gate stack structure 120 or penetrating the gate stack structure 120 and extending in a cross direction (e.g., a vertical direction perpendicular to the horizontal conductive layer 110) intersecting the horizontal conductive layer 110 may be formed. The channel structure CH may have a column shape. For example, in a cross-sectional view, the channel structure CH may have an inclined side surface whose width becomes narrower as it approaches the horizontal conductive layer 110 according to the aspect ratio. However, the embodiment is not limited thereto, and the structure and shape of the channel structure CH may be variously modified.

[0038] The channel structures CH each form a memory cell string, and the plurality of channel structures CH may be separated from each other while forming rows and columns in a plan view. For example, in a plan view, the plurality of channel structures CH may be arranged to have any of various forms such as a lattice form and a sawtooth form. However, the embodiment is not limited thereto, and the arrangement and shape of the channel structure CH may be variously modified.

[0039] In an embodiment, the channel structure CH may include an inner portion CHI extending into the gate stack structure 120 and a portion CHI protruding from one surface 120p of the gate stack structure 120 toward the outside of the horizontal conductive layer 110 (eg, toward the Figure 2 The protruding part CHP of the upper protrusion in the middle).

[0040] The horizontal conductive layer 110 may be connected to the protruding portion CHP of the channel structure CH. The horizontal conductive layer 110 may also be referred to as a second substrate, a common source electrode, a common source substrate, a common source line, etc. The horizontal conductive layer 110 may be formed of a conductive material (e.g., a semiconductor layer doped with a p-type or n-type dopant). In an embodiment, the horizontal conductive layer 110 may be formed of a polycrystalline semiconductor material (e.g., polysilicon) doped with a p-type or n-type dopant. Current may stably flow through the horizontal conductive layer 110 doped with a dopant. However, the embodiment is not limited thereto, and the horizontal conductive layer 110 may be formed of any of a variety of materials.

[0041] As described above, when the horizontal conductive layer 110 includes polysilicon, the grain size of the polycrystalline region 140b having a polycrystalline structure may be smaller than the grain size of the horizontal conductive layer 110. However, the embodiment is not limited thereto, and the grain size of the polycrystalline region 140b may be equal to or larger than the grain size of the horizontal conductive layer 110. The polycrystalline region 140b provided in the semiconductor layer 140 included in the channel structure CH will be described in more detail below.

[0042] In an embodiment, the horizontal conductive layer 110 may be completely formed on the outer surface of the protruding portion CHP and may be completely connected to the outer surface of the protruding portion CHP. In more detail, the horizontal conductive layer 110 is completely formed on the bottom surface of the semiconductor layer 140 at the protruding portion CHP (refer to Figure 3 140t, the same below) and side surface (refer to Figure 3 140s, the same below), and thus can be completely connected to the semiconductor layer 140 at the protruding portion CHP (ie, the bottom surface 140t and the side surface 140s of the polycrystalline region 140b).

[0043] For example, the horizontal conductive layer 110 may have a substrate shape that completely covers the bottom surface 140t and the side surface 140s of the semiconductor 140 (e.g., the polycrystalline region 140b) at the protruding portion CHP. That is, the outer surface of the horizontal conductive layer 110 may be entirely located on the same plane or formed of a flat surface. The height of the protruding portion CHP (refer to Figure 3 The sum of the height of the horizontal conductive layer 110 at the protruding portion CHP and the thickness of the horizontal conductive layer 110 in the portion where the protruding portion CHP is not provided may be completely consistent. However, the embodiment is not limited thereto. According to the shape of the protruding portion CHP, the outer surface of the horizontal conductive layer 110 may have a curve, or the horizontal conductive layer 110 may have any of various other shapes.

[0044] In an embodiment, electrical performance may be improved by increasing the connection area between the protruding portion CHP of the channel structure CH and the horizontal conductive layer 110. In addition, the protruding portion CHP of the channel structure CH and the horizontal conductive layer 110 may be connected by a process of reasonable complexity.

[0045] The channel structure CH may include a semiconductor layer 140 and a gate dielectric layer 150 on the semiconductor layer 140 between the gate electrode 130 and the semiconductor layer 140. In addition, the channel structure CH may further include a core insulating layer 142 and a channel pad 144.

[0046] The gate dielectric layer 150 may include a tunneling layer 152, a charge storage layer 154, and a blocking layer 156 formed sequentially on the semiconductor layer 140. The tunneling layer 152 may include an insulating material capable of performing charge tunneling. For example, the tunneling layer 152 may include silicon oxide or silicon oxynitride. The charge storage layer 154 is used as a data storage area and may include polysilicon, silicon nitride, etc. The blocking layer 156 may include an insulating material that can reduce or prevent undesired charges from flowing into the gate electrode 130. For example, the blocking layer 156 may include silicon oxide, silicon nitride, silicon oxynitride, a high dielectric constant material having a higher dielectric constant than silicon oxide, or a combination thereof. In an embodiment, the blocking layer 156 may include a first blocking layer 156a and a second blocking layer 156b, the first blocking layer 156a including a portion extending parallel to the gate electrode 130, and the second blocking layer 156b extending vertically between the first blocking layer 156a and the charge storage layer 154. However, the material and stack structure of the gate dielectric layer 150 may be variously modified, and the embodiment is not limited thereto.

[0047] The core insulating layer 142 may be inside the semiconductor layer 140. For example, the core insulating layer 142 may be formed in a channel region ( Figure 3 Therefore, by reducing the thickness of the channel region 140a of the semiconductor layer 140, the magnitude of the electric field applied to the channel region 140a can be reduced, thereby suppressing or preventing the electric fields from adjacent gate electrodes in the plurality of gate electrodes 130 from interfering with each other.

[0048] The core insulating layer 142 may include any one of various insulating materials. For example, the core insulating layer 142 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. However, the material of the core insulating layer 142 may be variously modified, and the embodiment is not limited thereto.

[0049] The semiconductor layer 140 may mean a layer including a semiconductor material. At least a portion of the semiconductor layer 140 may be formed of a semiconductor material layer including a semiconductor material alone. A portion of the semiconductor layer 140 may include a portion including a semiconductor material and another material (eg, an interface portion 140f).

[0050] In an implementation, the semiconductor layer 140 may include a polycrystalline region 140b and a channel region 140a each having a different crystal structure. Figure 3 as well as Figure 1 and Figure 2 , the semiconductor layer 140 will be described in more detail.

[0051] Figure 3 yes Figure 2 An enlarged cross-sectional view of portion B.

[0052] Reference Figures 1 to 3 In an embodiment, the semiconductor layer 140 may include a polycrystalline region 140b that at least partially fills at least a portion of the inner portion CHI and the protruding portion CHP and includes a polycrystalline semiconductor material. The channel region 140a in the inner portion CHI may have a crystal structure different from that of the polycrystalline region 140b. In some embodiments, the channel region 140a may have a single crystal structure or a quasi-single crystal structure.

[0053] Here, the polycrystalline structure may mean a crystal structure having a grain boundary including a plurality of crystal grains having different crystal orientations. For example, the polycrystalline region 140b may have a plurality of randomly crystallized crystal grains. For example, the polycrystalline region 140b may have a polycrystalline structure through solid state crystallization.

[0054] Here, a single crystal structure may mean a crystal structure having one crystal orientation and no crystal boundaries. A quasi-single crystal structure may mean a crystal structure determined to have one crystal orientation as a whole, but atoms are missing, or defects (such as twin boundaries) are locally located in a limited area. A quasi-single crystal structure may be referred to as a similar single crystal structure, etc. For example, by metal-induced crystallization, the channel region 140a may have a single crystal or quasi-single crystal structure.

[0055] In an embodiment, the polycrystalline region 140b and the channel region 140a may be formed by forming a first region (refer to Figure 5A 140g in, the same below) and the second zone (refer to Figure 5A 140h in the preliminary semiconductor layer (refer to Figure 5A In the crystallization process, the second region 140h is crystallized by a metal induced crystallization (MIC) process, such as a metal induced lateral crystallization (MILC) process, thereby forming a channel region 140a having a single crystal structure or a quasi-single crystal structure. In the crystallization process, the first region 140g is crystallized by a solid phase crystallization (SPC) process, thereby forming a polycrystalline region 140b having a polycrystalline structure.

[0056] In an embodiment, the first region 140g or the polycrystalline region 140b may have a shape or size that promotes solid phase crystallization, and the second region 140h or the channel region 140a may have a shape or size that promotes metal induced crystallization. In this way, by forming the first region 140g and the second region 140h in different shapes or sizes, the first region 140g and the second region 140h are crystallized in different ways during the crystallization process to form the polycrystalline region 140b and the channel region 140a having different shapes and different crystal structures.

[0057] In an embodiment, the first region 140g may have a shape substantially the same as that of the polycrystalline region 140b, and the second region 140h may have a shape substantially the same as that of the channel region 140a. Hereinafter, the description of the shape or size of the polycrystalline region 140b may be applied to the first region 140g, and the description of the shape or size of the channel region 140a may be applied to the second region 140h.

[0058] In an embodiment, the polycrystalline region 140b may at least partially fill the protruding portion CHP and may be additionally located in a portion of the inner portion CHI. When viewed from the extension direction of the channel structure CH (the Z-axis direction of the drawing), the channel region 140a may be located on the entire portion or a portion of the inner portion CHI. That is, in the extension direction of the channel structure CH, the channel region 140a may be located in a portion of the channel structure CH other than the portion where the polycrystalline region 140b and / or the channel pad 144 are located.

[0059] For example, the polycrystalline region 140b may at least partially fill the protruding portion CHP and may not be in the inner portion CHI. In this case, in the extension direction of the channel structure CH, the channel region 140a may be completely located in the inner portion CHI or completely located in the inner portion CHI except for the channel pad 144. As another example, the polycrystalline region 140b may be located in a portion of the inner portion CHI and in the protruding portion CHP. In this case, in the extension direction of the channel structure CH, except for the portion where the polycrystalline region 140b and / or the channel pad 144 are located, the channel region 140a may be partially located in the inner portion CHI.

[0060] The boundary portion 140i between the polycrystalline region 140b and the channel region 140a may be on the same plane as one surface 120p of the gate stack structure 120, or may be inside the gate stack structure 120. The height H1 of the polycrystalline region 140b in the extension direction of the channel structure CH (the Z-axis direction of the drawing) may be equal to or greater than the height H of the protruding portion CHP. In this case, the boundary portion 140i between the polycrystalline region 140b and the channel region 140a may be located at a portion where the bottom insulating layer 1321 is located. That is, the boundary portion 140i may be on the same plane as at least one of one surface and the other surface of the bottom insulating layer 1321, or may be between one surface and the other surface of the bottom insulating layer 1321.

[0061] For example, the boundary portion 140i between the polycrystalline region 140b and the channel region 140a may be inside the gate stack structure 120, and the height H1 of the polycrystalline region 140b may be greater than the height H of the protruding portion CHP. That is, the boundary portion 140i may be between one surface and the other surface of the bottom insulating layer 1321. Then, the polycrystalline region 140b may at least partially fill the protruding portion CHP.

[0062] In this case, the bottom surface of the gate dielectric layer 150 may be disposed on the same plane as one surface 120p of the gate stack structure 120. This is because the gate dielectric layer 150 is removed based on one surface 120p of the gate stack structure 120 during the manufacturing process. However, the embodiment is not limited thereto. The bottom surface of the gate dielectric layer 150 may be disposed higher or lower than one surface 120p of the gate stack structure 120. For example, when the boundary portion 140i is on the same plane as one surface 120p of the gate stack structure 120, the bottom surface of the gate dielectric layer 150 and the boundary portion 140i may be on the same plane (one surface 120p of the gate stack structure 120). As another example, when the boundary portion 140i is inside the gate stack structure 120, the boundary portion 140i may not be on the same plane as the bottom surface of the gate dielectric layer 150.

[0063] In an implementation, the poly region 140 b may at least partially fill the overhang portion CHP, and the channel region 140 a may be formed to fill a portion of an inner space defined by the gate dielectric layer 150 in the inner portion CHI.

[0064] In this case, when the polycrystalline region 140b completely fills the protruding portion CHP without any empty space or gap, the polycrystalline region 140b may be considered to fill the protruding portion CHP. When the polycrystalline region 140b is completely on the outer surface of the protruding portion CHP and on the boundary portion 140i, the polycrystalline region 140b may be considered to fill the protruding portion CHP. That is, when the polycrystalline region 140b is completely on the bottom surface 140t and the side surface 140s of the protruding portion CHP and completely fills the inner portion of the gate dielectric layer 150 at the boundary portion 140i in a plan view, the polycrystalline region 140b may be considered to fill the protruding portion CHP.

[0065] When the polycrystalline region 140 b is completely located at a portion where the boundary portion 140 i is located without the core insulating layer 142 in a plan view, it may be considered that the polycrystalline region 140 b may fill the protruding portion CHP.

[0066] Therefore, at least a portion of the polycrystalline region 140b may include a completely filled portion in which there is no empty space or core insulating layer 142 in a plan view. For example, the polycrystalline region 140b may have a plug shape, a plug shape, or a truncated cone shape in the end or protruding portion CHP of the channel structure CH. In this case, the lower surface (i.e., the bottom surface 140t) of the polycrystalline region 140b may have a smaller size than the upper surface of the polycrystalline region 140b, and the side surface 140s of the polycrystalline region 140b may have or include an inclined side surface. However, the embodiment is not limited thereto, and the shape of the polycrystalline region 140b may be any one of a variety of shapes.

[0067] For example, Figure 3 As shown, the polycrystalline region 140b can be formed while completely filling at least the protruding portion CHP. As a modified embodiment, Figure 4 As shown, the gap V may be inside the polycrystalline region 140b. Even in this case, the polycrystalline region 140b is completely formed on the outer surface of the protruding portion CHP and the boundary portion 140i, and the core insulating layer 142 is not provided therein. Therefore, the polycrystalline region 140b may fill the protruding portion CHP. For example, the gap V may have a shape extending in the extension direction of the channel structure CH (the Z-axis direction of the accompanying drawings) at the central region of the channel structure CH. This shape may be formed according to a manufacturing process. For example, the gap V is retained at a portion where the inner surface of the preliminary semiconductor layer 140p formed on the side surface of the penetration portion is not completely in contact, so that the gap V has the above-mentioned shape, and the penetration portion is provided for forming the channel structure CH. However, the embodiment is not limited thereto, and the shape, position, etc. of the gap V may be variously modified.

[0068] Refer again Figures 1 to 3 , the core insulating layer 142 may be inside the channel region 140a on the polycrystalline region 140b. Therefore, the channel region 140a may have a layered shape bordering or surrounding the outer surface of the core insulating layer 142 on the gate dielectric layer 150 formed on the side surface of the channel structure CH. When viewed in a plan view, the channel region 140a may be partially in the inner portion of the gate dielectric layer 150, and the empty space (the space where the core insulating layer 142 is located) may be located in the central region. For example, when the channel region 140a is viewed in a plan view, the channel region 140a may have a ring shape or an annular shape, and may have a shape extending longitudinally in the extension direction of the channel structure CH (Z-axis direction of the drawing). For example, the core insulating layer 142 has a cylindrical shape or a truncated cone shape, and the channel region 140a may have a shape extending along the outer surface of the core insulating layer 142 in the direction of the channel structure CH (Z-axis direction of the drawing). However, embodiments are not limited thereto, and the channel region 140 a may have any of various shapes.

[0069] In this case, the bottom surface of the core insulating layer 142 may be disposed on the same plane as the boundary portion 140i. This is because the core insulating layer 142 is inside the channel region 140a, and the core insulating layer 142 is not inside the polycrystalline region 140b. For example, the bottom surface of the core insulating layer 142 may be disposed on the same plane as the bottom surface of the gate dielectric layer 150, or may be inside the gate stack structure 120. For example, when the boundary portion 140i is on the same plane as one surface 120p of the gate stack structure 120, the bottom surface of the gate dielectric layer 150 and the bottom surface of the core insulating layer 142 may be on the same plane (one surface 120p of the gate stack structure 120). As another example, when the boundary portion 140i is inside the gate stack structure 120, the bottom surface of the core insulating layer 142 may be inside the gate stack structure 120, rather than at the bottom surface of the gate dielectric layer 150.

[0070] In an embodiment, the preliminary semiconductor layer 140p for forming the semiconductor layer 140 may be formed to have a layered shape by deposition or the like. In this case, the inner surfaces of the preliminary semiconductor layer 140p on the bottom surface 140t or the side surface 140s of the protruding portion CHP at the location where the protruding portion CHP is located may contact each other to form a first region 140g in the protruding portion CHP. Except for the first region 140g, the layered shape of the second region 140h may remain as it is. Therefore, the first region 140g or the polycrystalline region 140b may have a relatively large thickness, size, or volume to have a polycrystalline structure through solid phase crystallization. The second region 140h or the channel region 140a may have a relatively small thickness, size, or volume to have a single crystal or quasi-single crystal structure through metal induced crystallization.

[0071] As described above, when viewed in a plan view, at the protruding portion CHP, the polycrystalline region 140b may completely form the channel structure CH without the core insulating layer 142. For example, in the protruding portion CHP, the polycrystalline region 140b may form the protruding portion CHP without the gate dielectric layer 150. In the inner portion CHI, the polycrystalline region 140b may completely fill the inner space of the gate dielectric layer 150. When viewed in a plan view, the channel region 140a may be disposed in the inner space of the gate dielectric layer 150 together with the core insulating layer 142. That is, when viewed in a plan view, the channel region 140a may be partially formed in the inner space of the gate dielectric layer 150. Therefore, the polycrystalline region 140b may have a relatively large size, while the channel region 140a may have a relatively small size.

[0072] The thickness T of the channel region 140a in a direction intersecting the side surface of the channel structure CH (e.g., a direction perpendicular to the side surface of the channel structure CH) may be less than the height H1 of the polycrystalline region 140b in the extension direction of the channel structure CH (the Z-axis direction of the drawing). Here, the thickness T of the channel region 140a may mean the maximum thickness among the thicknesses of the channel region 140a. The diameter or width W of the polycrystalline region 140b in the bottom surface 140t may mean the minimum diameter or width among the diameters or widths passing through the center of the bottom surface 140t in a direction intersecting the extension direction of the channel structure CH (e.g., one direction in the XY plane of the drawing). The height H1 of the polycrystalline region 140b may mean the minimum distance among the distances between one surface and the other surface of the polycrystalline region 140b.

[0073] For example, the ratio of the diameter or width W of the bottom surface 140t of the polycrystalline region 140b or the protruding portion CHP to the thickness T of the channel region 140a may be 2 or less. Within this range, the polycrystalline region 140b may be arranged to at least partially fill the protruding portion CHP. For example, among the diameters or widths of the channel structure CH, the diameter or width W of the bottom surface 140t of the polycrystalline region 140b or the protruding portion CHP may have a minimum value. However, embodiments are not limited thereto. Therefore, the ratio of the diameter or width W of the bottom surface 140t of the polycrystalline region 140b or the protruding portion CHP to the thickness T of the channel region 140a may be greater than 2. In some embodiments, a portion having a diameter or width smaller than the diameter or width W of the bottom surface 140t of the polycrystalline region 140b or the protruding portion CHP may be provided in the channel structure CH.

[0074] The height H1 of the polycrystalline region 140b in the extension direction of the channel structure CH may be greater than the thickness T of the channel region 140a. In more detail, the ratio of the height H1 of the polycrystalline region 140b to the thickness T of the channel region 140a may be 2 or greater. This is because the inner surfaces of the preliminary semiconductor layer 140p at least partially fill the protruding portion CHP while in contact with each other. Within the above range, the height H1 of the polycrystalline region 140b has a size sufficient to at least partially fill the protruding portion CHP. For example, the ratio of the height H1 of the polycrystalline region 140b to the thickness T of the channel region 140a may be 2 to 10. Within the above range, the height H1 of the polycrystalline region 140b may have an appropriate height in consideration of the height H of the protruding portion CHP. However, the embodiment is not limited thereto, and the above ratio may have any one of various values.

[0075] The height H1 of the polycrystalline region 140b may be equal to or greater than the bottom surface 140t of the polycrystalline region 140b or the diameter or width W of the protruding portion CHP. For example, the ratio of the height H1 of the polycrystalline region 140b to the bottom surface 140t of the polycrystalline region 140b or the diameter or width W of the protruding portion CHP may be 1.5 or greater. This is because the inner surfaces of the preliminary semiconductor layer 140p contact each other to at least partially fill the protruding portion CHP. Within the above range, the height H1 of the polycrystalline region 140b has a size sufficient to at least partially fill the protruding portion CHP. For example, the ratio of the height H1 of the polycrystalline region 140b to the bottom surface 140t of the polycrystalline region 140b or the diameter or width W of the protruding portion CHP may be 1.5 to 3. Within the above range, the height H1 of the polycrystalline region 140b may have an appropriate height in consideration of the height H of the protruding portion CHP. However, the embodiment is not limited thereto, and the above ratio may have any one of various values.

[0076] In an embodiment, the channel region 140a may include a channel portion 140e and an interface portion 140f disposed between the channel portion 140e and the polycrystalline region 140b. When viewed in the extension direction of the channel structure CH (Z-axis direction of the drawing), the channel portion 140e of the channel region 140a may be disposed at a portion where the plurality of gate electrodes 130 are disposed. When viewed in the extension direction of the channel structure CH, the interface portion 140f of the channel region 140a may be disposed between the channel portion 140e and the polycrystalline region 140b, and the interface portion 140f of the channel region 140a may be at a portion where the plurality of gate electrodes 130 are not disposed. For example, when viewed from the extension direction of the channel structure CH, the interface portion 140f of the channel region 140a may be adjacent to the one surface 120p of the gate stack structure 120, and the interface portion 140f may be between an adjacent gate electrode adjacent to the one surface 120p of the gate stack structure 120 among the plurality of gate electrodes 130 and the horizontal conductive layer 110. For example, when viewed from the extension direction of the channel structure CH, the interface portion 140f may be at a portion of the bottom insulating layer 132l forming the one surface 120p of the gate stack structure 120 among the disposed unit insulating layers 132.

[0077] In this case, the channel portion 140e and the interface portion 140f may have the same crystal structure (e.g., a single crystal structure or a quasi-single crystal structure), but may include different materials. For example, the interface portion 140f may include a metal, and the polycrystalline region 140b or the channel portion 140e may not include a metal or may include a metal having a lower content than the interface portion 140f. In this case, the metal included in the interface portion 140f may be a crystallization inducing metal used in a metal induced crystallization process.

[0078] Since the channel portion 140e is at the portion where the gate electrode 130 is disposed and is directly related to the operation of the memory cell, the channel portion 140e may not include a metal or have a very low metal content in consideration of the performance of the memory cell. For this purpose, the process conditions in the metal-induced crystallization process may be adjusted so that the crystallization-inducing metal does not remain in the channel portion 140e or remains in the channel portion 140e at a low content. In some embodiments, a process of removing the crystallization-inducing metal remaining in the channel portion 140e or reducing the content of the crystallization-inducing metal remaining in the channel portion 140e may be additionally performed before or after the metal-induced crystallization process. For example, the channel portion 140e may not include a crystallization-inducing metal.

[0079] In an embodiment, the crystallization inducing metal may be provided from one surface 120p of the gate stack structure 120 and another surface 120q of the gate stack structure 120 opposite to the one surface 120p. That is, the crystallization inducing metal is provided from the other surface 120q and moves toward the one surface 120p of the gate stack structure 120 through the channel portion 140e, but cannot easily move to the polycrystalline region 140b. This is because the polycrystalline region 140b has a crystal structure (e.g., a polycrystalline structure), which makes it difficult for the crystallization inducing metal to migrate to the polycrystalline region 140b.

[0080] Therefore, the crystallization inducing metal may remain between the polycrystalline region 140b and the channel portion 140e, and an interface portion 140f including a metal (e.g., crystallization inducing metal) and a metal-semiconductor compound of a semiconductor material included in the channel region 140a may be formed in the corresponding portion. For example, the interface portion 140f may directly contact the polycrystalline region 140b.

[0081] In an embodiment, the height H2 of the interface portion 140f may be less than the height H1 of the polycrystalline region 140b in the extension direction of the channel structure CH. This is because the interface portion 140f is a portion formed by the remaining crystallization inducing metal and may have a relatively small thickness H2. For example, the height H2 of the interface portion 140f in the extension direction of the channel structure CH may be 10nm to 30nm. However, the embodiment is not limited thereto, and the height H2 of the interface portion 140f may have a different value.

[0082] In an embodiment, the channel portion 140e, the interface portion 140f, and the polycrystalline region 140b may include the same semiconductor material together. This is because the channel portion 140e, the interface portion 140f, and the polycrystalline region 140b are formed by the same preliminary semiconductor layer 140p. In this case, the channel portion 140e and the polycrystalline region 140b may be formed by the same semiconductor material. For example, the channel portion 140e and the polycrystalline region 140b may be formed by a semiconductor material (e.g., silicon). This is because the channel region 140a and the polycrystalline region 140b having different crystal structures are formed without a substantial material change from the preliminary semiconductor layer 140p formed by a semiconductor material (e.g., silicon). The interface portion 140f has the same crystal structure as the channel portion 140e, but is formed by a metal-semiconductor compound in which a crystallization-inducing metal is combined with a semiconductor material provided in the channel region 140a, which is a material different from the material of the channel portion 140e and / or the polycrystalline region 140b.

[0083] For example, the channel portion 140 e may include single crystal or quasi single crystal silicon, the interface portion 140 f may include single crystal or quasi single crystal metal silicide, and the polycrystalline region 140 b may include polycrystalline silicon.

[0084] In an embodiment, the crystallization inducing metal may include nickel (Ni), cobalt (Co), palladium (Pd), and / or copper (Cu), etc. The interface portion 140f may be made of nickel silicide (eg, NiSi 2 ), cobalt silicide, palladium silicide, copper silicide, etc. However, the embodiment is not limited thereto, and the crystallization inducing metal and / or material of the interface portion 140f may be variously changed.

[0085] As described, the polycrystalline region 140b including the polycrystalline semiconductor material but not including the crystallization inducing metal may be at the bottom of the channel structure CH or at the protruding portion CHP without the gate dielectric layer 150. In this case, when the gate dielectric layer 150 is etched, the polycrystalline region 140b is substantially not etched, so that the polycrystalline region 140b may be a kind of etching stop layer. The polycrystalline region 140b may also be referred to as an etching stop region, a stop region, etc. That is, the portion provided with the metal-semiconductor compound (e.g., the interface portion 140f) is not directly exposed to the outside through the polycrystalline region 140b. Therefore, defects that may occur when the metal-semiconductor compound is exposed to the protruding portion CHP can be prevented.

[0086] For reference, conventionally, since the polycrystalline region containing the polycrystalline semiconductor material is not provided in the protruding portion of the channel structure, a portion of the metal-semiconductor compound may be at the bottom surface of the protruding portion. In the process of removing the gate dielectric layer on the protruding portion, the metal-semiconductor compound exposed to the outside may be removed together. As a result, the core insulating layer is also exposed to the outside and may be removed together. Therefore, in the process of forming the horizontal conductive layer, the material forming the horizontal conductive layer may be disposed in the portion where the core insulating layer is removed. When such damage or defects in the core insulating layer occur, the performance of the semiconductor device may deteriorate. In an embodiment, by disposing the interface portion 140f including the metal-semiconductor compound inside the gate stack structure 120, the above problems can be fundamentally alleviated or prevented.

[0087] In addition, when the channel region 140a in the inner portion CHI where the plurality of gate electrodes 130 are provided has a single crystal structure or a quasi-single crystal structure, the resistance of the channel region 140a can be reduced. As a result, the cell current can be increased, and the performance of the semiconductor device 10 can be improved. In particular, when the number of gate electrodes 130 increases, the cell current can be effectively increased.

[0088] exist Figure 3 , it is shown that the boundary portion 140i of the channel region 140a and the polycrystalline region 140b and the boundary between the channel portion 140e and the interface portion 140f are clear. However, the embodiment is not limited to this. Therefore, the boundary portion 140i of the channel region 140a and the polycrystalline region 140b and the boundary between the channel portion 140e and the interface portion 140f may not be clearly divided. Even in this case, the polycrystalline region 140b having a polycrystalline semiconductor material can be distinguished from the channel region 140a, and the channel portion 140e and the interface portion 140f having different materials can be distinguished from each other.

[0089] In addition, in the above description and Figure 3 , a case where the boundary between the first region 140g and the second region 140h forms a boundary portion 140i between the polycrystalline region 140b and the channel region 140a is shown by way of example. That is, a portion having a plug shape, a plug shape, or a truncated cone shape forms the polycrystalline region 140b including a semiconductor material, and a portion having a layered shape can form the channel region 140a having a single crystal or quasi-single crystal structure.

[0090] However, the embodiment is not limited thereto. For example, the boundary portion 140i between the polycrystalline region 140b and the channel region 140a may be at a position different from the boundary between the first region 140g and the second region 140h. In this case, the polycrystalline region 140b including the semiconductor material may partially include a portion having a layered shape, and the channel region 140a having a single crystal or quasi-single crystal structure may partially include a portion having a plug shape, a plug shape, or a truncated cone shape.

[0091] For example, the channel pad 144 connected to the semiconductor layer 140 at the upper portion of the channel structure CH may be on the core insulating layer 142 and may be connected to the semiconductor layer 140. The channel pad 144 may be formed of a conductive material, such as a semiconductor layer doped with a p-type or n-type dopant. In an embodiment, the channel pad 144 may be formed of a polycrystalline semiconductor material (e.g., polysilicon) doped with a p-type or n-type dopant. Current may flow through the dopant-doped channel pad 144. However, the embodiment is not limited thereto, and the horizontal conductive layer 110 may be formed of any of a variety of materials.

[0092] As described above, when the channel pad 144 includes polysilicon, the grain size of the polycrystalline region 140b may be smaller than that of the channel pad 144. However, embodiments are not limited thereto, and the grain size of the polycrystalline region 140b may be equal to or larger than that of the channel pad 144.

[0093] In an embodiment, the gate stack structure 120 may include a plurality of gate stack structures 120a and 120b sequentially stacked on the horizontal conductive layer 110, and the channel structure CH may include a plurality of channel structures CH1 and CH2 extending into or penetrating the plurality of gate stack structures 120a and 120b. Then, because the number of stacked gate electrodes 130 can be increased, the number of memory cells can be increased in a stable structure. In the drawings, two gate stack structures 120 are shown, but the embodiment is not limited thereto. Therefore, the gate stack structure 120 may be formed of one gate stack structure, or may include three or more gate stack structures.

[0094] The plurality of channel structures CH1 and CH2 forming one channel structure CH may have a form in which they are connected to each other. Each of the plurality of channel structures CH1 and CH2 may have an inclined side surface, the width of which is narrower as it approaches the horizontal conductive layer 110 according to the aspect ratio on the cross section. Figure 2 As shown, due to the width difference in the portion where the first channel structure CH1 and the second channel structure CH2 are connected, a bent portion may be provided. As another example, the plurality of channel structures CH1 and CH2 may have continuously connected inclined side surfaces without a bent portion.

[0095] exist Figure 2 In the embodiment, the gate dielectric layer 150, the semiconductor layer 140 (e.g., the channel region 140a), and the core insulating layer 142 of the multiple channel structures CH1 and CH2 are shown by way of example to extend to each other, thereby forming an integral structure. However, the embodiment is not limited thereto, and the gate dielectric layer 150, the semiconductor layer 140, and the core insulating layer 142 of the multiple channel structures CH1 and CH2 may be formed separately from each other and may be electrically connected to each other. In addition, a separate channel pad may be additionally provided at the connection portion of the multiple channel structures CH1 and CH2. Therefore, the embodiment is not limited to the shape of the multiple channel structures CH1 and CH2.

[0096] In an embodiment, in a plan view, the gate stack structure 120 may be separated into a plurality of gate stack structures 120 by a separation structure 146. The separation structure 146 may extend in a crossing direction (e.g., a vertical direction) crossing the horizontal conductive layer 110, or in an extending direction (Z-axis direction of the drawing) of the channel structure CH to extend into or penetrate the gate stack structure 120. In addition, an upper separation region 148 may be formed adjacent to the circuit region 200 in the gate stack structure 120. In a plan view, a plurality of separation structures 146 and / or upper separation regions 148 may be provided, such that the separation structures 146 and / or upper separation regions 148 extend in a first direction (Y-axis direction of the drawing), and are spaced apart from each other at predetermined intervals in a second direction (X-axis direction of the drawing) crossing the first direction.

[0097] For example, the separation structure 146 may extend into or penetrate the gate stack structure 120 and extend to one surface 120p, and the upper separation region 148 may separate one or a portion of the plurality of gate electrodes 130 from each other. The upper separation region 148 may be disposed between the separation structures 146 .

[0098] For example, the separation structure 146 is shown by way of example to have an inclined side surface, and due to the high aspect ratio, the width of the inclined side surface gradually decreases in cross section toward the horizontal conductive layer 110 or one surface 120p of the gate stack structure 120, but the embodiment is not limited thereto. The side surface of the separation structure 146 may be perpendicular to the horizontal conductive layer 110, or may have a curved portion at a connection portion of the plurality of gate stack structures 120a and 120b.

[0099] The separation structure 146 or the upper separation region 148 may be at least partially filled with any of a variety of insulating materials. For example, the separation structure 146 or the upper separation region 148 may include an insulating material such as silicon oxide, silicon nitride and / or silicon oxynitride. As another example, the separation structure 146 may further include a semiconductor material, a metal material, etc. In this case, the separation structure 146 may include a spacer layer including an insulating material and a portion formed on the spacer layer and including a semiconductor material, a metal material, etc. However, the embodiment is not limited thereto, and the structure, shape, and material of the separation structure 146 or the upper separation region 148 may be variously modified.

[0100] The connection region 104 and the second wiring portion 180 may be provided to connect the gate stack structure 120 and / or the channel structure CH provided in the cell array region 102 to the circuit region 200 or an external circuit. In addition, the second bonding structure 192 and the second insulating layer 190 may be at a surface of the second wiring portion 180 facing the circuit region 200.

[0101] Here, the second wiring portion 180 may include a member that electrically connects the gate electrode 130, the channel structure CH, etc. to the circuit area 200 or an external circuit. For example, the second wiring portion 180 may include a bit line 182, a gate contact portion 184, a source contact portion 186, an input / output connection line 188, and a contact path 180a connected to each of them. In addition, the second wiring portion 180 may further include an input / output pad 198. Depending on the embodiment, the second wiring portion 180 may further include a connection line 190a connected to the bit line 182, the gate contact portion 184, and / or the input / output connection line 188.

[0102] The bit line 182 may be disposed on the cell insulating layer 132 of the gate stack structure 120 formed in the cell array region 102. The bit line 182 may extend in a second direction (the X-axis direction of the drawing) that intersects the first direction (the Y-axis direction of the drawing) in which the gate electrode 130 extends. The bit line 182 may be electrically connected to the channel structure CH (e.g., the channel pad 144) through a contact path 180a (e.g., a bit line contact path).

[0103] The connection region 104 may be disposed around the cell array region 102 , and a portion of the second wiring portion 180 may be disposed therein.

[0104] The connection region 104 may include a member for connecting the gate electrode 130 and the circuit region 200. In an embodiment, the gate electrodes 130 and the interlayer insulating layer 132m of the plurality of gate stack structures 120 may extend in a first direction (the Y-axis direction of the drawing) in the connection region 104. For example, the lengths of the plurality of gate electrodes 130 in a direction away from the cell array region 102 may sequentially extend toward the horizontal conductive layer 110, thereby forming a stepped shape. In this case, the plurality of gate electrodes 130 may have a stepped shape in one direction or in multiple directions.

[0105] In the drawings, the gate contact portion 184 is shown between the gate electrode 130 and the connection line 190a to connect the gate electrode 130 and the connection line 190a. However, the embodiment is not limited thereto, and the gate contact portion 184 may be formed by extending into or penetrating a plurality of gate electrodes 130. In this case, each gate contact portion 184 is electrically connected to one connection gate electrode and may be separated from other connection gate electrodes by an insulating pattern.

[0106] In addition, source contact portion 186, input / output pad 198, and input / output connection line 188 may be in connection area 104. For example, source contact portion 186 may penetrate cell insulating layer 132 and thus may be electrically connected to horizontal conductive layer 110. For example, input / output connection line 188 may be connected to at least one of input / output pad 198 and second bonding structure 192. Input / output pad 198 may be disposed on, for example, insulating layer 198b at least partially covering at least the outer surface of horizontal conductive layer 110. Depending on the implementation, a separate input / output pad electrically connected to circuit area 200 may be provided. In Figure 1 In the figure, it is shown by way of example that the insulating layer 198b is arranged between the input / output connection line 188 and the horizontal conductive layer 110, so that the input / output connection line 188 and the horizontal conductive layer 110 are not electrically connected. For example, the penetration portion of the insulating layer 198b can be arranged to extend into or penetrate the horizontal conductive layer 110, and the input / output connection line 188 can be located inside the penetration portion of the insulating layer 198b. However, the embodiment is not limited to this. The insulating layer 198b that at least partially covers the outer surface of the horizontal conductive layer 110 and the penetration portion that extends into or penetrates the horizontal conductive layer 110 can be formed by different processes or can include different materials. In some embodiments, the horizontal conductive layer 110 may not be formed in the portion where the input / output connection line 188 is arranged. According to different embodiments, many other changes are possible.

[0107] The gate contact portion 184, the source contact portion 186, or the input / output connection line 188 may include a conductive material, for example, may include tungsten (W), copper (Cu), aluminum (Al), etc., and may further include a diffusion barrier layer. However, the embodiment is not limited to the material of the gate contact portion 184, the source contact portion 186, or the input / output connection line 188. Figure 1 In the figure, it is shown by way of example that the gate contact portion 184 and the source contact portion 186 have inclined side surfaces, in each of which the width gradually narrows as it becomes closer to the horizontal conductive layer 110, and the input / output connection line 188 has an inclined side surface, and its width becomes wider as it becomes closer to the horizontal conductive layer 110. However, the embodiment is not limited to this. For example, the gate contact portion 184, the source contact portion 186 and / or the input / output connection line 188 may have a vertical side surface or may have an inclined side surface different from the above-mentioned inclined side surface. Figure 1 In the embodiment, it is shown by way of example that the gate contact portion 184 and the source contact portion 186 are provided with a curved portion at the boundary portion of the plurality of gate stack structures 120a and 120b. However, the embodiment is not limited to this. It is also possible that the gate contact portion 184 or the source contact portion 186 does not have a curved portion at the boundary between the plurality of gate stack structures 120a and 120b. According to different embodiments, many other changes are possible.

[0108] One surface of the circuit region 200 adjacent to the cell region 100 is a bonding surface with the cell region 100, and is formed by a first bonding structure 240 and a first insulating layer 250 disposed at the periphery of the first bonding structure 240. One side of the cell region 100 adjacent to the circuit region 200 is a bonding surface with the circuit region 200, and is formed by a second bonding structure 192 and a second insulating layer 190 disposed at the periphery of the second bonding structure 192. The first bonding structure 240 may be disposed on the first wiring portion 230 and electrically connected to the first wiring portion 230, and the second bonding structure 192 may be disposed on the second wiring portion 180 and electrically connected to the second wiring portion 180.

[0109] One surface of the cell region 100 and one surface of the circuit region 200 may be bonded to each other by hybrid bonding. In more detail, the first bonding structure 240 of the circuit region 200 and the second bonding structure 192 of the cell region 100 are in direct contact and bonded to each other to form a metal bond. In addition, the first insulating layer 250 at one surface of the circuit region 200 and the second insulating layer 190 at one surface of the cell region 100 are in direct contact and bonded to form an insulating layer bond at the periphery of the first bonding structure 240 and the second bonding structure 192.

[0110] For example, the first bonding structure 240 and / or the second bonding structure 192 may be formed of copper, aluminum, tungsten, nickel, gold, tin, manganese, cobalt, titanium, tantalum, ruthenium or an alloy containing them. For example, the first bonding structure 240 and / or the second bonding structure 192 include copper at least in the bonding surface, and the metal bonding of the circuit area 200 and the cell area 100 may be copper to copper (Cu to Cu) bonding. In an embodiment, the first insulating layer 250 and the second insulating layer 190 may include the same insulating material in the bonding surface. For example, the first insulating layer 250 and / or the second insulating layer 190 may have a layer including silicon carbon nitride (SiCN) at least on the bonding surface. However, the embodiment is not limited to the materials of the first bonding structure 240, the second bonding structure 192, the first insulating layer 250 and the second insulating layer 190.

[0111] As described, the first bonding structure 240 of the circuit region 200 and the second bonding structure 192 of the cell region 100 may be bonded to provide an electrical connection path between the circuit region 200 and the cell region 100. For example, the bit line 182 connected to the channel structure CH and the gate electrode 130 may be electrically connected to the circuit element 220 of the circuit region 200 through the second wiring portion 180 and the first wiring portion 230.

[0112] According to this embodiment, the semiconductor layer 140 including the polycrystalline region 140b having a polycrystalline semiconductor material can reduce or prevent damage or defects of the channel structure CH. In addition, the cell current can be increased by including the semiconductor layer 140 having the channel region 140a having a crystal structure different from the crystal structure of the polycrystalline region 140b. Therefore, the reliability and performance of the semiconductor device 10 can be improved.

[0113] Will refer to FIG. 5A to FIG. 5H as well as Figures 1 to 3 An example of a method of manufacturing the semiconductor device 10 is described in detail. To the extent an element is not described in detail below, it is understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure. Portions not described in the above description will be described in detail.

[0114] FIG. 5A to FIG. 5H is a partial cross-sectional view of a semiconductor manufacturing method according to some embodiments. FIG. 5A to FIG. 5H , a portion of the cell array region 102 and a portion of the circuit region 200 corresponding to the portion are shown. Hereinafter, a method for manufacturing the semiconductor device 10 will be mainly described, focusing on the horizontal conductive layer 110, the gate stack structure 120, the channel structure CH and the separation structure 146 formed in the cell region 100.

[0115] like Figure 5AAs shown, a stack structure 120s is formed on a semiconductor substrate 110s, and a preliminary channel structure CS extending into or penetrating the stack structure 120s may be formed.

[0116] The semiconductor substrate 110s may be a semiconductor substrate including a semiconductor material. For example, the semiconductor substrate 110s may be a semiconductor substrate formed of a semiconductor material, and may be a semiconductor substrate in which a semiconductor layer is formed on a base substrate. For example, the semiconductor substrate 110s may be formed of single crystal silicon or polycrystalline silicon, epitaxial silicon, germanium, or silicon germanium, silicon on insulator, and / or germanium on insulator.

[0117] The stack structure 120s may be formed by alternately stacking a plurality of sacrificial insulating layers 130s and a plurality of unit insulating layers 132 on the semiconductor substrate 110s. The unit insulating layer 132 may include a bottom insulating layer 1321, an interlayer insulating layer 132m, upper insulating layers 132a and 132b, etc. Here, the sacrificial insulating layer 130s may be a gate electrode (see FIG. 1 ) formed by a subsequent process. Figure 5D Thus, the sacrificial insulating layer 130s may be formed to correspond to a portion where the gate electrode 130 is to be formed.

[0118] The sacrificial insulating layer 130s may be formed of a material different from that of the cell insulating layer 132. For example, the cell insulating layer 132 includes silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material, etc., and the sacrificial insulating layer 130s includes silicon, silicon oxide, silicon carbide, and / or silicon nitride, etc., and may be formed of a material different from that of the cell insulating layer 132.

[0119] Subsequently, a penetration portion extending into or penetrating the stacked structure 120s may be formed to correspond to a channel structure to be formed thereat (see Figure 5D In the case of the first barrier layer (refer to CH in the gate dielectric layer 150, the same below), the preliminary channel structure CS may be formed in the penetration portion. That is, the gate dielectric layer 150, the preliminary semiconductor layer 140p, and the core insulating layer 142 may be sequentially formed to at least partially fill the penetration portion. Figure 2 156a, the same below) may not be formed, but may be formed later in another process. The preliminary channel structure CS may be in a state without a channel pad (refer to Figure 5D 144) status.

[0120] In this case, the bottom surface of the preliminary channel structure CS may be disposed within the semiconductor substrate 110s. In the preliminary channel structure CS, a portion protruding from one surface 120p of the stacked structure 120s may be a portion that will later form a protruding portion CHP of the channel structure CH. Accordingly, the protruding portion CHP of the channel structure CH may be stably formed, and a horizontal conductive layer (refer to FIG. 1 ) to be formed later may be formed. Figure 5E 110, the same below) can be stably connected to the protruding portion CHP. In other words, the process margin can be ensured.

[0121] In an embodiment, the stack structure 120s may include a plurality of stack structures 120d and 120e sequentially stacked on the semiconductor substrate 110s, and the preliminary channel structure CS may include a plurality of preliminary channel structures CS1 and CS2 extending into or penetrating the plurality of stack structures 120d and 120e. However, embodiments are not limited thereto.

[0122] In an embodiment, the preliminary semiconductor layer 140p may be formed of an amorphous semiconductor layer having an amorphous structure. For example, the preliminary semiconductor layer 140p may be formed of an amorphous silicon layer. Accordingly, the preliminary semiconductor layer 140p may be easily formed through a process such as deposition.

[0123] Here, the preliminary semiconductor layer 140p may include a first region 140g at least partially filling the protruding portion CHP and a second region 140h located inside (refer to Figure 2 The description of the polycrystalline region 140b may be applied as is to the shape and size of the first region 140g. The description of the channel region 140a may be applied as is to the shape and size of the second region 140h. For example, the first region 140g may have a plug shape, a plug shape, or a truncated cone shape that at least partially fills the end or protruding portion CHP of the preliminary channel structure CS. The second region 140h may have a layered shape that borders or surrounds the outer surface of the core insulating layer 142 and is formed on the gate dielectric layer 150 on the side surface of the preliminary channel structure CS.

[0124] The first region 140g is to be formed into a polycrystalline region after the crystallization process (refer to Figure 5C The second region 140h is a portion where a channel region is to be formed after the crystallization process (refer to Figure 5C 140a) in the section.

[0125] In an embodiment, the first region 140g and the second region 140h having the above-mentioned shapes may be formed by adjusting the size of the channel structure CH or the penetration portion, the thickness of the preliminary semiconductor layer 140p, etc. For example, the diameter or width of the channel structure CH or the penetration portion, the bottom surface of the preliminary semiconductor layer 140p at the protruding portion CHP (refer to Figure 3 The diameter or width of the preliminary semiconductor layer 140t), the height of the protruding portion CHP, the thickness of the preliminary semiconductor layer 140p, etc., are such that the inner surfaces of the preliminary semiconductor layer 140p contact each other in the protruding portion CHP, while the inner surfaces of the preliminary semiconductor layer 140p do not contact each other in the inner portion CHI.

[0126] In an embodiment, the preliminary semiconductor layer 140p is formed after the gate dielectric layer 150 is formed, and therefore, a process of removing the gate dielectric layer 150 formed on the preliminary semiconductor layer 140p (eg, the first region 140g) may not be necessary. Therefore, even in the case of a large number of gate electrodes 130, it can be generally easily applied.

[0127] Then, if Figure 5B As shown, a metal layer 140m may be formed on the upper surface of the preliminary channel structure CS or the other surface 120q of the stacked structure 120s. Here, the metal layer 140m may be a metal layer including a crystallization inducing metal, or, for example, may be a single metal layer including a single crystallization inducing metal. In an embodiment, the metal layer 140m may include nickel, cobalt, palladium, copper, etc. The metal layer 140m may be formed by any of a variety of methods, and may be formed by, for example, deposition, etc.

[0128] However, the embodiment is not limited thereto. Therefore, the metal layer 140m may include a material other than metal, and the metal layer 140m may be formed by a process other than deposition.

[0129] Then, if Figure 5C As shown, the preliminary semiconductor layer (see Figure 5B 140p in the figure, the same below) is crystallized by a heat treatment process to form a semiconductor layer 140 having a channel region 140a and a polycrystalline region 140b.

[0130] In an embodiment, a heat treatment process is performed to form a metal layer (refer to Figure 5B 140m in, the same below) may be a metal-semiconductor compound of a metal contained in the metal layer 140m, and a process of removing the metal layer 140m may be performed, and then a heat treatment process for crystallization may be performed.

[0131] In this case, the heat treatment process for forming the metal-semiconductor compound may be performed at a lower temperature (e.g., less than 500 degrees Celsius, e.g., 300 degrees Celsius to 400 degrees Celsius) than the heat treatment process for crystallization. In the annealing process, the crystallization inducing metal included in the metal layer 140m diffuses into the second region 140h and may be chemically combined with the semiconductor material provided in the second region 140h. Therefore, a compound portion including a metal-semiconductor compound (e.g., metal silicide) in which the crystallization inducing metal and the semiconductor material (e.g., silicon) are chemically bonded may be formed in the second region 140h. For example, the compound portion may be formed in a portion of the second region 140h (e.g., an upper portion of the second region 140h).

[0132] The process of removing the metal layer 140m may be performed by any one of various processes (eg, an etching process, etc.) that may remove the metal layer 140m.

[0133] The heat treatment process for crystallization may be performed at a higher heat treatment temperature (e.g., 500 degrees Celsius or higher, in more detail, 500 degrees Celsius to 700 degrees Celsius) than the heat treatment process for forming the metal-semiconductor compound. In this case, the heat treatment process for crystallization may be performed at a heat treatment temperature at which both solid phase crystallization and metal induced crystallization are possible. That is, the polycrystalline region 140b and the channel region 140a having different crystal structures may be formed in one process.

[0134] In this case, the first region 140g having a relatively large size or thickness may be crystallized by a solid phase crystallization process to form a polycrystalline region 140b having a polycrystalline structure. The second region 140h having a relatively small size or thickness may be crystallized by a metal induced crystallization process to form a channel region 140a having a single crystal structure or a quasi-single crystal structure. In this case, the crystallization inducing metal does not move to the polycrystalline region 140b, but remains in a portion adjacent to the polycrystalline region 140b. Therefore, an interface portion 140f may be formed adjacent to the polycrystalline region 140b. The interface portion 140f may include a metal-semiconductor compound in which the semiconductor material included in the preliminary semiconductor layer 140p or the semiconductor layer 140 and the crystallization inducing metal are chemically bonded to each other.

[0135] Thus, the semiconductor layer 140 including the channel region 140 a having the channel portion 140 e and the interface portion 140 f and the polycrystalline region 140 b may be formed.

[0136] However, the above crystallization process is given as an example, but the embodiment is not limited thereto. For example, the process of removing the metal layer 140m may be performed after the metal induced crystallization process, or the heat treatment process (e.g., annealing process) for forming the metal-semiconductor compound and the metal induced crystallization process may be performed as a continuous process or the same process. Many other variations are possible.

[0137] As in the above-described embodiment, a heat treatment process for crystallization may be performed before forming the channel pad 144. The heat treatment process is included in the process of forming the channel pad 144. If the preliminary semiconductor layer 140p is crystallized by the heat treatment process performed in the process of forming the channel pad 144, it may be difficult to form the semiconductor layer 140 having desired characteristics. However, the embodiment is not limited thereto.

[0138] Then, if Figure 5D As shown, the channel structure CH can be formed by forming a channel pad 144 connected to the semiconductor layer 140. In addition, the sacrificial insulating layer (refer to Figure 5C 130s in the figure, the same below) can be replaced by the gate electrode 130, and a separation structure 146 can be formed.

[0139] First, an opening through the stacked structure 120s may be formed in a region corresponding to the separation structure 146. The sacrificial insulating layer 130s may be selectively removed by an etching process (e.g., a wet etching process) with the aid of the opening. In addition, the gate electrode 130 may be formed by at least partially filling a conductive material in a portion from which the sacrificial insulating layer 130s is removed. As a result, the region where the sacrificial insulating layer 130s is provided may be replaced by the gate electrode 130. In this case, before at least partially filling a process for forming the conductive material for forming the gate electrode 130, a process for forming the first barrier layer 156a may be further performed. Subsequently, an insulating material or the like may be at least partially filled in the opening to form the separation structure 146.

[0140] According to this embodiment, an upper separation region (refer to Figure 1 The upper separation region 148 may be formed by forming an upper separation opening by an etching process using a mask layer and depositing an insulating material in the upper separation opening. The process of forming the upper separation region 148 may be performed before or after the metal induced crystallization process, before or after the process of forming the opening or separation structure 146, etc. That is, the order of the process of forming the upper separation region 148 is not limited. In some embodiments, the upper separation region 148 may not be formed.

[0141] Then, a second wiring portion 180 connected to the channel structure CH, a second bonding structure 192, a second insulating layer 190, etc. may be formed to form a preliminary cell region 100a. The preliminary cell region 100a may mean a cell region before formation of the horizontal conductive layer 110 is completed.

[0142] Then, if Figure 5E As shown, the preliminary unit region 100a may be bonded to the circuit region 200. For example, the upper surface ( Figure 5D The upper surface of Figure 5E The bottom surface in the circuit region 200 may be bonded to the circuit region 200 .

[0143] In the bonding process between the circuit region 200 and the preliminary cell region 100a, the preliminary cell region 100a may be bonded on the circuit region 200 in a vertically inverted state. The circuit region 200 and the preliminary cell region 100a are bonded by hybrid bonding including metal bonding of the first bonding structure 240 and the second bonding structure 192 and insulating layer bonding of the first insulating layer 250 and the second insulating layer 190. For example, the hybrid bonding may be performed by performing an annealing process while the circuit region 200 and the preliminary cell region 100a are in contact with each other.

[0144] Then, if Fig. 5F As shown, the semiconductor substrate can be removed (see Figure 5E As a process for removing the semiconductor substrate 110s, at least one of an etching process (a wet etching process, a dry etching process, etc.), a chemical mechanical polishing process, and a stripping process may be applied.

[0145] For example, the semiconductor substrate 110s may be removed by performing a wet etching process using an etching material that can etch the semiconductor substrate 110s after performing a chemical mechanical polishing process. The etching material of the semiconductor substrate 110s may be a material having an etching selectivity relative to the cell insulating layer 132 (e.g., the bottom insulating layer 1321), the gate dielectric layer 150, etc., so that the etching material is not as effective when etching the cell insulating layer 132, the gate dielectric layer 150, etc. as when etching the semiconductor substrate 110s, or the etching material may be a material having a low etching rate for the cell insulating layer 132 (e.g., the bottom insulating layer 1321), the gate dielectric layer 150, etc.

[0146] Then, if Figure 5G As shown, the gate dielectric layer 150 disposed on the protruding portion CHP of the channel structure CH may be removed. The process of removing the gate dielectric layer 150 may be performed by an etching process using an etching material capable of etching the gate dielectric layer 150, such as a wet etching process.

[0147] In this case, the etching material for etching the gate dielectric layer 150 may be a material having an etching selectivity relative to a polycrystalline semiconductor material (e.g., polycrystalline silicon), so that the etching material is not as effective in etching the polycrystalline semiconductor material as in etching the gate dielectric layer 150, or the etching material is a material in which the etching speed for the polycrystalline semiconductor material (e.g., polycrystalline silicon) is relatively low. For example, the etching material of the gate dielectric layer 150 may be a fluorine-based material, but the embodiment is not limited thereto.

[0148] In this embodiment, the polycrystalline region 140b including a polycrystalline semiconductor material (e.g., polysilicon) is disposed at the lower portion of the gate dielectric layer 150 at the protruding portion CHP of the channel structure CH. Therefore, in the process of removing the gate dielectric layer 150, the gate dielectric layer 150 may be selectively removed without damaging or etching the polycrystalline region 140b.

[0149] That is, the polycrystalline region 140b can protect the channel structure CH during the process of removing the gate dielectric layer 150. For example, the polycrystalline region 140b can inhibit or prevent the etching material from removing the insulating material included in the gate dielectric layer 150 and reaching the core insulating layer 142 formed of the insulating material. Therefore, during the process of removing the gate dielectric layer 150, damage or removal of the core insulating layer 142 can be reduced or prevented.

[0150] For reference, conventionally, the portion containing metal silicide is located at the protruding portion of the channel structure. Accordingly, in the process of removing the gate dielectric layer, the portion containing metal silicide is removed, the core insulating layer is exposed, and a defect that the core insulating layer is also removed may occur. When such a defect occurs, the performance and reliability of the semiconductor device may deteriorate.

[0151] Then, if Figure 5H As shown, the horizontal conductive layer 110 may be formed to at least partially cover the protruding portions CHP of the plurality of channel structures CH and one surface 120 p of the gate stack structure 120 exposed between the protruding portions CHP.

[0152] The process of forming the horizontal conductive layer 110 may be performed using a deposition method or the like. For deposition, chemical vapor deposition, atomic layer deposition, etc. may be used. However, the embodiment is not limited thereto, and the horizontal conductive layer 110 may be formed by any of various processes. For example, after forming an amorphous silicon layer including a dopant, a heat treatment process for crystallization and / or activation may be performed to form the horizontal conductive layer 110. However, the embodiment is not limited thereto.

[0153] After forming the horizontal conductive layer 110 , a process of forming an insulating layer 198 b on an outer surface of the horizontal conductive layer 110 may be further performed.

[0154] According to this embodiment, in the heat treatment process for crystallization, the first region 140g of the preliminary semiconductor layer 140p is crystallized into a polycrystalline region 140b having a polycrystalline structure, and the second region 140h of the preliminary semiconductor layer 140p is crystallized into a channel region 140a having a single crystal structure or a quasi-single crystal structure. That is, by utilizing the shape difference between the first region 140g and the second region 140h, a polycrystalline region 140b and a channel region 140a having different crystal structures can be formed in the same heat treatment process. Therefore, the channel region 140a has a single crystal structure or a quasi-single crystal structure, and the polycrystalline region 140b may not include a metal or a metal-semiconductor compound. The polycrystalline region 140b can reduce or prevent the semiconductor layer 140 and / or the core insulating layer 142 from being undesirably damaged or removed at the protruding portion CHP of the channel structure CH. That is, a semiconductor device 10 having improved reliability and performance can be formed by a process of reasonable complexity.

[0155] An example of an electronic system including the above-described semiconductor device will be described in detail.

[0156] Figure 6 An electronic system including a semiconductor device according to some embodiments is schematically illustrated.

[0157] Reference Figure 6 , an electronic system 1000 according to an embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including the storage device. For example, the electronic system 1000 may be a solid state drive (SSD) device, a medical device, or a communication device including one or more semiconductor devices 1100.

[0158] The semiconductor device 1100 may be a nonvolatile memory device, for example, a reference Figures 1 to 4 and FIG. 5A to FIG. 5H The NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an embodiment, the first structure 1100F may be disposed adjacent to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0159] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be variously modified according to the embodiment.

[0160] In an embodiment, the lower transistors LT1 and LT2 may include ground selection transistors, and the upper transistors UT1 and UT2 may include string selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the first gate upper line UL1 and the second gate upper line UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0161] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0162] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may control the operation of at least one memory cell among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0163] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . Depending on the implementation, the electronic system 1000 may include a plurality of semiconductor devices 1100 , in which case the controller 1200 may control the plurality of semiconductor devices 1100 .

[0164] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to the execution of a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be recorded in the memory cell transistor MCT of the semiconductor device 1100, data to be read from the semiconductor device 1100, etc. may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0165] Figure 7 An electronic system including a semiconductor device according to some embodiments is schematically illustrated.

[0166] Reference Figure 7 , an electronic system 2000 according to an embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through a wiring pattern 2005 formed in the main substrate 2001.

[0167] The main substrate 2001 may include a connector 2006, which includes a plurality of pins combined with an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the electronic system 2000 and the external host. In an embodiment, the electronic system 2000 may communicate with an external host through one of the interfaces such as a universal serial bus (USB), a fast peripheral component interface (PCI-express), a serial advanced technology attachment (ADTA), and / or M-Phy (UFS) for universal flash memory. In an embodiment, the electronic system 2000 may be operated by power provided from an external host through the connector 2006. The electronic system 2000 may further include a power management integrated circuit (PMIC) that distributes the power provided from the external host to the controller 2002 and the semiconductor package 2003.

[0168] The controller 2002 may record data to or read data from the semiconductor package 2003 , and may improve the operation speed of the electronic system 2000 .

[0169] The DRAM 2004 may be a buffer memory for alleviating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the electronic system 2000 may operate as one of the high-speed cache memories and may provide a space for temporarily storing data in a control operation of the semiconductor package 2003. When the DRAM 2004 is included in the electronic system 2000, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0170] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may be respective semiconductor packages including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the bottom surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a mold layer 2500 at least partially covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0171] The package substrate 2100 may be a printed circuit board including the package upper pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Figure 6 Each semiconductor chip 2200 may include a gate stack structure 4210 and a channel structure 4220. The semiconductor chip 2200 may include a reference Figures 1 to 4 and FIG. 5A to FIG. 5H A semiconductor device is described.

[0172] In an embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pad 2210 and the on-package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the on-package pad 2130 of the package substrate 2100. Depending on the embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 are electrically connected to each other by a connection structure including a through electrode (through silicon via, TSV) instead of a bonding wire type connection structure 2400.

[0173] In an embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 are mounted on a separate interposer substrate different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through wires formed in the interposer substrate.

[0174] Figure 8 is a schematic cross-sectional view of a semiconductor package according to an embodiment. Figure 8 An embodiment of a semiconductor package 2003 is shown, and a schematic diagram conceptually illustrates the Figure 7 The semiconductor package 2003 is cut along the line II'.

[0175] Reference Figure 8 In the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate main body 2120, an upper pad 2130 disposed on the upper surface of the package substrate main body 2120, a lower pad 2125 disposed on the bottom surface of the package substrate main body 2120 or exposed through the bottom surface, and an internal wire 2135 in the package substrate main body 2120 electrically connecting the upper pad 2130 and the lower pad 2125. The upper pad 2130 may be electrically connected to the connection structure 2400. The lower pad 2125 may be connected to the conductive connection portion 2800 as shown in FIG. Figure 7 The electronic system 2000 is shown with a wiring pattern 2005 on a main substrate 2001 .

[0176] In the semiconductor package 2003 , each semiconductor chip 2200 may include a semiconductor substrate 4010 , a first structure 4100 on the semiconductor substrate 4010 , and a second structure 4200 bonded to the first structure 4100 by a wafer bonding method.

[0177] The first structure 4100 may include a peripheral circuit region including a peripheral conductive line 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a channel structure 4220 and a separation structure 4230 extending into or penetrating the gate stack structure 4210, and a word line (see FIG. 4 ) connected to the channel structure 4220 and the gate stack structure 4210. Figure 6The second bonding structure 4250 may be electrically connected to the channel structure 4220 and the word line WL through a bit line 4240 electrically connected to the channel structure 4220 and a gate connection line electrically connected to the word line WL. The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be bonded to each other while in contact with each other. The bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be formed of, for example, copper (Cu).

[0178] In the semiconductor chip 2200 or the semiconductor device according to the embodiment, the semiconductor layer including the polycrystalline region can reduce or prevent damage or defects of the channel structure, and the semiconductor layer including the channel region can increase the cell current. Therefore, the reliability and performance of the semiconductor chip 2200 or the semiconductor device can be improved.

[0179] Each semiconductor chip 2200 may further include an input / output pad 2210 and an input / output connection line 4265 under the input / output pad 2210. The input / output connection line 4265 may be electrically connected to a portion of the second bonding structure 4250.

[0180] In an implementation, the plurality of semiconductor chips 2200 in the semiconductor package 2003 may be electrically connected to each other through a connection structure 2400 in the form of bonding wires. As another example, the plurality of semiconductor chips 2200 or a plurality of parts forming the same may be electrically connected through a connection structure including through electrodes.

[0181] The embodiments have been described in detail above, but the scope of the present disclosure is not limited thereto. Many variations and improvements made by ordinary technicians in the art using the basic concepts of the present disclosure as defined in the appended claims may also fall within the scope of the present disclosure.

[0182] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0085944 filed in the Korean Intellectual Property Office on July 3, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: A gate stack structure, comprising a plurality of gate electrodes and a plurality of insulating layers stacked alternately; a channel structure including an inner portion extending into the gate stack structure and a protruding portion protruding from one surface of the gate stack structure; as well as a horizontal conductive layer connected to the protruding portion of the channel structure, The channel structure includes a semiconductor layer, the semiconductor layer includes a polycrystalline region and a channel region, the polycrystalline region is at least in the protruding portion and includes a polycrystalline semiconductor material, the channel region is located in the inner portion and has a crystal structure different from that of the polycrystalline region. 2 . The semiconductor device according to claim 1 , wherein the channel region has a single crystal structure or a quasi-single crystal structure.

3. The semiconductor device according to claim 1, wherein the channel region includes a channel portion and an interface portion between the channel portion and the polycrystalline region, and The channel portion and the interface portion include different materials.

4. The semiconductor device according to claim 3, wherein the interface portion comprises metal, wherein the channel portion does not contain the metal or includes a lower content of the metal than the interface portion, and The polycrystalline region does not contain the metal or contains a lower content of the metal than the interface portion.

5. The semiconductor device according to claim 3, wherein the channel portion comprises the same material as the polycrystalline region, and The interface portion includes a metal-semiconductor compound including a metal and the polycrystalline semiconductor material contained in the channel portion.

6. The semiconductor device according to claim 3, further comprising: a bottom insulating layer between a gate electrode adjacent to the one surface of the gate stack structure among the plurality of gate electrodes and the horizontal conductive layer, and The interface portion is located at a position where the bottom insulating layer is located in an extending direction of the channel structure.

7. The semiconductor device according to claim 1, wherein the channel region includes a channel portion and an interface portion between the channel portion and the polycrystalline region, wherein the polycrystalline region comprises polycrystalline silicon, wherein the channel portion comprises single crystal or quasi-single crystal silicon, and The interface portion includes single crystal or quasi-single crystal metal silicide. 8 . The semiconductor device according to claim 1 , wherein a height of the polycrystalline region in an extending direction of the channel structure is greater than a thickness of the channel region in a direction intersecting a side surface of the channel structure. 9 . The semiconductor device according to claim 8 , wherein a ratio of the height of the polycrystalline region to the thickness of the channel region is 2 or more. 10 . The semiconductor device according to claim 1 , wherein a height of the polycrystalline region in an extending direction of the channel structure is equal to or greater than a diameter or a width of a bottom surface of the polycrystalline region in a direction intersecting the extending direction. 11 . The semiconductor device according to claim 10 , wherein a ratio of the height of the polycrystalline region to the diameter or the width of the bottom surface of the polycrystalline region is 1.5 or more. 12 . The semiconductor device according to claim 1 , wherein a height of the polycrystalline region in an extending direction of the channel structure is equal to or greater than a height of the protruding portion in the extending direction of the channel structure.

13. The semiconductor device according to claim 1, wherein the channel region includes a channel portion and an interface portion between the channel portion and the polycrystalline region and including metal, and Wherein a height of the interface portion in an extension direction of the channel structure is smaller than a height of the polycrystalline region in the extension direction of the channel structure. 14 . The semiconductor device according to claim 1 , further comprising a core insulating layer inside the channel region and on the polycrystalline region.

15. The semiconductor device according to claim 1, wherein the channel structure further comprises a gate dielectric layer at least partially surrounding the semiconductor layer in the inner portion and a core insulating layer inside the channel region and on the polycrystalline region, and Wherein a boundary portion between the polycrystalline region and the channel region or a bottom surface of the core insulating layer is on the same plane as a bottom surface of the gate dielectric layer adjacent to the protruding portion, or inside the gate stack structure or on the bottom surface of the gate dielectric layer.

16. The semiconductor device according to claim 1, further comprising a circuit region including a peripheral circuit structure, A cell region including the gate stack structure, the channel structure and the horizontal conductive layer is bonded to the circuit region, and The horizontal conductive layer includes a substrate on side surfaces and a bottom surface of the polycrystalline region at the protruding portion.

17. An electronic system comprising: Main substrate; a semiconductor device on the main substrate; as well as a controller, electrically connected to the semiconductor device on the main substrate, The semiconductor device comprises: A gate stack structure, comprising a plurality of gate electrodes and a plurality of insulating layers stacked alternately; a channel structure including an inner portion extending into the gate stack structure and a protruding portion protruding from one surface of the gate stack structure; and a horizontal conductive layer connected to the protruding portion of the channel structure, The channel structure includes a polycrystalline region and a channel region, the polycrystalline region is in the protruding portion and includes a polycrystalline semiconductor material, the channel region is located in the inner portion and has a crystal structure different from that of the polycrystalline region.

18. A method for manufacturing a semiconductor device, comprising: forming a stacked structure, the stacked structure comprising a plurality of sacrificial insulating layers and a plurality of insulating layers alternately stacked on a substrate; forming a preliminary channel structure by forming a penetration portion extending into the stacked structure, the preliminary channel structure comprising a preliminary semiconductor layer including an amorphous semiconductor material in the penetration portion; forming a semiconductor layer by performing a heat treatment process for crystallization of the preliminary semiconductor layer; as well as forming the plurality of gate electrodes by replacing the plurality of sacrificial insulating layers with a plurality of gate electrodes, In the forming of the semiconductor layer, a first region of the preliminary semiconductor layer is crystallized to have a polycrystalline structure, and a second region of the preliminary semiconductor layer is crystallized to have a single crystal structure or a quasi-single crystal structure.

19. The method for manufacturing a semiconductor device according to claim 18, further comprising: between forming the preliminary channel structure and forming the semiconductor layer, forming a metal layer including a metal on the preliminary channel structure, In the formation of the semiconductor layer, the first region is crystallized by a solid phase crystallization process to have the polycrystalline structure, and the second region is crystallized by a metal induced crystallization process using the metal to have the single crystal structure or the quasi-single crystal structure.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: In the forming of the preliminary channel structure, the preliminary channel structure includes an inner portion extending into the stacked structure and a protruding portion protruding from one surface of the stacked structure, and wherein the first region of the preliminary semiconductor layer is in at least a portion of the protruding portion, and the second region of the preliminary semiconductor layer is located in the inner portion and has a layered shape such that a core insulating layer is inside the second region.

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