Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate, a functional film layer and a plurality of first light-emitting elements, the functional film layer comprises a power signal line layer, a data line layer and a compensation functional layer; the power supply signal line layer comprises power supply signal line patterns arranged in the sub-pixel areas, the data line layer comprises data line patterns arranged in the sub-pixel areas, and the compensation function layer comprises a compensation function pattern arranged in at least one sub-pixel area; the first light-emitting element comprises a first anode, a first light-emitting pattern and a first cathode which are stacked; the orthographic projection of the first anode on the substrate and the orthographic projection of the corresponding power signal line pattern on the substrate have a first overlapping area, the orthographic projection of the first anode on the substrate and the orthographic projection of the corresponding data line pattern on the substrate have a second overlapping area, and the orthographic projection of the first anode on the substrate and the orthographic projection of the corresponding compensation function pattern on the substrate have a third overlapping area. The second overlapping region is located between the first overlapping region and the third overlapping region.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201980002526.4, filed on November 21, 2019. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Active-matrix organic light-emitting diode (AMOLED) display products are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility and high luminous efficiency.

[0004] As the application scope of AMOLED display products becomes wider and wider, the display quality requirements of AMOLED display products are also getting higher and higher. Among them, the color flake phenomenon that is easily generated when display products are displaying has attracted widespread attention. Summary of the invention

[0005] An object of the present disclosure is to provide a display panel and a display device.

[0006] A first aspect of the present disclosure provides a display panel, comprising: a substrate, a functional film layer disposed on the substrate, and a plurality of first light-emitting elements disposed on a side of the functional film layer facing away from the substrate; and a plurality of sub-pixel regions arranged in an array;

[0007] The functional film layer comprises: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer comprises a power signal line pattern arranged in each of the sub-pixel regions, the data line layer comprises a data line pattern arranged in each of the sub-pixel regions, the power signal line pattern comprises a first portion extending along a first direction, and the data line pattern extends along the first direction; the compensation function layer comprises a compensation function pattern arranged in at least one of the sub-pixel regions;

[0008] Each of the first light-emitting elements includes: a first anode, a first light-emitting pattern and a first cathode, which are stacked in sequence in a direction away from the substrate; the orthographic projection of the first anode on the substrate has a first overlapping area with the orthographic projection of the corresponding power signal line pattern on the substrate, has a second overlapping area with the orthographic projection of the corresponding data line pattern on the substrate, and has a third overlapping area with the orthographic projection of the corresponding compensation function pattern on the substrate, and the second overlapping area is located between the first overlapping area and the third overlapping area.

[0009] Optionally, the first anode includes a first edge portion and a second edge portion disposed opposite to each other along a second direction, and a first middle portion located between the first edge portion and the second edge portion; the second direction intersects the first direction;

[0010] The orthographic projection of the first edge portion on the substrate includes the first overlapping area; the orthographic projection of the second edge portion on the substrate includes the third overlapping area; and the orthographic projection of the first middle portion on the substrate includes the second overlapping area.

[0011] Optionally, the orthographic projection of the first edge portion on the substrate does not overlap with the orthographic projection of the first luminous pattern on the substrate, the orthographic projection of the second edge portion on the substrate does not overlap with the orthographic projection of the first luminous pattern on the substrate; the orthographic projection of the first middle portion on the substrate overlaps with the orthographic projection of the first luminous pattern on the substrate.

[0012] Optionally, the functional film layer further includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emitting control signal line layer;

[0013] The gate scan line layer includes a gate scan line pattern arranged in each of the sub-pixel areas, the initialization signal line layer includes an initialization signal line pattern arranged in each of the sub-pixel areas, the reset signal line layer includes a reset signal line pattern arranged in each of the sub-pixel areas, and the light-emitting control signal line layer includes a light-emitting control signal line pattern arranged in each of the sub-pixel areas; the gate scan line pattern, the initialization signal line pattern, the reset signal line pattern and the light-emitting control signal line pattern all extend along a second direction, and the second direction intersects with the first direction.

[0014] Optionally, the first anode further includes a third edge portion and a fourth edge portion disposed opposite to each other along the first direction, the first middle portion is located between the third edge portion and the fourth edge portion; the third edge portion is coupled to the first edge portion and the second edge portion respectively, and the fourth edge portion is coupled to the first edge portion and the second edge portion respectively;

[0015] The orthographic projection of the first middle portion on the substrate, the orthographic projection of the corresponding gate scan line pattern on the substrate, and the orthographic projection of the corresponding reset signal line pattern on the substrate include a sixth overlapping area.

[0016] Optionally, the first anode includes a main body portion and a via connection portion, the main body portion includes the first edge portion, the second edge portion, the third edge portion, the fourth edge portion and the first middle portion; the main body portion is a centrally symmetrical figure.

[0017] Optionally, the first middle portion is a centrally symmetrical figure, and an orthographic projection of the first middle portion on the substrate coincides with an orthographic projection of the first luminous figure on the substrate.

[0018] Optionally, the display panel includes a first metal layer, a second metal layer and a third metal layer;

[0019] The gate scanning line layer, the reset signal line layer and the light emitting control signal line layer are located in the first metal layer;

[0020] The initialization signal line layer is located in the second metal layer;

[0021] The data line layer, the power signal line layer and the compensation function layer are located in the third metal layer;

[0022] The functional film layer further includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer.

[0023] Optionally, the compensation function pattern is made of conductive material and is coupled to the initialization signal line pattern.

[0024] Optionally, the compensation function pattern and the data line pattern are arranged in the same layer.

[0025] Optionally, the display panel further includes: a plurality of sub-pixel driving circuits, a first portion of sub-pixel driving circuits in the plurality of sub-pixel driving circuits corresponding one-to-one to the first light-emitting elements, and the first portion of sub-pixel driving circuits are used to drive the corresponding first light-emitting elements to emit light; the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor;

[0026] The gate of the first transistor is coupled to the corresponding gate scanning line pattern, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor;

[0027] The gate of the second transistor is coupled to the corresponding reset signal line pattern, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor;

[0028] A gate of the fourth transistor is coupled to the corresponding gate scan line pattern, a first electrode of the fourth transistor is coupled to the corresponding data line pattern, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0029] The first electrode of the driving transistor is coupled to the corresponding power signal line pattern, and the second electrode of the driving transistor is coupled to the corresponding first light emitting element;

[0030] The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power signal line pattern.

[0031] Optionally, the sub-pixel driving circuit further includes a first conductive connection portion, and the second electrode of the first transistor is coupled to the gate of the driving transistor through the first conductive connection portion;

[0032] The display panel also includes a third metal layer, the first conductive connection portion is located in the third metal layer, and the orthographic projection of the first conductive connection portion included in the first partial sub-pixel driving circuit on the substrate does not overlap with the orthographic projection of the corresponding first anode on the substrate.

[0033] Optionally, the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements; each of the second light-emitting elements includes a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; each of the third light-emitting elements includes two sub-light-emitting elements that are oppositely arranged in the first direction, and each of the sub-light-emitting elements includes a third anode, a third light-emitting pattern, and a third cathode, which are sequentially stacked in a direction away from the substrate;

[0034] The plurality of sub-pixel driving circuits further include a second portion of sub-pixel driving circuits and a third portion of sub-pixel driving circuits, wherein the second portion of sub-pixel driving circuits correspond one-to-one to the second light-emitting elements, and the second portion of sub-pixel driving circuits are used to drive the corresponding second light-emitting elements to emit light, and the third portion of sub-pixel driving circuits correspond one-to-one to the sub-light-emitting elements, and the third portion of sub-pixel driving circuits are used to drive the corresponding sub-light-emitting elements to emit light;

[0035] The orthographic projection of the first conductive connection portion included in the second partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the second anode corresponding to it on the electrode; the orthographic projection of the first conductive connection portion included in the third partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the third anode corresponding to it on the substrate.

[0036] Optionally, the gate of the first transistor is in direct contact with the corresponding gate scan line pattern.

[0037] Optionally, an orthographic projection of the first electrode of the first transistor on the substrate does not overlap with an orthographic projection of the corresponding compensation function pattern on the substrate.

[0038] Optionally, an orthographic projection of the second electrode of the first transistor on the substrate does not overlap with an orthographic projection of the corresponding compensation function pattern on the substrate.

[0039] Optionally, the sub-pixel driving circuit also includes a seventh transistor, a gate of the seventh transistor is coupled to the reset signal line pattern, the second electrode of the seventh transistor in the first part of the sub-pixel driving circuit is coupled to the first anode, and there is a seventh overlapping area between the orthographic projection of the first electrode of the seventh transistor on the substrate and the orthographic projection of the corresponding compensation function pattern on the substrate, and the first electrode of the seventh transistor is coupled to the corresponding compensation function pattern through a via arranged in the seventh overlapping area, so as to be indirectly coupled to the corresponding initialization signal line pattern through the compensation function pattern.

[0040] Optionally, an orthographic projection of the gate of the driving transistor on the substrate at least partially overlaps with an orthographic projection of the corresponding compensation function pattern on the substrate.

[0041] Optionally, an orthographic projection of the gate of the driving transistor on the substrate and an orthographic projection of the corresponding compensation function pattern on the substrate include a first overlapping portion;

[0042] An orthographic projection of the first overlapping portion on the substrate at least partially overlaps with an orthographic projection of the corresponding first anode on the substrate.

[0043] Optionally, the first plate of the storage capacitor is made of the same material as the gate scan line pattern and the reset signal line pattern, and the second plate of the storage capacitor is made of the same material as the initialization signal line pattern;

[0044] The orthographic projection of the first plate of the storage capacitor on the substrate and the orthographic projection of the second plate of the storage capacitor on the substrate are both located between the orthographic projection of the corresponding gate scan line pattern on the substrate and the orthographic projection of the corresponding light-emitting control signal line pattern on the substrate.

[0045] Optionally, the functional film layer also includes a gate insulating layer, and a first insulating layer located on the side of the gate insulating layer facing away from the substrate; the first plate of the storage capacitor, the gate scan line pattern and the reset signal line pattern are all located on the surface of the gate insulating layer facing away from the substrate; the second plate of the storage capacitor and the initialization signal line pattern are both located on the surface of the first insulating layer facing away from the substrate.

[0046] Optionally, an orthographic projection of the first electrode plate of the storage capacitor on the substrate and an orthographic projection of the second electrode plate of the storage capacitor on the substrate both partially overlap with an orthographic projection of the corresponding first anode on the substrate.

[0047] Optionally, the orthographic projection of the first plate of the storage capacitor on the substrate and the orthographic projection of the second plate of the storage capacitor on the substrate both partially overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.

[0048] Optionally, a central area of ​​the second electrode plate of the storage capacitor includes an opening, and an orthographic projection of the opening on the substrate does not overlap with an orthographic projection of the corresponding compensation function pattern on the substrate.

[0049] Optionally, in a direction perpendicular to the substrate, a thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or, a thickness difference between the compensation function layer and the data line layer is within a threshold range.

[0050] Optionally, the display panel further includes a plurality of second light emitting elements;

[0051] Each of the second light-emitting elements comprises a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; the second anode comprises a fifth edge portion and a sixth edge portion which are oppositely arranged along the second direction, and a second middle portion located between the fifth edge portion and the sixth edge portion, and the orthographic projection of the second middle portion on the substrate coincides with the orthographic projection of the second light-emitting pattern on the substrate;

[0052] The orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate, and the orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate.

[0053] Optionally, the second light-emitting pattern is symmetrical about a second symmetry axis, the second symmetry axis extends along the first direction, and an orthographic projection of the second symmetry axis on the substrate is located inside an orthographic projection of the corresponding power signal line pattern on the substrate.

[0054] Optionally, the display panel further includes a plurality of third light emitting elements;

[0055] Each of the third light-emitting elements includes two sub-light-emitting elements arranged opposite to each other along the first direction, and each of the sub-light-emitting elements includes a third anode, a third light-emitting pattern, and a third cathode which are sequentially stacked in a direction away from the substrate; the third anode includes a seventh edge portion and an eighth edge portion which are arranged opposite to each other along the second direction, and a third middle portion located between the seventh edge portion and the eighth edge portion, and the orthographic projection of the third middle portion on the substrate coincides with the orthographic projection of the third light-emitting pattern on the substrate;

[0056] The orthographic projection of the third middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate;

[0057] The orthographic projection of the seventh edge portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate.

[0058] Optionally, the first light-emitting element includes a red sub-pixel, the second light-emitting element includes a blue sub-pixel, and the third light-emitting element includes a green sub-pixel.

[0059] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel.

[0060] Based on the technical solution of the display panel, a third aspect of the present invention provides a method for manufacturing a display panel, wherein the display panel includes a plurality of sub-pixel areas arranged in an array, and the manufacturing method includes:

[0061] A functional film layer is formed on a substrate; the functional film layer comprises: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer comprises a power signal line pattern arranged in each of the sub-pixel regions, the data line layer comprises a data line pattern arranged in each of the sub-pixel regions, the power signal line pattern comprises a first portion extending along a first direction, and the data line pattern extends along the first direction; the compensation function layer comprises a compensation function pattern arranged in at least one of the sub-pixel regions;

[0062] A plurality of first light-emitting elements are fabricated on a side of the functional film layer facing away from the substrate, each of the first light-emitting elements comprising: a first anode, a first light-emitting pattern and a first cathode which are sequentially stacked in a direction away from the substrate; an orthographic projection of the first anode on the substrate has a first overlapping region with an orthographic projection of a corresponding power signal line pattern on the substrate, has a second overlapping region with an orthographic projection of a corresponding data line pattern on the substrate, and has a third overlapping region with an orthographic projection of a corresponding compensation function pattern on the substrate, and the second overlapping region is located between the first overlapping region and the third overlapping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0064] Figure 1 A schematic diagram of the layout of a sub-pixel driving circuit in the related art;

[0065] Figures 2 to 5 It is a schematic diagram of the structure of each film layer of the sub-pixel driving circuit described in the related art;

[0066] Figure 6 A first structural schematic diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0067] Figure 7 A second structural schematic diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0068] Figure 8 A working timing diagram corresponding to the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0069] Fig. 9 A first schematic layout diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0070] Fig.10 for Fig. 9 Schematic diagram of the cross section along the A1A2 direction;

[0071] Fig.11 A schematic diagram of the layout of the active layer provided in an embodiment of the present disclosure;

[0072] Fig.12 A schematic diagram of the layout of the first gate metal layer provided in an embodiment of the present disclosure;

[0073] Fig.13 A schematic diagram of the layout of the second gate metal layer provided in an embodiment of the present disclosure;

[0074] Fig.14 A first schematic diagram of the layout of the source-drain metal layer provided in an embodiment of the present disclosure;

[0075] Fig.15 A second schematic layout diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0076] Fig.16 for Fig.15 Schematic diagram of the layout of the source and drain metal layers;

[0077] Fig.17 for Fig.15 Schematic diagram of the cross section along the B1B2 direction;

[0078] Fig.18 for Fig.15 Schematic diagram of the cross section along the C1C2 direction;

[0079] Fig.19 A third schematic layout diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0080] Fig. 20 A fourth schematic layout diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0081] Fig.21 A fifth schematic layout diagram of a sub-pixel driving circuit in a display panel provided by an embodiment of the present disclosure;

[0082] Fig. 22 for Fig.21 Schematic diagram of the cross section along the D1D2 direction;

[0083] Fig.23 for Fig.21 Schematic diagram of the cross section along the E1E2 direction;

[0084] Fig.24 A schematic diagram of a layout of a sub-pixel driving circuit corresponding to a pixel unit provided in an embodiment of the present disclosure

[0085] Fig.25 A schematic diagram of the structure of a first anode provided in an embodiment of the present disclosure;

[0086] Fig.26 A schematic diagram of the structure of a second anode provided in an embodiment of the present disclosure;

[0087] Fig. 27 A schematic structural diagram of the third anode provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0088] In order to further illustrate the display panel and the display device provided by the embodiments of the present disclosure, a detailed description is given below in conjunction with the accompanying drawings.

[0089] The structure of the AMOLED display panel includes: a substrate, a plurality of sub-pixel driving circuits arranged on the substrate, and a plurality of light-emitting elements arranged on the side of the sub-pixel driving circuits facing away from the substrate, wherein the light-emitting elements correspond one-to-one to the sub-pixel driving circuits, and the sub-pixel driving circuits are used to drive the corresponding light-emitting elements to emit light, thereby realizing the display function of the display panel.

[0090] In the related art, the sub-pixel driving circuit generally includes a plurality of thin film transistors, such as Figure 1 As shown, Figure 1 FIG. 2 shows a specific layout of the seven thin film transistors M1 to M7 when the sub-pixel driving circuit includes seven thin film transistors. When arranged in this manner, the sub-pixel driving circuit includes the following: Figure 2 The active layer shown, such as Figure 3 The first metal layer shown, such as Figure 4 The second metal layer shown, and Figure 5 The third metal layer shown; the active layer includes an active pattern (such as Figure 2 The portion within the dotted frame in FIG. 1 ), and a doped active pattern (such as a doped active pattern having conductive properties) coupled to the active pattern. Figure 2 The first metal layer includes the gates of each thin film transistor, the scanning signal line pattern GATE coupled to the gates, a plate CE1 of a storage capacitor in the sub-pixel driving circuit, a reset signal line pattern RST, and a light-emitting control signal line pattern EM; the second metal layer includes the initialization signal line pattern VINT, and another electrode plate CE2 of the storage capacitor in the sub-pixel driving circuit; the third metal layer includes the data line pattern DATA, the power signal line pattern VDD, and some conductive connecting parts (such as marks 341~343).

[0091] It is worth noting that Figure 1 As shown, when laying out the sub-pixel driving circuit, in order to achieve coupling between functional patterns arranged in different layers, some vias (such as marks: 381-388) may also be arranged.

[0092] like Figure 6 and Figure 7 As shown, the present disclosure provides a display panel, which includes multiple sub-pixel driving circuits. Exemplarily, each sub-pixel driving circuit includes 7 thin-film transistors and 1 capacitor; the display panel also includes an initialization signal line graph VINT, a gate scanning line graph GATE, a light-emitting control signal line graph EM, a reset control signal line graph RST, a data line graph DATA and a power signal line graph VDD, and each graph is located in a sub-pixel area of ​​the display panel in a one-to-one correspondence.

[0093] The multiple sub-pixel driving circuits are distributed in an array and are located one by one in the sub-pixel area of ​​the display panel. The multiple sub-pixel driving circuits can be divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The initialization signal line graphics VINT corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence to form an integrated structure; the gate scanning line graphics GATE corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence to form an integrated structure; the light-emitting control signal line graphics EM corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence to form an integrated structure; the reset control signal line graphics RST corresponding to the sub-pixel driving circuits located in the same row are electrically connected in sequence to form an integrated structure; the data line graphics DATA corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence to form an integrated structure; the power signal line graphics VDD corresponding to the sub-pixel driving circuits located in the same column are electrically connected in sequence to form an integrated structure.

[0094] Exemplarily, each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged in sequence along the X direction, the initialization signal line graph VINT, the gate scan line graph GATE, the light control signal line graph EM and the reset control signal line graph RST all extend along the X direction, and the plurality of sub-pixel driving circuits included in each row of sub-pixel driving circuits can be respectively coupled to the corresponding initialization signal line graph VINT, the gate scan line graph GATE, the light control signal line graph EM, and the reset control signal line graph RST; each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged in sequence along the Y direction, the data line graph DATA and the power signal line graph VDD all extend along the Y direction, and the plurality of sub-pixel driving circuits included in each column of sub-pixel driving circuits can be respectively coupled to the corresponding data line graph DATA and the power signal line graph VDD.

[0095] like Figure 6 As shown, each sub-pixel driving circuit included in the display panel may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst; the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors.

[0096] The first transistor T1 is a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the corresponding gate scan line pattern GATE, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0097] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is coupled to the corresponding first reset signal line graph RST1, a source S2 of the second transistor T2 is coupled to the corresponding first initialization signal line graph VINT1, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0098] The gate 204g of the fourth transistor T4 is coupled to the corresponding gate scanning line pattern GATE, the source S4 of the fourth transistor T4 is coupled to the corresponding data line pattern DATA, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0099] The gate 205g of the fifth transistor T5 is coupled to the corresponding first light emitting control signal line pattern EM1, the source S5 of the fifth transistor T5 is coupled to the corresponding power signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0100] The gate 206g of the sixth transistor T6 is coupled to the corresponding second light emitting control signal line pattern EM2, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the first anode 501 of the light emitting element OLED.

[0101] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the first anode 501 of the light emitting element OLED, and the source S7 of the seventh transistor T7 is coupled to the corresponding second initialization signal line pattern VINT2.

[0102] The first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3. Therefore, the gate 203g of the third transistor T3 can be directly reused as the first plate Cst1 of the storage capacitor Cst. The second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power signal line pattern VDD.

[0103] like Figure 7 As shown, the first light-emitting control signal line pattern EM1 and the second light-emitting control signal line pattern EM2 can reuse the same light-emitting control signal line pattern EM, so that the on-off status of the fifth transistor T5 and the sixth transistor T6 can be simultaneously controlled by the light-emitting control signal line pattern.

[0104] like Figure 8 As shown, Figure 7 When the sub-pixel driving circuit of the structure is working, each working cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0105] In the first reset period P1, the first reset signal input by the first reset signal line graph RST1 is at a valid level, the second transistor T2 is turned on, and the initialization signal transmitted by the first initialization signal line graph VINT1 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0106] During the write compensation period P2, the first reset signal is at a non-valid level, the second transistor T2 is turned off, the gate scan signal input by the gate scan line pattern GATE is at a valid level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, the data line pattern DATA writes the data signal, and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage compensation of the third transistor T3 is realized by the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to finally reach Vdata+Vth, where Vdata represents the data signal and Vth represents the threshold voltage of the third transistor T3.

[0107] In the second reset period P3, the gate scan signal is at a non-valid level, the first transistor T1 and the fourth transistor T4 are both turned off, the second reset signal input by the second reset signal line graph RST2 is at a valid level, the seventh transistor T7 is controlled to be turned on, and the first initialization signal transmitted by the first initialization signal line graph VINT1 is input to the anode of the light-emitting element OLED, controlling the light-emitting element OLED not to emit light.

[0108] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line graphic EM is at a valid level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line graphic VDD is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-Vdd, Vdd is the potential corresponding to the power signal, and the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element OLED, driving the corresponding light-emitting element OLED to emit light.

[0109] like Fig. 9 and Fig.10 As shown, Fig. 9, a schematic diagram of the layout of three adjacent sub-pixel driving circuits is shown. When manufacturing the above sub-pixel driving circuit, the layout of each film layer corresponding to the sub-pixel driving circuit is as follows:

[0110] An active layer (generally a low-temperature polysilicon layer), a gate insulating layer GI1, a first gate metal layer, a first interlayer insulating layer GI2, a second gate metal layer, a second interlayer insulating layer ILD, a first source and drain metal layer and a planarizing layer PLN are stacked in sequence in a direction away from the substrate 70.

[0111] like Fig.11 As shown, the active layer is used to form the channel region (such as: 101pg~107pg), the source formation region (such as: 101ps~107ps) and the drain formation region (such as: 101pd~107pd) of each transistor in the sub-pixel driving circuit. The active layer corresponding to the source formation region and the drain formation region has better conductivity than the active layer corresponding to the channel region due to doping. The active layer corresponding to the source formation region can be used as the source of each transistor (such as: S1~S7), and the active layer corresponding to the drain formation region can be used as the drain of each transistor (such as: D1~D7).

[0112] like Fig.12 As shown, the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (such as: 201g~207g), and the display panel includes a gate scanning signal line graphic GATE, a light-emitting control signal line graphic EM, a first reset signal line graphic RST1 and a second reset signal line graphic RST2 and other structures, wherein the gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.

[0113] like Fig.13 As shown, the second gate metal layer is used to form the second plate Cst2 of the storage capacitor Cst, the shielding pattern 301 (used to shield the active layer between the two channel regions corresponding to the first transistor T1), and the display panel includes a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2.

[0114] like Fig. 9 and Fig.14 As shown, the first source-drain metal layer is used to form data line patterns (such as DATA1, DATA2, DATA3) and power signal line patterns (such as VDD1, VDD2, VDD3) included in the display panel.

[0115] For more details, please refer to Fig. 9 , Fig.11 and Fig.12, the gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0116] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0117] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0118] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.

[0119] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0120] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0121] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0122] The gate 203g of the third transistor T3 is multiplexed as a first plate Cst1 of the storage capacitor Cst, and a second plate Cst2 of the storage capacitor Cst is coupled to the power signal line VDD.

[0123] Please continue reading Fig. 9 , Fig. 9A red light-emitting element and a blue light-emitting element are illustrated in the figure. The anode included in at least one of the red light-emitting element and the blue light-emitting element can cover the power signal line pattern and the data line pattern at the same time. Exemplarily, the anode pattern 901 included in the blue light-emitting element covers the power signal line pattern VDD1 and the data line pattern DATA1 at the same time, and the anode pattern 902 included in the red light-emitting element covers the power signal line pattern VDD2 and the data line pattern DATA2 at the same time. Since the power signal line pattern and the data line pattern are both whole patterns extending longitudinally (such as in the Y direction), the above-mentioned layout method makes the anode pattern have a smaller step difference in the longitudinal extension direction, which is beneficial to improving the color deviation phenomenon produced by the light-emitting element.

[0124] Although the above display panel has improved the color cast phenomenon caused by the light-emitting element, Fig.10 It can be seen that the power signal line pattern VDD and the data line pattern DATA can produce a step difference in the lateral extension direction (such as the X direction), which causes the subsequently formed anode pattern 902 to tilt in the lateral extension direction, and then causes the organic light-emitting material layer 802 formed on the anode pattern 902 to tilt as well, so that the display panel still has color deviation when displaying.

[0125] Based on the above problems, Fig.15 and Fig.17 As shown, the embodiment of the present disclosure provides a display panel, comprising: a substrate 50, a functional film layer disposed on the substrate 50, and a plurality of first light-emitting elements disposed on a side of the functional film layer facing away from the substrate 50; and also comprising a plurality of sub-pixel regions arranged in an array;

[0126] The functional film layer includes: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer includes a power signal line pattern (such as Fig.15 The data line layer includes a data line pattern (such as VDD1 and VDD2) arranged in each of the sub-pixel areas. Fig.15 DATA1 and DATA2 in the figure), the power signal line pattern includes a first portion extending along a first direction, and the data line pattern extends along the first direction; the compensation function layer includes a compensation function pattern 401 arranged in at least one of the sub-pixel areas;

[0127] Each of the first light-emitting elements includes: a first anode 501, a first light-emitting pattern 601 and a first cathode, which are stacked in sequence in a direction away from the substrate 50; the orthographic projection of the first anode 501 on the substrate 50 has a first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern on the substrate 50, has a second overlapping area F2 with the orthographic projection of the corresponding data line pattern on the substrate 50, and has a third overlapping area F3 with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, and the second overlapping area F2 is located between the first overlapping area F1 and the third overlapping area F3.

[0128] Specifically, the plurality of sub-pixel areas arranged in an array can be divided into a sub-pixel area column extending along a first direction, and a sub-pixel area row extending along a second direction, the sub-pixel area column including a plurality of sub-pixel areas arranged along the first direction, and the sub-pixel area row including a plurality of sub-pixel areas arranged along the second direction; the first direction intersects with the second direction, exemplarily, the first direction includes the Y direction, and the second direction includes the X direction.

[0129] The power signal line layer includes a power signal line pattern arranged in each of the sub-pixel areas, and the power signal line pattern may be in a grid shape, and the grid-shaped power signal line pattern includes a first portion extending along the first direction. The power signal line pattern corresponds to the sub-pixel area one by one, and the power signal line pattern is located in the corresponding sub-pixel area. The power signal line patterns VDD corresponding to the sub-pixel areas in the same column are electrically connected in sequence to form an integrated structure.

[0130] The data line layer includes a data line pattern arranged in each of the sub-pixel areas, the data line pattern extends along the first direction, the data line pattern corresponds to the sub-pixel area one by one, the data line pattern is located in the corresponding sub-pixel area, and the data line patterns DATA corresponding to the sub-pixel areas located in the same column are electrically connected in sequence to form an integrated structure.

[0131] The display panel also includes a plurality of first light-emitting elements located on the side of the functional film layer facing away from the substrate 50, wherein the first light-emitting elements include: a first anode 501, a first light-emitting pattern 601 and a first cathode, which are sequentially stacked in a direction away from the substrate 50; when the display panel is operating, a driving signal is provided to the first anode 501, and a common signal is provided to the first cathode, so that an electric field is generated between the first anode 501 and the first cathode, thereby controlling the first light-emitting pattern 601 to emit light of a corresponding color; illustratively, the first light-emitting element includes a red light-emitting element capable of emitting red light.

[0132] The compensation function layer includes a compensation function pattern 401 disposed in at least one of the sub-pixel regions. Exemplarily, the compensation function pattern 401 corresponds to the first light-emitting element one by one;

[0133] When laying out the display panel, a functional film layer is first formed on the substrate 50, and then a first light-emitting element is made on the side of the functional film layer facing away from the substrate 50. When laying out the functional film layer, the power signal line pattern and the data line pattern can be arranged alternately along the second direction, and the compensation functional pattern 401 can be set in the vicinity of the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the substrate 50 has a first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern on the substrate 50, has a second overlapping area F2 with the orthographic projection of the corresponding data line pattern on the substrate 50, and has a third overlapping area F3 with the orthographic projection of the corresponding compensation functional pattern 401 on the substrate 50, and the second overlapping area F2 is located between the first overlapping area F1 and the third overlapping area F3.

[0134] According to the specific structure of the above-mentioned display panel, it can be known that in the display panel provided by the embodiment of the present disclosure, the compensation function pattern 401 can compensate for the step difference between the power signal line pattern and the data line pattern below the first anode 501, so that in the display panel, the first anode 501 included in the first light-emitting element can have a higher flatness when simultaneously covering part of the corresponding power signal line pattern, part of the corresponding data line pattern, and at least part of the corresponding compensation function pattern 401, thereby effectively reducing the color cast phenomenon generated by the display panel during display.

[0135] like Fig.25 As shown, in some embodiments, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 arranged opposite to each other along a second direction, and a first middle portion 501a5 located between the first edge portion 501a1 and the second edge portion 501a2; the second direction intersects with the first direction; the orthographic projection of the first edge portion 501a1 on the substrate 50 includes the first overlapping area F1; the orthographic projection of the second edge portion 501a2 on the substrate 50 includes the third overlapping area F3; the orthographic projection of the first middle portion 501a5 on the substrate 50 includes the second overlapping area F2.

[0136] Specifically, the specific structure of the first anode 501 is varied. Exemplarily, the first anode 501 includes a first edge portion 501a1 and a second edge portion 501a2 arranged opposite to each other along the second direction, and a first middle portion 501a5 located between the first edge portion 501a1 and the second edge portion 501a2. The first edge portion 501a1, the second edge portion 501a2 and the middle portion may all extend along the first direction.

[0137] The orthographic projection of the first edge portion 501a1 on the substrate 50 can form the first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern on the substrate 50, the orthographic projection of the first middle portion 501a5 on the substrate 50 can form the second overlapping area F2 with the orthographic projection of the corresponding data line pattern on the substrate 50, and the orthographic projection of the second edge portion 501a2 on the substrate 50 can form the third overlapping area F3 with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50.

[0138] In the display panel provided by the above embodiment, the first edge portion 501a1 and the second edge portion 501a2 of the first anode 501, which are relatively arranged along the second direction, can respectively cover the corresponding power signal line pattern and the corresponding compensation function pattern 401, and at the same time, the middle portion of the first anode 501 located between the first edge portion 501a1 and the second edge portion 501a2 can cover the corresponding data line pattern, so that the power signal line pattern, data signal line pattern and compensation function pattern 401 covered by the first anode 501 can be evenly distributed in the area covered by the first anode 501, thereby better ensuring the flatness of the first anode 501.

[0139] like Fig.15 and Fig.25 As shown, in some embodiments, the orthographic projection of the first edge portion 501a1 on the substrate 50 does not overlap with the orthographic projection of the first luminous pattern 601 on the substrate 50, and the orthographic projection of the second edge portion 501a2 on the substrate 50 does not overlap with the orthographic projection of the first luminous pattern 601 on the substrate 50; the orthographic projection of the first middle portion 501a5 on the substrate 50 overlaps with the orthographic projection of the first luminous pattern 601 on the substrate 50.

[0140] Specifically, when the first light-emitting pattern 601 is formed on the surface of the first anode 501 facing away from the substrate 50, the specific layout of the first light-emitting pattern 601 is various. Exemplarily, the orthographic projection of the first light-emitting pattern 601 on the substrate 50 is located between the orthographic projection of the first edge pattern on the substrate 50 and the orthographic projection of the second edge pattern on the substrate 50, and overlaps with the orthographic projection of the first middle part 501a5 on the substrate 50. When the first light-emitting pattern 601 is laid out in this way, the first light-emitting pattern 601 can be located on the surface of the middle part of the first anode 501, and the surface of the middle part of the first anode 501 has a higher flatness, which is more conducive to improving the flatness of the first light-emitting pattern 601.

[0141] like Fig.25 As shown, in some embodiments, the first middle portion 501a5 is a centrally symmetrical figure, and the orthographic projection of the first middle portion 501a5 on the substrate 50 coincides with the orthographic projection of the first luminous figure 601 on the substrate 50 .

[0142] Specifically, the first middle part 501a5 of the first anode 501 can be optionally a centrally symmetrical figure. Exemplarily, the orthographic projection of the first middle part 501a5 on the substrate 50 is a hexagon. In this case, when the orthographic projection of the first light-emitting figure 601 on the substrate 50 is set to coincide with the orthographic projection of the first middle part 501a5 on the substrate 50, the first light-emitting figure 601 is also a centrally symmetrical figure. Such a structure of the first middle part 501a5 and the first light-emitting figure 601 is more conducive to the flatness of the first light-emitting figure 601 and the uniformity of light output.

[0143] In some embodiments, a ratio of a sum of an area of ​​the first overlapping region F1 and an area of ​​the second overlapping region F2 to an area of ​​the third overlapping region F3 is close to 2:1.

[0144] Specifically, when laying out the first anode 501, the power signal line pattern, the data line pattern and the compensation function pattern 401, the flatness of the first anode 501 can be adjusted by controlling the degree of overlap of the first anode 501 with the power signal line pattern, the data line pattern and the compensation function pattern 401 in a direction perpendicular to the substrate 50; illustratively, the ratio of the sum of the area of ​​the first overlapping area F1 and the area of ​​the second overlapping area F2 to the area of ​​the third overlapping area F3 can be set to be close to 2:1; this setting method makes the first overlapping area, the second overlapping area and the third overlapping area close to each other, that is, the areas of the power signal line pattern, the data line pattern and the compensation function pattern 401 covered by the first anode 501 are close to each other, which is more conducive to improving the flatness of the first anode 501.

[0145] like Fig.15 As shown, in some embodiments, the functional film layer further includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emitting control signal line layer;

[0146] The gate scan line layer includes a gate scan line graphic GATE arranged in each of the sub-pixel areas, the initialization signal line layer includes an initialization signal line graphic VINT arranged in each of the sub-pixel areas, the reset signal line layer includes a reset signal line graphic RST arranged in each of the sub-pixel areas, and the light-emitting control signal line layer includes a light-emitting control signal line graphic EM arranged in each of the sub-pixel areas; the gate scan line graphic GATE, the initialization signal line graphic VINT, the reset signal line graphic RST and the light-emitting control signal line graphic EM all extend along a second direction, and the second direction intersects with the first direction.

[0147] Specifically, the gate scan line layer includes a gate scan line graphic GATE arranged in each of the sub-pixel areas, the gate scan line graphic GATE extends along the second direction, and the gate scan line graphics GATE corresponding to each of the sub-pixel areas in the same row are electrically connected in sequence to form an integrated structure.

[0148] The initialization signal line layer includes an initialization signal line pattern VINT arranged in each of the sub-pixel areas. The initialization signal line layer extends along the second direction. The initialization signal line patterns VINT corresponding to the sub-pixel areas in the same row are electrically connected in sequence to form an integrated structure.

[0149] The reset signal line layer includes a reset signal line pattern RST arranged in each of the sub-pixel areas, the reset signal line pattern RST extends along the second direction, and the reset signal line patterns RST corresponding to the sub-pixel areas in the same row are electrically connected in sequence to form an integrated structure.

[0150] The light-emitting control signal line layer includes a light-emitting control signal line pattern EM arranged in each of the sub-pixel areas, the light-emitting control signal line pattern EM extends along the second direction, and the light-emitting control signal line patterns EM corresponding to each of the sub-pixel areas in the same row are electrically connected in sequence to form an integrated structure.

[0151] like Fig.15 and Fig.25 As shown, in some embodiments, the first anode 501 also includes a third edge portion 501a3 and a fourth edge portion 501a4 arranged opposite to each other along the first direction, and the first middle portion 501a5 is located between the third edge portion 501a3 and the fourth edge portion 501a4; the third edge portion 501a3 is coupled to the first edge portion 501a1 and the second edge portion 501a2 respectively, and the fourth edge portion 501a4 is coupled to the first edge portion 501a1 and the second edge portion 501a2 respectively; the orthographic projection of the first middle portion 501a5 on the substrate 50 and the orthographic projection of the corresponding gate scan line pattern on the substrate 50, as well as the orthographic projection of the corresponding reset signal line pattern on the substrate 50 include a sixth overlapping area.

[0152] Specifically, the first anode 501 also includes a third edge portion 501a3 and a fourth edge portion 501a4 arranged opposite to each other along the first direction, the first middle portion 501a5 is located between the third edge portion 501a3 and the fourth edge portion 501a4, and the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3 and the fourth edge portion 501a4 jointly surround the middle portion.

[0153] When laying out the first anode 501, the positive projection of the third edge portion 501a3 on the substrate 50 may be set to be aligned with the corresponding initialization signal line pattern VINT (eg, Fig.15The orthographic projection of the first initialization signal line pattern VINT1 in the substrate 50 forms a fourth overlapping area; the orthographic projection of the fourth edge portion 501a4 on the substrate 50 and the orthographic projection of the corresponding light-emitting control signal line pattern EM on the substrate 50 form a fifth overlapping area; the orthographic projection of the first middle portion 501a5 on the substrate 50 and the orthographic projection of the corresponding gate scanning line pattern GATE on the substrate 50, as well as the corresponding reset signal line pattern RST (as Fig.15 The first reset signal line graphic RST1) is projected onto the substrate 50 to form a sixth overlapping area; this layout makes the fourth overlapping area and the fifth overlapping area relatively arranged along the first direction, and the sixth overlapping area is located between the fourth overlapping area and the fifth overlapping area, so that the initialization signal line graphic VINT, the light-emitting control signal line graphic EM, the gate scanning line graphic GATE and the reset signal line graphic RST covered by the first anode 501 can be evenly distributed in the area covered by the first anode 501, thereby better ensuring the flatness of the first anode 501.

[0154] like Fig.25 As shown, in some embodiments, the first anode 501 includes a main body portion 501a and a via connection portion 501b, the main body portion 501a includes the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3, the fourth edge portion 501a4 and the first middle portion 501a5; the main body portion 501a is a centrally symmetrical figure.

[0155] Specifically, the first anode 501 may include a main body portion 501a and a via connection portion 501b coupled to each other, wherein the surface of the main body portion 501a facing away from the substrate 50 is used to form the first light-emitting pattern 601, and the via connection portion 501b is used to couple with the sub-pixel driving circuit in the display panel through a via hole to receive a driving signal provided by the sub-pixel driving circuit.

[0156] The above-mentioned first anode 501 is configured to include the main body portion 501a and the via-hole connection portion 501b, thereby avoiding the need to make vias on the portion of the first anode 501 used to form the first light-emitting pattern 601, thereby ensuring the light-emitting effect of the first light-emitting element. In addition, the main body portion 501a is configured to include the first edge portion 501a1, the second edge portion 501a2, the third edge portion 501a3, the fourth edge portion 501a4 and the first middle portion 501a5, and the main body portion 501a is configured to be a centrally symmetrical pattern, so that the power signal line pattern VDD (such as Fig.15 VDD1 in), data line graphics DATA (such as Fig.15 DATA1 in), gate scanning line pattern GATE, reset signal line pattern RST (such as Fig.15 The first reset signal line pattern RST1 in the figure), the light emitting control signal line pattern EM, the initialization signal line pattern VINT (such as Fig.15 The portion of the first initialization signal line pattern VINT1) covered by the first anode 501 can be evenly distributed below the first anode 501, which is more conducive to improving the flatness of the first anode 501.

[0157] like Fig.12 , Fig.13 , Fig.16 , Fig.17 and Fig.18 As shown, in some embodiments, the display panel includes a first metal layer, a second metal layer and a third metal layer; the gate scan line layer, the reset signal line layer and the light emitting control signal line layer are located in the first metal layer; the initialization signal line layer is located in the second metal layer; the data line layer, the power signal line layer and the compensation function layer are located in the third metal layer; the functional film layer also includes a first insulating layer (such as Fig.17 GI2 in) and the second insulating layer (such as Fig.17 The first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer.

[0158] Specifically, when laying out the display panel, functional layer graphics extending in the same direction can be laid out on the same layer. For example, the gate scan line layer, the reset signal line layer and the light emitting control signal line layer are arranged on the same layer and together form a first metal layer; the data line layer, the power signal line layer and the compensation functional layer are arranged on the same layer and together form a third metal layer.

[0159] Since the size of the display panel is fixed, the layout space on the same layer is limited. When the functional layer graphics extending in the same direction cannot be arranged on the same layer, some functional layer graphics can be arranged on other film layers. Exemplarily, the initialization signal line layer is formed as a second metal layer, and the second metal layer is arranged on a different layer from the first metal layer.

[0160] It is worth noting that when making each metal layer, in order to avoid short circuit between adjacent metal layers, an insulating layer can be formed between adjacent metal layers. Exemplarily, the functional film layer also includes a first insulating layer and a second insulating layer, the first insulating layer is located between the first metal layer and the second metal layer, and the second insulating layer is located between the second metal layer and the third metal layer.

[0161] In the display panel provided by the above-mentioned embodiment, by arranging the functional layer graphics extending in the same direction on the same layer and arranging the insulating layer between adjacent conductive film layers, the layout space in the display panel is utilized to the maximum extent while avoiding short circuits between the functional graphics in the display panel, which is more conducive to the thinning development of the display panel.

[0162] like Fig.15 As shown, in some embodiments, the compensation function pattern 401 is made of conductive material and is connected to the initialization signal line pattern VINT (eg Fig.15 The first initialization signal line pattern VINT1) is coupled.

[0163] Specifically, the material of the compensation function graphic 401 can be set according to actual needs, and exemplarily includes conductive materials or insulating materials. When the compensation function graphic 401 is made of conductive materials, the compensation function can be coupled to the fixed signal output terminal so that the compensation function graphic 401 has a fixed potential, thereby avoiding the compensation function graphic 401 being in a floating state and affecting the stability of the display panel.

[0164] Furthermore, the initialization signal line graphic VINT can be multiplexed as a fixed potential output terminal. Since the initialization signal line graphic VINT is used to transmit an initialization signal with a fixed potential, coupling the compensation function graphic 401 with the initialization signal line graphic VINT can make the compensation function graphic 401 have the same fixed potential as the initialization signal.

[0165] The above-mentioned multiplexing of the initialization signal line graphic VINT as the fixed potential output terminal not only avoids the production of an additional fixed potential output terminal in the display substrate that is specifically used to provide a fixed potential for the compensation function graphic 401, effectively improving the layout space of the functional film layer; but also realizes the enhancement of the voltage of the initialization signal line, so that the voltage of the initialization signal transmitted on the initialization signal line is more stable, which is more conducive to the sub-pixel driving circuit to achieve stable working performance.

[0166] Note: Please continue reading Figure 5When the initialization signal line graphic VINT is multiplexed as the fixed potential output terminal, the orthographic projection of the compensation function graphic 401 on the substrate 50 can be set to have an overlapping area with the orthographic projection of the initialization signal line graphic VINT on the substrate 50. In this way, by setting a via in the overlapping area, the compensation function graphic 401 can be coupled to the initialization signal line graphic VINT.

[0167] In some embodiments, the compensation function pattern 401 is disposed on the same layer as the data line pattern DATA.

[0168] Specifically, when laying out the compensation function pattern 401, the compensation function pattern 401 and the data line pattern DATA may be arranged on the same layer. This layout avoids the compensation function pattern 401 occupying a single layer, which is more conducive to thinning the display panel.

[0169] Furthermore, the compensation function pattern 401 and the data line pattern DATA may be set with the same material. This setting method enables the compensation function pattern 401 to be formed in the same patterning process as the data line pattern DATA, thereby effectively simplifying the production process of the display panel and saving the production cost of the display panel.

[0170] In some embodiments, the display panel also includes: a plurality of sub-pixel driving circuits, a first part of the sub-pixel driving circuits among the plurality of sub-pixel driving circuits corresponding one-to-one to the first light-emitting elements, and the first part of the first sub-pixel driving circuits are used to drive the corresponding first light-emitting elements to emit light; the sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor.

[0171] The gate of the first transistor is coupled to the corresponding gate scan line graph GATE, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor; the gate of the second transistor is coupled to the corresponding reset signal line graph RST, the first electrode of the second transistor is coupled to the corresponding initialization signal line graph VINT, and the second electrode of the second transistor is coupled to the gate of the driving transistor; the gate of the fourth transistor is coupled to the corresponding gate scan line graph GATE, the first electrode of the fourth transistor is coupled to the corresponding data line graph DATA, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; the first electrode of the driving transistor is coupled to the corresponding power signal line graph VDD, and the second electrode of the driving transistor is coupled to the corresponding first light-emitting element; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power signal line graph VDD.

[0172] Exemplarily, the functional film layer includes n+1 power signal line graphics VDD, n+1 data line graphics DATA, n+1 gate scan line graphics GATE, n+1 initialization signal line graphics VINT, n+1 reset signal line graphics RST and n+1 light emission control signal line graphics EM, the display panel includes a plurality of sub-pixel driving circuits corresponding to the sub-pixel areas one by one, the plurality of sub-pixel driving circuits can be divided into n+1 rows of sub-pixel driving circuits, and can be divided into n+1 columns of sub-pixel driving circuits; the ... The line pattern VDD corresponds one-to-one to the n+1 column sub-pixel driving circuit, the n+1 data line patterns DATA correspond one-to-one to the n+1 column sub-pixel driving circuit, the n+1 gate scan line patterns GATE correspond one-to-one to the n+1 row sub-pixel driving circuit, the n+1 initialization signal line patterns VINT correspond one-to-one to the n+1 row sub-pixel driving circuit, the n+1 reset signal line patterns RST correspond one-to-one to the n+1 row sub-pixel driving circuit, and the n+1 light emitting control signal line patterns EM correspond one-to-one to the n+1 row sub-pixel driving circuit.

[0173] Based on the above exemplary structure, the sub-pixel driving circuit located in the nth row and the nth column is taken as an example to describe in detail its specific structure and the connection method with various signal line patterns.

[0174] like Figure 7 and Fig.15As shown, the sub-pixel driving circuit includes: a driving transistor (i.e., a third transistor T3, described as the third transistor T3 below), a first transistor T1, a second transistor T2, a fourth transistor T4 and a storage capacitor Cst; the first transistor T1, the second transistor T2 and the fourth transistor T4 are P-type transistors.

[0175] The gate 201g of the first transistor T1 is coupled to the gate scan line pattern GATE, the first electrode (i.e., source S1) of the first transistor T1 is coupled to the second electrode (i.e., drain D3) of the third transistor T3, and the second electrode (i.e., drain D1) of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0176] The gate 202g of the second transistor T2 is coupled to the first reset signal line graph RST1, the first electrode (ie, source S2) of the second transistor T2 is coupled to the first initialization signal line graph VINT1, and the second electrode (ie, drain D2) of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0177] The gate 204g of the fourth transistor T4 is coupled to the gate scan line pattern GATE, the first electrode (ie, source S4) of the fourth transistor T4 is coupled to the data line pattern DATA, and the second electrode (ie, drain D4) of the fourth transistor T4 is coupled to the first electrode (ie, source S3) of the third transistor T3.

[0178] A first electrode (ie, source S3 ) of the third transistor T3 is coupled to the power signal line pattern VDD, and a second electrode (ie, drain D3 ) of the third transistor T3 is coupled to the corresponding light emitting element OLED.

[0179] The first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0180] In some embodiments, the functional film layer also includes: a light-emitting control signal line pattern and a second reset signal line pattern RST2; the sub-pixel driving circuit also includes: a fifth transistor, a sixth transistor and a seventh transistor; wherein the gate of the fifth transistor is coupled to the light-emitting control signal line pattern, the first electrode of the fifth transistor is coupled to the power signal line pattern VDD, and the second electrode of the fifth transistor is coupled to the first electrode of the driving transistor; the gate of the sixth transistor is coupled to the light-emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the corresponding light-emitting element; the gate of the seventh transistor is coupled to the second reset signal line pattern, the first electrode of the seventh transistor is coupled to the initialization signal line, and the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor.

[0181] Specifically, Figure 7 and Fig.15 As shown, continuing to take the sub-pixel driving circuit located in the nth row and the nth column as an example, the gate 205g of the fifth transistor T5 is coupled to the light-emitting control signal line pattern EM, the first electrode (i.e., source S5) of the fifth transistor T5 is coupled to the power signal line pattern VDD, and the second electrode (i.e., drain D5) of the fifth transistor T5 is coupled to the first electrode (i.e., source S3) of the driving transistor (i.e., the third transistor T3).

[0182] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the first electrode (i.e., source S6) of the sixth transistor T6 is coupled to the second electrode (i.e., drain D3) of the driving transistor (i.e., third transistor T3), and the second electrode (i.e., drain D6) of the sixth transistor T6 is coupled to the corresponding light emitting element OLED;

[0183] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line graph RST2 (exemplarily, the second reset signal line graph RST2 may be the reset signal line graph RST corresponding to the n+1th row of sub-pixel driving circuit), the first electrode (i.e., source S7) of the seventh transistor T7 is coupled to the second initialization signal line graph VINT2 (exemplarily, the second initialization signal line graph VINT2 may be the initialization signal line graph VINT corresponding to the n+1th row of sub-pixel driving circuit), and the second electrode (i.e., drain D7) of the seventh transistor T7 is coupled to the second electrode (i.e., drain D6) of the sixth transistor T6.

[0184] In the display panel provided in the above embodiment, the sub-pixel driving circuit is set to also include the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, so that the sub-pixel driving circuit can only drive the corresponding light-emitting element OLED to emit light in the light-emitting stage, thereby avoiding the phenomenon of abnormal light emission of the light-emitting element OLED, thereby better improving the display quality of the display panel.

[0185] like Fig.21 and Fig. 22 As shown, in some embodiments, the sub-pixel driving circuit also includes a first conductive connection portion 701, and the second electrode (i.e., the drain D1) of the first transistor T1 is coupled to the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) through the first conductive connection portion 701; the display panel also includes a third metal layer, and the first conductive connection portion 701 is located on the third metal layer, and the orthographic projection of the first conductive connection portion included in the first part of the sub-pixel driving circuit on the substrate does not overlap with the orthographic projection of the corresponding first anode 501 on the substrate.

[0186] Specifically, the compensation function pattern 401 can be set between the data line pattern (such as DATA1) and the first conductive connection part included in the first part of the sub-pixel driving circuit, and the data line pattern is located directly below the first anode in the first part of the sub-pixel driving circuit; in the display panel with the above structure, the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) can be separated from the data line pattern (such as DATA1) by the compensation function pattern 401, so as to better avoid the signal change on the data line pattern and the crosstalk to the gate potential of the driving transistor. Moreover, the display panel with the above structure also avoids the short circuit between the first conductive connection part 701 and the compensation function pattern 401.

[0187] Furthermore, if Fig.21 and Fig.23 As shown, the compensation function pattern 401 can be coupled to the initialization signal line pattern (such as VINT1), so that the compensation function pattern 401 has a fixed potential, thereby further avoiding signal changes on the data line pattern and generating crosstalk on the gate potential of the driving transistor.

[0188] In addition, the first conductive connection part 701 is located in the third metal layer, so that the first conductive connection part 701 can be formed in one patterning process with other patterns included in the third metal layer, thereby greatly simplifying the manufacturing process of the display substrate.

[0189] like Fig.24As shown, in some embodiments, the display panel further includes a plurality of second light-emitting elements and a plurality of third light-emitting elements; each of the second light-emitting elements includes a second anode 502, a second light-emitting pattern 602, and a second cathode, which are sequentially stacked in a direction away from the substrate; each of the third light-emitting elements includes two sub-light-emitting elements that are oppositely arranged along the first direction, and each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode, which are sequentially stacked in a direction away from the substrate;

[0190] The plurality of sub-pixel driving circuits further include a second portion of sub-pixel driving circuits and a third portion of sub-pixel driving circuits, wherein the second portion of sub-pixel driving circuits correspond one-to-one to the second light-emitting elements, and the second portion of sub-pixel driving circuits are used to drive the corresponding second light-emitting elements to emit light, and the third portion of sub-pixel driving circuits correspond one-to-one to the sub-light-emitting elements, and the third portion of sub-pixel driving circuits are used to drive the corresponding sub-light-emitting elements to emit light;

[0191] The orthographic projection of the first conductive connection portion included in the second partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the second anode 502 corresponding to it on the electrode; the orthographic projection of the first conductive connection portion included in the third partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the third anode 503 corresponding to it on the substrate.

[0192] In the above-mentioned setting, the orthographic projection of the first conductive connection portion included in the second partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the second anode 502 corresponding to it on the electrode; and the orthographic projection of the first conductive connection portion included in the third partial sub-pixel driving circuit on the substrate overlaps with the orthographic projection of the third anode 503 corresponding to it on the substrate, so that the second anode 502 and the third anode 503 have higher flatness.

[0193] like Fig.15 As shown, in some embodiments, the gate 201g of the first transistor T1 is in direct contact with the corresponding gate scanning line pattern GATE.

[0194] Specifically, the gate 201g of the first transistor T1 and the corresponding gate scan line pattern GATE can be manufactured in the same layer and form an integrated structure, so that not only the gate 201g of the first transistor T1 and the corresponding gate scan line pattern GATE can be formed in the same patterning process, but also the gate of the first transistor formed can be in direct contact with the corresponding gate scan line pattern GATE, and there is no need to set an additional conductive connection part for connecting the gate of the first transistor and the corresponding gate scan line pattern GATE.

[0195] In some embodiments, the gate of the second transistor and the gate of the seventh transistor may be an integrated structure with the corresponding gate scan line graphic GATE, or the gate of the second transistor and the gate of the seventh transistor may be in direct contact with the corresponding gate scan line graphic GATE, or the gate of the second transistor and the gate of the seventh transistor may serve as part of the corresponding gate scan line graphic GATE.

[0196] In some embodiments, the orthographic projection of the first electrode of the first transistor on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding compensation functional pattern 401 on the substrate 50; and / or, the orthographic projection of the second electrode of the first transistor on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding compensation functional pattern 401 on the substrate 50.

[0197] Specifically, Fig.15 As shown, in the sub-pixel driving circuit of the above structure, the positive projection of the compensation function pattern 401 on the substrate 50 can be set to be connected to the second electrode (ie, Fig.15 The positive projection of the compensation function pattern 401 on the substrate 50 at least partially overlaps with the first electrode of the first transistor T1 (formed on the Fig.15 101ps in the figure) have their orthographic projections on the substrate 50 at least partially overlap.

[0198] The above-mentioned arrangement enables the compensation function pattern 401 to cover the second electrode of the first transistor T1 and / or the first electrode of the first transistor T1 in a direction perpendicular to the substrate 50, thereby shielding the second electrode of the first transistor T1 and / or the first electrode of the first transistor T1, thereby preventing the first transistor T1 from generating crosstalk when the data signal transmitted on the data line pattern DATA adjacent to the first transistor T1 changes; at the same time, since the second electrode of the first transistor T1 is coupled to the gate 203g of the third transistor T3, the first electrode of the first transistor T1 is coupled to the second electrode of the third transistor T3, thereby further preventing the third transistor T3 from generating crosstalk when the data signal transmitted on the data line pattern DATA adjacent to the first transistor T1 changes.

[0199] like Fig.21As shown, in some embodiments, the orthographic projection of the first electrode of the first transistor T1 on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate; and / or, the orthographic projection of the second electrode of the first transistor T1 on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.

[0200] The above-mentioned setting method not only ensures a wider distance between the compensation function pattern 401 and the first conductive connection part 701, thereby avoiding a short circuit between the compensation function pattern 401 and the first conductive connection part 701; but also avoids the formation of parasitic capacitance between the compensation function pattern 401 and the shielding pattern 301 while ensuring the flatness of the first anode 501.

[0201] In some embodiments, the sub-pixel driving circuit further includes a seventh transistor T7, the gate 207g of the seventh transistor T7 is connected to the reset signal line pattern (eg, Fig.15 RST2 in the first part of the sub-pixel driving circuit is coupled, the second electrode of the seventh transistor T7 in the first part of the sub-pixel driving circuit is coupled to the first anode 501, and there is a seventh overlapping area between the orthographic projection of the first electrode of the seventh transistor in the first part of the sub-pixel driving circuit on the substrate 50 and the orthographic projection of the corresponding compensation function graphic 401 on the substrate 50, and the first electrode of the seventh transistor is coupled to the corresponding compensation function graphic 401 through a via hole arranged in the seventh overlapping area, so as to be indirectly coupled to the corresponding initialization signal line graphic VINT through the compensation function graphic 401.

[0202] Specifically, when there is a seventh overlapping area between the orthographic projection of the first electrode of the seventh transistor on the substrate 50 and the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, a via can be made in the seventh overlapping area so that the first electrode of the seventh transistor can be coupled to the compensation function pattern 401 through the via. At the same time, since the compensation function pattern 401 is coupled to the initialization signal line, the first electrode of the seventh transistor can be indirectly coupled to the initialization signal line through the compensation function pattern 401.

[0203] In the above embodiment, the first electrode of the seventh transistor is indirectly coupled to the initialization signal line through the compensation function pattern 401, avoiding the need to produce a dedicated conductive connection portion for coupling the first electrode of the seventh transistor to the initialization signal line, thereby simplifying the production process of the display panel and saving production costs.

[0204] It is worth noting that Fig.15As shown, the orthographic projection of the compensation function pattern 401 on the substrate 50 may overlap with the orthographic projection of the second electrode of the seventh transistor on the substrate 50; or Fig.19 As shown, the orthographic projection of the compensation function pattern 401 on the substrate 50 may not overlap with the orthographic projection of the second electrode of the seventh transistor on the substrate 50 .

[0205] like Fig.15 As shown, in some embodiments, the orthographic projection of the gate of the driving transistor on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50 .

[0206] For details, please continue to see Fig.15 By setting the orthographic projection of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3) on the substrate 50 to at least partially overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, the compensation function pattern 401 can cover at least a portion of the gate of the driving transistor, thereby shielding the gate of the driving transistor, avoiding crosstalk to the driving transistor when the data signal transmitted on the data line pattern DATA adjacent to the driving transistor changes, thereby well ensuring that the driving transistor has stable working performance.

[0207] Continue reading Fig.15 In some embodiments, the orthographic projection of the gate of the driving transistor on the substrate 50 includes an overlapping first overlapping portion with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50; the orthographic projection of the first overlapping portion on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding first anode 501 on the substrate 50.

[0208] Specifically, the above-mentioned arrangement makes it possible for the gate of the driving transistor, the compensation function pattern 401 and the first anode 501 to have a common overlapping area in a direction perpendicular to the substrate 50, so that the compensation function pattern 401 can not only avoid the crosstalk to the driving transistor when the data signal transmitted on the data line pattern DATA adjacent to the driving transistor changes, but also avoid the crosstalk to the driving transistor when the driving signal transmitted on the first anode 501 changes.

[0209] Furthermore, the compensation function pattern 401 may be disposed between the gate of the driving transistor and the first anode 501 , so that the compensation function pattern 401 can better prevent the driving transistor from generating crosstalk when the driving signal transmitted on the first anode 501 changes.

[0210] like Fig.15 As shown, in some embodiments, the first plate Cst1 of the storage capacitor Cst is set with the same material as the gate scan line pattern GATE and the reset signal line pattern RST, and the second plate Cst2 of the storage capacitor Cst is set with the same material as the initialization signal line pattern VINT; the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50, are both located between the corresponding orthographic projection of the gate scan line pattern GATE on the substrate 50 and the corresponding orthographic projection of the light-emitting control signal line pattern EM on the substrate 50.

[0211] Specifically, when manufacturing each functional graphics in the display panel, some of the functional graphics in the display panel can be made of the same material. For example, some of the functional graphics with conductive properties in the display panel are made of the same material with conductive properties, and some of the functional graphics with insulating properties in the display panel are made of the same material with insulating properties.

[0212] In more detail, the first plate Cst1 of the storage capacitor Cst can be set with the same material as the gate scan line graphic GATE and the reset signal line graphic RST, and the second plate Cst2 of the storage capacitor Cst can be set with the same material as the initialization signal line graphic VINT; this setting method makes it possible to use the same process equipment in the same production environment to manufacture the first plate Cst1 of the storage capacitor Cst, the gate scan line graphic GATE and the reset signal line graphic RST; similarly, when manufacturing the second plate Cst2 of the storage capacitor Cst and the initialization signal line graphic VINT, they can also be formed in the same production environment by using the same process equipment; therefore, this setting method can effectively simplify the production process of the display panel and save the production cost of the display panel.

[0213] In addition, when laying out the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst, the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 can be set to be located between the orthographic projection of the corresponding gate scan line pattern GATE on the substrate 50 and the orthographic projection of the corresponding light-emitting control signal line pattern on the substrate 50; this setting method not only ensures that the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst can have a certain facing area in the direction perpendicular to the substrate 50, but also avoids the overlap between the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst and the gate scan line pattern GATE and the light-emitting control signal line pattern in the direction perpendicular to the substrate 50, so that the storage capacitor Cst will not form other parasitic capacitances between the gate scan line pattern GATE and the light-emitting control signal line pattern EM, thereby ensuring the stable working performance of the sub-pixel driving circuit.

[0214] In some embodiments, the functional film layer further includes a gate insulating layer (eg Fig.17 GI1 in ), and a first insulating layer (such as GI2 in GI1) located on the side of the gate insulating layer facing away from the substrate 50 Fig.17 GI2 in the figure); the first plate Cst1 of the storage capacitor Cst, the gate scan line pattern GATE and the reset signal line pattern RST are all located on the surface of the gate insulation layer facing away from the substrate 50; the second plate Cst2 of the storage capacitor Cst and the initialization signal line pattern VINT are both located on the surface of the first insulation layer facing away from the substrate 50.

[0215] Specifically, the functional film layer also includes the gate insulating layer and the first insulating layer, the gate insulating layer is used to insulate the gate and the active layer in the thin film transistor, and the first insulating layer is used to insulate the conductive functional patterns arranged in different layers in the display substrate.

[0216] When laying out the functional film layers of the display substrate, illustratively, the first plate Cst1 of the storage capacitor Cst, the gate scan line pattern GATE and the reset signal line pattern RST can all be arranged on the surface of the gate insulation layer facing away from the substrate 50; in this way, when the first plate Cst1 of the storage capacitor Cst, the gate scan line pattern GATE and the reset signal line pattern RST are made of the same material, the first plate Cst1 of the storage capacitor Cst, the gate scan line pattern GATE and the reset signal line pattern RST can be formed simultaneously in the same patterning process.

[0217] Similarly, the second plate Cst2 of the storage capacitor Cst and the initialization signal line graphic VINT can be both arranged on the surface of the first insulating layer facing away from the substrate 50; in this way, when the second plate Cst2 of the storage capacitor Cst and the initialization signal line graphic VINT are made of the same material, the second plate Cst2 of the storage capacitor Cst and the initialization signal line graphic VINT can be formed simultaneously in the same composition process.

[0218] When the functional film layers in the display panel are arranged in the above manner, not only can the layout space be effectively saved, which is beneficial to the thinning of the display panel, but also the manufacturing process of the display panel can be effectively simplified, saving the manufacturing cost of the display panel.

[0219] like Fig.15 As shown, in some embodiments, the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 both overlap with the orthographic projection of the corresponding first anode 501 on the substrate 50.

[0220] Specifically, when laying out the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst, exemplarily, the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 can be set to overlap with the orthographic projection of the corresponding first anode 501 on the substrate 50; since the first anode 501 and the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst are arranged in different layers, this layout method avoids a short circuit between the first anode 501 and the first plate Cst1 and the second plate Cst2 of the storage capacitor Cst, while making greater use of the layout space of the display panel.

[0221] like Fig.15 As shown, in some embodiments, the orthographic projection of the first plate Cst1 of the storage capacitor Cst on the substrate 50 and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 both overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50.

[0222] For details, please continue to see Fig.15By setting the positive projection of the compensation function pattern 401 on the substrate 50 to at least partially overlap with the positive projections of the first electrode plate Cst1 and the second electrode plate Cst2 of the storage capacitor Cst on the substrate 50, the compensation function pattern 401 can cover at least a portion of the first electrode plate Cst1 of the storage capacitor Cst and at least a portion of the second electrode plate Cst2. In this way, the compensation function pattern 401 can not only avoid the crosstalk to the storage capacitor Cst when the data signal transmitted on the data line pattern DATA adjacent to the storage capacitor Cst changes, but also avoid the crosstalk to the storage capacitor Cst when the driving signal transmitted on the first anode 501 changes, thereby better ensuring the stability of the operation of the sub-pixel driving circuit in the display panel.

[0223] like Fig.13 and Fig.15 As shown, in some embodiments, the central area of ​​the second plate Cst2 of the storage capacitor Cst includes an opening 302 , and the orthographic projection of the opening 302 on the substrate 50 does not overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50 .

[0224] Specifically, the area where the opening 302 on the second plate Cst2 of the storage capacitor Cst is located is generally used to form a via and a conductive portion passing through the via, and the via and the conductive portion are used to couple the functional patterns located on the upper and lower sides of the second plate together.

[0225] In the display panel provided in the above embodiment, by setting the orthographic projection of the opening 302 on the substrate 50 so as not to overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, it is possible to better avoid a short circuit between the compensation function pattern 401 and the conductive portion at the opening 302, thereby better ensuring the stability of the operation of the sub-pixel driving circuit in the display panel.

[0226] It is worth noting that when the layout space is limited, the orthographic projection of the opening 302 on the substrate 50 can also be set to overlap with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, and it is only necessary to ensure that the compensation function pattern 401 and the conductive part at the opening 302 will not short-circuit.

[0227] like Fig.15 and Fig.18 As shown, in some embodiments, the orthographic projection of the compensation function pattern 401 on the substrate 50 may be arranged to overlap with the orthographic projection of the shielding pattern 301 on the substrate; or Fig. 20As shown, in some embodiments, the orthographic projection of the compensation function pattern 401 on the substrate 50 may be set to not overlap with the orthographic projection of the shielding pattern 301 on the substrate.

[0228] In some embodiments, in a direction perpendicular to the substrate 50 , a thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or, a thickness difference between the compensation function layer and the data line layer is within a threshold range.

[0229] Specifically, when manufacturing the compensation function pattern 401, the thickness of the compensation function pattern 401 in the direction perpendicular to the substrate 50 can be set according to actual needs. For example, in the direction perpendicular to the substrate 50, the thickness difference between the compensation function layer and the power signal line layer is set within a threshold range; or, the thickness difference between the compensation function layer and the data line layer is within a threshold range; this setting method enables the compensation function layer to well compensate for the step difference generated by the power signal line layer and the data line layer.

[0230] It is worth noting that the threshold range can be set to be less than or equal to 0.1 μm, so that the thicknesses of the compensation function layer, the power signal line layer and the data line layer are close in the direction perpendicular to the substrate 50, thereby better ensuring the compensation effect for the step difference.

[0231] like Fig.24 and Fig.26 As shown, in some embodiments, the display panel further includes a plurality of second light-emitting elements; each of the second light-emitting elements includes a second anode 502, a second light-emitting pattern 602, and a second cathode, which are sequentially stacked in a direction away from the substrate 50; the second anode 502 includes a fifth edge portion 502a1 and a sixth edge portion 502a2 that are oppositely arranged along the second direction, and a second middle portion 502a3 located between the fifth edge portion 502a1 and the sixth edge portion 502a2, and the orthographic projection of the second middle portion 502a3 on the substrate 50 coincides with the orthographic projection of the second light-emitting pattern 602 on the substrate 50;

[0232] The orthographic projection of the second middle portion 502a3 on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50, and the orthographic projection of the second middle portion 502a3 on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding data line pattern DATA on the substrate 50.

[0233] Specifically, the display panel may further include a second light-emitting element, the light-emitting color of the second light-emitting element being different from that of the first light-emitting element, and the second light-emitting element may include a second anode 502, a second light-emitting pattern 602, and a second cathode, which are stacked in sequence in a direction away from the substrate 50, the second anode 502 being coupled to a corresponding second sub-pixel driving circuit in the display panel and receiving a driving signal provided by the second sub-pixel driving circuit, the second cathode receiving a common signal, and under the joint action of the second anode 502 and the second cathode, the second light-emitting pattern 602 emits light of a corresponding color.

[0234] The structure of the second anode 502 is varied. Exemplarily, the second anode 502 includes a fifth edge portion 502a1 and a sixth edge portion 502a2 that are disposed opposite to each other along the second direction, and a second middle portion 502a3 between the fifth edge portion 502a1 and the sixth edge portion 502a2.

[0235] When laying out the second light-emitting element, the orthographic projection of the second middle portion 502a3 on the substrate 50 can be set to coincide with the orthographic projection of the second light-emitting pattern 602 on the substrate 50, the orthographic projection of the second middle portion 502a3 on the substrate 50 and the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50 at least partially overlap, and the orthographic projection of the second middle portion 502a3 on the substrate 50 and the orthographic projection of the corresponding data line pattern DATA on the substrate 50 at least partially overlap; this layout method enables the middle portion of the second anode 502 to evenly cover the power signal line pattern VDD and the data line pattern DATA, so that the middle portion of the second anode 502 has a higher flatness, so that when the second light-emitting pattern 602 is formed on the second middle portion 502a3 of the second anode 502, it can be ensured that the second light-emitting pattern 602 has a higher flatness, thereby ensuring the light-emitting effect of the second light-emitting element and weakening the color shift phenomenon that occurs when the display panel is displayed.

[0236] like Fig.26 As shown, in some embodiments, the second light-emitting pattern 602 is symmetrical about a second symmetry axis, the second symmetry axis extends along the first direction, and the orthographic projection of the second symmetry axis on the substrate 50 is located inside the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50.

[0237] Specifically, the structure of the second light-emitting pattern 602 can be set according to actual needs. Exemplarily, the second light-emitting pattern 602 is set to be an axisymmetric pattern, which is more conducive to improving the uniformity of the light emitted by the second light-emitting element.

[0238] Furthermore, the second light-emitting pattern 602 can be set to be symmetrical about a second symmetry axis, which extends along the first direction, and the orthographic projection of the second symmetry axis on the substrate 50 is located inside the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50. This layout allows the central part of the second light-emitting pattern 602 to cover the power signal line pattern VDD. Since the power signal line pattern VDD extends along the first direction and is wider in a direction perpendicular to the first direction, most of the second light-emitting pattern 602 is formed on the power signal line pattern VDD, thereby better ensuring the flatness of the second light-emitting pattern 602 and weakening the color shift phenomenon that occurs when the display panel is displayed.

[0239] like Fig.24 and Fig. 27 As shown, in some embodiments, the display panel further includes a plurality of third light-emitting elements; each of the third light-emitting elements includes two sub-light-emitting elements arranged opposite to each other along the first direction, and each of the sub-light-emitting elements includes a third anode 503, a third light-emitting pattern 603, and a third cathode, which are sequentially stacked in a direction away from the substrate 50; the third anode 503 includes a seventh edge portion 503a1 and an eighth edge portion 503a2 arranged opposite to each other along the second direction, and a third middle portion located between the seventh edge portion 503a1 and the eighth edge portion 503a2, and the orthographic projection of the third middle portion on the substrate 50 coincides with the orthographic projection of the third light-emitting pattern 603 on the substrate 50;

[0240] The orthographic projection of the third middle portion on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding data line graphic DATA on the substrate 50; the orthographic projection of the seventh edge portion 503a1 on the substrate 50 at least partially overlaps with the orthographic projection of the corresponding power signal line graphic VDD on the substrate 50.

[0241] Specifically, the display panel may further include a plurality of third light-emitting elements, each of the third light-emitting elements including two sub-light-emitting elements arranged opposite to each other along the first direction, each of the sub-light-emitting elements emitting light in a different color from the first light-emitting element and the second light-emitting element, and the sub-light-emitting elements may include a third anode 503, a third light-emitting pattern 603 and a third cathode, which are sequentially stacked in a direction away from the substrate 50, the third anode 503 being coupled to a corresponding third sub-pixel driving circuit in the display panel to receive a driving signal provided by the third sub-pixel driving circuit, and the third cathode receiving a common signal, and under the joint action of the third anode 503 and the third cathode, the third light-emitting pattern 603 emits light of a corresponding color.

[0242] The structure of the third anode 503 is varied. Exemplarily, the third anode 503 includes a seventh edge portion and an eighth edge portion that are arranged opposite to each other along the second direction, and a third middle portion between the seventh edge portion and the eighth edge portion.

[0243] When laying out the third light-emitting element, the orthographic projection of the third middle part on the substrate 50 can be set to coincide with the orthographic projection of the third light-emitting pattern 603 on the substrate 50; the orthographic projection of the third middle part on the substrate 50 and the orthographic projection of the corresponding data line pattern DATA on the substrate 50 at least partially overlap; the orthographic projection of the seventh edge part on the substrate 50 and the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50 at least partially overlap; this layout method makes the overlapping area of ​​the third anode 503 and the corresponding power signal line pattern VDD and data line pattern DATA smaller, which can ensure that the third light-emitting pattern 603 has a high flatness, thereby ensuring the light-emitting effect of the third light-emitting element and weakening the color cast phenomenon that occurs when the display panel is displayed.

[0244] In some embodiments, the first light emitting element includes a red sub-pixel, the second light emitting element includes a blue sub-pixel, and the third light emitting element includes a green sub-pixel.

[0245] Specifically, the light emitting colors of the first light emitting element, the second light emitting element and the third light emitting element can be set according to actual needs. For example, the first light emitting element includes a red sub-pixel, the second light emitting element includes a blue sub-pixel, and the third light emitting element includes a green sub-pixel.

[0246] An embodiment of the present disclosure further provides a display device, comprising the display panel provided by the above embodiment.

[0247] In the display panel provided in the above embodiment, the compensation function pattern 401 can compensate for the step difference generated by the power signal line pattern VDD and the data line pattern DATA below the first anode 501, so that in the display panel, the first anode 501 included in the first light-emitting element can have a higher flatness when simultaneously covering part of the corresponding power signal line pattern VDD, part of the corresponding data line pattern DATA, and at least part of the corresponding compensation function pattern 401, thereby effectively reducing the color cast phenomenon generated by the display panel during display; therefore, the display device provided in the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the display panel provided in the above embodiment.

[0248] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0249] The embodiment of the present disclosure further provides a method for manufacturing a display panel, wherein the display panel includes a plurality of sub-pixel areas arranged in an array, and the manufacturing method includes:

[0250] A functional film layer is formed on a substrate 50; the functional film layer comprises: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer comprises a power signal line pattern VDD arranged in each of the sub-pixel regions, the data line layer comprises a data line pattern DATA arranged in each of the sub-pixel regions, the power signal line pattern VDD comprises a first portion extending along a first direction, and the data line pattern DATA extends along the first direction; the compensation function layer comprises a compensation function pattern 401 arranged in at least one of the sub-pixel regions;

[0251] A plurality of first light-emitting elements are fabricated on a side of the functional film layer facing away from the substrate 50, each of the first light-emitting elements comprising: a first anode 501, a first light-emitting pattern 601 and a first cathode which are sequentially stacked in a direction away from the substrate 50; an orthographic projection of the first anode 501 on the substrate 50 has a first overlapping region F1 with an orthographic projection of the corresponding power signal line pattern VDD on the substrate 50, a second overlapping region F2 with an orthographic projection of the corresponding data line pattern DATA on the substrate 50, and a third overlapping region F3 with an orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, and the second overlapping region F2 is located between the first overlapping region F1 and the third overlapping region F3.

[0252] Specifically, the plurality of sub-pixel areas arranged in an array can be divided into a sub-pixel area column extending along a first direction, and a sub-pixel area row extending along a second direction, the sub-pixel area column including a plurality of sub-pixel areas arranged along the first direction, and the sub-pixel area row including a plurality of sub-pixel areas arranged along the second direction; the first direction intersects with the second direction, exemplarily, the first direction includes the Y direction, and the second direction includes the X direction.

[0253] The power signal line layer includes a power signal line pattern VDD arranged in each of the sub-pixel areas, and the power signal line pattern VDD may be in a grid shape, and the grid-shaped power signal line pattern VDD includes a first portion extending along the first direction. The power signal line pattern VDD corresponds to the sub-pixel area columns one by one, and the power signal line pattern VDD is located in each sub-pixel area included in the corresponding sub-pixel area column.

[0254] The data line layer includes a data line graphic DATA arranged in each of the sub-pixel areas, the data line graphic DATA extends along the first direction, the data line graphic DATA corresponds to the sub-pixel area columns one by one, and the data line graphic DATA is located in each sub-pixel area included in the corresponding sub-pixel area column.

[0255] The display panel also includes a plurality of first light-emitting elements located on the side of the functional film layer facing away from the substrate 50, wherein the first light-emitting elements include: a first anode 501, a first light-emitting pattern 601 and a first cathode, which are sequentially stacked in a direction away from the substrate 50; when the display panel is operating, a driving signal is provided to the first anode 501, and a common signal is provided to the first cathode, so that an electric field is generated between the first anode 501 and the first cathode, thereby controlling the first light-emitting pattern 601 to emit light of a corresponding color; illustratively, the first light-emitting element includes a red light-emitting element capable of emitting red light.

[0256] The compensation function layer includes a compensation function pattern 401 disposed in at least one of the sub-pixel regions. Exemplarily, the compensation function pattern 401 corresponds to the first light-emitting element one by one;

[0257] When manufacturing the display panel, a functional film layer is first formed on the substrate 50, and then a first light-emitting element is manufactured on the side of the functional film layer facing away from the substrate 50. When manufacturing the functional film layer, the power signal line pattern VDD and the data line pattern DATA can be alternately arranged along the second direction, and the compensation function pattern 401 can be arranged near the corresponding first light-emitting element. Exemplarily, the orthographic projection of the first anode 501 in the first light-emitting element on the substrate 50 has a first overlapping area F1 with the orthographic projection of the corresponding power signal line pattern VDD on the substrate 50, has a second overlapping area F2 with the orthographic projection of the corresponding data line pattern DATA on the substrate 50, and has a third overlapping area F3 with the orthographic projection of the corresponding compensation function pattern 401 on the substrate 50, and the second overlapping area F2 is located between the first overlapping area F1 and the third overlapping area F3.

[0258] In the display panel manufactured by the manufacturing method provided by the embodiment of the present disclosure, the compensation function pattern 401 can compensate for the step difference between the power signal line pattern VDD and the data line pattern DATA below the first anode 501, so that in the display panel, the first anode 501 included in the first light-emitting element can have a higher flatness when simultaneously covering part of the corresponding power signal line pattern VDD, part of the corresponding data line pattern DATA, and at least part of the corresponding compensation function pattern 401, thereby effectively reducing the color deviation phenomenon generated by the display panel during display.

[0259] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0260] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "couple" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0261] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0262] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0263] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising: A substrate, a functional film layer disposed on the substrate, and a plurality of first light-emitting elements disposed on a side of the functional film layer facing away from the substrate; Also included are a plurality of sub-pixel regions arranged in an array; The functional film layer comprises: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer comprises a power signal line pattern arranged in each of the sub-pixel regions, the data line layer comprises a data line pattern arranged in each of the sub-pixel regions, the power signal line pattern comprises a first portion extending along a first direction, and the data line pattern extends along the first direction; the compensation function layer comprises a compensation function pattern arranged in at least one of the sub-pixel regions; The first light-emitting element comprises: a first anode, a first light-emitting pattern and a first cathode which are sequentially stacked in a direction away from the substrate; an orthographic projection of the first anode on the substrate has a first overlapping region with an orthographic projection of the corresponding power signal line pattern on the substrate, a second overlapping region with an orthographic projection of the corresponding data line pattern on the substrate, and a third overlapping region with an orthographic projection of the corresponding compensation function pattern on the substrate; In a direction perpendicular to the substrate, a thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or a thickness difference between the compensation function layer and the data line layer is within a threshold range.

2. The display panel according to claim 1, wherein: The first anode includes a first edge portion and a second edge portion disposed opposite to each other along a second direction, and a first middle portion located between the first edge portion and the second edge portion; the second direction intersects the first direction; The orthographic projection of the first edge portion on the substrate includes the first overlapping area; the orthographic projection of the second edge portion on the substrate includes the third overlapping area; and the orthographic projection of the first middle portion on the substrate includes the second overlapping area.

3. The display panel according to claim 2, wherein: The functional film layer also includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emitting control signal line layer; The gate scan line layer includes a gate scan line pattern arranged in each of the sub-pixel areas, the initialization signal line layer includes an initialization signal line pattern arranged in each of the sub-pixel areas, the reset signal line layer includes a reset signal line pattern arranged in each of the sub-pixel areas, and the light-emitting control signal line layer includes a light-emitting control signal line pattern arranged in each of the sub-pixel areas; the gate scan line pattern, the initialization signal line pattern, the reset signal line pattern and the light-emitting control signal line pattern extend along a second direction, and the second direction intersects with the first direction.

4. The display panel according to claim 3, wherein: The first anode further includes a third edge portion and a fourth edge portion disposed opposite to each other along the first direction, the first middle portion is located between the third edge portion and the fourth edge portion; the third edge portion is coupled to the first edge portion and the second edge portion respectively, and the fourth edge portion is coupled to the first edge portion and the second edge portion respectively; The orthographic projection of the first middle portion on the substrate, the orthographic projection of the corresponding gate scan line pattern on the substrate, and the orthographic projection of the corresponding reset signal line pattern on the substrate include a sixth overlapping area.

5. The display panel according to claim 4, wherein: The first anode includes a main body portion and a via connection portion, the main body portion includes the first edge portion, the second edge portion, the third edge portion, the fourth edge portion and the first middle portion; the main body portion is a centrally symmetrical figure.

6. The display panel according to claim 2, wherein: The first middle portion is a centrally symmetrical figure, and the orthographic projection of the first middle portion on the substrate coincides with the orthographic projection of the first luminous figure on the substrate.

7. The display panel according to claim 3, wherein: The display panel includes a first metal layer, a second metal layer and a third metal layer; The gate scanning line layer, the reset signal line layer and the light emitting control signal line layer are located in the first metal layer; The compensation function pattern and the data line pattern are arranged in the same layer.

8. The display panel according to claim 3, wherein: The compensation function pattern is made of conductive material and is coupled to the initialization signal line pattern.

9. The display panel according to claim 3, wherein: The display panel further comprises: a plurality of sub-pixel driving circuits, wherein a first portion of the sub-pixel driving circuits in the plurality of sub-pixel driving circuits correspond to the first light-emitting elements one by one, and the first portion of the sub-pixel driving circuits are used to drive the corresponding first light-emitting elements to emit light; the sub-pixel driving circuit comprises: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor; The gate of the first transistor is coupled to the corresponding gate scanning line pattern, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor; The gate of the second transistor is coupled to the corresponding reset signal line pattern, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor; A gate of the fourth transistor is coupled to the corresponding gate scan line pattern, a first electrode of the fourth transistor is coupled to the corresponding data line pattern, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; The first electrode of the driving transistor is coupled to the corresponding power signal line pattern, and the second electrode of the driving transistor is coupled to the corresponding first light emitting element; The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power signal line pattern.

10. The display panel according to claim 9, wherein: The sub-pixel driving circuit further includes a first conductive connection portion, and the second electrode of the first transistor is coupled to the gate of the driving transistor through the first conductive connection portion; The display panel further includes a third metal layer, and the first conductive connection portion is located in the third metal layer; The display panel further comprises a plurality of second light-emitting elements and a plurality of third light-emitting elements; the second light-emitting elements comprise a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; the third light-emitting element comprises two sub-light-emitting elements which are oppositely arranged in the first direction, and the sub-light-emitting elements comprise a third anode, a third light-emitting pattern, and a third cathode, which are sequentially stacked in a direction away from the substrate; The plurality of sub-pixel driving circuits further include a second portion of sub-pixel driving circuits and a third portion of sub-pixel driving circuits, wherein the second portion of sub-pixel driving circuits correspond one-to-one to the second light-emitting elements, and the second portion of sub-pixel driving circuits are used to drive the corresponding second light-emitting elements to emit light, and the third portion of sub-pixel driving circuits correspond one-to-one to the sub-light-emitting elements, and the third portion of sub-pixel driving circuits are used to drive the corresponding sub-light-emitting elements to emit light; The orthographic projection of the first conductive connection portion on the substrate overlaps with at least one of the following: the orthographic projection of the first anode corresponding thereto on the substrate, the orthographic projection of the second anode corresponding thereto on the substrate, and the orthographic projection of the third anode corresponding thereto on the substrate.

11. The display panel according to claim 9, wherein: The gate of the first transistor is in direct contact with the corresponding gate scanning line pattern; or, The orthographic projection of the first electrode of the first transistor on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate; or, The orthographic projection of the second electrode of the first transistor on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.

12. The display panel according to claim 9, wherein: The sub-pixel driving circuit also includes a seventh transistor, a gate of the seventh transistor is coupled to the reset signal line pattern, a second electrode of the seventh transistor in the first part of the sub-pixel driving circuit is coupled to the first anode, a first electrode of the seventh transistor has a seventh overlapping area between an orthographic projection of the first electrode of the seventh transistor on the substrate and an orthographic projection of the corresponding compensation function pattern on the substrate, and the first electrode of the seventh transistor is coupled to the corresponding compensation function pattern through a via hole arranged in the seventh overlapping area, so as to be indirectly coupled to the corresponding initialization signal line pattern through the compensation function pattern.

13. The display panel according to claim 9, wherein: The orthographic projection of the gate of the driving transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding compensation function pattern on the substrate; An orthographic projection of the gate of the driving transistor on the substrate and an orthographic projection of the corresponding compensation function pattern on the substrate include a first overlapping portion where the overlapping portions are included; An orthographic projection of the first overlapping portion on the substrate at least partially overlaps with an orthographic projection of the corresponding first anode on the substrate.

14. The display panel according to claim 9, wherein: The first plate of the storage capacitor is provided with the same material as the gate scan line pattern and the reset signal line pattern, and the second plate of the storage capacitor is provided with the same material as the initialization signal line pattern; The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the second electrode plate of the storage capacitor on the substrate are located between the orthographic projection of the corresponding gate scanning line pattern on the substrate and the orthographic projection of the corresponding light emitting control signal line pattern on the substrate; or, The functional film layer further includes a gate insulating layer and a first insulating layer located on a side of the gate insulating layer facing away from the substrate; The first electrode plate of the storage capacitor, the gate scanning line pattern and the reset signal line pattern are located on the surface of the gate insulating layer facing away from the substrate; The second electrode plate of the storage capacitor and the initialization signal line pattern are located on the surface of the first insulating layer facing away from the substrate; or, The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the second electrode plate of the storage capacitor on the substrate overlap with the orthographic projection of the corresponding compensation function pattern on the substrate; Alternatively, the central region of the second electrode plate of the storage capacitor includes an opening, and the orthographic projection of the opening on the substrate does not overlap with the orthographic projection of the corresponding compensation function pattern on the substrate.

15. The display panel according to claim 1, wherein: In a direction perpendicular to the substrate, a thickness difference between the compensation function layer and the power signal line layer is within a threshold range; or a thickness difference between the compensation function layer and the data line layer is within a threshold range; or, The display panel further includes a plurality of second light emitting elements; The second light-emitting element comprises a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; the second anode comprises a fifth edge portion and a sixth edge portion which are oppositely arranged in a second direction, and a second middle portion located between the fifth edge portion and the sixth edge portion, and an orthographic projection of the second middle portion on the substrate coincides with an orthographic projection of the second light-emitting pattern on the substrate; The orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate, and the orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate.

16. The display panel according to claim 1, wherein: The display panel further includes a plurality of second light emitting elements; The second light-emitting element comprises a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; the second anode comprises a fifth edge portion and a sixth edge portion which are oppositely arranged in a second direction, and a second middle portion located between the fifth edge portion and the sixth edge portion, and an orthographic projection of the second middle portion on the substrate coincides with an orthographic projection of the second light-emitting pattern on the substrate; The orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate, and the orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate; The second light-emitting pattern is symmetrical about a second symmetry axis, the second symmetry axis extends along the first direction, and the orthographic projection of the second symmetry axis on the substrate is located inside the orthographic projection of the corresponding power signal line pattern on the substrate.

17. The display panel according to claim 1, wherein: The display panel further includes a plurality of second light emitting elements; The second light-emitting element comprises a second anode, a second light-emitting pattern, and a second cathode, which are sequentially stacked in a direction away from the substrate; the second anode comprises a fifth edge portion and a sixth edge portion which are oppositely arranged in a second direction, and a second middle portion located between the fifth edge portion and the sixth edge portion, and an orthographic projection of the second middle portion on the substrate coincides with an orthographic projection of the second light-emitting pattern on the substrate; The orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate, and the orthographic projection of the second middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate; The display panel further includes a plurality of third light emitting elements; The third light-emitting element includes two sub-light-emitting elements arranged opposite to each other along the first direction, and the sub-light-emitting elements include a third anode, a third light-emitting pattern, and a third cathode which are sequentially stacked in a direction away from the substrate; the third anode includes a seventh edge portion and an eighth edge portion which are arranged opposite to each other along the second direction, and a third middle portion located between the seventh edge portion and the eighth edge portion, and an orthographic projection of the third middle portion on the substrate coincides with an orthographic projection of the third light-emitting pattern on the substrate; The orthographic projection of the third middle portion on the substrate at least partially overlaps with the orthographic projection of the corresponding data line pattern on the substrate; The orthographic projection of the seventh edge portion on the substrate at least partially overlaps with the orthographic projection of the corresponding power signal line pattern on the substrate.

18. A display panel, comprising: A substrate, a functional film layer disposed on the substrate, and a plurality of first light-emitting elements disposed on a side of the functional film layer facing away from the substrate; Also included are a plurality of sub-pixel regions arranged in an array; The functional film layer comprises: a power signal line layer, a data line layer and a compensation function layer; the power signal line layer comprises a power signal line pattern arranged in each of the sub-pixel regions, the data line layer comprises a data line pattern arranged in each of the sub-pixel regions, the power signal line pattern comprises a first portion extending along a first direction, and the data line pattern extends along the first direction; the compensation function layer comprises a compensation function pattern arranged in at least one of the sub-pixel regions; The first light-emitting element comprises: a first anode, a first light-emitting pattern and a first cathode which are sequentially stacked in a direction away from the substrate; an orthographic projection of the first anode on the substrate has a first overlapping region with an orthographic projection of the corresponding power signal line pattern on the substrate, a second overlapping region with an orthographic projection of the corresponding data line pattern on the substrate, and a third overlapping region with an orthographic projection of the corresponding compensation function pattern on the substrate; The display panel further comprises: a plurality of sub-pixel driving circuits, wherein a first portion of the sub-pixel driving circuits in the plurality of sub-pixel driving circuits corresponds to the first light-emitting elements one by one, and the first portion of the sub-pixel driving circuits are used to drive the corresponding first light-emitting elements to emit light; the sub-pixel driving circuit comprises: a driving transistor, a first transistor, a second transistor, a fourth transistor and a storage capacitor; The gate of the first transistor is coupled to the corresponding gate scanning line pattern, the first electrode of the first transistor is coupled to the second electrode of the driving transistor, and the second electrode of the first transistor is coupled to the gate of the driving transistor; The gate of the second transistor is coupled to the corresponding reset signal line pattern, the first electrode of the second transistor is coupled to the corresponding initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor; A gate of the fourth transistor is coupled to the corresponding gate scan line pattern, a first electrode of the fourth transistor is coupled to the corresponding data line pattern, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; The first electrode of the driving transistor is coupled to the corresponding power signal line pattern, and the second electrode of the driving transistor is coupled to the corresponding first light emitting element; The first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the corresponding power signal line pattern; The orthographic projection of the first electrode plate of the storage capacitor on the substrate and the orthographic projection of the second electrode plate of the storage capacitor on the substrate partially overlap with the orthographic projection of the corresponding first anode on the substrate.

19. The display panel according to claim 18, wherein: The first anode includes a first edge portion and a second edge portion disposed opposite to each other along a second direction, and a first middle portion located between the first edge portion and the second edge portion; the second direction intersects the first direction; The orthographic projection of the first edge portion on the substrate includes the first overlapping area; the orthographic projection of the second edge portion on the substrate includes the third overlapping area; the orthographic projection of the first middle portion on the substrate includes the second overlapping area; Wherein, the functional film layer further includes: a gate scanning line layer, an initialization signal line layer, a reset signal line layer and a light emitting control signal line layer; The gate scan line layer includes a gate scan line pattern arranged in each of the sub-pixel areas, the initialization signal line layer includes an initialization signal line pattern arranged in each of the sub-pixel areas, the reset signal line layer includes a reset signal line pattern arranged in each of the sub-pixel areas, and the light-emitting control signal line layer includes a light-emitting control signal line pattern arranged in each of the sub-pixel areas; the gate scan line pattern, the initialization signal line pattern, the reset signal line pattern and the light-emitting control signal line pattern extend along a second direction, and the second direction intersects with the first direction.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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