Encoded data dependency matrices for power efficiency scheduling

Abstract

The disclosed system may include a processor configured to encode dependencies using an encoding scheme that reduces the number of bits required to represent one or more instructions in an instruction set in an instruction buffer represented by a dependency matrix, the dependency indicates that the child instruction represented in the dependency matrix depends on the parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependencies in a dependency matrix and dispatch an instruction in an instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix of the instruction. Various other methods, systems, and computer readable media are also disclosed.

Description

Background Art

[0001] The computing device may include a processor for executing instructions from a program code such as firmware, an operating system, an application, etc. The processor may read instructions from the program code as macroinstructions. To execute the macroinstructions, the processor may first decode each macroinstruction into micro-operations, which may form a processor-level operation of the macroinstruction. For example, an addition macroinstruction may be decoded into micro-operations (μops or uops) that may cause the processor to perform a specific portion of an addition operation, such as fetching / loading data, adding the data together, storing the result of the addition, etc. The processor may execute each micro-operation to execute the corresponding macroinstruction.

[0002] Although processors can execute micro-operations in order (e.g., in an order based on the decoding of macroinstructions), some processors can improve processing efficiency by executing micro-operations out of order. Executing micro-operations out of order can reduce the wait time associated with waiting for a particular micro-operation (which may be waiting for a particular resource) by executing a different micro-operation instead of waiting. For example, a processor can execute a ready micro-operation (e.g., a micro-operation that is not waiting for any resource) before an older micro-operation that may not be ready.

[0003] The processor may include a scheduler to facilitate scheduling micro-operations to be dispatched (e.g., sent to an execution unit in the processor to execute the micro-operation). The decoded micro-operation may be forwarded to the scheduler to be queued in a buffer. When an execution unit is available to execute a micro-operation, the scheduler may select a ready micro-operation to send to the available execution unit.

[0004] A micro-operation may depend on another micro-operation to obtain a resource. In the addition example, the addition micro-operation (e.g., the consumer operation in this example) may depend on a previous load / store micro-operation (e.g., the producer operation in this example) to complete the load of the data to be added to the register (e.g., the fast local storage on the processor). In other words, the consumer operation may be ready when all of the producer operations of the consumer operation are completed. To facilitate determining whether the dependencies of a micro-operation have been resolved, the scheduler can use a dependency matrix to track which micro-operations depend on which other micro-operations. The dependency matrix can track which micro-operations in the scheduler's buffer depend on which other micro-operations in the scheduler's buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings illustrate several exemplary implementations and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0006] Figure 1is a block diagram of an exemplary system for scheduling an encoded dependency matrix of instructions.

[0007] Figure 2 is a schematic diagram of an exemplary dependency matrix.

[0008] Figure 3 is a schematic diagram of a partial encoding scheme for the dependency matrix.

[0009] Figure 4 is a schematic diagram of the complete encoding scheme for the dependency matrix.

[0010] Figure 5 is a flow chart of an exemplary method for encoding a dependency matrix for scheduling instructions.

[0011] Throughout the drawings, the same reference numerals and descriptions represent similar but not necessarily identical elements. Although the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been illustrated by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims. DETAILED DESCRIPTION

[0012] As will be described in more detail below, the present disclosure describes systems and methods for encoding a dependency matrix to more efficiently schedule instructions for a processor. In one example, a method for encoding a dependency matrix may include encoding a dependency using an encoding scheme, the dependency indicating that a newly allocated instruction to an instruction buffer represented by the dependency matrix depends on another instruction in the instruction buffer. The method may also include storing the encoded dependencies in the dependency matrix. The method may further include dispatching instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix of the instruction. The dispatch may be further based on identifying the readiness of each of the decoded dependencies.

[0013] In one example, a method for encoding a dependency matrix may include encoding a first dependency using an encoding scheme, the first dependency indicating that a first instruction represented in the dependency matrix depends on a second instruction represented in the dependency matrix. The method may also include storing the encoded first dependency in the dependency matrix. The method may further include dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction. In some examples, the dispatch may be further based on identifying the readiness of each of the decoded dependencies.

[0014] In some examples, the encoding scheme may correspond to a partial encoding scheme that groups an instruction set represented by a dependency matrix into groups and represents the source instructions of the dependency using a group value that may correspond to a group containing source instructions and an index value that may correspond to a source instruction within the group. In some examples, decoding the dependency may include using the group value to identify the group containing the source instructions and using the index value to identify which instruction in the identified group corresponds to the source instruction.

[0015] In some examples, the encoding scheme may correspond to a complete encoding scheme that uses a position value to represent a source instruction of a dependency, the position value may correspond to an index position of the source instruction in a dependency matrix. In some examples, decoding the dependency may include identifying the source instruction using the position value.

[0016] In some examples, the method may include encoding a second dependency, which may indicate that the newly allocated instruction to the instruction buffer depends on two instructions represented in the dependency matrix. In some examples, the method may include encoding a second dependency, which may indicate that the first instruction depends on a third instruction represented in the dependency matrix. The method may further include storing the encoded second dependency in the dependency matrix. The second dependency may be encoded using a second encoding scheme that is different from the encoding scheme. In some examples, the encoding scheme may include a special value indicating no dependency.

[0017] In one example, a method for encoding a dependency matrix may include storing a newly allocated instruction in a buffer for queuing the instruction. The newly allocated instruction may depend on another instruction in the buffer. The method may also include encoding the dependency using an encoding scheme that reduces the number of bits required to represent one or more instructions in the instruction set in the buffer, the dependency indicating that the child instruction represented in the dependency matrix depends on the parent instruction represented in the dependency matrix. The method may further include storing the encoded dependency in the dependency matrix. In addition, the method may include dispatching the instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix of the instruction. The dispatch may be further based on identifying the readiness of each of the decoded dependencies. In some examples, the index position in the dependency matrix may correspond to the buffer position in the buffer.

[0018] In one example, a method for encoding a dependency matrix may include storing a first instruction in a buffer for queuing the instruction. The first instruction may depend on a second instruction in the buffer. The method may also include encoding a first dependency using a coding scheme that reduces the number of bits required to represent one or more instructions in an instruction set in the buffer, the first dependency indicating that the first instruction depends on the second instruction. The method may further include storing the encoded first dependency in the dependency matrix. In addition, the method may include dispatching the first instruction based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction. In some examples, the dispatch may be further based on identifying the readiness of each of the decoded dependencies. In some examples, the index position in the dependency matrix may correspond to the buffer position in the buffer.

[0019] In some examples, the encoding scheme may correspond to a partial encoding scheme that divides an instruction set into groups and represents a source instruction of a dependency using a group value corresponding to a group containing source instructions and an index value corresponding to a source instruction within the group. In some examples, decoding the dependency may include identifying a group containing source instructions using the group value, and identifying which instruction in the identified group corresponds to the source instruction using the index value.

[0020] In some examples, the encoding scheme may correspond to a complete encoding scheme that uses a position value corresponding to a buffer position of the source instruction in the buffer to represent the source instruction of the dependency. In some examples, decoding the dependency may include identifying the source instruction using the position value.

[0021] In one example, a system for encoding a dependency matrix may include a physical memory and at least one physical processor. The physical processor may include: a buffer for queuing instructions; a dependency matrix for tracking dependencies between instructions in the buffer; and a control circuit for identifying ready instructions in the buffer using the dependency matrix. In some examples, the control circuit may be configured to encode the dependency using an encoding scheme that reduces the number of bits required to represent one or more instructions in an instruction set in the buffer, the dependency indicating that a new instruction allocated and / or written to the buffer depends on another instruction in the buffer represented in the dependency matrix. The control circuit may also be configured to store the encoded dependency in the dependency matrix in an index position corresponding to the buffer position of the first instruction in the buffer. The control circuit may further be configured to dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix of the instruction.

[0022] In one example, a system for encoding a dependency matrix may include a physical memory and at least one physical processor. The physical processor may include: a buffer for queuing instructions; a dependency matrix for tracking dependencies between instructions in the buffer; and a control circuit for identifying ready instructions in the buffer using the dependency matrix. In some examples, the control circuit may be configured to encode a first dependency using an encoding scheme that reduces the number of bits required to represent one or more instructions in an instruction set in the buffer, the first dependency indicating that a first instruction in the buffer depends on a second instruction in the buffer. The control circuit may also be configured to store the encoded first dependency in the dependency matrix in an index position corresponding to a buffer position of the first instruction in the buffer. The control circuit may be further configured to dispatch the first instruction based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction. In some examples, the dispatch may be further based on identifying the readiness of each of the decoded dependencies.

[0023] Features from any of the above-described implementations may be used in combination with each other according to the general principles described herein. These and other implementations, features and advantages will be more fully understood after reading the following detailed description in conjunction with the accompanying drawings and claims.

[0024] The present disclosure as a whole relates to an encoded dependency matrix. Although increasing the size of the scheduler's buffer can provide certain performance benefits, the corresponding dependency matrix can increase in size accordingly. Because the dependency matrix can be implemented with physical circuits, there may be additional considerations for larger dependency matrices, such as power, heat, and area on the die. As will be explained in more detail below, a specific implementation of the present disclosure can use an encoding scheme to encode dependencies. A dependency can indicate that a child instruction represented in a dependency matrix depends on a parent instruction represented in the dependency matrix. The encoding scheme can reduce the number of bits required to represent one or more instructions in an instruction set represented by a dependency matrix. The encoded dependencies can be stored in a dependency matrix. In order to determine whether an instruction is ready for dispatch, a specific implementation of the present disclosure can decode one or more dependencies stored in a dependency matrix for a given instruction, and identify the readiness of each of the decoded dependencies.

[0025] According to the general principles described herein, the features of any specific implementation described herein can be used in combination with each other. These and other specific implementations, features and advantages will be more fully understood after reading the following detailed description in conjunction with the accompanying drawings and claims.

[0026] refer to Figures 1 to 5 , the following will provide a detailed description of various specific implementations of the encoding scheme for the dependency matrix. Figure 1 A detailed description of an exemplary system for encoding a dependency matrix is ​​provided. Figures 2 to 4 Provides detailed descriptions of various encoding schemes for dependency matrices, including partial encoding schemes (e.g., Figure 3 ) and the full encoding scheme (e.g. Figure 4 ) description. Combined Figure 5 A detailed description of an exemplary method for encoding a dependency matrix is ​​provided.

[0027] Figure 1 is a block diagram of an exemplary system 100 for encoding a dependency matrix. System 100 may correspond to a computing device such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. Figure 1 As shown, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, variations or combinations of one or more of the above components, and / or any other suitable memory.

[0028] like Figure 1 As shown, the exemplary system 100 includes one or more physical processors, such as processor 110. Processor 110 generally represents a hardware-implemented processing unit of any type or form capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 can access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SOC), a portion of one or more of the above components, a variation or combination of one or more of the above components, and / or any other suitable physical processor.

[0029] In some implementations, the term "instruction" may refer to computer code that can be read and executed by a processor. Examples of instructions may include, but are not limited to, macroinstructions (e.g., program code that may need to be decoded by a processor into processor instructions that the processor can directly execute) and micro-operations (e.g., low-level processor instructions that can be decoded from macroinstructions and form part of the macroinstructions).

[0030] like Figure 1 As further shown, processor 110 includes control circuitry 112, buffer 114, and dependency matrix 116. Control circuitry 112 may correspond to a scheduler and may include circuitry and / or instructions for scheduling instructions for dispatch. Buffer 114 may correspond to a local memory of processor 110 for queuing instructions prior to dispatch and may have a buffer size N (e.g., buffer 114 may queue up to N instructions). Dependency matrix 116 may correspond to a dependency matrix for tracking which instructions in buffer 114 depend on which other instructions in buffer 114.

[0031] In some examples, the processor 110 (and / or its functional unit) can read program instructions from the memory 120 and decode the read program instructions into micro-operations. The processor 110 (and / or its functional unit) can forward the newly decoded micro-operations to the control circuit 112. The control circuit 112 can store the decoded micro-operations in the buffer 114 and update the dependency matrix 116 to reflect the newly queued micro-operations and dependencies. When the execution unit of the processor 110 is available to execute the micro-operation (in some examples, the micro-operation can be broadcast in an N-wide format, presenting the updated status of N instructions in the buffer 114), the control circuit 112 can select the ready micro-operation from the buffer 114 and dispatch it to the available execution unit. In order to determine whether the micro-operation in the buffer 114 is ready, the control circuit 112 can access the dependency matrix 116 to identify the dependencies of the micro-operation and determine whether these dependencies have been resolved (for example, whether the corresponding micro-operation has been completed). If the dependency has been resolved, control circuitry 112 may pick a micro-op for dispatch and update buffer 114 and dependency matrix 116 accordingly (eg, by removing or otherwise refreshing the associated entry).

[0032] Figure 2 A dependency matrix 200 (which may correspond to dependency matrix 116) for tracking dependencies between instructions is shown. An instruction (e.g., a consumer) may depend on a second instruction (e.g., a producer) when the instruction uses a value that is not known until the second instruction completes. For example, the instruction may perform an operation on the result of the second instruction. More specifically, the instruction may perform an operation using a value in a register that will be updated by the second instruction. Because a consumer depends on a value from its producer, the consumer may not be ready for dispatch until its producer completes execution. Therefore, dependency matrix 200 may track dependencies between instructions to facilitate tracking when instructions are ready.

[0033] Dependency matrix 200 can track dependencies between instructions stored in a buffer (e.g., buffer 114) or other similar queue structure that can queue instructions for out-of-order execution, as described herein. In some examples, dependency matrix 200 can follow the index of the buffer. For example, row 1 of dependency matrix 200 can reference instruction 1 in the buffer. Thus, the number of rows of dependency matrix 200 can correspond to the size of the buffer.

[0034] exist Figure 2 , each column of dependency matrix 200 may also correspond to each instruction in the buffer, following the same index. Thus, each row of dependency matrix 200 may indicate the dependency of the corresponding instruction (e.g., consumer) by marking the appropriate column (e.g., producer). For example, in Figure 2 In the example, row 1 has marks in columns 5 and 8 to indicate that instruction 1 (in the buffer) depends on instruction 5 and instruction 8. Figure 2 As shown, an instruction may depend on any number (such as 0, 1, 2, 3, etc.) of other instructions.

[0035] In some examples, dependency matrix 200 can be implemented with physical circuitry that can maintain the value of each matrix element (eg, a bit based on a stored charge). Figure 2 A dependency matrix 200 for a buffer size N of 8 instructions is shown. Due to the one-to-one correspondence between rows and buffer sizes and columns and buffer sizes, the dependency matrix 200 can have a size of N×N (e.g., 8×8). As the buffer size increases, the dependency matrix 200 can increase quadratically or exponentially accordingly. Because the dependency matrix 200 can be implemented with circuits, the size of the dependency matrix 200 can become very large when considering the area required for the dependency matrix 200 in the processor, the timing required to update the dependency matrix 200, and the power consumption and heat dissipation required to operate the dependency matrix 200.

[0036] The present disclosure provides various encoding schemes that can reduce the size of the dependency matrix. As described above, for N instructions, the dependency matrix can have a size of N×N. An instruction can typically depend on at most a few other instructions (e.g., typically three or less, but also less than N), so that each row in the dependency matrix can be mostly empty. Therefore, the dependency matrix can be a sparse matrix and is suitable for efficient encoding or other similar compression. In order to maintain a one-to-one correspondence with the instruction buffer, the number of rows in the dependency matrix can remain unchanged. Therefore, reducing the size of the dependency matrix can include reducing the number of columns according to partial and / or complete encoding schemes as described herein. In addition, although the present disclosure relates to rows and columns of a dependency matrix, in other examples, the matrix dimensions can be exchanged (e.g., reducing the number of rows while maintaining the number of columns, using columns instead of rows to reference instructions, etc.).

[0037] Figure 3 A dependency matrix 300 (which may correspond to dependency matrix 116) using a partial encoding scheme is shown. Similar to dependency matrix 200, dependency matrix 300 may include a number of rows (e.g., 8) corresponding to the number of instructions that may be stored in a buffer. The entire instruction set may be divided into groups, which may be identified via group values ​​310. Within each group, a specific instruction may be identified via index values ​​320.

[0038] For example, in Figure 3 , the eight instructions may be divided into two groups (e.g., "rows 1-4" and "rows 5-8"). Group value 310 may identify a particular group based on bits corresponding to each group (e.g., the first bit is for "rows 1-4" and the second bit is for "rows 5-8"), or may identify a particular group based on an identification value (e.g., using a predetermined number of bits to store a binary number or vector, with each group associated with a different numeric value). Index value 320 may identify a particular instruction within a group, for example, by using bits corresponding to each index position, although in other examples, the index value may also use an encoded value.

[0039] like Figure 3 As shown, instruction 1 (e.g., row 1) may have two dependencies. The first dependency may correspond to instructions from "rows 5-8" (as indicated by the first group value 310). The first index value 320 indicates the first instruction from the group (i.e., row 5). The second dependency identifies row 8 (e.g., the fourth instruction in "rows 5-8"). Therefore, instruction 1 depends on instruction 5 and instruction 8.

[0040] In some examples, a special value or default value may indicate no dependency. For example, row 5 may use a default value for group value 310 (e.g., defaulting to "rows 5-8") and a special value for index value 320 (e.g., a blank value). In other examples, other special values ​​may be used, such as values ​​where all bits are empty, all bits are full, etc.

[0041] Figure 3 A simple example of 8 instructions divided into two groups is shown in order to explain the partial decoding scheme. Figure 3 The specific example shown in does not necessarily reduce the number of columns from the dependency matrix 200, but the number of columns can be further reduced by increasing the number of groups. In addition, as the number of instructions increases, the column reduction may be more significant. For example, for a buffer capable of accommodating 100 instructions, if using Figure 2 For the scheme shown, a 100×100 dependency matrix may be required. However, dividing the instructions into 4 groups of 25 instructions may use 4 bits for the group value 310 (e.g., one bit per group) and 25 bits for the index value 320 (e.g., one bit for each instruction in a group), so that each dependency can be encoded with 29 bits. For two dependencies, the size of the dependency matrix may be 100×58. The matrix size may be further adjusted by adjusting the number of groups and further encoding the group value 310 and / or the index value 320.

[0042] Figure 4 A dependency matrix 400 (which may correspond to dependency matrix 116) using a complete encoding scheme is shown. Similar to dependency matrix 200 and dependency matrix 300, dependency matrix 400 may include a number of rows (e.g., 8) corresponding to the number of instructions that may be stored in a buffer. Each instruction may be identified by encoding its index or buffer position in the buffer as a position value 410.

[0043] For example, Figure 4 In the example, each dependency may be stored in a vector or bit sequence, which may include, for example, a binary number that may uniquely identify each instruction in the buffer. As indicated by the corresponding position value 410, row 1 (e.g., instruction 1) depends on row 5 and row 8. Figure 4 As shown, no dependency can be indicated by a special value.

[0044] Figure 4 A simple example of eight instructions is shown in order to explain the complete decoding scheme. When the number of bits required for the two position values ​​410 is less than the total number of instructions, the number of columns can be reduced from the dependency matrix 200 (and in some examples, the dependency matrix 300). Furthermore, as the number of instructions increases, the column reduction may be more significant. For example, for a buffer capable of accommodating 100 instructions, if one uses Figure 2The scheme shown may require a dependency matrix of 100×100. However, encoding 100 index positions may require at least a 7-bit vector (e.g., 2^7=128 to ensure a unique value for each index position). For two dependencies, the size of the dependency matrix may be 100×14.

[0045] In addition, in some examples, a hybrid encoding scheme can be used, where a partial encoding scheme can combine aspects of a complete encoding scheme and / or vice versa. In another example, some dependency entries (e.g., a first dependency) can be encoded with one encoding scheme, while other dependency entries (e.g., a second dependency) can be encoded with a different encoding scheme.

[0046] Figure 5 is a flow chart of an exemplary computer-implemented method 500 for encoding a dependency matrix. Figure 5 The steps shown may be implemented by any suitable computer executable code and / or computing system (including Figure 1 In one example, Figure 5 Each of the steps shown in may represent an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0047] like Figure 5 As shown, at step 502, one or more of the systems described herein may encode a first dependency using an encoding scheme that reduces the number of bits required to represent one or more instructions in an instruction set represented by a dependency matrix, the first dependency indicating that a first instruction represented in the dependency matrix depends on a second instruction represented in the dependency matrix. For example, the control circuit 112 may encode the first dependency using an encoding scheme described herein.

[0048] The systems described herein may perform step 502 in a variety of ways. In one example, after storing the newly received instruction in buffer 114, control circuitry 112 may determine that the instruction depends on at least a second instruction (e.g., a source instruction) in buffer 114. Control circuitry 112 may then use, for example, the partial encoding scheme described herein (see Figure 3 ) and / or the complete coding scheme (see Figure 4 ) to encode this dependency.

[0049] As described herein, a partial encoding scheme may include dividing an instruction set into groups and using a group value and an index value to represent a source instruction of a dependency. The group value may correspond to a group containing a source instruction, and the index value may correspond to a source instruction within the group. As described herein, a complete encoding scheme may include using a position value to represent a source instruction of a dependency, and the position value may correspond to an index position of the source instruction in a dependency matrix.

[0050] In some examples, the first instruction may depend on a third instruction in buffer 114, such that the first instruction may depend on two instructions (e.g., the second instruction and the third instruction). Control circuitry 112 may encode the second dependency of the instruction using the same or a different encoding scheme than that used to encode the first dependency. For example, Figure 3 and Figure 4 As shown, line 1 (eg, instruction 1) depends on lines 5 and 8. In some examples, the second dependency can be an update and / or a portion of the first dependency.

[0051] Returning to method 500 , at step 504 , one or more of the systems described herein may store the encoded first dependency in a dependency matrix. For example, control circuitry 112 may store the encoded first dependency in dependency matrix 116 .

[0052] The systems described herein may perform step 504 in various ways. In one example, control circuitry 112 may store the encoded first dependency in dependency matrix 116 as part of a final step of encoding. In some examples, control circuitry 112 may also store the encoded second dependency in dependency matrix 116. In such examples, control circuitry 112 stores both dependencies in dependency matrix 116 as part of a process for encoding and / or storing all dependencies of an instruction.

[0053] At step 506, one or more of the systems described herein may dispatch the first instruction based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction. For example, control circuitry 112 may dispatch the first instruction based on decoding the dependencies in dependency matrix 116.

[0054] The systems described herein may perform step 506 in various ways. In some examples, the control circuitry 112 may also dispatch the first instruction based on identifying the readiness of each of the decoded dependencies. For example, the decoded dependencies may be ready when the corresponding instruction has completed loading data into the appropriate register. In some examples, in a partial encoding scheme, the control circuitry 112 may decode the encoded dependencies by using a group value to identify a group containing a source instruction and using an index value to identify which instruction in the identified group corresponds to the source instruction. In some examples, in a full encoding scheme, the control circuitry 112 may decode the encoded dependencies by using a position value to identify the source instruction in the buffer 114.

[0055] The systems and methods described herein provide a coding scheme that can reduce the size of a dependency matrix associated with an instruction buffer of a processor. Reducing the size of the dependency matrix can reduce the area that may be required to implement the dependency matrix and the storage device and the wiring to the storage device. In some examples, the dependency matrix with reduced size can allow the size of the instruction buffer to be increased without exhausting the available space in the processor. In addition, the coding scheme can be selected based on timing considerations. Certain operations can broadcast signals to wake up sub-operations when completed. In some examples, sub-operations may not necessarily wake up grandchildren operations. A complete coding scheme may be suitable for such examples. In other examples, operations (e.g., address generation operations, storage operations, etc.) may not require broadcasts for waking up sub-operations. In such examples, timing may be critical, making partial coding schemes more suitable. In addition, the coding scheme can be applicable to other matrices that the processor can implement, particularly sparse matrices.

[0056] As described above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions (such as those contained in the modules described herein). In its most basic configuration, these computing devices can each include at least one storage device and at least one physical processor.

[0057] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device can store, load, and / or maintain one or more modules described herein. Examples of storage devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, variations or combinations of one or more of the above components, or any other suitable memory.

[0058] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, a physical processor can access and / or modify one or more modules stored in the above-mentioned memory device. Examples of physical processors include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SOC), a portion of one or more of the above components, a variation or combination of one or more of the above components, or any other suitable physical processor.

[0059] In addition, one or more of the elements described herein can convert data, physical devices, and / or representations of physical devices from one form to another. For example, one or more of the units described herein can receive instruction data to be converted, convert the instruction data, output conversion results to queue instructions, use the conversion results to determine dependencies, and store conversion results to track dependencies between instructions. Additionally or alternatively, one or more of the modules described herein can convert a processor, a volatile memory, a non-volatile memory, and / or any other part of a physical computing device from one form to another by executing on a computing device, storing data on a computing device, and / or otherwise interacting with a computing device.

[0060] In some implementations, the term "computer-readable medium" generally refers to any form of device, carrier, or medium that can store or carry computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media, such as carrier waves, and non-transitory media, such as magnetic storage media (e.g., hard drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and BLU-ray disks), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0061] The process parameters and order of steps described and / or shown herein are provided as examples only and may be changed as desired. For example, although the steps shown and / or described herein may be shown or discussed in a particular order, the steps do not necessarily need to be performed in the order shown or discussed. The various exemplary methods described and / or shown herein may also omit one or more of the steps described or shown herein, or include additional steps in addition to those disclosed steps.

[0062] The foregoing description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0063] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) used in the specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. In addition, the terms "a" or "an" used in the specification and claims should be understood to mean "at least one of..." Finally, for ease of use, the terms "including" and "having" (and their derivatives) used in the specification and claims are interchangeable with the word "comprising" and have the same meaning as the word "including".

Claims

1. A method, comprising: encoding a first dependency using an encoding scheme, the first dependency indicating that a first instruction represented in a dependency matrix depends on a second instruction represented in the dependency matrix; storing the encoded first dependency in the dependency matrix; as well as The first instruction is dispatched based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction.

2. The method according to claim 1, wherein: The encoding scheme corresponds to a partial encoding scheme that includes dividing the instruction set represented by the dependency matrix into groups, and using a group value corresponding to the group containing the subject instruction and an index value corresponding to the subject instruction within the group to represent the subject instruction of dependency.

3. The method according to claim 2, wherein: In the partial encoding scheme, the decoding includes: identifying the group containing the subject instruction using the group value; and The index value is used to identify which instruction in the identified group corresponds to the subject instruction.

4. The method according to claim 1, wherein: The encoding scheme corresponds to a complete encoding scheme that includes representing the subject instructions of dependencies using position values ​​corresponding to index positions of the subject instructions in the dependency matrix.

5. The method according to claim 4, wherein: In the full encoding scheme, the decoding includes identifying the subject instruction using the location value.

6. The method according to claim 1, further comprising: encoding a second dependency indicating that the first instruction depends on a third instruction represented in the dependency matrix; as well as The encoded second dependency is stored in the dependency matrix.

7. The method according to claim 6, wherein: The second dependency is encoded using a second encoding scheme different from the encoding scheme.

8. The method according to claim 1, wherein: The encoding scheme includes a special value indicating no dependency.

9. The method according to claim 1, wherein: Dispatching the first instruction is further based on identifying a readiness of each of the decoded one or more dependencies.

10. A method comprising: storing a first instruction in a buffer for queuing instructions, wherein the first instruction is dependent on a second instruction in the buffer; encoding a first dependency indicating that the first instruction depends on the second instruction using an encoding scheme that reduces the number of bits required to represent one or more instructions in the instruction set in the buffer; storing the encoded first dependency in a dependency matrix; as well as The first instruction is dispatched based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction.

11. The method according to claim 10, wherein: The encoding scheme corresponds to a partial encoding scheme that includes dividing the instruction set into groups and representing the subject instructions of dependency using a group value corresponding to the group containing the subject instructions and an index value corresponding to the subject instructions within the group.

12. The method according to claim 11, wherein: In the partial encoding scheme, the decoding includes: identifying the group containing the subject instruction using the group value; and The index value is used to identify which instruction in the identified group corresponds to the subject instruction.

13. The method according to claim 10, wherein: The encoding scheme corresponds to a complete encoding scheme that includes representing the subject instructions of dependencies using position values ​​corresponding to buffer positions of the subject instructions in the buffer.

14. The method according to claim 13, wherein: In the full encoding scheme, the decoding includes identifying the subject instruction using the location value.

15. The method according to claim 10, further comprising: encoding a second dependency indicating that the first instruction depends on a third instruction in the buffer; as well as The encoded second dependency is stored in the dependency matrix.

16. The method according to claim 10, wherein: The encoding scheme includes a special value indicating no dependency.

17. The method according to claim 10, wherein: The index positions in the dependency matrix correspond to buffer positions in the buffer.

18. A system, comprising: Physical storage; as well as At least one physical processor, the at least one physical processor comprising: a buffer for queuing instructions; a dependency matrix for tracking dependencies between instructions in the buffer; and A control circuit is configured to identify ready instructions in the buffer using the dependency matrix, the control circuit being configured to: encoding a first dependency indicating that a first instruction in the buffer depends on a second instruction in the buffer using an encoding scheme that reduces the number of bits required to represent one or more instructions in the instruction set in the buffer; storing a first dependency encoded in the dependency matrix in an index location corresponding to a buffer location of the first instruction in the buffer; and The first instruction is dispatched based at least on decoding one or more dependencies stored in the dependency matrix of the first instruction.

19. The system of claim 18, wherein: The encoding scheme corresponds to a partial encoding scheme that includes dividing the instruction set into groups and representing the subject instructions of dependency using a group value corresponding to the group containing the subject instructions and an index value corresponding to the subject instructions within the group; as well as In the partial encoding scheme, the decoding includes: identifying the group containing the subject instruction using the group value; as well as The index value is used to identify which instruction in the identified group corresponds to the subject instruction.

20. The system of claim 18, wherein: The encoding scheme corresponds to a complete encoding scheme including representing the subject instructions of dependencies using position values ​​corresponding to buffer positions of the subject instructions in the buffer; and In the full encoding scheme, the decoding includes identifying the subject instruction using the location value.

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