Bayesian decomposition of semiconductor device mismatch performance

Abstract

Bayesian reasoning and modeling techniques and model decomposition may be used to improve mismatch performance in semiconductor processing devices by identifying sources of intrinsic and extrinsic variations in performance. A network of causal relationships between processing and hardware in semiconductor processing devices may be accessed to generate a first Bayesian model for a first semiconductor processing device using the causal relationships and performance data in the network. A second Bayesian model for a second semiconductor processing device may also be generated using causal relationships and associated performance data in the network. Response distributions generated by the first Bayesian model and the second Bayesian model may be compared to identify effects of intrinsic / extrinsic variables by decomposing the model transfer function to determine whether performance of the first semiconductor processing device matches performance of the second semiconductor processing device.

Description

Technical Field

[0001] The present disclosure generally describes identifying and correcting mismatched performance between semiconductor processing devices. More specifically, the present disclosure describes a method for using Bayesian modeling and decomposition to identify intrinsic / extrinsic variations to adjust device operating parameters to achieve optimal results. Background Art

[0002] Complex engineered systems can fail in many different ways. As engineered systems become more complex, the number of system functions that can have a causal impact on a failure continues to increase. When a failure occurs, it is often difficult to point to the precise function that caused the failure. However, despite this difficulty, accurately identifying the causal risk factors for engineered failures is critical to preventing such failures from continuing to occur in the future. The most advanced approach today uses a linguistic scale basis to rank the risk of each input in a semi-quantitative manner. For example, this ranking can be performed by a team of subject matter experts using a numerical scale (e.g., a scale of 1-5). Although this approach uses a numerical ranking system, these rankings are often assigned based on the user's intuition and personal experience, which makes these rankings susceptible to cognitive biases. As a result, manual ranking systems result in longer times to identify the root causes of engineering failures in complex systems. Summary of the invention

[0003] In some embodiments, a method for identifying mismatched performance between semiconductor processing devices may include accessing a network of causal relationships between processes and hardware in a semiconductor processing device; using the causal relationships in the network and first performance data to generate a first Bayesian model for a first semiconductor processing device; using the causal relationships in the network and second performance data to generate a second Bayesian model for a second semiconductor processing device; and comparing response distributions generated by the first Bayesian model and the second Bayesian model to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device.

[0004] In some embodiments, a system may include one or more processors and one or more memory devices storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations. The operations may include accessing a network of causal relationships between processes and hardware in a semiconductor processing device; using the causal relationships in the network and first performance data to generate a first Bayesian model for a first semiconductor processing device; using the causal relationships in the network and second performance data to generate a second Bayesian model for a second semiconductor processing device; and comparing response distributions generated by the first Bayesian model and the second Bayesian model to determine whether performance of the first semiconductor processing device matches performance of the second semiconductor processing device.

[0005] In some embodiments, one or more non-transitory computer-readable media may include instructions that, when executed by one or more processors, cause the one or more processors to perform operations including accessing a network of causal relationships between processes and hardware in a semiconductor processing device; using the causal relationships in the network and first performance data to generate a first Bayesian model for a first semiconductor processing device; using the causal relationships in the network and second performance data to generate a second Bayesian model for a second semiconductor processing device; and comparing response distributions generated by the first Bayesian model and the second Bayesian model to determine whether performance of the first semiconductor processing device matches performance of the second semiconductor processing device.

[0006] In any embodiment, any and all of the following features may be implemented in any combination without limitation. The method / operation may also include identifying changes in extrinsic variables in the first Bayesian model and the second Bayesian model, the changes indicating the sensitivity of the response distribution to the hardware components in the first semiconductor processing device and the second semiconductor processing device. The method / operation may also include identifying changes in intrinsic variables in the first Bayesian model and the second Bayesian model, the changes indicating the sensitivity of the response distribution to the connection between the hardware components in the first semiconductor processing device and the second semiconductor processing device. The first Bayesian model may be represented using a transfer function. The transfer function may represent the main effects, nonlinear effects, and interaction effects of the first semiconductor processing device that affect the response distribution of the first Bayesian model. The method / operation may also include performing a first decomposition of the transfer function by subtracting the second Bayesian model from the first Bayesian model to produce changes in different extrinsic variables within the operating range of the different extrinsic variables, and / or performing a second decomposition of the transfer function by aggregating each factor in the transfer function into a coefficient change of the intrinsic variable representing the different extrinsic variable. The system may be implemented on a controller of a semiconductor processing chamber. The system may be implemented on a central platform that communicates with controllers of multiple semiconductor processing chambers in the facility. The system may be implemented on a remote server that communicates with multiple different semiconductor processing facilities, each of which operates multiple semiconductor processing chambers. The step of determining whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device may include calculating the JS divergence between the response distributions generated by the first Bayesian model and the second Bayesian model, and / or determining whether the similarity between the response distributions generated by the first Bayesian model and the second Bayesian model falls within a threshold of the Region of Practical Equivalence (ROPE). The method / operation may also include performing a sensitivity analysis on external variables to identify at least one external variable that causes a mismatch in performance between the first semiconductor processing device and the second semiconductor processing device. The non-transitory computer-readable medium, processor, and / or memory device may be distributed between the controller of the semiconductor processing chamber and the remote server. The method / operation may also include identifying the cause of the mismatch in performance between the first semiconductor processing device and the second semiconductor processing device. The method / operation may also include using the network of causal relationships to identify hardware devices, wherein operating parameters of the hardware devices may be adjusted to correct for a mismatch in performance between the first semiconductor processing device and the second semiconductor processing device. The network of causal relationships may include a node layer representing on-wafer effects, a node layer representing functional requirements, and a node layer representing hardware components.The method / operation may also include accessing a system functional diagram comprising a data structure that associates requirements of a first semiconductor processing device with functional requirements of components in the first semiconductor processing device, then with technology components, and then with on-wafer effects; and automatically generating a network based on the functional diagram. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The nature and advantages of the various embodiments may be further understood with reference to the remainder of the specification and the accompanying drawings, in which similar reference numerals are used in some of the drawings to represent similar components. In some cases, a sub-label is associated with a reference numeral to represent one of multiple similar components. When a reference numeral is cited without specifying an existing sub-label, it is intended to represent all such multiple similar components.

[0008] FIG. 1 shows a simplified diagram of a system for operating a SAE software application according to some embodiments.

[0009] FIG. 2 illustrates a flow chart of a method for detecting mismatched performance between semiconductor processes, according to some embodiments.

[0010] 3 illustrates a mapping between product requirements and functional requirements that can be used to generate an interconnected network of cause-effect relationships according to some embodiments.

[0011] 4 illustrates a flow diagram of a process for building one or more models based on Bayesian reasoning, according to some implementations.

[0012] FIG. 5 illustrates how the above prior knowledge can be combined with experimental data to design a model of a semiconductor processing system.

[0013] FIG. 6A shows a model for two different chambers for comparing chamber performance, according to some embodiments.

[0014] FIG. 6B shows an example of how a deposition chamber may be used to perform the matching process described above, according to some embodiments.

[0015] FIG. 6C illustrates the performance response between matched and mismatched thickness locations according to some embodiments.

[0016] FIG. 7 illustrates the results of a sensitivity analysis of predicted responses according to some embodiments.

[0017] FIG. 8 illustrates intrinsic variation at two locations on a substrate according to some embodiments.

[0018] FIG. 9 illustrates how the causal relationships described in the network structure may be used to change the operating parameters of a process according to some embodiments.

[0019] FIG. 10 illustrates an exemplary computer system in which various embodiments may be implemented. DETAILED DESCRIPTION

[0020] This article describes an implementation for providing an unbiased, physics-based and probability-driven method to identify performance mismatches in semiconductor processing systems. This method is mainly based on probabilistic mathematics, physical simulation, physical experiments and quantitative analysis, which eliminates cognitive biases that previously plagued system failure analysis. This system combines physics-based cause-effect relationships to produce a Bayesian network that links functional causes to fault outputs. The Bayesian network can be generated directly from functional mapping, device requirements and design / technology requirements. Statistical checks can then be used to verify the Bayesian network, and discrete groupings of sensor data and / or simulation data can be used to set the probability of each node in the network. The Bayesian network can then represent known causal and probabilistic relationships between operational requirements, technical functions and design / technology components.

[0021] This network can be used to represent the cause-and-effect interconnected processes of a semiconductor processing device, such as a substrate processing chamber. This network can capture the system energy flow in a set of interconnected program and hardware elements to represent the cause-and-effect relationships in a real system. After verification, such as through structured physical experiments, these cause-and-effect relationships in the network can be used to build models, which can then be used to simulate system performance responses in the form of system transfer functions. The transfer function can be decomposed and used to analyze various extrinsic and / or intrinsic processing characteristics. The results can be used to compare two different processes, whether on the same machine using different substrates or on different machines using different substrates. For example, the system can determine whether the resulting substrate characteristics (e.g., film thickness) will match between the two different systems based on the model output. Subsequently, the process can identify and measure extrinsic changes that represent the contribution of tolerances or degradation of architectural elements (e.g., knobs and hardware) and their interaction with system performance. The process can also identify and measure intrinsic changes that represent the contribution of the interconnection strength of the architectural elements of the system under certain operating conditions. The identified extrinsic and / or intrinsic changes can then be used to identify possible causes of potential mismatches and update the operating parameters of the system to produce matching results.

[0022] The process of generating a network of cause-effect relationships, modeling the system, using the model to compare different device responses, identifying extrinsic and / or intrinsic changes, and adjusting device operating parameters can be performed in whole or in part by a software program. For example, an automated statistics-aided engineering (SAE) software application can be operated on one or more computing systems to perform the operations described herein. These computing systems can be distributed in different facilities involved in semiconductor manufacturing processes.

[0023] FIG. 1 illustrates a simplified diagram of a system 100 for operating an SAE software application 108 according to some embodiments. A semiconductor processing facility 102 may include a plurality of different semiconductor processing devices 106. The semiconductor processing devices 106 may include semiconductor processing stations, such as etching chambers, deposition chambers, polishing chambers, cleaning chambers, metrology chambers, lithography chambers, and / or any other type of semiconductor processing chamber. Some of the semiconductor processing devices 106 may include a controller 107 integrated with or in communication with the semiconductor processing device 106. For example, a controller 107-1 may be integrated with the semiconductor processing device 106-1 to execute recipes and control operating parameters and environments within the semiconductor processing device 106-1. Alternatively, the controller 107-1 may be communicatively coupled to the semiconductor processing device 106-1 via wired or wireless communications, such as an EtherCAT connection.

[0024] The controller 107 may include any type of computing system. For example, the controller 107 may include one or more processors and one or more memory devices. The memory device may include instructions for causing the processor to perform operations associated with the SAE software application 108. For example, the instructions may be stored on one or more non-transitory computer-readable media for execution by the processor. In such a configuration as shown in FIG. 1 , the controller 107 may operate an instance of the SAE software application 108 at the semiconductor processing device 106. This may allow an operator of the semiconductor processing device 106 to perform the analysis and optimization operations described in detail below directly at the semiconductor processing device itself. For example, the controller 107 may include a display device and I / O devices (e.g., a keyboard, a mouse, etc.) that the operator may use to interact with the SAE software application 108. An example of hardware / software that may be used to implement the controller 107 is described in detail below in conjunction with FIG. 10 .

[0025] Alternatively or additionally, the semiconductor processing facility 102 may include a central platform 110 in communication with the controller 107 and / or some or all of the semiconductor processing devices 106. The central platform 110 may include a server that may perform operations such as monitoring the performance of the semiconductor processing devices 106, updating the software of the controller 107, collecting and storing data measured from semiconductor substrates or recorded during semiconductor processing, and / or other data monitoring operations. In some embodiments, the central platform 110 may also include an instance of the SAE software application 108. This may allow an operator of the central platform 110 to analyze data from different semiconductor processing devices 106 and compare the performance of these devices using the SAE software application 108. For example, the central platform 110 may collect data from various semiconductor processing devices 106 in the semiconductor processing facility 102, generate and validate models based on the collected data and domain knowledge, and simulate the performance of the semiconductor processing devices within a range of operating parameters. The operator at the central platform 110 may then analyze the simulation results to identify intrinsic and / or extrinsic factors that may cause performance mismatches between the various devices in the semiconductor processing facility 102.

[0026] In some configurations, the remote monitoring facility 104 may include a server that also communicates with the semiconductor processing facility 102. For example, a remote server 112 located in a separate facility may communicate with the central platform 110 and / or any individual controllers 107 to collect and aggregate performance data. The remote server 112 may also include an instance of the SAE software application 108 so that data can be collected, analyzed, and optimized remotely. Although not explicitly shown in FIG. 1 , the remote monitoring facility 104 may communicate with many semiconductor processing facilities. Thus, the remote monitoring facility 104 may include a data storage 114 that collects operational data of semiconductor processing devices 106 from a plurality of different processing facilities in addition to the semiconductor processing facility 102 shown in FIG. 1 . This allows the remote server 112 to compare the performance of semiconductor processing devices 106 operating at different facilities. For example, the remote monitoring facility 104 may be owned / operated by the manufacturer of at least some of the semiconductor processing devices 106. As the semiconductor processing device 106 is sold or distributed to different semiconductor processing facilities, the remote monitoring facility 104 may continue to monitor and collect data from these facilities for analysis by the SAE software application 108. This allows the results calculated by the SAE software application 108 (e.g., the cause of a performance mismatch) to be adjusted not only at the semiconductor processing facility 102 for immediate improvement, but it may also be used by the semiconductor processing device manufacturer to improve the design of the semiconductor processing device 106.

[0027] A prior art problem in semiconductor manufacturing occurs when the same semiconductor manufacturing process is performed with the same or similar equipment, but produces different results, referred to herein as a "mismatch." For example, a single semiconductor processing chamber may repeatedly execute a recipe to perform a particular process on a batch of semiconductor substrates. A "recipe" may include a set of operating parameters (e.g., current levels, timing, power levels, gas flow rates, etc.) performed by the semiconductor processing chamber. However, not all semiconductor substrates in the batch will achieve the same results, even if the same recipe and chamber are used throughout the batch. For example, the thickness of a deposited film may vary between individual substrates or between locations on the same substrate. The embodiments described herein provide a method for identifying when these mismatched results occur and identifying possible causes and specific actions that can be taken to produce better results.

[0028] In another example, two different semiconductor processing stations may operate on separate semiconductor substrates. For example, two etch chambers of the same type (same manufacturer, recipe, operating parameters, etc.) may be configured to operate in the same manner, executing the same recipe on the same type of substrate. However, the substrates produced by the processing on the two etch chambers may not have exactly the same results. The embodiments described herein also provide a method for identifying when a mismatch occurs between different semiconductor processing devices of the same type, and can be used to identify possible causes and specific actions that can be taken to produce better results.

[0029] FIG2 shows a flowchart 200 of a method for identifying mismatched performance between semiconductor processing devices according to some embodiments. Semiconductor processing may include the same processing performed by the same processing chamber or by different chambers as described above. This method can be performed using any computer system described in the present disclosure, including the controller, server, or central platform in FIG1. ​​Each step in flowchart 200 is described in detail in FIGS. 3 to 9, and reference will be made to these figures when describing each step. In addition, this method is not particularly limited to semiconductor processing chambers. Semiconductor processing devices may also include parts, modules, or components. For example, mismatches between different parts can be detected, and this method can be used to identify potential sources of performance mismatches.

[0030] The method may include accessing an interconnected network of cause-effect relationships between processes and hardware in a semiconductor processing device (202). The network may begin with a performance definition or product specification of a customer-specified result, which may flow into a process specification, which in turn flows into a specific hardware setting and device. The network may include components of a semiconductor processing system and may represent energy and information flow through the system. In some cases, a system performing the method may begin by importing a system functional map and / or importing a component functional map. These functional maps may be maintained in specialized software that tracks these relationships between functions, components, and results, and the software may provide data structures representing these functional maps to the method. Thus, the method steps may include using these functional maps to generate an interconnected network of cause-effect relationships.

[0031] FIG3 illustrates a mapping between product requirements and functional requirements that can be used to generate a cause-and-effect interconnected network according to some embodiments. For example, some embodiments may include a chemical vapor deposition (CVD) chamber for depositing films on a semiconductor substrate. The operations and data generated by the CVD chamber are used only as an example and are not meant to be limiting. Any other type of semiconductor processing equipment may be used in a similar manner.

[0032] Product requirements 302 may represent requirements placed on the system for proper operation. A "product" may be a product of the chamber, such as a semiconductor wafer having a film deposited thereon. These product requirements 302 may be set by a customer and may specify a performance metric for the chamber or a characteristic of the resulting wafer. Product requirements may include measurable outputs such as deposition rate, film thickness, resistivity, layer impurities, yield, process time, and / or other results of a semiconductor manufacturing process. Product requirements may be expressed at the system level, and component requirements may be expressed at the component level.

[0033] A set of functional requirements 304 may be derived directly from the product requirements 302. For example, the product requirements 302 may be mapped to a set of functional requirements 304 that may have a cause-and-effect relationship with the product requirements 302. Based on the product requirements 302, a set of functional requirements 304 may be selected to be built into the processing chamber in order to produce the product requirements 302. For example, film thickness may be directly mapped to control wafer temperature, control precursor dosage, and / or other functional requirements 304. The mapping may mean that the performance of the functional requirements 304 may affect the product requirements 302.

[0034] The mapping may be generated in a user interface where a subject matter expert may provide a relationship in a matrix between specific product requirements 302 and specific functional requirements 304, as shown in FIG3. For example, a known relationship between a product requirement and a functional requirement may be represented. A user may provide an estimate of the strength of the relationship between the product requirement and the functional requirement. This may be characterized using a numerical requirement (e.g., 5.00). Thus, this step may include contributions of domain knowledge provided by an operator to form these relationships.

[0035] The multi-level mapping may be represented by different data structures. For example, some embodiments may also map functional requirements 304 to design requirements 306. Design requirements may represent different operations performed by technologies or components in the system. Functional requirements 304 to control pressure or control wafer temperature may be related to technical requirements 306, such as controlling base temperature, controlling the flow of various gases or other reactants (e.g., NH3, etc.), controlling chamber pressure, and / or other requirements that may be imposed on different technical components. Similarly, design requirements 306 may be mapped to a set of hardware requirements 308, which represent specific hardware devices or components present in a semiconductor processing device.

[0036] To generate the network structure 300, the structure may include a plurality of nodes. Each individual node may represent an entry in the requirements 302, 304, 306, 308 described above. The edges between these nodes in the data structure may represent the relationships between the nodes. These relationships may be causal relationships between the functions, components, and / or requirements represented by the nodes. For example, the relationship or edge between two nodes in the data structure may indicate a causal relationship between a function in a parent node and a result in a child node.

[0037] In some embodiments, the system may automatically import data structures representing requirements 302, 304, 306, 308 to establish the nodes and relationships shown in the network structure 300. It should be noted that some embodiments do not require relationships to be established between each node represented in the data structure. For example, the strength of a relationship (e.g., a numerical score) may be affected by a threshold. If the strength of a relationship is not greater than a threshold, it is not necessary to represent the relationship in the network structure 300. Other embodiments may represent all relationships. This method may be performed automatically by creating a node for each function, requirement, component, etc., each of which has at least one relationship with another function, requirement, component, etc. that has a sufficient numerical score or a user-specified qualitative relationship. The method may then generate relationships between nodes based on the relationships specified in the imported data structure.

[0038] In the example of FIG. 3 , different levels of requirements may be mapped into layers of nodes in the network structure 300 . For example, the nodes in the topmost layer of the network structure 300 may represent hardware requirements 308 . The nodes in the next highest layer may represent design requirements 306 , and so on. In general, the nodes (and any other internal layers not specifically shown in FIG. 3 ) may be referred to as component functions. For example, controlling gas flow may be a functional requirement corresponding to a component function, such as a gas valve that controls gas flow. Similarly, the partial pressure of a gas at a specific location on a wafer may also be included as a component function because it is related to the requirements of the gas control component. The nodes in the bottom layer of the network structure 300 may represent measurable on-wafer effects and represent product requirements 302 . Therefore, the bottom layer of nodes may represent on-wafer effects, and all nodes on which on-wafer effects depend may be broadly referred to as component functions or hardware devices. The relationships in the network may represent the causal dependencies between various component functions and the resulting on-wafer effects.

[0039] Returning briefly to FIG. 2 , after developing the interconnected network of causal relationships, the method may also include using the relationships and Bayesian reasoning to generate a model of the semiconductor processing device ( 204 ). When performing a matched comparison, this step may involve generating a model for each semiconductor processing device. In some embodiments, a Bayesian model may be used. For example, when comparing the performance of two chambers, this process may involve generating a first Bayesian model for the first semiconductor processing device using the causal relationships in the network, and generating a second Bayesian model for the second semiconductor processing device also using the causal relationships in the network. As described below, the Bayesian models for the two semiconductor processing devices may use performance data from structured experiments (e.g., first performance data and second performance data, respectively) to estimate coefficients used in the Bayesian model.

[0040] FIG4 illustrates a flow chart 400 of a process for building one or more models based on Bayesian reasoning according to some embodiments. One input may include data from a structured experiment 404. Typically, data from a structured experiment 404 may be limited in scope because it may be too expensive to run a large number of marathon experiments on semiconductor substrates. Instead, the system may be customized to use a smaller number of experiments (e.g., 15 to 30 substrates). Data may be collected from semiconductor processing chambers in the form of unstructured observations of the responses of these chambers. Alternatively, a structured experiment may be run. For example, data from a structured experiment 404 may be collected as metrology data from a metrology station.

[0041] In contrast to existing methods, these methods do not require reliance on separate data. Instead, domain knowledge 406 may be used to supplement the data. The domain knowledge may include the network structure 300 described above, which includes the physical relationships between different variables in the system. In addition to the architectural design information 402, the data may be supplemented with acquisition data 408 received before the model is constructed. The acquisition data 408 may also be received after the model is created and used to refine the model. The acquisition data may include field tests, reliability data, observational data, marathon testing, iterative designs, laboratory testing, and / or any other additional data source relevant to the modeling process.

[0042] When using Bayesian rules to build a model, domain knowledge 406 and acquired data 408 may be referred to as "prior information" 410. Additional prior information may include prior model definitions or engineering knowledge. For example, network structure 300 and / or engineering knowledge may indicate that temperature and pressure are related and follow certain distributions. A specific model structure 412 may be selected and combined with prior information 410 using Bayesian rules 414 to produce a model 416.

[0043] FIG5 illustrates how the above-described prior knowledge can be combined with experimental data to design a model of a semiconductor processing system. Specifically, Bayes' theorem provides a method for updating or generating a model using prior knowledge when prior knowledge about the physical operation of the system becomes available. For example, an architecture design 520 may include the physical architecture of a semiconductor processing device. This architecture design 520 may include the components listed in the network structure 300 described above, which indicate the cause-effect relationships in the functionality of the architecture design 520. This forms the initial starting point for the model. However, it is still necessary to determine whether the initial design is accurate and reasonable. According to Bayes' rule, this question about the feasibility of the initial architecture design may be referred to as p(design), or the probability that the design is correct.

[0044] Next, experimental data 522 generated by experiments conducted using semiconductor processing equipment can be collected. This experimental data 522 can be used to verify or validate the validity of the architecture design 520, including the causal relationships between hardware, functions, and design requirements. As one of the Bayesian rules, this step can be formalized and formulated as follows.

[0045]

[0046] Finally, Bayes' rule can be used to combine a prior or initial design with the experimental results to produce a posterior design, indicating the probability of the design after the results occurred.

[0047]

[0048] The resulting model can be represented by a transfer function 500. The transfer function 500 produces an output (Y) 502 that represents the system performance response. The output 502 is represented in the transfer function 500 as a function of an extrinsic variable (X) and an intrinsic variable (β). Extrinsic variables can represent variations due to tolerances or degradation of architectural elements (e.g., hardware components, knobs, etc.) and their interactions. In contrast, intrinsic variables can represent variations due to the interconnection strength of architectural elements in the system. These intrinsic variables measure the contribution of the system to the sensitivity of the operating window in the operating parameters. For example, an example of a transfer function for the thickness of a film formed in a deposition chamber with estimated coefficients may include the following.

[0049]

[0050] In terms of transfer function 500, the X terms representing extrinsic variables may correspond to physical properties such as pressure, temperature, plasma power, gas flow, pedestal spacing, etc. The β terms representing intrinsic variables may be coefficients in transfer function 500. To create an accurate transfer function 500, transfer function 500 may include base signal 504, main effects 506, nonlinear effects 508, interaction effects 510, noise 512, and / or other terms. In other words, the X terms may represent hardware components, while the β terms represent how those components are connected. It should be noted that different X terms may have different β terms. i Term and β i The number of terms may be large (e.g., more than 10), each of which may involve aggregation / integration, resulting in computationally complex calculations. It should be noted that transfer function 500 does not represent a single value, but rather a distribution of values ​​for each variable in the function. As described above, the validity of transfer function 500 may be determined based on measurements and system responses to ensure that the model is accurate.

[0051] Returning briefly to FIG. 2 , the method may further include using the model to compare semiconductor processing device responses ( 206 ). Although the model structure of each semiconductor processing device may be similar, the different X i Term and β i Items may differ from one another. Processing performed by a semiconductor processing device may ideally produce identical substrates. However, as described above, processing involving different substrates processed by the same device, or processing involving different substrates processed by different devices of the same type, may differ, resulting in a so-called "mismatch." For example, when comparing the performance of two different semiconductor processing devices, this may involve comparing the response distributions generated by a first Bayesian model and a second Bayesian model to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device.

[0052] FIG6A illustrates a model for two different chambers for comparing chamber performance according to some embodiments. The models for these chambers use the transfer functions in the form of equations derived above in FIG5. Equation 602 may represent a first chamber, while equation 604 may represent a second chamber. These chambers may be chambers of the same type processing different substrates, where similar results are expected. In other embodiments, these equations 602, 604 may represent other aspects of semiconductor processing, such as different devices or substrate positions. Using the output Y to represent the measured performance of each chamber or device, a comparison can be made between the two chambers to determine if the performance is mismatched. Specifically, equation 606 can be derived by calculating the difference between equation 602 for the first chamber and equation 604 for the second chamber. If the performance of the chambers is the same, then the resulting Y is 1 -Y 2 should be approximately 0. However, since the resulting Y 1 -Y 2 The term deviates from zero, which may indicate a performance mismatch between the first chamber and the second chamber.

[0053] Equation 606 may also represent the first level of a two-level Bayesian decomposition of the response. When comparing two semiconductor processing devices, equation 606 may represent a first decomposition of the transfer function by subtracting a second Bayesian model from a first Bayesian model to produce an example of a change in a different external variable over an operating range of the different external variable. For example, equation 606 may use a probabilistic sensitivity analysis to decompose the change in response into a value over the entire range of values ​​of X (e.g., from X 低 To X 高 )X i Measurable variation of different X's in the set to identify and measure extrinsic variation as described above.

[0054] Equation 610 may represent the second level of a Bayesian second-level decomposition that uses aggregate variance analysis to decompose response changes into measurable changes in coefficients (β) for different X's at their optimal settings to identify and measure exogenous changes as described above. For example, equation 610 may represent a second decomposition of a transfer function by aggregating each factor in the transfer function into changes in coefficients of an intrinsic variable representing a different exogenous variable. The result of equation 610 may produce a distribution of response values ​​for different X's at their optimal settings.

[0055] A variety of different methods can be used to determine whether the responses of the first chamber and the second chamber match or represent unmatched performance. These methods can use a Bayesian matching method that considers the entire distribution of values ​​rather than just a single value (e.g., mean, standard deviation, etc.). In some embodiments, the difference between the distributions of the first chamber and the second chamber can be compared with a reference value. For example, the practical equivalent region (ROPE) can be used to determine how much of the result distribution of each chamber is within a specified practical range. Some embodiments can also use a high density interval (High Density Interval, HDI) method to summarize the range of the most credible values ​​of the measurement within a limited range. This range can be determined by the actual operating conditions or recipes used in the chamber, rather than by the entire range of possible values. Some embodiments can also use matching techniques such as JS divergence to calculate a similarity measure between two distributions. For example, when comparing two semiconductor processing devices, this process can calculate the JS divergence between the response distributions generated by the first Bayesian model and the second Bayesian model.

[0056] 6B shows an example of how a deposition chamber may be used to perform the above-described matching process according to some embodiments. The above-described first chamber and second chamber may represent deposition chambers of the same type that process different substrates. Alternatively, this method may be used to identify mismatched performance within the same physical chamber and / or on the same substrate. In this example, a contour map 600 represents the thickness of a deposited film on a semiconductor substrate. Based on the contour map 600, the thickness of the substrate at position 642 and at position 646 is approximately the same. However, the thickness of the substrate at position 640 may be significantly different from that at position 644. A model describing the above-described process may be used to identify such performance mismatches and provide indications of possible causes of the performance mismatch.

[0057] FIG6C illustrates the performance responses between matched and mismatched thickness locations according to some embodiments. The performance responses match when the matching response distributions for any possible design variable settings are consistently matched within specifications. In this example, a threshold of 5% or less may be used. If any response distribution for any design variable setting exceeds this 5% match between the two locations, a performance mismatch may be identified. Thus, when comparing the performance of two semiconductor processing devices, this step may involve determining whether the similarity between the response distributions generated by the first Bayesian model and the second Bayesian model falls within a threshold of ROPE.

[0058] In this example, the results of different experiments (DOEs) have been identified in the table shown in Figure 6C. Table 620 shows the matching results of the predicted responses of positions 642 and 646 over different input ranges represented by different DOEs. The matching responses are determined to be greater than 95% within the ROPE and they match across the entire design space (i.e., the recorded "cutoff" value is less than the allowed 5% variation). Curves 633 and 635 show these matching thickness performances when 100% of the 95% HDI is within the ROPE of DOE-3.

[0059] In contrast, the different predicted response distributions used to compare between the responses at location 640 and location 646 illustrate many variable settings (e.g., DOE-3) where the predicted responses do not match, even though other predicted responses in table 622 fall within 95% of the ROPE range. Curves 637 and 639 show these matching thickness performances when 0% of the 95% HDI is within the ROPE of DOE-3.

[0060] These distributions and responses can be calculated using the Bayesian method described above. A Bayesian model can be used based on the DOE data points to detect whether the thickness values ​​between different locations are functionally matched. In this example, these data can indicate that within the same chamber, location 642 matches location 646, while a mismatch occurs between location 640 and location 644.

[0061] Returning briefly to FIG. 2 , the method may also include identifying extrinsic variations ( 208 ). The extrinsic variations may be identified using the Bayesian decomposition described above and, for example, performing a probabilistic sensitivity analysis on them over an operating range of the extrinsic variables. For example, when comparing the performance of two different devices, this process may involve identifying variations in the extrinsic variables in the first Bayesian model and the second Bayesian model. These variations in the extrinsic variables may indicate the sensitivity of the response distribution to hardware components in the first semiconductor processing device and the second semiconductor processing device.

[0062] Continuing with this example, the transfer function described above can be used to identify extrinsic variations between position 640 and position 644 that may be the cause of a detected thickness mismatch. For example, the extrinsic variations represented by the X variables in the transfer function can be used to perform a sensitivity analysis on these variable settings. In other words, the probabilistic sensitivity analysis can determine the effect of variations in each of the X variable settings over the entire range of values ​​on the mismatch performance Y. 1 -Y 2 When comparing the performance of two semiconductor processing devices, this step may involve performing a sensitivity analysis on the extrinsic variables to identify at least one extrinsic variable that causes a performance mismatch between the first semiconductor processing device and the second semiconductor processing device.

[0063] FIG. 7 shows the results of a sensitivity analysis of the predicted responses according to some embodiments. Graph 700 shows how much the change in each variable X affects the resulting thickness at each location. Bar 702 represents the sensitivity of the X variable at location 640, bar 704 represents the sensitivity of the X variable at location 644, and bar 706 represents the difference between these predicted responses at each location. Bar 706 shows the main contributors that have an impact on the mismatched thickness of the deposited layer. Specifically, about 77% of the mismatched thickness on the substrate can be attributed to PDMAT dose flow (27.74%), NH3 dose flow (18.73%), PDMAT purge Ar flow (18.52%), and chamber pressure (12.55%).

[0064] This information can be used to highlight the main causes of substrate performance mismatch due to external factors. In this example, adjusting the PDMAT dose flow rate may have the greatest impact on the mismatch between the two locations. Each of these parameters can be adjusted so that the mismatched performance is within the ROPE range.

[0065] However, adjusting the external factors alone may not be sufficient to eliminate all mismatched performance on the substrate. Some embodiments may also include evaluating the intrinsic variation at these two locations under the optimal recipe settings. Recall that the intrinsic variables (β) represented in the transfer function can be analyzed using Bayesian decomposition to determine the parameter differences (β) for each variable setting at a certain level. i 1 -β i 2 ) Response to mismatch Y 1 -Y 2 tant (e.g., the optimal setting determined from adjustment for external changes).

[0066] Returning briefly to FIG. 2 , the method may also include identifying intrinsic variations ( 210 ). These intrinsic variations may be identified using the Bayesian decomposition described above. When comparing two different semiconductor processing devices, identifying variations in the intrinsic variables in the first Bayesian model and the second Bayesian model may indicate the sensitivity of the response distribution to connections between hardware components in the first semiconductor processing device and the second semiconductor processing device.

[0067] FIG8 shows the intrinsic variation at two locations on the substrate according to some embodiments. The set of optimal settings can be determined using external variation adjustments as described above. In this example, the optimal settings may include values ​​for each variable X shown in FIG7 (e.g., chamber pressure = 5 kPa, NH3 dose flow rate = 158804 sccm, etc.). These values ​​can then be used to generate each parameter β i The parameter difference (β i1 -β i 2 A set of response graphs 800 may be generated to illustrate the distribution of the responses.

[0068] In the case of very narrow distributions, this may indicate that these particular intrinsic variables do not have a large impact on the change in response. For example, graphs 808 and 810 show very narrow distributions, indicating that changes in NH3 purge Ar flow and NH3 purge time do not significantly affect the response. However, larger distributions, such as those shown in graphs 802 and 804, may indicate that changes in the corresponding intrinsic variables (such as intrinsic characteristics that cause chamber pressure and NH3 dose flow to change) more significantly affect the change in the response distribution. To illustrate the data in another way, table 801 shows how the chamber pressure, dose flow, and base temperature distributions have larger variances and / or means relative to other intrinsic variables. These values ​​can be compared to thresholds to identify these intrinsic variables as significant.

[0069] Returning briefly to FIG. 2 , the method may further include adjusting device parameters to compensate for intrinsic and / or extrinsic variations ( 212 ). How this step is implemented may vary depending on the type of mismatch identified. As described above, mismatches may be identified between semiconductor substrates, locations on a semiconductor substrate, different semiconductor substrates in the same chamber, different semiconductor substrates in different chambers, etc. Based on a particular implementation, intrinsic / extrinsic variations may be mapped to physical or engineering knowledge to adjust the operation of a semiconductor chamber, adjust the design of a semiconductor device, determine optimal performance settings for a semiconductor device, etc. For example, this step may involve using a causal network to identify hardware devices, wherein operating parameters of the hardware devices may be adjusted to correct for a performance mismatch between a first semiconductor processing device and a second semiconductor processing device.

[0070] In order to make adjustments based on these intrinsic variations, the network structure 300 described above can be used to identify the sources of the intrinsic variations. FIG. 9 illustrates how the cause-effect relationships described in the network structure 300 can be used to make changes to the operating parameters of the process according to some embodiments. For example, the data in FIG. 8 indicates that the base temperature 904 and the NH3 dose flow rate 910 are related to the intrinsic variations. The cause-effect relationships identified in the network structure 300 can identify specific hardware elements that can be controlled to adjust for these intrinsic variations. For example, the heater 902 can be adjusted to compensate for the intrinsic variations found in the base temperature 904. The mass flow controller 908 of NH3 can be adjusted to control the intrinsic variations found in the NH3 dose flow rate 910. These adjustments may ultimately affect the thickness 906 of the semiconductor substrate.

[0071] For example, when the optimal settings for the chamber are applied, the thickness 906 is sensitive to the NH3 dose flow rate 910 and the base temperature 904, because they affect the total reactant concentration in the chamber, and should be investigated to identify the source of the mismatched thickness. By using this cause-and-effect relationship in the network structure 300, the operator can focus his investigation on the mass flow controller 908 and heater 902 of NH3. He can focus not only on the direct interpretation of these parameters, but also on the inherent variability of the design and installation of these devices in the chamber. For example, the heater 902 may be susceptible to asymmetric heater installation, thermocouple offset, PID adjustment, recipe setting steps, etc. The mass flow controller 908 of NH3 may have variations in delay time, correction factor, inlet pressure, etc. between different devices.

[0072] It should be noted that the above examples of mismatched performance on substrates in chambers are provided as examples only and are not meant to be limiting. Many other applications of the above Bayesian modeling process can be used in different situations. For example, the same techniques can be used to identify mismatched performance between semiconductor chambers tested in a laboratory and semiconductor chambers operating in a customer facility. For example, the same techniques can be used to determine whether the thickness or other characteristics of semiconductor substrates are matched between two chambers or chamber types. The same analysis used above can be used to determine, for example, that temperature is the main variable that causes thickness or other characteristic variations. Intrinsically, temperature can be identified as having a variability that strongly causes thickness mismatch between two chambers, even at different temperature setting levels (e.g., low, medium, high, optimal, etc.). The model can then be used to simulate and identify recipes where the differences or mismatches between the two chambers are minimized. The customer can then choose to use the recommended recipe to minimize the variation in thickness. Hardware components that affect temperature (e.g., lamp heads, pyrometers, reflective plates, etc.) can also be identified, and these hardware components can be adjusted.

[0073] Each method described herein can be implemented by a computer system. Each step of these methods can be automatically performed by a computer system, and / or input / output involving a user can be provided. For example, a user can provide input for each step in the method, and each of these inputs can be in response to a specific output requesting such input, wherein this output is generated by a computer system. Each input can be received in response to a corresponding request output. In addition, input can be received from a user, from another computer system as a data stream, from a memory location, from a network, from a network service request input, and / or the like. Similarly, output can be provided to a user, provided to another computer system as a data stream, stored in a memory location, sent via a network, provided to a network service, and / or the like. In short, each step of the method described herein can be performed by a computer system, and can involve any number of inputs, outputs, and / or requests from or to a computer system of a computer system, which can involve or not involve a user. Those steps that do not involve a user can be said to be automatically performed by a computer system without human intervention. Therefore, it will be understood from this disclosure that each step of each method described herein can be changed to include input and output sent to and from a user, or can be completed automatically by a computer system without human intervention, wherein any determination is made by a processor. In addition, some embodiments of each method described herein can be implemented as a set of instructions stored on a tangible, non-transitory storage medium to form a tangible software product.

[0074] FIG. 10 shows an exemplary computer system 1000 in which various embodiments may be implemented. System 1000 may be used to implement any of the above-described computer systems. As shown, computer system 1000 includes a processing unit 1004 that communicates with a plurality of peripheral subsystems via a bus subsystem 1002. These peripheral subsystems may include a processing acceleration unit 1006, an I / O subsystem 1008, a storage subsystem 1018, and a communication subsystem 1024. Storage subsystem 1018 includes a tangible computer-readable storage medium 1022 and a system memory 1010.

[0075] The bus subsystem 1002 provides a mechanism for making the various components and subsystems of the computer system 1000 communicate with each other as expected. Although the bus subsystem 1002 is schematically shown as a single bus, alternative embodiments of the bus subsystem can use multiple buses. The bus subsystem 1002 can be any one of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, and a regional bus using any of various bus architectures. For example, such architectures can include an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MCA) bus, an Enhanced ISA (EISA) bus, a Video Electronics Standards Association (VESA) regional bus, and a Peripheral Component Interconnect (PCI) bus, which can be implemented as a mezzanine bus manufactured according to the IEEE P1386.1 standard.

[0076] The processing unit 1004 may be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers) to control the operation of the computer system 1000. One or more processors may be included in the processing unit 1004. These processors may include single-core or multi-core processors. In some embodiments, the processing unit 1004 may be implemented as one or more independent processing units 1032 and / or 1034, each of which includes a single-core or multi-core processor. In other embodiments, the processing unit 1004 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors into a single chip.

[0077] In various embodiments, the processing unit 1004 may execute various programs in response to program code, and may maintain multiple concurrently executing programs or processes. At any given time, some or all of the program code to be executed may reside in the processor 1004 and / or the storage subsystem 1018. Through appropriate programming, the processor 1004 can provide the various functions described above. The computer system 1000 may further include a processing acceleration unit 1006, which may include a digital signal processor (DSP), a special processor, and / or the like.

[0078] I / O subsystem 1008 may include user interface input devices and user interface output devices. User interface input devices may include keyboards, pointing devices such as mice or trackballs, touch pads or touch screens integrated into displays, scroll wheels, click wheels, dials, buttons, switches, keyboards, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices may include, for example, motion sensing and / or gesture recognition devices, such as Microsoft Kinect® motion sensors, which enable users to control input devices such as Microsoft Xbox® 360 game controllers and interact with them via natural user interfaces using gestures and verbal commands. User interface input devices may also include eye gesture recognition devices, such as Google Glass® blink detectors, which detect eye activity of a user (e.g., "blinking" when taking pictures and / or making menu selections) and convert eye gestures as input to an input device (e.g., Google Glass®). In addition, user interface input devices may include voice recognition sensing devices, which enable users to interact with voice recognition systems (e.g., Siri® Navigator) via voice commands.

[0079] The user interface input device may also include, but is not limited to, a three dimensional (3D) mouse, a joystick or pointing stick, a game pad, and a drawing tablet, as well as audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye gaze tracking devices. In addition, the user interface input device may include, for example, medical imaging input devices such as computed tomography, magnetic resonance imaging, positron emission tomography, and medical ultrasound devices. The user interface input device may also include, for example, audio input devices such as MIDI keyboards, digital musical instruments, etc.

[0080] The user interface output device may include a display subsystem, indicator lights, or non-visual displays such as audio output devices. The display subsystem may be a cathode ray tube (CRT), a flat panel device such as one using a liquid crystal display (LCD) or plasma display, a projection device, a touch screen, etc. In general, the use of the term "output device" is intended to include all possible types of devices and mechanisms for outputting information from the computer system 1000 to a user or other computers. For example, the user interface output device may include, but is not limited to, various display devices that visually convey text, graphics, and audio / video information, such as monitors, printers, speakers, headphones, car navigation systems, plotters, voice output devices, and modems.

[0081] Computer system 1000 may include storage subsystem 1018, which includes software elements, shown as currently located within system memory 1010. System memory 1010 may store program instructions loadable and executable on processing unit 1004, as well as data generated during the execution of these programs.

[0082] Depending on the configuration and type of computer system 1000, system memory 1010 may be volatile (such as random access memory (RAM)) and / or non-volatile (such as read-only memory (ROM), flash memory, etc.). RAM typically contains data and / or program modules that are immediately accessible to and / or currently being operated on and executed by processing unit 1004. In some implementations, system memory 1010 may include a variety of different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, a basic input / output system (BIOS) containing the basic routines that help transfer information between elements within computer system 1000, such as during startup, may typically be stored in ROM. By way of example and not limitation, system memory 1010 further illustrates application programs 1012, which may include client applications, web browsers, middle-tier applications, relational database management systems (RDBMS), etc., program data 1014, and operating system 1016. For example, operating system 1016 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS.

[0083] Storage subsystem 1018 may also provide a tangible computer-readable storage medium for storing basic programming and data structures that provide the functionality of some embodiments. Software (programs, code modules, instructions) that provide the above-described functionality when executed by a processor may be stored in storage subsystem 1018. These software modules or instructions may be executed by processing unit 1004. Storage subsystem 1018 may also provide a repository for storing data used in accordance with some embodiments.

[0084] The storage subsystem 1000 may also include a computer-readable storage media reader 1020, which may be further connected to a computer-readable storage medium 1022. The computer-readable storage medium 1022, together with and optionally in combination with the system memory 1010, may collectively represent remote, local, fixed and / or removable storage devices plus storage media for temporarily and / or more permanently containing, storing, transferring, and retrieving computer-readable information.

[0085] The computer-readable storage medium 1022 containing the code or portions of the code may also include any suitable media, including storage media and communication media, such as, but not limited to, volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing and / or transmitting information. This may include tangible computer-readable storage media, such as RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other tangible computer-readable media. This may also include non-detectable computer-readable media, such as data signals, data transmissions, or any other media that can be used to transmit the desired information and can be accessed by the computing system 1000.

[0086] For example, the computer-readable storage medium 1022 may include a hard disk drive that reads from or writes to a non-removable, non-volatile magnetic medium, a magnetic disk drive that reads from or writes to a removable, non-volatile magnetic disk, and an optical disk drive that reads from or writes to a removable, non-volatile optical disk such as a CD ROM, a DVD, and a Blu-Ray® disk or other optical media. The computer-readable storage medium 1022 may include, but is not limited to, a Zip® drive, a flash memory card, a universal serial bus (USB) flash drive, a secure digital (SD) card, a DVD disk, a digital video tape, and the like. The computer-readable storage medium 1022 may also include a solid-state drive (SSD) based on non-volatile memory, such as a flash memory-based SSD, an enterprise flash drive, a solid-state ROM, and the like, a volatile memory-based SSD, such as a solid-state RAM, a dynamic RAM, a static RAM, a DRAM-based SSD, a magnetoresistive RAM (MRAM) SSD, and a hybrid SSD using a combination of DRAM and a flash memory-based SSD. The disk drives and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules and other data for the computer system 1000 .

[0087] The communication subsystem 1024 provides an interface for other computer systems and networks. The communication subsystem 1024 is used as an interface for receiving data from the computer system 1000 and sending data from the computer system to other systems. For example, the communication subsystem 1024 can enable the computer system 1000 to be connected to one or more devices via the Internet. In some embodiments, the communication subsystem 1024 may include a radio frequency (RF) transceiver component for accessing a wireless voice and / or data network (e.g., using cellular phone technology, advanced data network technology such as 3G, 4G or EDGE (Enhanced Data Rate for Global Evolution), WiFi (IEEE 802.11 family standards), or other mobile communication technologies, or any combination thereof), a global positioning system (GPS) receiver component and / or other components. In some embodiments, as a supplement or alternative to a wireless interface, the communication subsystem 1024 can provide a wired network connection (e.g., Ethernet).

[0088] In some implementations, the communication subsystem 1024 may also receive input communications in the form of structured and / or unstructured data feeds 1026 , event streams 1028 , event updates 1030 , and the like on behalf of one or more users that may use the computer system 1000 .

[0089] For example, the communication subsystem 1024 may be configured to instantly receive data feeds 1026 from users of social networks and / or other communication services, such as Twitter® feeds, Facebook® updates, web feeds such as Rich Site Summary (RSS) feeds, and / or instant updates from one or more third-party information sources.

[0090] In addition, the communication subsystem 1024 may also be configured to receive data in the form of continuous data streams, which may include event streams 1028 of instant events and / or event updates 1030, which may be continuous or endless in nature, without a clear end. Examples of applications that generate continuous data may include, for example, sensor data applications, financial market makers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automobile traffic monitoring, etc.

[0091] The communication subsystem 1024 may also be configured to output structured and / or unstructured data feeds 1026 , event streams 1028 , event updates 1030 , etc. to one or more databases that may communicate with one or more streaming data source computers coupled to the computer system 1000 .

[0092] Computer system 1000 can be one of various types, including a handheld portable device (e.g., an iPhone® cell phone, an iPad® tablet computer, a PDA), a wearable device (e.g., a Google Glass® head-mounted display device), a PC, a workstation, a mainframe, a kiosk, a server rack, or any other data processing system.

[0093] Due to the ever-changing nature of computers and networks, the description of the computer system 1000 shown in the figure is only used as a specific example. Many other configurations with more or fewer components are possible compared to the system shown in the figure. For example, customized hardware and / or specific elements can be implemented in hardware, firmware, software (including small applications) or a combination thereof. In addition, connections with other computing devices such as network input / output devices can be adopted. Based on the disclosure and teachings provided herein, other ways and / or methods of implementing various embodiments should be obvious.

[0094] As used herein, the term "about" or "approximately" or "substantially" may be interpreted as being within a range expected by those skilled in the art based on the description.

[0095] In the above description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various embodiments. However, it is apparent that some embodiments may be practiced without these specific details. In other cases, well-known structures and devices are shown in the form of block diagrams.

[0096] The above description provides only exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the foregoing description of various embodiments will provide a feasible disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of some embodiments set forth in the appended claims.

[0097] Specific details are given in the foregoing description to provide a comprehensive understanding of the embodiments. However, it should be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, programs, and other components may be shown as components in block diagram form so as not to obscure the embodiments with unnecessary details. In other cases, in order to avoid obscuring the embodiments, well-known circuits, programs, algorithms, structures, and techniques may be shown without unnecessary details.

[0098] In addition, it should be noted that individual embodiments may have been described as processes depicted as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed, but there may be other steps not included in the diagram. A process may correspond to a method, function, procedure, routine, subroutine, etc. When a process corresponds to a function, its termination may correspond to the function returning to the calling function or the main function.

[0099] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent any combination of steps, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted in any suitable manner, including memory sharing, message passing, token passing, network transmission, etc.

[0100] In addition, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, the program code or program code segments for performing the necessary tasks may be stored in a machine-readable medium. The processor may perform the necessary tasks.

[0101] In the foregoing description, features are described with reference to specific embodiments thereof, but it will be appreciated that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used alone or in combination. Furthermore, the embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. Accordingly, the description and drawings should be regarded as illustrative rather than restrictive.

[0102] In addition, for ease of explanation, the methods are described in a specific order. It should be understood that in alternative embodiments, these methods can be performed in a different order than described. It should also be appreciated that the above methods can be performed by hardware components, or can be embodied in machine executable instruction sequences, which can be used to make machines (such as general or special processors or logic circuits programmed with instructions) perform these methods. These machine executable instructions can be stored on one or more machine-readable media, such as CD-ROM or other types of optical disks, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods can be performed by a combination of hardware and software.

Claims

1. A method for identifying mismatched performance between semiconductor processing devices, the method comprising the following steps: Accessing a network of cause-and-effect relationships between processes and hardware in a semiconductor processing device; generating a first Bayesian model for a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model for a second semiconductor processing device using the causal relationships in the network and second performance data; and The response distributions generated by the first Bayesian model and the second Bayesian model are compared to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device.

2. The method according to claim 1, further comprising the following steps: Changes in extrinsic variables in the first Bayesian model and the second Bayesian model are identified, the changes indicating sensitivity of the response distribution to hardware components in the first semiconductor processing device and the second semiconductor processing device.

3. The method according to claim 1, further comprising the following steps: Changes in intrinsic variables in the first Bayesian model and the second Bayesian model are identified, the changes indicating sensitivity of the response distribution to connections between hardware components in the first semiconductor processing device and the second semiconductor processing device. The method according to claim 1 , wherein the first Bayesian model is represented using a transfer function. 5 . The method of claim 4 , wherein the transfer function represents main effects, nonlinear effects, and interaction effects of the first semiconductor processing device that affect a response distribution of the first Bayesian model.

6. The method of claim 4, further comprising the step of performing a first decomposition of the transfer function by subtracting the second Bayesian model from the first Bayesian model to produce variations of different extrinsic variables within an operating range of the different extrinsic variables.

7. The method of claim 6, further comprising the step of performing a second decomposition of the transfer function by aggregating each factor in the transfer function into coefficient variations of intrinsic variables representing the different extrinsic variables.

8. A system comprising: one or more processors; and One or more memory devices comprising instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising the following steps: Accessing a network of cause-and-effect relationships between processes and hardware in a semiconductor processing device; generating a first Bayesian model for a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model for a second semiconductor processing device using the causal relationships in the network and second performance data; and The response distributions generated by the first Bayesian model and the second Bayesian model are compared to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device.

9. The system of claim 8, wherein the system is implemented on a controller of a semiconductor processing chamber.

10. The system of claim 8, wherein the system is implemented on a central platform that communicates with controllers of a plurality of semiconductor processing chambers in a facility.

11. The system of claim 8, wherein the system is implemented on a remote server that communicates with a plurality of different semiconductor processing facilities, each semiconductor processing facility operating a plurality of semiconductor processing chambers.

12. The system of claim 8, wherein the step of determining whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device comprises the following steps: The JS divergence between the response distributions generated by the first Bayesian model and the second Bayesian model is calculated.

13. The system of claim 8, wherein the step of determining whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device comprises the following steps: A determination is made as to whether a similarity between the response distributions produced by the first Bayesian model and the second Bayesian model falls within a threshold of a region of practical equivalence (ROPE).

14. The system of claim 8, wherein the operations further comprise the step of performing a sensitivity analysis on extrinsic variables to identify at least one extrinsic variable that causes a mismatch in the performance between the first semiconductor processing device and the second semiconductor processing device.

15. One or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising: Accessing a network of cause-and-effect relationships between processes and hardware in a semiconductor processing device; generating a first Bayesian model for a first semiconductor processing device using the causal relationships in the network and first performance data; generating a second Bayesian model for a second semiconductor processing device using the causal relationships in the network and second performance data; and The response distributions generated by the first Bayesian model and the second Bayesian model are compared to determine whether the performance of the first semiconductor processing device matches the performance of the second semiconductor processing device.

16. The one or more non-transitory computer readable media of claim 15, wherein the one or more non-transitory computer readable media are distributed between a controller of a semiconductor processing chamber and a remote server.

17. The one or more non-transitory computer-readable media of claim 15, wherein the operations further comprise the step of identifying a cause of the performance mismatch between the first semiconductor processing device and the second semiconductor processing device.

18. One or more non-transitory computer-readable media according to claim 17, wherein the operation further comprises the following steps: using the network of causal relationships to identify a hardware device, wherein operating parameters of the hardware device are adjusted to correct the mismatch in the performance between the first semiconductor processing device and the second semiconductor processing device.

19. The one or more non-transitory computer-readable media of claim 15, wherein the network of causal relationships comprises a layer of nodes representing on-wafer effects, a layer of nodes representing functional requirements, and a layer of nodes representing hardware components.

20. The one or more non-transitory computer-readable media of claim 15, wherein the operations further comprise the steps of: accessing a system functional map comprising a data structure that relates requirements of the first semiconductor processing apparatus to functional requirements of components in the first semiconductor processing apparatus, then to technology components, and then to on-wafer effects; and The network is automatically generated according to the functional graph.

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