Three-dimensional memory device with self-aligned word line contact via structure and method of manufacturing same

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and conductive layers having a stepped surface in a contact region; a memory opening extending vertically through the alternating stack; a memory opening filling structure in the memory opening; at least one backward stepped dielectric material portion overlying the alternating stack; a fin-like dielectric pillar structure extending vertically through the alternating stack in the contact region; a support column structure; and a layer contact via structure extending vertically through the at least one backward stepped dielectric material portion. Each of the layer contact via structures contacts a respective one of the conductive layers and a respective one of the fin-shaped dielectric pillar structures.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 385,083 filed on November 28, 2022 and U.S. Provisional Patent Application No. 63 / 385,089 filed on November 28, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular to a three-dimensional memory device having a self-aligned wordline contact via structure and a method for manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers, the alternating stack having a stepped surface in a contact area; a memory opening, the memory opening vertically extending through the alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each of the memory opening filling structures comprises a corresponding vertical memory element stack and a corresponding vertical semiconductor channel; at least one backward stepped dielectric material portion, the at least one backward stepped dielectric material portion covering the alternating stack; a fin-shaped dielectric pillar structure; , the fin-like dielectric pillar structure vertically extending through the alternating stack in the contact area; a support pillar structure, the support pillar structure vertically extending through the at least one backward stepped dielectric material portion and the alternating stack and located in the contact area, wherein the top surface of the support pillar structure is located in a horizontal plane including the top surface of the memory opening filling structure; and a layer contact through-hole structure, the layer contact through-hole structure vertically extending through the at least one backward stepped dielectric material portion, wherein each of the layer contact through-hole structures contacts a corresponding one of the conductive layers and a corresponding one of the fin-like dielectric pillar structures.

[0006] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers above a substrate; forming a memory opening and a contact opening through the alternating stack; forming a sacrificial contact opening filling structure in the contact opening; forming a memory opening filling structure in the memory opening, wherein each of the memory opening filling structures comprises a corresponding vertical semiconductor channel and a corresponding vertical memory element stack; replacing the sacrificial material layer with a conductive layer; forming a contact cavity by removing the sacrificial contact opening filling structure after replacing the sacrificial material layer; laterally extending the contact cavity by performing an isotropic etching process, wherein the isotropic etching process selectively recesses a proximal portion of the insulating layer surrounding each of the contact cavities in the contact cavity laterally relative to the conductive layer; forming a fin-shaped dielectric pillar structure in a lower portion of the laterally extended contact cavity; and forming a layer contact through-hole structure in an upper portion of the laterally extended contact cavity.

[0007] According to another aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers, the alternating stack having a stepped surface in a contact area; a memory opening, the memory opening vertically extending through the alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening, wherein each of the memory opening filling structures comprises a corresponding vertical memory element stack and a corresponding vertical semiconductor channel; a dielectric liner, the dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a dielectric liner covering the stepped surface; a memory opening filling structure, the memory opening filling structure being located in the memory opening; a memory opening filling structure The invention relates to a fin-shaped dielectric material layer having a plurality of horizontal surface segments and a plurality of vertical surface segments of a back-stepped surface and extending over a plurality of levels of the conductive layer; a back-stepped dielectric material portion, the back-stepped dielectric material portion contacting a top surface segment of the dielectric liner; a fin-shaped dielectric pillar structure, the fin-shaped dielectric pillar structure extending vertically through the alternating stack in the contact area; and a layer contact through-hole structure, the layer contact through-hole structure extending vertically through the back-stepped dielectric material portion and contacting a corresponding one of the conductive layers and a corresponding one of the fin-shaped dielectric pillar structures.

[0008] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device, the method comprising: forming an alternating stack of an insulating layer and a sacrificial material layer above a substrate; forming a stepped surface by patterning the alternating stack; forming a backward stepped dielectric material portion above the stepped surface; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein each of the memory opening filling structures comprises a corresponding vertical semiconductor channel and a corresponding vertical memory element stack; forming a contact through the backward stepped dielectric material portion, the stepped surface, and the alternating stack; contact cavity; laterally expanding the contact cavity by performing an isotropic etching process, wherein the isotropic etching process selectively recesses the proximal portion of the insulating layer and the rear stepped dielectric material portion surrounding each contact cavity in the contact cavity laterally relative to the sacrificial material layer; forming a fin-shaped dielectric pillar structure in a lower portion of the laterally expanded contact cavity; forming a sacrificial contact via structure in an upper portion of the contact cavity on a corresponding one of the fin-shaped dielectric pillar structures; replacing the sacrificial material layer with a conductive layer; and replacing the sacrificial contact via structure with a layer contact via structure contacting a corresponding one of the conductive layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a vertical cross-sectional view of the first exemplary structure after forming a first-tier alternating stack of first insulating layers and first sacrificial material layers according to the first embodiment of the present disclosure.

[0010] Figure 2 is a vertical cross-sectional view of a first exemplary structure after forming a first stepped surface by patterning a first hierarchical alternating stack according to the first embodiment of the present disclosure.

[0011] Figure 3 is a vertical cross-sectional view of the first exemplary structure after forming a first level dielectric liner according to the first embodiment of the present disclosure.

[0012] Figure 4 is a vertical cross-sectional view of the first exemplary structure after patterning a first level dielectric liner and forming a first backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0013] Figure 5 is a vertical cross-sectional view of the first exemplary structure after forming a first insulating cap layer and a first level memory opening according to the first embodiment of the present disclosure.

[0014] Figure 6is a vertical cross-sectional view of the first exemplary structure after forming a first-level support opening and a first-level contact opening according to the first embodiment of the present disclosure.

[0015] Figure 7 is a vertical cross-sectional view of the first exemplary structure after forming various first level opening filling structures and inter-level dielectric layers according to the first embodiment of the present disclosure.

[0016] Figure 8 is a vertical cross-sectional view of the first exemplary structure after second levels of second insulating layers and second sacrificial material layers are alternately stacked and patterned according to the first embodiment of the present disclosure.

[0017] Fig. 9 is a vertical cross-sectional view of the first exemplary structure after second level dielectric liner deposition and patterning according to the first embodiment of the present disclosure.

[0018] Fig.10 is a vertical cross-sectional view of the first exemplary structure after forming a second backward stepped dielectric material portion and a second insulating cap layer according to the first embodiment of the present disclosure.

[0019] Fig.11 is a vertical cross-sectional view of the first exemplary structure after forming an inter-level memory opening according to the first embodiment of the present disclosure.

[0020] Fig.12 is a vertical cross-sectional view of the first exemplary structure after forming an inter-level support opening and an inter-level contact opening according to the first embodiment of the present disclosure.

[0021] Fig.13 is a vertical cross-sectional view of the first exemplary structure after forming a dielectric liner layer, a sacrificial opening filling structure, and a dielectric capping layer according to the first embodiment of the present disclosure.

[0022] Fig.14 is a vertical cross-sectional view of a first exemplary structure after forming a storage cavity and a support cavity according to the first embodiment of the present disclosure.

[0023] Fig.15 is a vertical cross-sectional view of the first exemplary structure after forming a memory opening filling structure and a support pillar structure according to the first embodiment of the present disclosure.

[0024] Fig.16 is a vertical cross-sectional view of the first exemplary structure after forming a contact level dielectric layer according to the first embodiment of the present disclosure.

[0025] Fig.17Ais a vertical cross-sectional view of the first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0026] Fig. 17B It is along Fig.17A A horizontal cross-sectional view of the first exemplary structure taken along a horizontal plane BB'.

[0027] Fig. 17C It is along Fig. 17B A vertical cross-sectional view of the first exemplary structure taken along a vertical plane CC'.

[0028] Fig.18 is a vertical cross-sectional view of the first exemplary structure after replacing the sacrificial material layer with a conductive layer according to the first embodiment of the present disclosure.

[0029] Fig.19 is a vertical cross-sectional view of the first exemplary structure after forming a contact cavity by removing a sacrificial contact opening filling structure according to the first embodiment of the present disclosure.

[0030] Fig. 20 is a vertical cross-sectional view of the first exemplary structure after laterally expanding the contact cavity according to the first embodiment of the present disclosure.

[0031] Fig.21 is a vertical cross-sectional view of the first exemplary structure after depositing a first dielectric fill material layer according to the first embodiment of the present disclosure.

[0032] Fig. 22 is a vertical cross-sectional view of the first exemplary structure after isotropic recessing of the first dielectric fill material layer according to the first embodiment of the present disclosure.

[0033] Fig.23 is a vertical cross-sectional view of the first exemplary structure after depositing a second dielectric fill material layer according to the first embodiment of the present disclosure.

[0034] Fig.24 is a vertical cross-sectional view of the first exemplary structure after isotropically recessing the second dielectric fill material layer according to the first embodiment of the present disclosure.

[0035] Fig.25 is a vertical cross-sectional view of the first exemplary structure after recessing the second and fourth dielectric liners according to the first embodiment of the present disclosure.

[0036] Fig.26 is a vertical cross-sectional view of the first exemplary structure after isotropically recessing the first and third dielectric liners according to the first embodiment of the present disclosure.

[0037] Fig. 27 is a vertical cross-sectional view of the first exemplary structure after forming a layer contact via structure according to the first embodiment of the present disclosure.

[0038] Fig.28 is a vertical cross-sectional view of a second exemplary structure after first level alternating stacking of first insulating layers and first sacrificial material layers is formed and patterned and first level dielectric liners are formed and patterned according to the second embodiment of the present disclosure.

[0039] Fig.29 is a vertical cross-sectional view of a second exemplary structure after forming a first backward stepped dielectric material portion according to a second embodiment of the present disclosure.

[0040] Fig.30 is a vertical cross-sectional view of a second exemplary structure after forming a first level memory opening according to the second embodiment of the present disclosure.

[0041] Fig.31 is a vertical cross-sectional view of a second exemplary structure after forming a first-level support opening and a first-level contact opening according to the second embodiment of the present disclosure.

[0042] Fig.32 is a vertical cross-sectional view of a second exemplary structure after forming various first-level opening filling structures and inter-level dielectric layers according to the second embodiment of the present disclosure.

[0043] Fig.33 is a vertical cross-sectional view of a second exemplary structure after second level alternating stacking of second insulating layers and second sacrificial material layers is formed and patterned and second level dielectric liners are formed and patterned according to the second embodiment of the present disclosure.

[0044] Fig.34 is a vertical cross-sectional view of a second exemplary structure after forming a second backward stepped dielectric material portion and a second insulating cap layer according to the second embodiment of the present disclosure.

[0045] Fig.35 is a vertical cross-sectional view of a second exemplary structure after forming an inter-level memory opening according to the second embodiment of the present disclosure.

[0046] Fig.36 is a vertical cross-sectional view of a second exemplary structure after forming an inter-level support opening and an inter-level contact opening according to the second embodiment of the present disclosure.

[0047] Fig.37 is a vertical cross-sectional view of a second exemplary structure after forming a dielectric liner layer, a sacrificial opening filling structure, and a dielectric capping layer according to the second embodiment of the present disclosure.

[0048] Fig.38 is a vertical cross-sectional view of a second exemplary structure after forming a storage cavity and a support cavity according to the second embodiment of the present disclosure.

[0049] Fig.39 is a vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure and a support pillar structure according to the second embodiment of the present disclosure.

[0050] Fig.40 is a vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer according to the second embodiment of the present disclosure.

[0051] Fig.41 is a vertical cross-sectional view of a second exemplary structure after replacing the sacrificial material layer with a conductive layer according to the second embodiment of the present disclosure.

[0052] Fig.42 is a vertical cross-sectional view of the second exemplary structure after forming a contact cavity by removing a sacrificial contact opening filling structure according to the second embodiment of the present disclosure.

[0053] Fig.43 is a vertical cross-sectional view of a second exemplary structure after laterally expanding the contact cavity according to the second embodiment of the present disclosure.

[0054] Fig.44 is a vertical cross-sectional view of a second exemplary structure after depositing a first dielectric fill material layer according to the second embodiment of the present disclosure.

[0055] Fig.45 is a vertical cross-sectional view of a second exemplary structure after isotropic recessing of a first dielectric fill material layer according to a second embodiment of the present disclosure.

[0056] Fig.46 is a vertical cross-sectional view of a second exemplary structure after depositing a second dielectric fill material layer according to the second embodiment of the present disclosure.

[0057] Fig.47 is a vertical cross-sectional view of a second exemplary structure after isotropic recessing of a second dielectric fill material layer according to a second embodiment of the present disclosure.

[0058] Fig.48 is a vertical cross-sectional view of a second exemplary structure after forming a layer contact via structure according to the second embodiment of the present disclosure.

[0059] Fig.49 is a vertical cross-sectional view of a third exemplary structure after forming a memory opening filling structure and a support pillar structure according to the third embodiment of the present disclosure.

[0060] Fig.50 is a vertical cross-sectional view of the third exemplary structure after forming a contact-level dielectric layer and forming a contact cavity by removing a sacrificial contact opening filling structure according to the third embodiment of the present disclosure.

[0061] Fig.51 is a vertical cross-sectional view of a third exemplary structure after laterally expanding the contact cavity according to the third embodiment of the present disclosure.

[0062] Fig.52 is a vertical cross-sectional view of a third exemplary structure after forming a first dielectric via liner layer according to the third embodiment of the present disclosure.

[0063] Fig.53 is a vertical cross-sectional view of a third exemplary structure after depositing a first dielectric fill material layer according to the third embodiment of the present disclosure.

[0064] Fig.54 is a vertical cross-sectional view of a third exemplary structure after isotropically recessing the first dielectric filling material layer and the first dielectric via liner layer according to the third embodiment of the present disclosure.

[0065] Fig.55 is a vertical cross-sectional view of the third exemplary structure after depositing a second dielectric fill material layer according to the third embodiment of the present disclosure.

[0066] Fig.56 is a vertical cross-sectional view of a third exemplary structure after isotropic recessing of a second dielectric fill material layer according to a third embodiment of the present disclosure.

[0067] Fig.57 is a vertical cross-sectional view of a third exemplary structure after recessing the second and fourth dielectric liners according to the third embodiment of the present disclosure.

[0068] Fig.58 is a vertical cross-sectional view of the third exemplary structure after converting surface portions of the second dielectric liner and the fourth dielectric liner into dielectric oxide liners according to the third embodiment of the present disclosure.

[0069] Fig.59 is a vertical cross-sectional view of the third exemplary structure after forming a sacrificial contact opening filling structure according to the third embodiment of the present disclosure.

[0070] Fig.60 is a vertical cross-sectional view of the third exemplary structure after adding more dielectric material to the contact level dielectric layer according to the third embodiment of the present disclosure.

[0071] Fig.61is a vertical cross-sectional view of a third exemplary structure after replacing the sacrificial material layer with a conductive layer and forming a stepped cavity between trenches according to the third embodiment of the present disclosure.

[0072] Fig.62A is a vertical cross-sectional view of a third exemplary structure after forming a first replacement dielectric liner and a second replacement dielectric liner according to a third embodiment of the present disclosure.

[0073] Fig.62B yes Fig.62A Magnified view of area B in FIG.

[0074] Fig.63 is a vertical cross-sectional view of the third exemplary structure after removal of the sacrificial contact opening filling structure according to the third embodiment of the present disclosure.

[0075] Fig.64 is a vertical cross-sectional view of a third exemplary structure after depositing a second dielectric via liner layer according to a third embodiment of the present disclosure.

[0076] Fig.65 is a vertical cross-sectional view of a third exemplary structure after anisotropic etching of the second dielectric via liner layer according to the third embodiment of the present disclosure.

[0077] Fig.66 is a vertical cross-sectional view of a third exemplary structure after forming a layer contact via structure according to the third embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] As discussed above, the present disclosure relates to a three-dimensional memory device employing a self-aligned contact via structure and a method for manufacturing the same, various aspects of which are described below.

[0079] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is shown, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Serial numbers such as "first," "second," and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0080] The same reference numerals represent the same element or similar element. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0081] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0082] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four dies). A die is the smallest unit that can independently execute a command or report a status. Each die contains one or more planes (usually one or two planes). Although there are some limitations, the same concurrent operations can occur on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, that is, the smallest units on which a read operation can be performed.

[0083] Reference Figure 1, a first exemplary structure according to a first embodiment of the present disclosure includes a substrate 9, such as a silicon wafer, which includes a semiconductor material, such as silicon, at least at a top portion thereof. The semiconductor material forms a continuous semiconductor material layer. In one embodiment, the substrate 9 may include a single crystal semiconductor material layer, such as a single crystal silicon layer, or may include a polycrystalline semiconductor material layer. The semiconductor material layer in the substrate may have a first conductivity type of doping, which may be p-type or n-type. A surface portion of the semiconductor material layer may be used as a horizontal semiconductor channel of a three-dimensional memory device to be subsequently formed.

[0084] An alternating stack of first material layers and second material layers is subsequently formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of first material layers and second material layers, the alternating stack is referred to herein as a first alternating stack. A level of the first alternating stack is referred to herein as a first hierarchical level, and a level of the alternating stack to be subsequently formed immediately above the first hierarchical level is referred to herein as a second hierarchical level, and so on.

[0085] The first alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer 142 may be a sacrificial material layer that is subsequently replaced by a conductive layer. As used herein, "sacrificial material" refers to a material that is removed during a subsequent processing step. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although described below is an embodiment of replacing the sacrificial material layer with a conductive layer, alternative embodiments in which the spacer material layer is formed as a conductive layer are clearly contemplated herein.

[0086] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. A plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed over the substrate 9.

[0087] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therebetween, or may have different thicknesses. The second element may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0088] The first alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0089] The second material of the first sacrificial material layer 142 is a sacrificial material that can be selectively removed relative to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective" relative to a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0090] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced by a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may include silicon nitride.

[0091] Thus, in one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0092] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the first alternating stack (132, 142) can have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0093] The first exemplary structure may include a memory array region 100, in which a three-dimensional array of memory elements will be subsequently formed, and a contact region 300, in which a contact via structure contacting the stepped surface of the conductive layer will be subsequently formed. In one embodiment, a peripheral device region containing at least one semiconductor device for peripheral circuitry may be located on a substrate 9 below the alternating stacks (132, 142) in the memory array region 100 in an under-array CMOS configuration. In another alternative embodiment, the peripheral device region may be located on a separate substrate that is subsequently bonded to the memory array region 100.

[0094] Reference Figure 2, the first alternating stack (132, 142) may be patterned to form a first stepped surface 301 in the contact region 300. The contact region 300 may include a first region and a second region, in which the first stepped surface 301 is formed, and in which an additional stepped surface is subsequently formed in a second hierarchical structure (which is subsequently formed above the first hierarchical structure) and / or an additional hierarchical structure. The first stepped surface 301 may be formed, for example, by etching a cavity in a pair of layers, in which a mask layer having an opening is formed, in a topmost first sacrificial material layer 142 and a topmost first insulating layer 132, and by iteratively extending the opening in the mask layer and vertically recessing the cavity by etching each pair of first insulating layers 132 and first sacrificial material layers 142 directly below the bottom surface of the etched cavity in the etched region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface 301. The cavity covering the first stepped surface 301 is referred to herein as a first stepped cavity.

[0095] Reference Figure 3 , at least one first level dielectric liner (23, 24) may be deposited on the first stepped surface 301 of the patterned alternating stack (132, 142). In one embodiment, the at least one first level dielectric liner (23, 24) may include a first dielectric liner 23 and a second dielectric liner 24. In one embodiment, the first dielectric liner 23 may include a silicon oxide liner, and the second dielectric liner 24 may include a silicon nitride liner, a silicon carbonitride liner, a semiconductor material liner (such as an amorphous silicon liner), or a doped silicate glass liner (such as a phosphosilicate glass liner or a borosilicate glass liner). In one embodiment, the first dielectric liner 23 may have a thickness in the range of 10 nm to 50 nm, and the second dielectric liner 24 may have a thickness in the range of 30 nm to 100 nm, but smaller and larger thicknesses may also be used for the first dielectric liner 23 and the second dielectric liner 24. Preferably, the thickness of the second dielectric liner 24 is at least 50% greater than the thickness of each of the first insulating layer 132 and the first sacrificial material layer 142. The at least one first-level dielectric liner (23, 24) may be patterned so that the at least one first-level dielectric liner (23, 24) may be removed from outside the region of the stepped surface. In other words, the at least one first-level dielectric liner (23, 24) is removed from each region of each layer of the patterned alternating stack (132, 142) in which there is a patterned alternating stack (132, 142). In addition, the at least one first-level dielectric liner (23, 24) may be patterned so that the at least one first-level dielectric liner (23, 24) is removed from all regions where a backside trench will be subsequently formed.

[0096] Reference Figure 4, a dielectric filling material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited to fill the first stepped cavity. For example, an excess portion of the dielectric filling material may be removed from above a horizontal plane including the top surface of the topmost layer of the at least one first-level dielectric liner (23, 24) by performing a chemical mechanical polishing (CMP) process. The remaining portion of the dielectric filling material filling the area covering the first stepped surface 301 constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The top surface of the first backward stepped dielectric material portion 165 may be vertically recessed to a certain height at or near the topmost surface of the first dielectric liner 23. Portions of the second dielectric liner 24 not masked by the first backward stepped dielectric material portion 165 can be removed by performing a timed isotropic etching process, such as a wet etching process using a mixture of hot phosphoric acid and / or hydrofluoric acid and ethylene glycol. The physically exposed top surface of the first dielectric liner 23 and the top surface of the first backward stepped dielectric material portion 165 can be formed in the same horizontal plane. Typically, the first backward stepped dielectric material portion 165 is formed above the at least one first level dielectric liner (23, 24).

[0097] Reference Figure 5 , an optional first insulating cap layer 172 may be formed over the first alternating stack (132, 142) and the first backward stepped dielectric material portion 165. The optional first insulating cap layer 172, if used, comprises an insulating material such as silicon oxide and may have a thickness in the range of 30 nm to 300 nm, although lesser and greater thicknesses may also be employed. The combination of the first alternating stack (132, 142), the first backward stepped dielectric material portion 165, and the optional first insulating cap layer 172 together constitute a first hierarchical structure, which is a process structure that is subsequently modified.

[0098] A first photoresist layer (not shown) may be applied over the first hierarchical structure and may be photolithographically patterned to form a periodic two-dimensional array of openings in the memory array region 100. A first anisotropic etching process may be performed to transfer the opening pattern in the first photoresist layer through the first hierarchical structure into an upper portion of the substrate 9. A two-dimensional array of first hierarchical memory openings 149 may be formed through the first alternating stacks (132, 142) in the memory array region 100. The first photoresist layer may then be removed, for example, by ashing.

[0099] Reference Figure 6, a second photoresist layer (not shown) may be applied over the first hierarchical structure and may be photolithographically patterned to form openings in the contact region 300. A second anisotropic etching process may be performed to transfer the opening pattern in the second photoresist layer through the first hierarchical structure into the upper portion of the substrate 9. In the contact region 300, an opening is formed through the first hierarchical structure. The opening includes a first hierarchical support opening 119, in which a portion of a support post structure is subsequently formed, and a first hierarchical contact opening 185, which is subsequently used to form a contact via structure.

[0100] A first subset of first level support openings 119 and first level contact openings 185 are formed through the first stepped surface 301 and the first backward stepped dielectric material portion 165, and a second subset of first level support openings 119 and first level contact openings 185 are formed outside the area of ​​the first backward stepped dielectric material portion 165 and through each layer in the first alternating stack (132, 142). Thus, openings 119 and 185 are formed during the same photolithography and etching steps. The second photoresist layer can then be removed, for example, by ashing.

[0101] Although the described embodiment forms the first level memory opening 149 before forming the first level support opening 119 and the first level contact opening 185, alternative embodiments are expressly contemplated in which the first level memory opening 149 is formed after or simultaneously with the formation of the first level support opening 119 and the first level contact opening 185 (by employing a common photoresist layer).

[0102] Reference Figure 7, a sacrificial filling material may be deposited in the first level memory opening 149, the first level support opening 119, and the first level contact opening 185, and excess portions of the sacrificial filling material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 172. The sacrificial filling material may include carbon (such as amorphous carbon or diamond-like carbon) or a semiconductor material (such as amorphous silicon or a silicon-germanium alloy) or an organosilicate glass. Optionally, a sacrificial liner (such as a silicon oxide liner or a dielectric metal oxide liner, not shown) may be formed therein before depositing the sacrificial filling material in each of the first level openings (149, 119, 185). Each remaining portion of the sacrificial filling material filling the first level memory opening 149 constitutes a first level memory opening filling structure 148. Each remaining portion of the sacrificial filling material filling the first level support opening 119 constitutes a first level support opening filling structure 118. Each remaining portion of the sacrificial filling material filling the first level contact opening 185 constitutes a first level contact opening filling structure 184. Generally, various first level opening filling structures (148, 118, 184) may be formed in various first level openings (149, 119, 185).

[0103] An inter-level dielectric layer 174 may optionally be formed over the first level structure. If present, the inter-level dielectric layer 174 includes a dielectric material such as silicon oxide. The thickness of the inter-level dielectric layer 174 may range from 20 nm to 200 nm, although lesser and greater thicknesses may also be used.

[0104] Reference Figure 8 , a second alternating stack (232, 242) of material layers may then be formed on the top surface of the first alternating stack (132, 142). The second stack (232, 242) includes a plurality of alternating third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0105] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed relative to the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0106] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0107] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed relative to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0108] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 may be in the range of 20 nm to 50 nm, but smaller and larger thicknesses may be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair may be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second stack (232, 242) may have a uniform thickness that is substantially constant within each corresponding second sacrificial material layer 242.

[0109] By performing the same set of processing steps as those for forming the first stepped surface 301 and appropriately adjusting the pattern of at least one mask layer, the second stepped surface 302 may be formed in a region of the contact region 300 that is laterally offset from the region of the first stepped surface 301 toward the memory array region 100. A second stepped cavity may be formed in the region of the contact region 300.

[0110] Reference Fig. 9 , at least one second level dielectric liner (27, 28) may be deposited on the patterned second alternating stack (232, 242). In one embodiment, the at least one second level dielectric liner (27, 28) may include a third dielectric liner 27 and a fourth dielectric liner 28. In one embodiment, the third dielectric liner 27 may include a silicon oxide liner, and the fourth dielectric liner 28 may include a silicon nitride liner, a silicon carbonitride liner, a semiconductor material liner (such as an amorphous silicon liner), or a doped silicate glass liner (such as a phosphosilicate glass liner or a borosilicate glass liner). In one embodiment, the third dielectric liner 27 may have a thickness in the range of 10nm to 50nm, and the fourth dielectric liner 28 may have a thickness in the range of 30nm to 100nm, but smaller and larger thicknesses may also be used for the first dielectric liner 27 and the second dielectric liner 28. Preferably, the thickness of the fourth dielectric liner 28 is at least 50% greater than the thickness of each of the second insulating layer 232 and the second sacrificial material layer 242. The at least one second level dielectric liner (27, 28) can be patterned so that the at least one second level dielectric liner (27, 28) is removed from above the area of ​​the first stepped surface 301 (i.e., from above the area of ​​the first rearward stepped dielectric material portion 165). In addition, the at least one second level dielectric liner (27, 28) can be patterned so that the at least one second level dielectric liner (27, 28) is removed from all areas where the backside trench will be subsequently formed.

[0111] Reference Fig.10, a dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. For example, an excess portion of the dielectric fill material may be removed from above a horizontal plane including the top surface of the topmost layer of the at least one second level dielectric liner (27, 28) by performing a chemical mechanical polishing (CMP) process. The remaining portion of the dielectric fill material in the contact area 300 constitutes the backward stepped dielectric material portion 265. The top surface of the second backward stepped dielectric material portion 265 may be vertically recessed to a certain height at or near the topmost surface of the third dielectric liner 27. The portion of the fourth dielectric liner 28 that is not shielded by the second backward stepped dielectric material portion 165 may be removed by performing a timed isotropic etching process, such as a wet etching process performed using a mixture of hot phosphoric acid and / or hydrofluoric acid and ethylene glycol. The physically exposed top surface of the third dielectric liner 27 and the top surface of the second backward stepped dielectric material portion 265 may be formed in the same horizontal plane. Typically, the second rear stepped dielectric material portion 265 is formed over the at least one second level dielectric liner (27, 28). The at least one second level dielectric liner (27, 28) is present on the second stepped surface 302 and is not present on the first stepped surface 301. The at least one first level dielectric liner (23, 24) is present on the first stepped surface 301 and is not present on the second stepped surface 302.

[0112] An optional second insulating cap layer 272 may be formed over the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265. The optional second insulating cap layer 272, if used, comprises an insulating material such as silicon oxide and may have a thickness in the range of 30 nm to 300 nm, although lesser and greater thicknesses may also be employed. The combination of the second alternating stack (232, 242), the second backward stepped dielectric material portion 265, and the optional second insulating cap layer 272 together constitute a second hierarchical structure, which is a process structure that is subsequently modified.

[0113] Reference Fig.11, a third photoresist layer (not shown) may be applied over the second level structure and may be photolithographically patterned to form a periodic two-dimensional array of openings in the memory array region 100. The periodic two-dimensional array of openings may overlie and may have an area overlap with the periodic two-dimensional array of first level memory opening filling structures 148. A third anisotropic etching process may be performed to transfer the opening pattern in the third photoresist layer through the second level structure to the top surface of the first level memory opening filling structure 148. The two-dimensional array of second level memory openings may be formed through the second alternating stacks (232, 242) in the memory array region 100. The first level memory opening filling structure 148 may then be selectively removed relative to the material of the first level alternating stacks (132, 142), the second level alternating stacks (232, 242), and the substrate 9 by ashing or selective etching. Inter-level memory openings 49 (also referred to as memory openings 49) may be formed through the first level alternating stacks (132, 142) and the second level alternating stacks (232, 242). Each memory opening 49 includes a certain volume of a first level memory opening 149 and a second level memory opening. The third photoresist layer may then be removed, for example, by ashing.

[0114] Reference Fig.12 , a fourth photoresist layer (not shown) may be applied over the second level structure and may be photolithographically patterned to form an opening in the contact region 300. The opening in the fourth photoresist layer may cover the first level support opening filling structure 118 and the first level contact opening filling structure 184 and may overlap them in area. A fourth anisotropic etching process may be performed to transfer the opening pattern in the fourth photoresist layer through the second level structure to the top surface of the first level support opening filling structure 118 and the first level contact opening filling structure 184. In the contact region 300, an opening is formed through the second level structure. The opening includes a second level support opening formed above the first level support opening filling structure 118 and a second level contact opening formed above the first level contact opening filling structure 184. The first level support opening filling structure 118 and the first level contact opening filling structure 184 may then be selectively removed relative to the materials of the first level alternating stack (132, 142), the second level alternating stack (232, 242) and the substrate 9 by ashing or selective etching.

[0115] Inter-level support openings 19 (also referred to as support openings 19) may be formed through the first level structure and the second level structure. Each support opening 19 includes a first level support opening 119 and a second level support opening of a certain volume. Inter-level contact openings 35 (also referred to as contact openings 35) may be formed through the first level structure and the second level structure. Each contact opening 35 includes a first level contact opening 185 and a second level contact opening of a certain volume. The fourth photoresist layer may then be removed, for example, by ashing.

[0116] Although the described embodiment forms the memory opening 49 before forming the support opening 19 and the contact opening 35, alternative embodiments are expressly contemplated herein in which the memory opening 49 is formed after or simultaneously (by employing a common photoresist layer) with the formation of the support opening 19 and the contact opening 35. In general, the memory opening 49 and the contact opening 35 can be formed by performing at least one anisotropic etching process through an alternating stack of at least one insulating layer (132, 232) and a spacer material layer (such as a sacrificial material layer (142, 242)), employing at least one patterned etching mask layer (such as a patterned photoresist layer), and removing the exposed sacrificial material filling the first level opening.

[0117] Reference Fig.13 , a dielectric liner layer 51L, a sacrificial opening filling structure (48, 18, 36), and a dielectric capping layer 274 may be formed on the first exemplary structure. The dielectric liner layer 51L may include a dielectric material, such as silicon oxide and / or a dielectric metal oxide. In one embodiment, the dielectric liner layer 51L includes a dielectric material that provides etching resistance to hot phosphoric acid that will be used to etch the silicon nitride sacrificial material layer (142, 242). The dielectric liner layer 51L may be deposited by conformal deposition (such as low pressure chemical vapor deposition). The thickness of the dielectric liner layer 51L may be in the range of 5nm to 30nm, such as 8nm to 20nm, but smaller and larger thicknesses may also be used. Portions of the dielectric liner layer 51 may be used as blocking dielectrics for vertical NAND strings in subsequent steps.

[0118] Sacrificial opening filling structures (48, 18, 36) may be formed in various openings (49, 19, 85) passing through the alternating stack {(132, 142), (232, 242)}. The sacrificial opening filling structures (48, 18, 36) may be formed by depositing a sacrificial filling material in the various openings (49, 19, 85) and by removing a portion of the sacrificial filling material deposited above the top surface of the horizontally extending portion of the dielectric liner layer 51L, which covers the alternating stack {(132, 142), (232, 242)}. The sacrificial filling material may include carbon (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or a silicon-germanium alloy), an organosilicate glass, or a polymer material. The sacrificial opening filling structures (48, 18, 36) may include a sacrificial memory opening filling structure 48 formed in the memory opening 49, a sacrificial support opening filling structure 18 formed in the support opening 19, and a sacrificial contact opening filling structure 36 formed in the contact opening 35.

[0119] The optional dielectric capping layer 274 comprises a dielectric material such as undoped silicate glass or doped silicate glass. The dielectric capping layer 274 may have a thickness in a range of 20 nm to 400 nm, such as 40 nm to 200 nm, although lesser and greater thicknesses may also be employed.

[0120] Reference Fig.14 , a photoresist layer (not shown) may be applied over the dielectric capping layer 274 and may be photolithographically patterned to form openings over the areas of the sacrificial memory opening filling structures 48 and the sacrificial support opening filling structures 18. An anisotropic etching process may be performed to form openings through the dielectric capping layer 274 and to physically expose the top surfaces of the sacrificial memory opening filling structures 48 and the sacrificial support opening filling structures 18. A selective etching process may be performed to selectively remove the sacrificial memory opening filling structures 48 and the sacrificial support opening filling structures 18 relative to the dielectric liner layer 51L. A memory cavity 49' is formed in each volume from which the sacrificial memory opening filling structure 48 is removed, and a support cavity 19' is formed in each volume from which the sacrificial support opening filling structure 18 is removed. Typically, the sacrificial memory opening filling structures 48 and the sacrificial support opening filling structures 18 may be removed without removing the sacrificial contact opening filling structures 36.

[0121] Reference Fig.15, a semiconductor base (not shown) may be optionally formed at the bottom of each memory opening 49 and each support opening 19. A memory film 50 may be formed in each of the memory openings 49 and the support openings 19. The memory film 50 may include any memory material that can store information by charge trapping, resistivity change, ferroelectric dipole moment direction change (e.g., in a ferroelectric material), or any other material in which information can be stored. For example, each memory film 50 may include a layer stack that includes a blocking dielectric layer 52, a charge storage material layer 54, and a tunneling dielectric layer 56. In one embodiment, the memory film 50 may be formed by depositing a material layer and / or a material portion, and removing excess portions of the material layer and / or the material portion from outside the memory openings 49 and the support openings 19, for example, by performing an anisotropic etching process.

[0122] In one embodiment, dielectric liner layer 51L may include a blocking dielectric material. In this embodiment, the vertically extending portion of dielectric liner layer 51L may serve as blocking dielectric layer 52. Charge storage material layer 54 may include a silicon nitride layer. Tunneling dielectric layer 56 may include a silicon oxide layer or an "ONO" stack of silicon oxide / silicon nitride / silicon oxide layers.

[0123] A vertical semiconductor channel 60 may be formed in each of the memory opening 49 and the support opening 19 by conformally depositing a semiconductor channel material (e.g., amorphous silicon or polycrystalline silicon) having a doping of a first conductivity type. The semiconductor channel material may have a doping of the same conductivity type as a horizontal semiconductor channel (not explicitly shown) located in the upper portion of the substrate 9. A dielectric fill material may be deposited in the remaining volume of the memory opening 49 and the support opening 19, and may be vertically recessed to form a dielectric core 62. A semiconductor material (e.g., amorphous silicon or polycrystalline silicon) having a doping of a second conductivity type may be deposited on each dielectric core 62 at the top of each vertical semiconductor channel 60 to form a drain region 63. The second conductivity type is opposite to the first conductivity type. Each continuous combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each memory stack structure 55 includes a corresponding vertical memory element stack. For example, each vertical stack of memory elements may include a portion of the charge storage layer 54 at the level of a sacrificial material layer (142, 242) that is subsequently replaced by a conductive layer.

[0124] Typically, the memory opening filling structures 58 are formed in the volume where the sacrificial memory opening filling structures 48 are removed and the sacrificial contact opening filling structures 36 are present in the contact openings 35. Each of the memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical memory element stack (e.g., a portion of the memory film 50), a drain region 63, and an optional dielectric core 62. Optionally, a drain select level dielectric isolation structure 72 (shown in FIG. 1 ) is provided. FIG. 17A to FIG. 17C ) may be formed through an uppermost set of second sacrificial material layers 242 at the level of the drain side select gate electrode to be formed.

[0125] Reference Fig.16 , a contact-level dielectric layer 280 may be formed over the dielectric capping layer 274. The contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be employed.

[0126] Reference FIG. 17A to FIG. 17C , the drain selection level dielectric isolation structure 72 may extend laterally along a first horizontal direction (e.g., a word line direction) hd1, and may be laterally spaced apart along a second horizontal direction (e.g., a bit line direction) hd2. A photoresist layer (not shown) may be applied over the contact level dielectric layer 280 and photolithographically patterned to form an opening in an area extending across the memory array region 100 and the contact region 300. The opening in the photoresist layer may extend laterally between each adjacent cluster of the memory opening filling structure 58 along the first horizontal direction hd1. The backside trench 79 may be formed by transferring the pattern in the photoresist layer through the contact level dielectric layer 280, the second alternating stack (232, 242, 272, 265, 72), and the first alternating stack (132, 142, 172, 165) into the substrate 9. The contact level dielectric layer 280, the second alternating stacks (232, 242, 272, 265, 72), the first alternating stacks (132, 142, 172, 165), and portions of the substrate 9 below the openings in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of memory opening fill structures 58. The clusters of memory opening fill structures 58 may be laterally spaced apart by backside trenches 79 along a second horizontal direction hd2.

[0127] refer to Fig.18, an etchant that selectively etches the material of the first and second sacrificial material layers (142, 242) relative to the material of the first and second insulating layers (132, 232), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the first and second sacrificial material layers (142, 242) can include silicon nitride, and the first and second insulating layers (132, 232), the first and second insulating cap layers (172, 272), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 can include silicon oxide material. The first backside recess is formed in the volume from which the first sacrificial material layer 142 is removed. The second backside recess is formed in the volume from which the second sacrificial material layer 242 is removed.

[0128] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the first and second sacrificial material layers (142, 242) include silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide and silicon.

[0129] Each of the first and second back side recesses can be a cavity extending laterally, the lateral dimension of the cavity being greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second back side recesses can be greater than the height of the corresponding back side recess. A plurality of first back side recesses can be formed in a volume from which the first sacrificial material layer 142 material is removed. A plurality of second back side recesses can be formed in a volume from which the second sacrificial material layer 242 material is removed. Each of the first and second back side recesses can extend substantially parallel to the top surface of the substrate 9. The back side recess can be vertically defined by the top surface of the lower insulating layer (132 or 232) and the bottom surface of the overlying insulating layer (132 or 232). In one embodiment, each of the first back side recess and the second back side recess can always have a uniform height.

[0130] A backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses and backside trenches 79, and over the contact-level dielectric layer 280. The backside blocking dielectric may include a dielectric metal oxide material, such as aluminum oxide. At least one conductive material may be conformally deposited in the plurality of backside recesses, on the sidewalls of the backside trenches 79, and over the contact-level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metal element.

[0131] A plurality of first conductive layers 146 may be formed in the plurality of first backside recesses, a plurality of second conductive layers 246 may be formed in the plurality of second backside recesses, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 280. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer.

[0132] The metal material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. The metal material can be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy, such as a metal silicide, an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that can be deposited in the back side recess include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and / or ruthenium. In one embodiment, the metal material may include a metal, such as tungsten and / or a metal nitride. In one embodiment, the metal material for filling the back side recess may be a combination of a titanium nitride layer and a tungsten filling material. In one embodiment, the metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0133] The deposited metal material of the continuous metal material layer may be etched back, for example, by anisotropic or isotropic etching, from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 280. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure.

[0134] A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode can be used as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55. One or more bottommost conductive layers 146 constitute a source select gate electrode.

[0135] Each of the memory opening filling structures 58 (which contains the corresponding memory stack structure 55) includes a vertical stack of memory elements at each level of the conductive layer (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. A horizontal source line (e.g., a direct strap contact) may be formed below the conductive layer 146 through the backside trench 79 to contact one side of the lower portion of the semiconductor channel 60. An insulating material layer may then be formed in the backside trench 79 to completely fill the entire volume of the backside trench 79.

[0136] Reference Fig.19 , a photoresist layer (not shown) may be applied over the contact level dielectric layer 280, and an opening may be formed over the region of the sacrificial contact opening filling structure 36. An anisotropic etching process may be performed to etch through the contact level dielectric layer 280 and the unmasked portion of the dielectric capping layer 274 and physically expose the top surface of the sacrificial contact opening filling structure 36. Subsequently, the sacrificial contact opening filling structure 36 may be removed by performing a selective etching process that selectively etches the sacrificial filling material of the sacrificial contact opening filling structure 36 relative to the material of the dielectric liner layer 51L. A contact cavity 85 is formed in the volume from which the sacrificial contact opening filling structure 36 is removed. The photoresist layer may then be removed, for example, by ashing.

[0137] Reference Fig. 20 A first isotropic etching process may be performed to selectively remove a portion of the dielectric liner layer 51L surrounding the contact cavity 85 relative to the material of the alternating stacks {(132, 146), (232, 246)} and the backward stepped dielectric material portion (165, 265).

[0138] Subsequently, the contact cavity 85 may be laterally expanded by performing a second isotropic etching process that selectively recesses proximal portions of the insulating layer (132, 232), the back stepped dielectric material portion (165, 265), the optional first insulating cap layer 172, the optional inter-level dielectric layer 174, the optional dielectric capping layer 274, and the contact-level dielectric layer 280 surrounding each of the contact cavities 85 relative to the conductive layer (146, 246). In an illustrative example, the insulating layer (132, 232), the back stepped dielectric material portion (165, 265), the optional first insulating cap layer 172, the optional inter-level dielectric layer 174, the optional dielectric capping layer 274, and the contact-level dielectric layer 280 may include a silicon oxide material (such as undoped silicate glass or doped silicate glass), and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The duration of the second isotropic etching process may be selected so that the lateral recess distance of the sidewalls of the insulating layer (132, 232) surrounding each of the contact cavities 85 is in the range of 20 nm to 200 nm, such as 40 nm to 100 nm, although smaller and larger lateral recess distances may also be employed. In embodiments where the dielectric liner layer 51L comprises silicon oxide, the first isotropic etching process and the second isotropic etching process may be combined into a single etching process.

[0139] The contact cavity 85 (hereinafter also referred to as the laterally extended contact cavity 85) includes a corresponding upper portion formed by laterally recessing at least one rearward stepped dielectric material portion (165, 265), and a corresponding lower portion extending through at least one dielectric liner {(23, 24) or (27, 28)} and a corresponding layer group in at least one alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246). The upper portion of each contact cavity 85 includes a corresponding cylindrical cavity, which is laterally surrounded by the remaining portion of at least one rearward stepped dielectric material portion (165, 265). The lower portion of each contact cavity 85 includes a corresponding fin-shaped cavity located below the corresponding cylindrical cavity. As used herein, a "fin-shaped cavity" refers to a cavity having a central cavity 85C and at least one fin-shaped cavity 85F, which extends laterally outward from the central cavity 85C and has a corresponding vertical extent that is less than the vertical extent of the central cavity 85C. Each fin-shaped cavity includes a central cavity 85C and at least one fin-shaped cavity 85F, which protrudes laterally outward from the central cavity. In one embodiment, each fin-shaped cavity can have a corresponding tubular shape, that is, the shape of a volume created by the vertical movement of a perforated disk having an inner perimeter and an outer perimeter.

[0140] Reference Fig.21, a first dielectric filling material layer 82L containing a first dielectric filling material can be conformally deposited in the laterally extended contact cavity 85 by a first conformal deposition process (such as a low pressure chemical vapor deposition (LPCVD) process). The first dielectric filling material layer 82L contains a first dielectric filling material, such as undoped silicate glass (i.e., silicon oxide), doped silicate glass, or organic silicate glass. The first dielectric filling material layer 82L can be conformally deposited in the fin-shaped cavity 85F and in the peripheral area of ​​the central cavity 85C of the laterally extended contact cavity 85. The thickness of the first dielectric filling material layer 82L can be less than half of the lateral dimension of each laterally extended contact cavity 85. The portion of the dielectric fin 82F of the first dielectric filling material layer 82L that protrudes laterally outward at the level of a corresponding one of the insulating layers (132, 232) is located in each corresponding fin-shaped cavity 85F.

[0141] In one embodiment, the duration of the first conformal deposition process may be selected so that the seam within the opening in at least one dielectric liner (23, 24, 27, 28) is sealed. A void 85' may exist within the upper portion of each laterally expanded contact cavity 85. In some embodiments, an air gap 85G may exist below the sealed seam in the first dielectric fill material layer 82L in the lower portion of one, more, or each laterally expanded contact cavity 85.

[0142] Reference Fig. 22 , a first isotropic etching process may be performed to isotropically etch a portion of the first dielectric filling material layer 82L from above the opening in at least one dielectric liner (23, 24, 27, 28) in the laterally extended contact cavity 85. The sidewalls of the backward stepped dielectric material portion (165, 265) may be physically exposed around the laterally extended contact cavity 85. The top surface of one of the at least one dielectric liner (23, 24, 27, 28) may be physically exposed to the void 85' within each laterally extended contact cavity 85. Generally, the first dielectric filling material of the first dielectric filling material layer 82L may be removed from the inside of the cylindrical cavity covering the top surface of the corresponding one of the at least one dielectric liner (23, 24, 27, 28). Each remaining portion of the first dielectric filling material remaining in the corresponding laterally extended contact cavity 85 constitutes a first dielectric filling material portion 82. If any air gaps 85G exist before the first isotropic etching process, they are connected to the voids 85' and converted into open gaps. The duration of the first isotropic etching process can be selected so that the top surface segments of the second dielectric liner 24 and the top surface segments of the fourth dielectric liner 28 are physically exposed after the first isotropic etching process.

[0143] Reference Fig.23, a second dielectric filling material layer 84L containing a second dielectric filling material can be conformally deposited in the void 85' in the laterally expanded contact cavity 85 by a second conformal deposition process (such as a low pressure chemical vapor deposition (LPCVD) process). The second dielectric filling material layer 84L contains a second dielectric filling material, such as undoped silicate glass, doped silicate glass, or organic silicate glass. The second dielectric filling material can be the same as or different from the first dielectric filling material. The second dielectric filling material layer 84L can be conformally deposited in the seams in the first dielectric filling material portion 82 and in the peripheral area of ​​the cylindrical cavity of the laterally expanded contact cavity 85. The thickness of the second dielectric filling material layer 84L can be selected so that the seams and gaps below the opening in at least one dielectric liner (23, 24, 27, 28) are filled by the second dielectric filling material layer 84L. Thus, void-free filling by dielectric material portions may be provided within each portion of the laterally extended contact cavity 85 laterally surrounded by the alternating stacks of insulating layers {(132, 146), (232, 246)}. A void 85′ may be present within an upper portion of each laterally extended contact cavity 85.

[0144] Reference Fig.24 , a second isotropic etching process may be performed to isotropically etch a portion of the second dielectric filling material layer 84L from above the opening in at least one dielectric liner (23, 24, 27, 28) in the laterally extended contact cavity 85. The sidewalls of the backward stepped dielectric material portion (165, 265) may be physically exposed around the laterally extended contact cavity 85. The top surface of one of the at least one dielectric liner (23, 24, 27, 28) may be physically exposed to the void 85' within each laterally extended contact cavity 85. Generally, the second dielectric filling material of the second dielectric filling material layer 84L may be removed from the interior of the cylindrical cavity overlying the top surface of the corresponding one of the at least one dielectric liner (23, 24, 27, 28). Each remaining portion of the second dielectric filling material remaining in the corresponding laterally extended contact cavity 85 (e.g., in the open gap portion of the cavity 85) constitutes a second dielectric filling material portion 84. Fig.23 and 24 The processing step is optional. Fig. 22 After the above processing steps, there is no seam in the first dielectric filling material portion 82, and the reference Fig.23 and Fig.24 The processing steps described.

[0145] Typically, at least one dielectric filling material may be conformally deposited in the laterally expanded contact cavity 85 and may be isotropically recessed in an upper portion thereof, i.e., in a cylindrical cavity within the laterally expanded contact cavity 85. Each remaining portion of the at least one dielectric filling material filling a fin cavity located at a lower portion of a corresponding one of the laterally expanded contact cavities 85 constitutes a fin-shaped dielectric pillar structure (82, 84). In other words, the fin-shaped dielectric pillar structure (82, 84) includes a remaining portion of the at least one dielectric filling material filling a fin cavity, which is a lower portion of the laterally expanded contact cavity 85.

[0146] Each fin-like dielectric pillar structure (82, 84) extends vertically through at least one of the alternating stacks {(132, 146), (232, 246)} in the contact region 300. In one embodiment, each of the fin-like dielectric pillar structures (82, 84) includes at least one dielectric fin 82F that protrudes laterally outward at the level of a corresponding one of the insulating layers (132, 232). In one embodiment, one or more of the at least one dielectric fin 82F includes a cylindrical sidewall that contacts a corresponding one of the insulating layers (132, 232). In one embodiment, each of the fin-like dielectric pillar structures (82, 84) includes a dielectric base structure 83 that is a cylindrical portion of the corresponding fin-like dielectric pillar structure (82, 84) that extends vertically from the substrate 9 to a corresponding one of the at least one dielectric liner (23, 24, 27, 28). Thus, each of the fin-like dielectric pillar structures (82, 84) may include a corresponding dielectric base structure 83 and a corresponding group of at least one dielectric fin 82F protruding laterally outward from the corresponding dielectric base structure 83. In one embodiment, for each of the fin-like dielectric pillar structures (82, 84), the combination of the at least one dielectric fin 82F and the tubular portion of the dielectric base structure 83 constitutes a first dielectric filling material portion 82 containing a first dielectric filling material, and the cylindrical core portion of the dielectric base structure 83 constitutes a second dielectric filling material portion 84 containing a second dielectric filling material, with a boundary therebetween.

[0147] Reference Fig.25, performing an etching process to recess the upper dielectric liner (24, 28) into each of the at least one dielectric liner (23, 24, 27, 28). For example, the proximal portion of the second dielectric liner 24 and the fourth dielectric liner 28 adjacent to the gap 85' may be selectively removed relative to the material of the first dielectric liner 23 and the third dielectric liner 27. The etching process may include an anisotropic etching process or an isotropic etching process. In an illustrative example, if the second dielectric liner 24 and the fourth dielectric liner 28 include silicon nitride, the etching process may include a wet etching process using a mixture of hot phosphoric acid and / or hydrofluoric acid and ethylene glycol. Alternatively, if the second dielectric liner 24 and the fourth dielectric liner 28 include silicon carbonitride, the etching process may include a reactive ion etching process. During the etching process to remove the physically exposed portions of the second dielectric liner 24 and the fourth dielectric liner 28, portions of the first dielectric liner 23 and the third dielectric liner 27 may or may not be recessed in parallel. In general, the protrusion profile of the dielectric base structure 83 depends on the details of the previous process, such as reference Fig. 20 The processing steps described above. The height of the vertical protrusion 83P of each dielectric base structure 83 may be relatively large or relatively small to appear as a bump, or may even include a depression instead of a protrusion. In addition, the lateral extent of the lateral protrusion 85P at the bottom of each void 85' may have a wavy vertical cross-sectional profile, so that the annular concave surface of the second dielectric liner 24 and the annular concave surface of the fourth dielectric liner 28 are physically exposed around the lateral protrusion 85P of the void 85'. Generally, the lateral extent of the lateral protrusion 85P of the void 85' can be controlled to avoid physically exposing the adjacent sacrificial material layer (142, 242).

[0148] Reference Fig.26, another etching process is performed to recess the lower dielectric liner (23, 27) into each of the at least one dielectric liner (23, 24, 27, 28). For example, the proximal portion of the first dielectric liner 23 and the third dielectric liner 27 adjacent to the gap 85' can be removed selectively relative to the material of the insulating layer (132, 232) and the conductive layer (146, 246). The etching process may include an anisotropic etching process or an isotropic etching process. In an illustrative example, the first dielectric liner 23 and the third dielectric liner 27 may include silicon oxide, and the etching process may include an anisotropic etching process that selectively etches the material of the first dielectric liner 23 and the third dielectric liner 27 (and the material of the backside blocking dielectric layer, if used) relative to the material of the conductive layer (146, 246). A remaining portion of at least one dielectric liner (23, 24, 27, 28) may be interposed between at least one rearward stepped dielectric material portion (165, 265) and the stepped surfaces (301, 302) of the alternating stacks {(132, 146), (232, 246)}.

[0149] If a backside blocking dielectric is formed in the backside recess, the backside blocking dielectric is also removed during the etching process to expose the top surface of the conductive layer (146, 246) in the void 85'.

[0150] Reference Fig. 27 , at least one conductive material (such as at least one metal material) may be deposited in the voids 85' within the laterally extended contact cavity 85 and on the contact level dielectric layer 280. The at least one conductive material may include a metal barrier material and a metal filling material. The metal barrier material may include a conductive metal nitride material, such as TiN, TaN, WN, MoN, or a combination thereof. The metal filling material may include W, Co, Ru, Mo, Cu, or a combination thereof. Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 280. Each remaining portion of the at least one conductive material filling the corresponding void 85' within the laterally extended contact cavity 85 constitutes a layer contact through-hole structure 86.

[0151] A layer contact via structure 86 is formed in an upper portion of the laterally expanded contact cavity 85. The layer contact via structure 86 extends vertically through at least one rearward stepped dielectric material portion (165, 265) and contacts a top surface segment of a corresponding one of the conductive layers (146, 246). In one embodiment, each layer contact via structure 86 includes a corresponding annular bottom surface that contacts an annular top surface segment of a corresponding one of the conductive layers (146, 246).

[0152] Each layer contact via structure 86 covers and contacts a corresponding one of the fin-like dielectric pillar structures (82, 84). Each layer contact via structure 86 may include a stepped bottom surface including a raised bottom surface 86R at a central portion and an annular bottom surface 86A at a peripheral portion. The lower fin-like dielectric pillar structure (82, 84) may protrude through a hole in the annular bottom surface 86A and contact the raised bottom surface 86R of the layer contact via structure 86. In one embodiment, each layer contact via structure 86 includes a corresponding raised bottom surface 86R that contacts a top surface segment of a corresponding one of the fin-like dielectric pillar structures (82, 84) and is located above a horizontal plane including the corresponding annular bottom surface 86A. In one embodiment, each layer contact via structure 86 includes an inner cylindrical sidewall 86S that contacts an upper portion of a cylindrical sidewall of a corresponding one of the fin-like dielectric pillar structures (82, 84). The inner cylindrical sidewall 86S may connect the perimeter of the raised bottom surface 86R and the inner perimeter of the annular bottom surface 86A of the layer contact via structure 86.

[0153] In one embodiment, one, more than one, or each of the layer contact via structures 86 includes: an upper cylindrical portion 86U that contacts at least one rear stepped dielectric material portion (165, 265); and a lower base portion 86L that has a greater lateral extent than the bottom perimeter of the cylindrical sidewall of the upper cylindrical portion 86U and includes an annular top surface having an inner perimeter that coincides with the bottom perimeter of the cylindrical sidewall of the upper cylindrical portion 86U. In one embodiment, the horizontal surface of at least one dielectric liner (23, 24, 27, 28) may be located in the same horizontal plane as the annular top surface of a corresponding one of the layer contact via structures 86.

[0154] In the second embodiment, the first to fourth dielectric spacers (23, 24, 27, 28) of the first embodiment are omitted. Fig.28 , the topmost first insulating layer 132 and the hard mask layer 16 may be patterned in a region outside the first stepped surface 301, from the reference Figure 2 The first exemplary structure described above leads to a second exemplary structure according to the second embodiment of the present disclosure. For example, the hard mask layer 16 may include a silicon nitride pad layer. The first stepped cavity exists on the first stepped surface 301 .

[0155] Reference Fig.29, a dielectric filling material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. For example, an excess portion of the dielectric filling material may be removed from above a horizontal plane including the top surface of the hard mask layer 16 by performing a chemical mechanical polishing (CMP) process. The remaining portion of the dielectric filling material filling the area covering the first stepped surface 301 constitutes the first backward stepped dielectric material portion 165. The top surface of the first backward stepped dielectric material portion 165 may be vertically recessed to a certain height at or near the bottom surface of the hard mask layer 16. The hard mask layer 16 may then be selectively removed relative to the topmost first insulating layer 132. For example, if the hard mask layer 16 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the hard mask layer 16. The physically exposed top surface of the topmost first insulating layer 132 and the top surface of the first backward stepped dielectric material portion 165 may be formed in the same horizontal plane.

[0156] Reference Fig.30 , executable reference Figure 5 The processing steps are described to form a two-dimensional array of first level memory openings 149 .

[0157] Reference Fig.31 , executable reference Figure 6 The processing steps are described to form the first level support openings 119 and the first level contact openings 185 .

[0158] Reference Fig.32 , executable reference Figure 7 The processing steps are described to form various first level opening filling structures (148, 118, 184) in various first level openings (149, 119, 185) and optionally form an inter-level dielectric layer 174.

[0159] Reference Fig.33 , executable reference Figure 8 The processing steps are described to form a second alternating stack (232, 242) having a second stepped surface. A topmost second insulating layer 232 and a hard mask layer 26 may be formed in the memory array region 100 outside the contact region 300.

[0160] Reference Fig.34 , executable reference Fig.10 The processing steps are described to form the second backward stepped dielectric material portion 265. The hard mask layer 26 may be removed. An optional second insulating cap layer 272 may be formed over the second alternating stack (232, 242) and the second backward stepped dielectric material portion 265.

[0161] Reference Fig.35 , executable reference Fig.11The processing steps are described to form a memory opening 49 through the first level alternating stack (132, 142) and the second level alternating stack (232, 242).

[0162] Reference Fig.36 , executable reference Fig.12 The processing steps are performed to form the support opening 19 and the contact opening 35 .

[0163] Reference Fig.37 , executable reference Fig.13 The processing steps are described to form a dielectric liner layer 51L and form sacrificial opening filling structures (48, 18, 36) in each opening (49, 19, 85) through the alternating stack {(132, 142), (232, 242)}. An optional dielectric capping layer 274 may be formed over the dielectric liner layer 51L and the sacrificial opening filling structures (48, 18, 36).

[0164] Reference Fig.38 , executable reference Fig.14 The processing steps are described to form the storage cavity 49' and the support cavity 19'.

[0165] Reference Fig.39 , executable reference Fig.15 The processing steps are described to form a reservoir opening filling structure 58 and a support pillar structure 20 in the reservoir opening 49 and the support opening 19, respectively.

[0166] Reference Fig.40 , executable reference Fig.16 The processing steps are described to form a contact level dielectric layer 280 .

[0167] Reference Fig.41 , executable reference FIG. 17A to FIG. 17C The processing steps are described to replace the sacrificial material layer (142, 242) with the conductive layer (146, 246).

[0168] Reference Fig.42 , executable reference Fig.19 The processing steps are described to form contact cavity 85. Contact cavity 85 is formed in the volume from which sacrificial contact opening fill structure 36 was removed.

[0169] Reference Fig.43 , executable reference Fig. 20 The processing steps are described to laterally expand the contact cavity 85, which is also referred to as the laterally expanded contact cavity 85 below.

[0170] Reference Fig.44 , executable reference Fig.21The processing steps are described to conformally deposit the first dielectric fill material layer 82L.

[0171] Reference Fig.45 , executable reference Fig. 22 The processing steps are described so as to isotropically recess the first dielectric filling material layer 82L. The first dielectric material portion 82 is formed at the bottom portion of each laterally extended contact cavity 85.

[0172] Reference Fig.46 , executable reference Fig.23 The processing steps are described to conformally deposit the second dielectric fill material layer 84L.

[0173] Reference Fig.47 , executable reference Fig.24 The processing steps are performed to isotropically recess the second dielectric filling material layer 84L. The second dielectric material portion 84 is formed at the bottom portion of each laterally extended contact cavity 85 inside a corresponding one of the first dielectric material portions 82 .

[0174] Reference Fig.48 , executable reference Fig. 27 The processing steps are described to form a layer contact via structure 86 in the upper portion of the laterally extended contact cavity 85. In the second exemplary structure, one, a plurality of and / or each of the layer contact via structures 86 includes a right cylindrical sidewall extending vertically from a top surface of a corresponding one of the layer contact via structures 86 to a horizontal surface of a corresponding one of the conductive layers (146, 246).

[0175] Reference Fig.49 , the second dielectric liner 24 and the fourth dielectric liner 28 may be increased in thickness and the pattern of the second dielectric liner 24 and the fourth dielectric liner 28 may be modified. Fig.15 The illustrated first exemplary structure leads to a third exemplary structure according to a third embodiment of the present disclosure.

[0176] Specifically, the thickness of the second dielectric liner 24 and the fourth dielectric liner 28 may be greater than the thickness of each of the first sacrificial material layer 142 and the second sacrificial material layer 242. For example, the first sacrificial material layer 142 and the second sacrificial material layer 242 may have the same thickness, and the thickness of each of the second dielectric liner 24 and the fourth dielectric liner may be greater than twice the thickness of the first sacrificial material layer 142 and the second sacrificial material layer 242, such as 2.2 to 5 times. The ratio of the thickness of the second dielectric liner 24 to the thickness of each of the first sacrificial material layer 142 and the second sacrificial material layer 242 may be in the range of 2.2 to 5, such as 2.5 to 4, and / or 2.75 to 3.5, but a larger ratio may also be adopted. The ratio of the thickness of the fourth dielectric liner 28 to the thickness of each of the first sacrificial material layer 142 and the second sacrificial material layer 242 may be in the range of 2.2 to 5, such as 2.5 to 4, and / or 2.75 to 3.5, but a larger ratio may also be adopted.

[0177] The patterns of the second dielectric liner 24 and the fourth dielectric liner 28 may be modified so that the patterns of the second dielectric liner 24 and the fourth dielectric liner 28 exist in the area where the backside trench is to be formed later. In one embodiment, the patterns of the second dielectric liner 24 and the fourth dielectric liner 28 may exist on the entire area of ​​the first stepped surface and the second stepped surface, respectively. In this case, each of the second dielectric liner 24 and the fourth dielectric liner 28 may be formed as a corresponding continuous material layer, i.e., a corresponding integral structure. In one embodiment, the first dielectric liner 22 and the third dielectric liner 26 may also be formed as a corresponding continuous material layer.

[0178] In general, support pillar structures 20 may or may not include the same set of materials as memory opening fill structures 58. Likewise, materials deposited in support openings 19 may or may not be deposited in memory openings 49. While embodiments are described in which the same set of materials are deposited in memory openings 49 and in support openings 19, embodiments are expressly contemplated herein in which different sets of materials are deposited between memory openings 49 and support openings 19. Furthermore, while embodiments are described in which a pedestal trench portion is not formed at the bottom of each memory opening 49, embodiments are expressly contemplated herein in which a pedestal trench portion is formed as the bottommost feature within each memory opening fill structure 58.

[0179] In general, each of the second insulating cap layer 272, the dielectric liner layer 51L, and the dielectric capping layer 274 is an optional layer and thus may or may not be employed in various exemplary structures. The topmost surface of the alternating stack {(132, 142), (232, 242)} is located at or below the horizontal plane including the top surface of the drain region 63.

[0180] Reference Fig.50 , executable reference Fig.16 The processing steps described above are performed to form the contact level dielectric layer 280. Subsequently, reference Fig.19 The processing steps are described to remove the sacrificial contact opening filling structure 36 , thereby forming a contact cavity 85 .

[0181] Reference Fig.51 , executable reference Fig. 20 The processing steps described above, wherein optional modifications are made in the etching chemistry. Specifically, the contact cavity 85 can be laterally expanded by performing an isotropic etching process, and the second isotropic etching process selectively recesses the insulating layer (132, 232), the rear stepped dielectric material portion (165, 265), the optional first insulating cap layer 172, the optional inter-level dielectric layer 174, the optional dielectric capping layer 274, and the proximal portion of the contact level dielectric layer 280 surrounding each contact cavity in the contact cavity 85 relative to the sacrificial material layer (142, 242). In an illustrative example, the insulating layer (132, 232), the back stepped dielectric material portion (165, 265), the optional first insulating cap layer 172, the optional inter-level dielectric layer 174, the optional dielectric capping layer 274, and the contact level dielectric layer 280 may include a silicon oxide material (such as undoped silicate glass or doped silicate glass), and the second isotropic etching process may include a wet etching process using dilute hydrofluoric acid. The duration of the second isotropic etching process may be selected so that the lateral recess distance of the sidewall of the insulating layer (132, 232) surrounding each of the contact cavities 85 is in the range of 20nm to 200nm, such as 40nm to 100nm, although smaller and larger lateral recess distances may also be used. If a silicon oxide dielectric liner layer 51L is present in the third embodiment, the portion of the dielectric liner layer 51L exposed to the contact cavity 85 is also removed during etching.

[0182] The contact cavity 85 (hereinafter also referred to as the laterally extended contact cavity 85) includes a corresponding upper portion formed by laterally recessing at least one rearward stepped dielectric material portion (165, 265), and a corresponding lower portion extending through at least one dielectric liner {(23, 24) or (27, 28)} and a corresponding layer group in at least one alternating stack {(132, 142), (232, 242)} of insulating layers (132, 232) and sacrificial material layers (142, 242). The upper portion of each contact cavity 85 includes a corresponding cylindrical cavity, which is laterally surrounded by the remaining portion of at least one rearward stepped dielectric material portion (165, 265). The lower portion of each contact cavity 85 includes a corresponding fin-shaped cavity located below the corresponding cylindrical cavity. Each fin-shaped cavity has a central cavity 85C and at least one fin-shaped cavity 85F, which extends laterally outward from the central cavity 85C and has a corresponding vertical range that is smaller than the vertical range of the central cavity 85C. Each fin-shaped cavity includes a central cavity 85C and at least one fin-shaped cavity 85F, which protrudes laterally outward from the central cavity. In one embodiment, each fin-shaped cavity can have a corresponding tubular shape.

[0183] Reference Fig.52 , an optional first dielectric via liner layer 81L may be formed by conformally depositing a dielectric material different from the material of the sacrificial material layer (142, 42). For example, the first dielectric via liner layer 81L may include undoped silicate glass, doped silicate glass, silicon carbide, silicon carbide nitride, or a dielectric metal oxide that is resistant to an etchant subsequently used to remove the sacrificial material layer (142, 242). The thickness of the first dielectric via liner layer 81L may be less than half the thickness of each of the sacrificial material layers (142, 242). The thickness of the first dielectric via liner layer 81L may be 2 nm to 3 nm. Thus, the fin void is retained within the volume of the corresponding fin cavity.

[0184] Reference Fig.53 , executable reference Fig.21 The processing steps are described to form a first dielectric fill material layer 82L. The seam may or may not be formed within the volume of the fin-shaped cavity (e.g., Fig.50 formed during the processing steps).

[0185] Reference Fig.54 , executable reference Fig. 22The processing steps are described to isotropically recess the first dielectric filling material layer 82L and remove the portion of the first dielectric via liner layer 81L covering the second dielectric liner 24 or the fourth dielectric liner 28. Each remaining portion of the first dielectric via liner layer 81L is referred to herein as a first dielectric via liner 81. Each first dielectric via liner 81 is laterally surrounded by a subset of the layers of the alternating stack {(132, 142), (232, 242)} and is located below a corresponding void having a larger lateral dimension than the opening in the overlying second dielectric liner 24 or the overlying fourth dielectric liner 28.

[0186] Reference Fig.55 , optionally perform a reference Fig.23 The processing steps are performed to form a second dielectric filling material layer 84L.

[0187] Reference Fig.56 , executable reference Fig.24 The processing steps are performed to form a second dielectric filling material portion 84.

[0188] Reference Fig.57 , an etching process may be performed to remove the portion of the second dielectric liner 24 and the fourth dielectric liner 28 located below the gap 85'. The etching process may include an anisotropic etching process or an isotropic etching process. In one embodiment, reference Fig.25 The physically exposed sidewalls of the second dielectric liner 24 and the fourth dielectric liner 28 may or may not be laterally recessed outwardly, and / or may or may not include a concave annular surface, depending on whether an isotropic etching process or an anisotropic etching process is used to etch the uncovered portions of the second dielectric liner 24 and the fourth dielectric liner 28.

[0189] A fin-shaped dielectric pillar structure (81, 82, 84) may be formed in a bottom portion of each contact cavity 85. Each of the fin-shaped dielectric pillar structures (81, 82, 84) includes a first dielectric via liner 81 having a laterally undulating vertical cross-sectional profile and protruding laterally outward at each level of the insulating layer (132, 232) below the void 85' in the upper portion of the corresponding contact cavity 85. The thickness of each first dielectric via liner 81 is less than half of the minimum thickness of the sacrificial material layer (142, 242).

[0190] Reference Fig.58, an oxidation process may be optionally performed to convert physically exposed surface portions of the second dielectric liner 24 and the fourth dielectric liner 28 into a dielectric oxide liner 87. For example, if the second dielectric liner 24 and the fourth dielectric liner 28 comprise silicon nitride, the dielectric oxide liner 87 may comprise silicon oxide or silicon oxynitride having a lateral nitrogen concentration gradient, wherein the atomic concentration of nitrogen atoms increases with the lateral distance from the respective interface between the void 85' and the respective dielectric oxide liner 86. The thickness of the dielectric oxide liner 87 may be in the range of 1 nm to 5 nm, such as 2 nm to 3 nm, although lesser and greater thicknesses may also be employed.

[0191] Reference Fig.59 , executable reference Fig.13 The processing steps are described to form a sacrificial contact opening filling structure 36 in the gap 85'. The sacrificial contact opening filling structure 136 includes a sacrificial filling material, such as carbon (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or silicon-germanium alloy), an organic silicate glass and / or a polymer material. The top surface of the sacrificial contact opening filling structure 136 can be formed in a horizontal plane including the top surface of the contact level dielectric layer 280.

[0192] Reference Fig.60 , additional dielectric material may be deposited on the contact-level dielectric layer 280 . The additional dielectric material is incorporated into the contact-level dielectric layer 280 . The contact-level dielectric layer 280 increases in volume when the additional dielectric material is incorporated, covering the sacrificial contact opening filling structure 136 .

[0193] Reference Fig.61 , executable reference FIG. 17A to FIG. 17C and Fig.18 As described above, the second dielectric liner 24 and the fourth dielectric liner 28 are present in the region where the backside trenches 79 are formed. The second dielectric liner 24 may be divided into a plurality of second dielectric liner 24 extending laterally between a corresponding adjacent pair of backside trenches 79. The fourth dielectric liner 28 may be divided into a plurality of fourth dielectric liner 28 extending laterally between a corresponding adjacent pair of backside trenches 79.

[0194] Subsequently, an etchant that selectively etches the material of the first and second sacrificial material layers (142, 242) relative to the material of the first and second insulating layers (132, 232), the material of the first and second backward stepped dielectric material portions (165, 265), and the material of the outermost layer of the memory film 50 may be introduced into the backside trench 79, for example, using an isotropic etching process. According to one aspect of the present disclosure, the second dielectric liner 24 and the fourth dielectric liner 28 may be etched in parallel during the isotropic etching process. In one embodiment, the second dielectric liner 24 and the fourth dielectric liner 28 include the same material as the sacrificial material layer (142, 242) and are removed during the removal of the sacrificial material layer (142, 242). In one embodiment, the second dielectric liner 24, the fourth dielectric liner 28, and the sacrificial material layer (142, 242) include silicon nitride, and the isotropic etching process includes a wet etching process using hot phosphoric acid. A backside recess is formed in the volume from which the sacrificial material layer (142, 242) is removed. An inter-trench stepped cavity (113, 117) is formed in the volume from which the second dielectric liner 24 and the fourth dielectric liner 28 are removed. Specifically, a first inter-trench stepped cavity 113 is formed in each volume from which the second dielectric liner 24 is removed, and a second inter-trench stepped cavity 117 is formed in each volume from which the fourth dielectric liner 28 is removed.

[0195] A backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses, the inter-trench stepped cavities (113, 117) and in the backside trenches 79. At least one conductive material may be deposited in the plurality of backside recesses, on physically exposed surfaces around the inter-trench stepped cavities (113, 117), on the sidewalls of the backside trenches 79, and over the contact-level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element, such as a metal nitride barrier and a tungsten filler. According to one aspect of the present disclosure, the thickness of the inter-trench stepped cavities (113, 117) is at least twice the thickness of each backside recess. Thus, the at least one conductive material only partially fills the inter-trench stepped cavities (113, 117) and completely fills the backside recesses. Thus, a continuous void connected to a pair of voids within a pair of backside trenches 79 exists within the volume of each of the inter-trench stepped cavities (113, 117). In contrast, each backside recess is completely filled with a corresponding conductive layer (146, 246) with no voids therein.

[0196] Portions of the deposited at least one conductive material may be isotropically etched back from within the volume of the partially filled inter-trench stepped cavity (113, 117), from the sidewalls of each backside trench 79, and from above the contact level dielectric layer 280. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. Each conductive layer (146, 246) may be a conductive line structure. Each of the inter-trench stepped cavities (113, 117) includes a void without any solid phase material. The void of each inter-trench stepped cavity (113, 117) extends from the top surface of the first liner 22 or the third dielectric liner 24 to the stepped bottom surface of the overlying backward stepped dielectric material portion (165, 265). Typically, the void of each inter-trench stepped cavity (113, 117) can be formed by isotropically recessing at least one conductive material of the conductive layer (146, 246).

[0197] Reference Fig.62A and Fig.62B , a dielectric material layer (also referred to as a replacement dielectric material layer) may be conformally deposited in the volume of the inter-trench stepped cavities (113, 117), at the peripheral portions of the backside trenches 79, and above the top surface of the contact-level dielectric layer 280 by performing a conformal deposition process (such as low pressure chemical vapor deposition). The thickness of the dielectric material layer is greater than half the height of each inter-trench stepped cavity (113, 117). An etch-back process (such as an anisotropic etching process) may be performed to remove horizontal portions of the replacement dielectric material layer located within the backside trenches 79 or above the contact-level dielectric layer 280. Each remaining portion of the replacement dielectric material layer that fills the inter-trench stepped cavities (113, 117) constitutes a replacement dielectric liner (124, 128). The replacement dielectric liners (124, 128) include a first replacement dielectric liner 124 replacing the second dielectric liner 24 and a second replacement dielectric liner 128 replacing the fourth dielectric liner 28. The first replacement dielectric liner 124 may be referred to as a second dielectric liner, and the second replacement dielectric liner 128 may be referred to as a fourth dielectric liner or an additional second dielectric liner. The replacement dielectric liners (124, 128) include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, a dielectric metal oxide, or a combination thereof.

[0198] Typically, after forming the conductive layer (146, 246), a replacement dielectric liner (124, 128) may be formed within the void within the volume of the inter-trench stepped cavity (113, 117). The replacement dielectric liner (124, 128) may be formed after forming the sacrificial contact via structure 136. The replacement dielectric liner (124, 128) may laterally surround the sacrificial contact via structure 136. In one embodiment, the second dielectric liner (124, 128) may have a respective thickness greater than the maximum thickness of the conductive layer (146, 246). In one embodiment, the conductive layers (146, 246) may have the same thickness.

[0199] The replacement dielectric liner (124, 128) (which may also be referred to as a dielectric liner or a second dielectric liner) is formed by conformally or nearly conformally depositing a dielectric fill material in the volume void of the inter-groove stepped cavity (113, 117), and thus may include a corresponding seam (124S or 128S) located intermediate between a first interface and a second interface, the first interface being between the second dielectric liner (124 or 128) and the first dielectric liner (22 or 26), and the second interface being between the second dielectric liner (124 or 128) and the backward stepped dielectric material portion (165, 265). In one embodiment, each seam (124S or 128S) includes a horizontally extending seam portion that is interconnected and abuts the vertically extending seam portion. In one embodiment, each seam ( 124S or 128S) is laterally spaced apart from a cylindrical opening in a corresponding replacement dielectric liner ( 124 or 128 ) through which the sacrificial contact via structure 136 extends.

[0200] Reference Fig.63 , executable reference Fig.19 The processing steps described modify the dimensions of the opening through the upper portion of the contact level dielectric layer 280 to remove the sacrificial contact opening fill structure 136. A void 85' is formed in the volume from which the sacrificial contact opening fill structure 136 was removed and through the overlying portion of the contact level dielectric layer 280.

[0201] Reference Fig.64 , a second dielectric via liner layer 89L may be optionally deposited by a conformal deposition process at the perimeter of the void 85' and over the contact level dielectric layer 280. The second dielectric via liner layer 89L comprises a dielectric material such as silicon oxide, silicon nitride, silicon carbide nitride, or a dielectric metal oxide. The second dielectric via liner layer 89L may have a thickness in the range of 1 nm to 30 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses may also be used.

[0202] Reference Fig.65, an anisotropic etching process may be performed to remove horizontally extending portions of the second dielectric via liner layer 89L. Each remaining vertically extending portion of the second dielectric via liner layer 89L comprises a second dielectric via liner 89. In one embodiment, each of the fin-like dielectric pillar structures (81, 82, 84) comprises a first dielectric via liner 81 having a laterally undulating vertical cross-sectional profile and protruding laterally outward at each level of the insulating layer (132, 232) located below the corresponding layer contact via structure 86. In one embodiment, the thickness of each first dielectric via liner 81 is less than half of the minimum thickness of the conductive layer (146, 246). In one embodiment, one, more than one and / or each of the conductive layers (146, 246) comprises a corresponding opening having a corresponding cylindrical sidewall that contacts a corresponding one of the first dielectric via liners 81. In one embodiment, each first dielectric via liner 81 includes a respective annular top surface exposed to the overlying void 85'. In one embodiment, the second dielectric via liner 89 differs from the first dielectric via liner 81 in at least one of material composition and thickness.

[0203] Reference Fig.66 , executable reference Fig. 27 The processing steps are performed to form a layer contact via structure 86 in the gap 85'.

[0204] Each layer contact via structure 86 in the third exemplary structure is overlaid on a fin-like dielectric pillar structure (81, 82, 84), which includes a first dielectric via liner 81, a first dielectric filling material portion 82, and an optional second dielectric filling material portion 84. In addition, each layer contact via structure 86 is laterally surrounded by a second dielectric via liner 89. The second dielectric via liner 89 and the first dielectric via liner 81 may differ from each other in at least one of material composition and thickness. In one embodiment, the fin-like dielectric pillar structure (81, 82, 84) may protrude above a horizontal plane including an annular interface between the layer contact via structure 86 and the underlying conductive layer (146, 246).

[0205] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246) having a stepped surface (301, 302) in a contact region 300; a memory opening 49 extending vertically through the alternating stack {(132, 146), (232, 246)}; a memory opening filling structure 58 located in the memory opening 49, wherein each of the memory opening filling structures 58 comprises a corresponding vertical memory element stack and a corresponding vertical semiconductor channel 60; at least one backward stepped dielectric material portion (165, 265) covering the alternating stack {(132, 146), (232, 246)}; a fin dielectric An electrical pillar structure (optionally 81, 82, 84) extending vertically through the alternating stack {(132, 146), (232, 246)} in the contact area 300; a support pillar structure 20 extending vertically through at least one backward stepped dielectric material portion (165, 265) and the alternating stack {(132, 146), (232, 246)} and located in the contact area 300, wherein the top surface of the support pillar structure is located in a horizontal plane including the top surface of the memory opening filling structure 58; and a layer contact via structure 86 extending vertically through at least one backward stepped dielectric material portion (165, 265), wherein each layer contact via structure 86 contacts a corresponding one of the conductive layers (146, 246) and a corresponding one of the fin dielectric pillar structures (optionally 81, 82, 84).

[0206] In one embodiment, each of the fin-like dielectric pillar structures (optionally 81, 82, 84) includes at least one dielectric fin 82F that protrudes laterally outward at the level of a corresponding one of the insulating layers (132, 232). In one embodiment, one or more of the at least one dielectric fin 82F includes a cylindrical sidewall that contacts a corresponding one of the insulating layers (132, 232). In one embodiment, each of the fin-like dielectric pillar structures (optionally 81, 82, 84) includes a dielectric base structure 83 that extends vertically from the substrate 9 to the bottom surface of a corresponding one of the layer contact via structures 86. In one embodiment, for each of the fin-like dielectric pillar structures (optionally 81, 82, 84), at least one dielectric fin 82F and the tubular portion of the dielectric base structure 83 contain a first dielectric filling material; and the cylindrical core portion 84 of the dielectric base structure 83 contains a second dielectric filling material.

[0207] In various embodiments, a top surface of a corresponding one of the fin-like dielectric post structures (optionally 81, 82, 84) is located at or above a top surface of a corresponding one of the conductive layers (146, 246), which is in contact with a layer contact via structure 86 that contacts a corresponding one of the fin-like dielectric post structures (optionally 81, 82, 84). In a first embodiment, a top surface of a corresponding one of the fin-like dielectric post structures (optionally 81, 82, 84) is located above a top surface of a corresponding one of the conductive layers (146, 246). In a second embodiment, a top surface of a corresponding one of the fin-like dielectric post structures (optionally 81, 82, 84) is located at (i.e., in the same horizontal plane as) a top surface of a corresponding one of the conductive layers (146, 246).

[0208] In one embodiment, each memory opening filling structure in the memory opening filling structure 58 includes a corresponding memory film 50, which includes a corresponding vertical memory element stack; each support pillar structure in the support pillar structure 20 includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50; the memory film 50 of the support pillar structure 20 and the memory film 50 of the memory opening filling structure 58 include the same material layer stack; and the vertical semiconductor channel 60 of the support pillar structure 20 and the vertical semiconductor channel 60 of the memory opening filling structure 58 have the same material composition and the same thickness.

[0209] In one embodiment, each layer contact via structure 86 includes a respective annular bottom surface that contacts an annular top surface segment of a respective one of the conductive layers (146, 246). In one embodiment, each layer contact via structure 86 includes a respective raised bottom surface that contacts a top surface segment of a respective one of the fin-like dielectric pillar structures (optionally 81, 82, 84) and is located above a horizontal plane including the respective annular bottom surface.

[0210] In one embodiment, each layer contact via structure 86 includes an inner cylindrical sidewall that contacts an upper portion of a cylindrical sidewall of a corresponding one of the fin-like dielectric pillar structures (optionally 81, 82, 84). In one embodiment, one, more than one, or each of the layer contact via structures 86 includes: an upper cylindrical portion 80U that contacts at least one rear stepped dielectric material portion (165, 265); and a lower base portion 86L that has a lateral extent greater than the bottom perimeter of the cylindrical sidewall of the upper cylindrical portion 80U and includes an annular top surface that has an inner perimeter that coincides with the bottom perimeter of the cylindrical sidewall of the upper cylindrical portion 80U.

[0211] In one embodiment, a three-dimensional memory device includes at least one dielectric liner (23, 24, 27, 28) interposed between at least one backward stepped dielectric material portion (165, 265) and the stepped surfaces (301, 302) of the alternating stacks {(132, 146), (232, 246)}, wherein a horizontal surface of the at least one dielectric liner (23, 24, 27, 28) is located in the same horizontal plane as an annular top surface of one of the layer contact via structures 86.

[0212] In one embodiment, one, more than one or each of the layer contact via structures 86 includes a straight cylindrical sidewall that extends vertically from a top surface of one of the layer contact via structures 86 to a horizontal surface of one of the conductive layers (146, 246).

[0213] According to another aspect of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and conductive layers (146, 246), which has a stepped surface in a contact area 300; a memory opening 49, which vertically extends through the alternating stack {(132, 146), (232, 246)}; a memory opening filling structure 58 located in the memory opening 49, wherein each of the memory opening filling structures 58 includes a corresponding vertical memory element stack (such as a portion of a corresponding charge storage layer 54) and a corresponding vertical semiconductor channel 60; a dielectric liner (124 or 128), which covers the stepped surface The invention relates to a contact region 300 and a plurality of dielectric pillar structures, wherein the dielectric pillar structures include a rear stepped dielectric material portion (165, 265) and a fin-shaped dielectric pillar structure (optionally 81, 82, 84) extending vertically through the alternating stacks {(132, 146), (232, 246)} in the contact region 300; and a layer contact via structure 86 extending vertically through the rear stepped dielectric material portion (165, 265) and contacting a corresponding one of the conductive layers (146, 246) and a corresponding one of the fin-shaped dielectric pillar structures (optionally 81, 82, 84).

[0214] In one embodiment, the thickness of the dielectric liner (124 or 128) is greater than the thickness of the conductive layer (146, 246). In one embodiment, an additional dielectric liner such as the first dielectric liner (22 or 26) is located below the dielectric liner (124 or 128), which is also referred to as the second dielectric liner (124 or 128). In one embodiment, the second dielectric liner (124 or 128) includes a seam (124S or 128S) located midway between the stepped bottom surface of the dielectric liner (124 or 128) and the stepped top surface of the contact rearward stepped dielectric material portion (165 or 265).

[0215] In one embodiment, the second dielectric liner (124 or 128) includes a seam (124S or 128S) located midway between a first interface and a second interface, the first interface being between the second dielectric liner (124 or 128) and the first dielectric liner (22 or 26), and the second interface being between the second dielectric liner (124 or 128) and the rearward stepped dielectric material portion (165, 265). In one embodiment, the seam (124S or 128S) includes a horizontally extending seam portion that is interconnected and abuts the vertically extending seam portion. In one embodiment, the seam (124S or 128S) is laterally spaced apart from a cylindrical opening in the dielectric liner (124 or 128) through which the layer contact via structure 86 extends.

[0216] In one embodiment, the device also includes an underlying dielectric liner (22 or 26) that contacts multiple horizontal surface segments and multiple vertical surface segments of the stepped surface and extends over multiple levels of the conductive layer (146, 246) and below the dielectric liner (124 or 128).

[0217] In one embodiment, each of the fin-like dielectric pillar structures (optionally 81, 82, 84) includes a first dielectric via liner 81 having a laterally undulating vertical cross-sectional profile and protruding laterally outward at each level of the insulating layer (132, 232), which is located below the corresponding layer contact via structure 86 in the layer contact via structure 86; and the thickness of each first dielectric via liner 81 is less than half the thickness of the conductive layer (146, 246).

[0218] In one embodiment, a corresponding one of the conductive layers (146, 246) includes a corresponding opening having a corresponding cylindrical side wall contacting a corresponding one of the first dielectric via pads 81; and each first dielectric via pad 81 includes a corresponding annular top surface contacting a corresponding one of the layer contact via structures 86.

[0219] In one embodiment, the layer contact via structure 86 is laterally surrounded by a corresponding second dielectric via liner 89 having a corresponding annular bottom surface in contact with a corresponding one of the conductive layers (146, 246); the second dielectric via liner 89 differs from the first dielectric via liner 81 in at least one of material composition and thickness.

[0220] In one embodiment, each of the fin-shaped dielectric pillar structures (optionally 81, 82, 84) includes at least one dielectric fin 82F that protrudes laterally outward at the level of a corresponding one of the insulating layers (132, 232). In one embodiment, one or more of the at least one dielectric fin 82F includes a cylindrical sidewall that contacts a corresponding one of the insulating layers (132, 232).

[0221] In one embodiment, each of the fin-like dielectric pillar structures (optionally 81, 82, 84) includes a dielectric base structure 83 that extends vertically from the substrate below the alternating stack {(132, 146), (232, 246)} to the bottom surface of a corresponding one of the layer contact via structures 86. In one embodiment, for each of the fin-like dielectric pillar structures (optionally 81, 82, 84), at least one dielectric fin 82F and the tubular portion of the dielectric base structure 83 include a first dielectric filling material; and the cylindrical core portion of the dielectric base structure 83 includes a second dielectric filling material.

[0222] In one embodiment, each layer-contact via structure 86 includes a respective annular bottom surface that contacts an annular top surface segment of a respective one of the conductive layers ( 146 , 246 ).

[0223] Although two levels of alternating stacking {(132, 146), (232, 246)} are described in the above embodiment, in alternative embodiments, one level or three or more levels may be included in the memory device.

[0224] Various embodiments of the present disclosure may be employed to provide a three-dimensional memory device including a self-aligned layer contact via structure 86 contacting a corresponding conductive layer (146, 246), wherein the depth of the layer contact via structure 86 relative to the top surface of a corresponding one of the conductive layers (146, 246) is precisely controlled to ensure reliable electrical contact therebetween. Thus, electrical opens between the layer contact via structure 86 and the conductive layer (146, 246) may be minimized. Furthermore, undesired electrical shorts between the layer contact via structure 86 and the additional conductive layer (146, 246) may be avoided by the self-aligned layer contact via structure 86 of the present disclosure embodiment.

[0225] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments employing specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack having a stepped surface in the contact region; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening, wherein each of the memory opening filling structures includes a respective vertical memory element stack and a respective vertical semiconductor channel; at least one backward stepped dielectric material portion, the at least one backward stepped dielectric material portion overlying the alternating stack; a fin-shaped dielectric post structure extending vertically through the alternating stacks in the contact region; a support post structure extending vertically through the at least one rear stepped dielectric material portion and the alternating stack and located in the contact region, wherein a top surface of the support post structure is located in a horizontal plane including a top surface of the memory opening filling structure; and A layer contact via structure extends vertically through the at least one backward stepped dielectric material portion, wherein each of the layer contact via structures contacts a corresponding one of the conductive layers and a corresponding one of the fin dielectric pillar structures. 2 . The three-dimensional memory device of claim 1 , wherein each of the fin-shaped dielectric pillar structures comprises at least one dielectric fin that protrudes laterally outward at the level of a corresponding one of the insulating layers. 3 . The three-dimensional memory device of claim 2 , wherein one or more of the at least one dielectric fin comprises a cylindrical sidewall in contact with a corresponding one of the insulating layers.

4. The three-dimensional memory device of claim 2, wherein each of the fin-like dielectric pillar structures comprises a dielectric base structure that vertically extends from a substrate to a bottom surface of a corresponding one of the layer contact via structures.

5. The three-dimensional memory device according to claim 4, wherein for each of the fin-shaped dielectric pillar structures: The at least one dielectric fin and the tubular portion of the dielectric base structure include a first dielectric fill material; and The cylindrical core portion of the dielectric base structure includes a second dielectric fill material.

6. The three-dimensional memory device of claim 1 , wherein a top surface of the corresponding one of the fin-like dielectric pillar structures is located at or above a top surface of the corresponding one of the conductive layers.

7. The three-dimensional memory device according to claim 1, wherein: Each of the memory opening filling structures comprises a respective memory film including the respective vertical memory element stack; Each of the support pillar structures includes a corresponding vertical semiconductor channel and a corresponding memory film; The memory film of the support pillar structure and the memory film of the memory opening filling structure include a same material layer stack; and The vertical semiconductor channel of the support pillar structure and the vertical semiconductor channel of the memory opening filling structure have the same material composition and the same thickness. 8 . The three-dimensional memory device of claim 1 , wherein each of the layer contact via structures comprises a respective annular bottom surface in contact with an annular top surface segment of the respective one of the conductive layers.

9. The three-dimensional memory device of claim 8, wherein each of the layer contact via structures further comprises a corresponding raised bottom surface, the raised bottom surface contacting a top surface segment of the corresponding one of the fin-like dielectric pillar structures and being located above a horizontal plane including the corresponding annular bottom surface.

10. The three-dimensional memory device of claim 9, wherein each of the layer contact via structures comprises an inner cylindrical sidewall that contacts an upper portion of a cylindrical sidewall of the corresponding one of the fin-like dielectric pillar structures.

11. The three-dimensional memory device according to claim 1 , wherein one of the layer contact via structures comprises: an upper cylindrical portion, the upper cylindrical portion contacting the at least one rearward stepped dielectric material portion; and A lower base portion having a greater lateral extent than the bottom periphery of the cylindrical sidewall of the upper cylindrical portion and including an annular top surface having an inner periphery coinciding with the bottom periphery of the cylindrical sidewall of the upper cylindrical portion.

12. The three-dimensional memory device according to claim 11, further comprising at least one dielectric liner interposed between the at least one backward stepped dielectric material portion and the stepped surfaces of the alternating stacks, wherein a horizontal surface of the at least one dielectric liner is located in the same horizontal plane as the annular top surface of the one of the layer contact via structures.

13. The three-dimensional memory device of claim 1 , wherein one of the layer contact via structures comprises a straight cylindrical sidewall extending vertically from a top surface of the one of the layer contact via structures to a horizontal surface of one of the conductive layers.

14. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers over the substrate; forming a memory opening and a contact opening through the alternating stack; forming a sacrificial contact opening filling structure in the contact opening; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures includes a respective vertical semiconductor channel and a respective vertical memory element stack; replacing the sacrificial material layer with a conductive layer; forming a contact cavity by removing the sacrificial contact opening filling structure after replacing the sacrificial material layer; Laterally expanding the contact cavities by performing an isotropic etching process that selectively laterally recesses a proximal portion of the insulating layer surrounding each of the contact cavities relative to the conductive layer; forming a fin-shaped dielectric pillar structure in a lower portion of the laterally expanded contact cavity; as well as A layer contact via structure is formed in an upper portion of the laterally expanded contact cavity.

15. The method according to claim 14, further comprising: forming a stepped surface on said alternating stack of said insulating layers and said sacrificial material layers; as well as A backward stepped dielectric material portion is formed on the stepped surface, wherein the contact opening is formed through the backward stepped dielectric material portion and the stepped surface.

16. The method of claim 15, wherein: The isotropic etching process laterally recesses the portion of the back stepped dielectric material surrounding the contact cavity to provide the upper portion of the laterally expanded contact cavity; and Each of the laterally expanded contact cavities includes a corresponding cylindrical cavity laterally surrounded by a remaining portion of the rearward stepped dielectric material portion and at least one corresponding fin-shaped cavity located below the corresponding cylindrical cavity.

17. The method according to claim 16, further comprising: conformally depositing at least one dielectric fill material in the fin-shaped cavity and in a peripheral region of the cylindrical cavity; as well as The at least one dielectric filling material is removed from the interior of the cylindrical cavity, wherein the fin-shaped dielectric pillar structure includes a remaining portion of the at least one dielectric filling material filling the fin-shaped cavity.

18. The method according to claim 15, further comprising: forming at least one dielectric liner on the stepped surface, wherein the backward stepped dielectric material portion is formed over the at least one dielectric liner; as well as A proximal portion of the at least one dielectric liner is recessed prior to forming the layer contact via structure.

19. The method of claim 18, wherein the at least one dielectric liner comprises: a first dielectric liner comprising silicon oxide, wherein the first dielectric liner is laterally recessed by the isotropic etching process; and A second dielectric liner, the second dielectric liner comprises silicon nitride, silicon carbonitride, a semiconductor material or doped silicate glass, wherein the method further comprises performing an additional isotropic etching process after forming the fin-shaped dielectric pillar structure and before forming the layer contact through-hole structure, the additional isotropic etching process causing the second dielectric liner to be isotropically recessed.

20. The method of claim 15, wherein: The memory opening and the contact opening are formed by performing an anisotropic etching process using a patterned etching mask layer; The method further includes forming a sacrificial memory opening fill structure in the memory opening, and removing the sacrificial memory opening fill structure without removing the sacrificial contact opening fill structure; and The memory opening filling structure is formed in a volume where the sacrificial memory opening filling structure is removed and the sacrificial contact opening filling structure is present in the contact opening.

21. A three-dimensional memory device, comprising: an alternating stack of insulating layers and conductive layers, the alternating stack having a stepped surface in the contact region; a reservoir opening extending vertically through the alternating stacks; a memory opening filling structure located in the memory opening, wherein each of the memory opening filling structures includes a respective vertical memory element stack and a respective vertical semiconductor channel; a dielectric liner overlying the plurality of horizontal surface segments and the plurality of vertical surface segments of the stepped surface and extending over the plurality of levels of the conductive layer; a rearwardly stepped dielectric material portion contacting a top surface segment of the dielectric liner; a fin-shaped dielectric post structure extending vertically through the alternating stacks in the contact region; and A layer contact via structure vertically extends through the rear stepped dielectric material portion and contacts a corresponding one of the conductive layers and a corresponding one of the fin-like dielectric pillar structures.

22. The three-dimensional memory device of claim 21, wherein a thickness of the dielectric liner is greater than a thickness of the conductive layer.

23. The three-dimensional memory device of claim 22, wherein the dielectric liner comprises a seam located midway between a stepped bottom surface of the dielectric liner and a stepped top surface contacting the backward stepped dielectric material portion.

24. The three-dimensional memory device according to claim 23, wherein: The seam includes a horizontally extending seam portion interconnected and abutting a vertically extending seam portion; and The seam is laterally spaced apart from a cylindrical opening in the dielectric liner through which the layer contact via structure extends.

25. The three-dimensional memory device of claim 21, further comprising an underlying dielectric liner contacting the plurality of horizontal surface segments and the plurality of vertical surface segments of the stepped surface and extending over the plurality of levels of the conductive layer and below the dielectric liner.

26. The three-dimensional memory device of claim 21, wherein: Each of the fin-like dielectric pillar structures includes a first dielectric via liner having a laterally undulating vertical cross-sectional profile and protruding laterally outward at each level of the insulating layer underlying a corresponding one of the layer contact via structures; and A thickness of each of the first dielectric via liners is less than half a thickness of the conductive layer.

27. The three-dimensional memory device of claim 26, wherein: a respective one of the conductive layers comprises a respective opening having a respective cylindrical sidewall contacting a respective one of the first dielectric via liners; and Each of the first dielectric via liners includes a respective annular top surface contacting a respective one of the layer contact via structures.

28. The three-dimensional memory device of claim 26, wherein: the layer contact via structure being laterally surrounded by a respective second dielectric via liner having a respective annular bottom surface in contact with a respective one of the conductive layers; and The second dielectric via liner differs from the first dielectric via liner in at least one of material composition and thickness. 29 . The three-dimensional memory device of claim 21 , wherein each of the fin-like dielectric pillar structures comprises at least one dielectric fin that protrudes laterally outward at the level of a corresponding one of the insulating layers.

30. The three-dimensional memory device of claim 29, wherein the at least one dielectric fin comprises a cylindrical sidewall in contact with a corresponding one of the insulating layers.

31. The three-dimensional memory device of claim 29, wherein each of the fin-like dielectric pillar structures further comprises a dielectric base structure extending vertically from a substrate beneath the alternating stack to a bottom surface of a corresponding one of the layer contact via structures.

32. The three-dimensional memory device of claim 31 , wherein for each of the fin-shaped dielectric pillar structures: The at least one dielectric fin and the tubular portion of the dielectric base structure include a first dielectric fill material; and The cylindrical core portion of the dielectric base structure includes a second dielectric fill material.

33. The three-dimensional memory device of claim 21, wherein each of the layer contact via structures comprises a respective annular bottom surface in contact with an annular top surface segment of the respective one of the conductive layers.

34. A method of forming a three-dimensional memory device, the method comprising: forming an alternating stack of insulating layers and sacrificial material layers over the substrate; forming a stepped surface by patterning the alternating stacks; forming a rearwardly stepped dielectric material portion over the stepped surface; forming a memory opening through the alternating stack; forming memory opening filling structures in the memory openings, wherein each of the memory opening filling structures includes a respective vertical semiconductor channel and a respective vertical memory element stack; forming a contact cavity through the rearward stepped dielectric material portion, the stepped surface, and the alternating stack; laterally expanding the contact cavities by performing an isotropic etching process that selectively laterally recesses a proximal portion of the insulating layer and the rear stepped dielectric material portion surrounding each of the contact cavities relative to the sacrificial material layer; forming a fin-shaped dielectric pillar structure in a lower portion of the laterally expanded contact cavity; forming a sacrificial contact via structure in an upper portion of the contact cavity on a corresponding one of the fin-like dielectric pillar structures; replacing the sacrificial material layer with a conductive layer; as well as The sacrificial contact via structure is replaced with a layer contact via structure contacting a corresponding one of the conductive layers.

35. The method of claim 34, further comprising: forming a dielectric liner on the stepped surface, wherein the backward stepped dielectric material portion is formed over the dielectric liner; forming a backside trench through the alternating stack, wherein sidewalls of the sacrificial material layer and sidewalls of a remaining portion of the dielectric liner are exposed in the backside trench; forming an inter-trench stepped cavity by removing the remaining portion of the dielectric liner; as well as A dielectric fill material is deposited in the stepped cavities between the trenches to form a replacement dielectric liner.

36. The method of claim 35, wherein: The thickness of the dielectric liner is greater than the thickness of the sacrificial material layer; and The method further comprises: forming a backside recess by selectively removing the sacrificial material layer relative to the insulating layer; depositing at least one conductive material in the backside recesses and in the inter-trench stepped cavities and in peripheral portions of the backside trenches; and The at least one conductive material is isotropically recessed, wherein voids are formed within the volume of the inter-trench stepped cavity, and the conductive layer is formed in the backside recess.

37. The method of claim 36, wherein the replacement dielectric liner is formed within the void within the volume of the inter-trench stepped cavity after forming the conductive layer.

38. The method of claim 35, wherein the replacement dielectric liner is formed after the sacrificial contact via structure is formed and laterally surrounds the sacrificial contact via structure.

39. The method of claim 35, wherein the dielectric liner comprises the same material as the sacrificial material layer and is removed during an isotropic etching step that removes the sacrificial material layer.

40. The method of claim 34, wherein: The isotropic etching process laterally recesses the portion of the back stepped dielectric material surrounding the contact cavity to provide the upper portion of the laterally expanded contact cavity; and Each of the laterally expanded contact cavities includes a corresponding cylindrical cavity laterally surrounded by a remaining portion of the rearward stepped dielectric material portion and at least one corresponding fin-shaped cavity located below the corresponding cylindrical cavity.

Images