Semiconductor test structure and failure analysis method thereof

Abstract

The invention relates to a semiconductor test structure and a failure analysis method thereof. The semiconductor test structure comprises a first test pattern, a second test pattern and a third test pattern. The first test pattern extends in a snakelike shape and is provided with a plurality of concave areas. The second test pattern and the third test pattern are located on the two sides of the first test pattern and each provided with at least one comb tooth part extending into the concave area. And the comb tooth parts of the second test pattern and the third test pattern are connected with the substrate or grounded. According to the invention, the FIB sample preparation efficiency can be improved, and the failure analysis time of the semiconductor test structure is effectively shortened, so that the FIB analysis efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor test structure and a failure analysis method thereof. Background Art

[0002] Focused ion beam (FIB) system refers to a microdissection instrument that can use an electric lens to focus an ion beam into a very small size. The basic principle of FIB sample preparation is to use an electric lens to accelerate and focus the ion beam generated by the ion source through an ion gun and then act on the sample surface to achieve milling, deposition, injection and imaging of sample materials. In addition, during the FIB sample preparation process, an electron beam can be used to monitor the sample processing progress in real time, thereby better controlling the processing accuracy and realizing the analysis and manufacturing of nano-scale semiconductor devices.

[0003] However, in the FIB sample preparation process, a larger sample cross section needs to be prepared in order to more accurately determine the location of the defect, which easily increases the usage time of the FIB system and reduces analysis efficiency. Summary of the invention

[0004] Based on this, the embodiments of the present application provide a semiconductor test structure and a failure analysis method thereof, which can improve the FIB sample preparation efficiency and effectively shorten the failure analysis time of the semiconductor test structure to improve the FIB analysis efficiency.

[0005] In order to achieve the above-mentioned purpose, in the first aspect, some embodiments of the present application provide a semiconductor test structure. The semiconductor test structure includes: a first test pattern, a second test pattern and a third test pattern. The first test pattern extends in a serpentine shape and has a plurality of concave areas. The second test pattern and the third test pattern are located on both sides of the first test pattern, and each has at least one comb-tooth portion extending into the concave area; wherein the comb-tooth portions of the second test pattern and the third test pattern are connected to the substrate or grounded.

[0006] In some embodiments of the present application, the semiconductor test structure further includes: a conductive contact structure respectively disposed at the free end of each comb-tooth portion; wherein the comb-tooth portion is connected to the substrate or the ground through the conductive contact structure.

[0007] In some embodiments of the present application, the comb teeth correspond to the concave areas one by one.

[0008] In some embodiments of the present application, the comb-tooth portions of the second test pattern and the comb-tooth portions of the third test pattern match the arrangement of the concave areas and are distributed alternately.

[0009] In some embodiments of the present application, the comb teeth are distributed at equal intervals.

[0010] In some embodiments of the present application, the first test pattern, the second test pattern, and the third test pattern are conductive patterns located in different areas of the same conductive material layer; or, at least one of the first test pattern, the second test pattern, and the third test pattern is a conductive pattern formed by interconnecting multiple conductive material layers.

[0011] In some embodiments of the present application, the semiconductor test structure further includes: a first test pad, a second test pad, and a third test pad. The first test pad and the second test pad are respectively arranged at two ends of the first test pattern and are correspondingly connected to two ends of the first test pattern. The third test pad connects the second test pattern and the third test pattern.

[0012] In some embodiments of the present application, the semiconductor test structure further includes: a first lead, a second lead, a third lead, and a fourth lead. The first lead connects the first test pad and the first end of the first test pattern. The second lead connects the second test pad and the second end of the first test pattern. The third lead connects the third test pad and the second test pattern. The fourth lead connects the third test pad and the third test pattern.

[0013] Optionally, the first test pad, the first lead, the first test pattern, the second lead and the second test pad are an integrated structure. The second test pattern, the third lead, the third test pad, the fourth lead and the third test pattern are an integrated structure.

[0014] In a second aspect, the present disclosure also provides a failure analysis method for a semiconductor test structure according to some embodiments, which is applied to the semiconductor test structure in some of the above embodiments. The failure analysis method includes the following steps.

[0015] Laser beam resistance anomaly detection on semiconductor test structures to pinpoint failure locations.

[0016] A cross-section of the semiconductor test structure at the failure position is obtained, and a measured image of the cross-section is determined.

[0017] The measured image is compared with a reference image to determine a failure pattern in a semiconductor test structure according to a difference between the measured image and the reference image; wherein the failure pattern includes a first test pattern, a second test pattern, a third test pattern, or a partial pattern of at least one of the three test patterns.

[0018] In some embodiments of the present application, the failure analysis method of a semiconductor test structure further includes: obtaining a cross-section of the failure pattern in the semiconductor test structure, and performing failure analysis on the cross-section.

[0019] The embodiments of the present application may or at least have the following advantages:

[0020] In the embodiment of the present application, by setting a first test pattern and a second test pattern and a third test pattern located on both sides of the first test pattern and having a comb-tooth portion, FIB sample preparation is facilitated, and the semiconductor test structure is used to measure open circuit defects and / or short circuit defects of the circuit. In addition, in the embodiment of the present application, the comb-tooth portions of the second test pattern and the third test pattern are connected to the substrate or grounded, and effective identification can be performed for circuit defects that appear between any two test patterns, which can not only reduce the cross-sectional size during FIB sample preparation, but also help shorten the FIB analysis time to improve the FIB analysis efficiency.

[0021] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a schematic top view of a semiconductor test structure provided in some embodiments;

[0024] Figure 2 A schematic flow chart of a failure analysis method for a semiconductor test structure provided in some embodiments;

[0025] Figure 3 A schematic flow chart of another failure analysis method for a semiconductor test structure provided in some embodiments;

[0026] Figure 4 A schematic diagram of a measurement image of a semiconductor test structure along the AA cross section when there is no circuit defect provided in some embodiments;

[0027] Figure 5 A schematic diagram of a measurement image of a semiconductor test structure along the AA cross section when there is a circuit defect provided in some embodiments;

[0028] Figure 6 A schematic diagram of a measurement image of a semiconductor test structure along the AA cross section when there is no circuit defect and the second test pattern is grounded and the third test pattern is not grounded, provided in some embodiments;

[0029] Figure 7It is a schematic diagram of a measurement image of a semiconductor test structure along the AA cross section provided in some embodiments when there is a circuit defect and the second test pattern is grounded but the third test pattern is not grounded.

[0030] Description of reference numerals:

[0031] 1-first test pattern, F-concave area, 2-second test pattern, 3-third test pattern, 21 and 31-comb teeth, 4-conductive contact structure, Pad1-first test pad, Pad2-second test pad, Pad3-third test pad, 51-first lead, 52-second lead, 53-third lead, 54-fourth lead. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0035] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0036] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.

[0037] Optical Beam Induced Resistance Change (OBIRCH) is commonly used for abnormal resistance (high impedance / low impedance) and circuit leakage path analysis inside chips, and can quickly locate defects in circuits, such as voids in metal wires, voids under vias, high resistance areas at the bottom of vias, and circuit short circuits or leakage points. The working principle of laser beam resistance anomaly detection is as follows: a laser beam is scanned on the surface of a chip (IC), and part of the energy of the laser beam is absorbed by the IC and converted into heat, causing a temperature change in the scanned area; in this way, if there are defects or voids in the metal interconnect structure of the IC, the heat conduction near these areas will be different from that of other intact areas, causing different temperature changes in these areas, thereby causing changes in the corresponding metal resistance values; based on this, if a constant voltage is applied to the metal interconnect structure of the IC while the laser beam is scanning, current changes can be detected.

[0038] However, when the hot spot signal generated by the laser beam resistance anomaly detection is superimposed with the IR (infrared) image of the test structure, it is easy to produce positional deviations, causing the defect position to shift. Therefore, in the FIB sample preparation process, a larger sample cross section needs to be prepared to more accurately determine the location of the defect, but this is likely to increase the use time of the FIB system and reduce analysis efficiency.

[0039] Based on this, the embodiments of the present application provide a semiconductor test structure and a failure analysis method thereof, which can improve the efficiency of FIB sample preparation and effectively solve the problem that the failure analysis of the semiconductor test structure is difficult to be accurate to each test pattern (for example, each metal line).

[0040] See also Figure 1 , some embodiments of the present application provide a semiconductor test structure including: a first test pattern 1, a second test pattern 2 and a third test pattern 3. The first test pattern 1 extends in a serpentine shape and has a plurality of concave areas F. The second test pattern 2 and the third test pattern 3 are located on both sides of the first test pattern 1, and each has at least one comb-tooth portion (21 and 31) extending into the concave area F; wherein the comb-tooth portions (21 and 31) of the second test pattern 2 and the third test pattern 3 are connected to a substrate or grounded.

[0041] Here, please combine Figure 1 It is understood that the first test pattern 1 extends in a serpentine shape, and a plurality of concave areas F can be formed on both sides thereof, and the concave areas F on both sides of the first test pattern 1 are alternately arranged in the length extension direction of the first test pattern 1. The embodiment of the present application does not limit the morphology and size of each concave area F. Optionally, each concave area F has the same morphology and the same size.

[0042] In some embodiments of this application, please continue to refer to Figure 1 The second test pattern 2 and the third test pattern 3 are located on both sides of the first test pattern 1, and may adopt a comb-tooth structure; that is, the second test pattern 2 and the third test pattern 3 may be composed of a comb handle portion and at least one comb tooth portion, wherein an extension direction of the comb handle portion is the same as an extension direction of a length of the first test pattern 1, and an extension direction of the comb tooth portion is the same as a depression direction of the corresponding concave area F.

[0043] For example, the comb teeth ( 21 and 31 ) correspond to the concave areas F one by one.

[0044] For example, the comb teeth (21 and 31) are in the shape of long strips and are perpendicular to the comb handle corresponding to the test pattern.

[0045] For example, the width of the comb teeth (21 and 31) is less than or equal to the width of the comb handle corresponding to the test pattern.

[0046] Here, if Figure 1 As shown in , the total number of comb-tooth portions ( 21 and 31 ) in the second test pattern 2 and the third test pattern 3 is the same as the total number of concave areas F, and they correspond one to one, which can effectively improve space utilization.

[0047] In addition, optionally, the comb teeth (21 and 31) of the second test pattern 2 and the third test pattern 3 have the same structure, that is, have the same morphology and the same size. However, this is not limited to this, and the comb teeth (21 and 31) of the second test pattern 2 and the third test pattern 3 may have different structures, which is also allowed.

[0048] By way of further example, the comb-tooth portions 21 of the second test pattern 2 and the comb-tooth portions 31 of the third test pattern 3 match the arrangement of the concave areas F and are distributed alternately and at intervals.

[0049] It should be supplemented that, in some examples, the comb teeth ( 21 and 31 ) are distributed at equal intervals.

[0050] For example, the comb-tooth portions 21 of the second test pattern 2 and the comb-tooth portions 31 of the third test pattern 3 are arranged alternately, wherein the distance between any two adjacent comb-tooth portions is the same.

[0051] In some examples, the first test pattern 1 , the second test pattern 2 , and the third test pattern 3 may be conductive patterns of the same conductive material layer located in different regions, so as to simplify the preparation process of the semiconductor test structure.

[0052] In some other examples, at least one of the first test pattern 1 , the second test pattern 2 , and the third test pattern 3 is a conductive pattern formed by interconnecting multiple conductive material layers.

[0053] By way of example, the first test pattern 1 , the second test pattern 2 , and the third test pattern 3 are all metal conductive patterns.

[0054] By way of example, the first test pattern 1 , the second test pattern 2 , and the third test pattern 3 are formed by metal traces having the same width.

[0055] In addition, it can be understood that an insulating medium is provided between different test patterns to insulate and isolate adjacent test patterns.

[0056] Please continue reading Figure 1 In some embodiments of the present application, the semiconductor test structure further includes: a conductive contact structure 4 respectively arranged at the free end of each comb tooth portion (21 and 31); wherein the comb tooth portion (21 and 31) is connected to the substrate or the ground through the conductive contact structure 4.

[0057] Here, the free end of the comb tooth portion refers to the end thereof away from the corresponding comb handle portion.

[0058] By way of example, the conductive contact structure 4 includes, but is not limited to, a via connection structure.

[0059] Please continue reading Figure 1 In some embodiments of the present application, the semiconductor test structure further includes: a first test pad Pad1, a second test pad Pad2 and a third test pad Pad3. The first test pad Pad1 and the second test pad Pad2 are respectively disposed at two ends of the first test pattern 1 and are correspondingly connected to two ends of the first test pattern 1. The third test pad Pad3 connects the second test pattern 2 and the third test pattern 3.

[0060] By way of example, the first test pad Pad1 , the second test pad Pad2 , and the third test pad Pad3 include, but are not limited to, metal pads.

[0061] Please continue reading Figure 1 In some embodiments of the present application, the semiconductor test structure further includes: a first lead 51, a second lead 52, a third lead 53 and a fourth lead 54. The first lead 51 connects the first test pad Pad1 and the first end of the first test pattern 1. The second lead 52 connects the second test pad Pad2 and the second end of the first test pattern 1. The third lead 53 connects the third test pad Pad3 and the second test pattern 2. The fourth lead 54 connects the third test pad Pad3 and the third test pattern 3.

[0062] Optionally, the first test pad Pad1, the first lead 51, the first test pattern 1, the second lead 52 and the second test pad Pad2 are an integrated structure. The second test pattern 2, the third lead 53, the third test pad Pad3, the fourth lead 54 and the third test pattern 3 are an integrated structure.

[0063] As described above, the test unit composed of the first test pad Pad1, the first lead 51, the first test pattern 1, the second lead 52 and the second test pad Pad2 can be used to measure the circuit open circuit, and the test unit composed of the second test pattern 2, the third lead 53, the third test pad Pad3, the fourth lead 54 and the third test pattern 3 can be used to measure the circuit short circuit.

[0064] In the embodiment of the present application, by setting the first test pattern 1 and the second test pattern 2 and the third test pattern 3 located on both sides of the first test pattern 1 and having comb teeth, it is convenient to perform FIB sample preparation, and the semiconductor test structure is used to measure the open circuit defect and / or short circuit defect of the circuit. In addition, in the embodiment of the present application, the comb teeth of the second test pattern 2 and the third test pattern 3 are connected to the substrate or grounded, which can effectively identify the circuit defects appearing between any two test patterns, which can not only reduce the cross-sectional size during FIB sample preparation, but also help shorten the FIB analysis time to improve the FIB analysis efficiency.

[0065] The present disclosure also provides a failure analysis method for a semiconductor test structure according to some embodiments, which is applied to the semiconductor test structure in some of the above embodiments. The failure analysis method also has the technical advantages of the above semiconductor test structure.

[0066] See also Figure 2 , the failure analysis method may include the following steps S100~S300.

[0067] S100, performing laser beam resistance anomaly detection on the semiconductor test structure to determine the failure location.

[0068] S200, obtaining a cross-section of the semiconductor test structure at the failure position, and determining a measured image of the cross-section.

[0069] S300, comparing the measured image with a reference image to determine a failure pattern in the semiconductor test structure according to a difference between the measured image and the reference image; wherein the failure pattern includes a first test pattern, a second test pattern, a third test pattern, or a partial pattern of at least one of the three test patterns.

[0070] See also Figure 3 In some embodiments of the present application, the failure analysis method of a semiconductor test structure may further include the following step S400.

[0071] S400, obtaining a cross-section of the failure pattern in the semiconductor test structure, and performing failure analysis on the cross-section.

[0072] From the above, after performing OBIRCH and FIB cross-section sampling on the semiconductor test structure provided in the embodiment of the present application, please combine Figure 4 As shown in Figures (a) and (b), the measured images of the AA cross section in the FIB sample are as follows: Figure 4 As shown in FIG. 2( b ), the measured image is, for example, a dark-light-dark-light repetitive combination (Video Compositing, VC for short) image, and can be used as a reference image for failure analysis of semiconductor test structures.

[0073] On this basis, please combine Figure 5 As shown in (a), (b) and (c), no matter whether the circuit defect M appears between the second test pattern 2 and the first test pattern 1 (e.g. Figure 5 ), or appears between the first test pattern 1 and the third test pattern 3 (for example Figure 5 As shown in (b) of FIG. 1 , the floating potential of the first test pattern 1 can be pulled down to a low potential by the corresponding second test pattern 2 or the third test pattern 3 connected to the substrate or the ground, so that the cross-sectional measurement image corresponding to the first test pattern 1 is a dark image; that is, the measurement image (i.e., the measured image) of the AA cross section in the FIB sample will be as follows: Figure 5 As shown in Figure (c) in the figure, the measured image is a dark and dark repetitive VC image, which can be clearly distinguished from the measured image when there is no circuit defect (for example Figure 4 (as shown in Figure (b)).

[0074] In order to more clearly understand the role of the comb teeth in connecting the substrate or grounding in the second test pattern 2 and the third test pattern 3 in the embodiments of the present application, the semiconductor test structure in which the second test pattern 2 is grounded and the third test pattern 3 is not grounded is taken as an example in the following embodiments, and compared and analyzed with the embodiments of the present application.

[0075] See also Figure 6 , when the second test pattern 2 is grounded and the third test pattern 3 is not grounded, the first test pattern 1 is at a floating potential, the second test pattern 2 is at a grounded potential, and the third test pattern 3 is at a floating potential, then the measured image of the AA section in the corresponding FIB sample is a repeated VC image of dark, bright, and bright.

[0076] On this basis, if the circuit defect M appears between the second test pattern 2 and the first test pattern 1, since the second test pattern 2 is at the ground potential and the first test pattern 1 is at the floating potential, the first test pattern 1 is also at the ground potential after the first test pattern 1 and the second test pattern 2 are short-circuited. Then, the measurement image of the AA section in the corresponding FIB sample is a repeated VC image of dark and bright, for example Figure 7 as shown in .

[0077] However, if the circuit defect M appears between the first test pattern 1 and the third test pattern 3, since the first test pattern 1 and the third test pattern 3 are both floating potentials, the first test pattern 1 and the third test pattern 3 are still floating potentials after being short-circuited. Then, the measurement image of the AA section in the corresponding FIB sample is a dark-bright-bright repeated VC image, which is different from the measurement image without the circuit defect M (for example Figure 6 ) are identical, making it impossible to identify the corresponding circuit defect.

[0078] From the above, the embodiment of the present application sets the comb teeth of the second test pattern 2 and the third test pattern 3 to connect the substrate or the ground, which can effectively identify the circuit defects appearing between any two test patterns; that is: regardless of whether the circuit defect M appears between the second test pattern 2 and the first test pattern 1, or between the first test pattern 1 and the third test pattern 3, the semiconductor test structure provided by the embodiment of the present application can effectively identify it.

[0079] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A semiconductor test structure, characterized in that: include: The first test pattern extends in a serpentine shape and has a plurality of concave areas; The second test pattern and the third test pattern are located on both sides of the first test pattern and each has at least one comb-tooth portion extending into the concave area; The comb-teeth parts of the second test pattern and the third test pattern are connected to the substrate or grounded.

2. The semiconductor test structure according to claim 1, characterized in that: Also includes: Conductive contact structures are respectively arranged at the free ends of the comb teeth; The comb-teeth portion is connected to the substrate or grounded via the conductive contact structure.

3. The semiconductor test structure according to claim 1, characterized in that: The comb teeth correspond to the concave areas one by one.

4. The semiconductor test structure according to claim 3, characterized in that: The comb-teeth portions of the second test pattern and the comb-teeth portions of the third test pattern match the arrangement of the concave areas and are distributed alternately.

5. The semiconductor test structure according to claim 4, characterized in that: The comb teeth are distributed at equal intervals.

6. The semiconductor test structure according to claim 1, characterized in that: The first test pattern, the second test pattern and the third test pattern are conductive patterns located in different areas of the same conductive material layer; Or, at least one of the first test pattern, the second test pattern and the third test pattern is a conductive pattern formed by interconnecting multiple conductive material layers.

7. The semiconductor test structure according to any one of claims 1 to 6, characterized in that: Also includes: A first test pad and a second test pad are respectively arranged at two ends of the first test pattern and are correspondingly connected to two ends of the first test pattern; The third test pad connects the second test pattern and the third test pattern.

8. The semiconductor test structure according to claim 4, characterized in that: Also includes: A first lead connecting the first test pad and a first end of the first test pattern; A second lead connecting the second test pad and a second end of the first test pattern; A third lead connecting the third test pad and the second test pattern; A fourth lead connecting the third test pad and the third test pattern; Wherein, the first test pad, the first lead, the first test pattern, the second lead and the second test pad are an integrated structure; The second test pattern, the third lead, the third test pad, the fourth lead and the third test pattern are an integrated structure.

9. A failure analysis method for a semiconductor test structure, characterized in that: The semiconductor test structure comprises: a first test pattern extending in a serpentine shape and having a plurality of concave areas, and a second test pattern and a third test pattern respectively located on both sides of the first test pattern; wherein the second test pattern and the third test pattern each have at least one comb-tooth portion extending into the concave area, and the comb-tooth portion is connected to a substrate or grounded; The failure analysis method comprises: Performing laser beam resistance anomaly detection on the semiconductor test structure to determine the failure location; Acquire a cross-section of the semiconductor test structure at the failure position, and determine a measured image of the cross-section; Comparing the measured image with a reference image to determine a failure pattern in the semiconductor test structure according to a difference between the measured image and the reference image; The failure pattern includes the first test pattern, the second test pattern, the third test pattern, or a partial pattern of at least one of the three test patterns.

10. The failure analysis method of a semiconductor test structure according to claim 9, characterized in that: Also includes: A cross-section of the failure pattern in the semiconductor test structure is obtained, and a failure analysis is performed on the cross-section.

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