A control circuit for realizing positive and negative polarity reversal

Abstract

The present invention relates to a control circuit, specifically a control circuit for realizing positive and negative polarity reversal, the control circuit comprising a positive and negative polarity reversal circuit, a first SR network signal circuit, and a second SR network signal circuit, wherein the positive and negative polarity reversal circuit is electrically connected to the first SR network signal circuit and the second SR network signal circuit, respectively, and the positive and negative polarity reversal circuit is composed of a resistor R70, a resistor R71, a resistor R72, a resistor R73, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a resistor R79, a resistor R80, a resistor R81, a resistor R102, a resistor R136, a resistor R137, a capacitor C68, a capacitor C69, a Zener diode Z11, a Zener diode Z12, a transistor Q18, a transistor Q19, a field effect transistor Q10, a field effect transistor Q12, a field effect transistor Q15, and a field effect transistor Q16. The control circuit of the present invention is simple and ingenious in design, low in cost, and can be widely used in situations requiring voltage polarity reversal, and is worthy of vigorous promotion and application.

Description

Technical Field

[0001] The present invention relates to a control circuit, in particular to a control circuit that realizes positive and negative polarity reversal. Background Art

[0002] Pool salt systems, also known as salt water chlorinators, use electrolysis to convert salt in pool water into chlorine, achieving disinfection. This process is not only environmentally friendly and healthy, but also cost-effective. Compared to traditional disinfection methods, salt systems reduce reliance on chemical disinfectants, reducing skin irritation, while also lowering operating costs and maintenance. Furthermore, salt systems are designed with user experience in mind. The highly automated system is easy to monitor and adjust, requiring users to only regularly check and replenish the appropriate amount of salt, significantly reducing routine maintenance. However, with long-term use, conventional salt machine electrodes can accumulate salt, compromising electrolysis efficiency. By controlling the on / off switching of a circuit and periodically reversing the polarity of the DC output voltage, this problem of salt accumulation on the electrodes can be effectively addressed. However, currently available control circuits capable of achieving positive and negative polarity reversal are complex and costly, making them unsuitable for widespread adoption. Summary of the Invention

[0003] The purpose of the present invention is to provide a control circuit for realizing positive and negative polarity reversal. The circuit has a simple and ingenious design, low cost, and can be widely used in situations where voltage polarity reversal is required, thereby solving the problems raised in the above technical background.

[0004] To achieve the above-mentioned object, the present invention provides the following technical solution: a control circuit for realizing positive and negative polarity reversal, the control circuit comprising a positive and negative polarity reversal circuit, a first SR network signal circuit and a second SR network signal circuit, the positive and negative polarity reversal circuit being electrically connected to the first SR network signal circuit and the second SR network signal circuit respectively, and the positive and negative polarity reversal circuit is composed of resistors R70, R71, R72, R73, R75, R76, R77, R78, R79, R80, R81, R102, and R136. , resistor R137, capacitor C68, capacitor C69, Zener diode Z11, Zener diode Z12, transistor Q18, transistor Q19, field effect transistor Q10, field effect transistor Q12, field effect transistor Q15 and field effect transistor Q16, wherein one end of resistor R71 is connected to the first SR network signal circuit, and the other end is connected to resistor R72 and the base of transistor Q18 respectively; the emitter of transistor Q18 is grounded, and the collector is connected to capacitor C69, resistor R76, resistor R137, Zener diode Z12 and the G electrode of field effect transistor Q12 respectively, and field effect transistor Q The S pole of the field effect transistor Q12 is connected to the electrode inversion terminal OUT1, the D pole of the field effect transistor Q12 and the D pole of the field effect transistor Q10 are connected to the potential difference V0 terminal, the S pole of the field effect transistor Q10 is connected to the electrode inversion terminal OUT2, the G pole of the field effect transistor Q10 is respectively connected to the capacitor C68, the resistor R102, the resistor R136, the voltage regulator diode Z11 and the collector of the transistor Q19, the base of the transistor Q19 is respectively connected to the resistor R79 and the resistor R80, and the emitter of the transistor Q19 is grounded, and the end of the resistor R79 away from the transistor Q19 is connected to the second SR network signal circuit; the resistor R7 One end of resistor R70 is connected to the first SR network signal circuit, and the other end is connected to the resistor R75 and the G electrode of the field effect transistor Q15 respectively; the S electrode of the field effect transistor Q15 is grounded, and the D electrode is connected to the electrode inversion terminal OUT1; the two ends of resistor R70 are connected to the S electrode and D electrode of the field effect transistor Q15 respectively, and the two ends of resistor R78 are connected to the S electrode and D electrode of the field effect transistor Q16 respectively, the S electrode of the field effect transistor Q16 is grounded, the D electrode is connected to the electrode inversion terminal OUT2, and the G electrode is connected to the resistor R77 and the resistor R81 respectively. The end of the resistor R81 away from the field effect transistor Q16 is connected to the second SR network signal circuit.

[0005] Preferably, the capacitor C69, the resistor R76 and the Zener diode Z12 are connected in parallel, and the capacitor C69, the resistor R76 and the Zener diode Z12 are all electrically connected to the electrode inversion end OUT1.

[0006] Preferably, the capacitor C68, resistor R102 and Zener diode Z11 are connected in parallel, and one end of the capacitor C68, resistor R102 and Zener diode Z11 is connected to the electrode inversion end OUT2, and the other end is connected to the resistor R136, field effect transistor Q10 and transistor Q19 respectively.

[0007] Preferably, the resistor R136 and the resistor R137 are both connected to the positive and negative polarity reversal circuit power supply end, and the power supply voltage of the positive and negative polarity reversal circuit power supply end is 18V.

[0008] Preferably, the first SR network signal circuit includes a resistor R93, a resistor R94, a resistor R95, a resistor R96, a resistor R97, a capacitor C40, a capacitor C41, a capacitor C56, a diode D27, an SR1 network signal terminal and an operational amplifier U9-A, wherein one end of the resistor R94 is connected to the SR1 network signal terminal, and the other end is respectively connected to the capacitor C40 and the pin 2 of the operational amplifier U9-A; the capacitor C40 is grounded away from the end of the resistor R94; the resistor R95 and the capacitor C41 are connected in parallel The resistor R95 and the capacitor C41 are connected, and one end of the resistor R95 and the capacitor C41 are grounded, and the other ends are respectively connected to the resistor R93, the resistor R96 and the pin 3 of the operational amplifier U9-A; the two ends of the capacitor C56 are respectively connected to the pins 4 and 8 of the operational amplifier U9-A; the pin 8 of the operational amplifier U9-A is connected to the 12V power supply end, the pin 4 is grounded, and the pin 1 is respectively connected to the resistor R97 and the diode D27; the resistor R97 is connected to the positive and negative polarity reversal circuit at one end away from the operational amplifier U9-A.

[0009] Preferably, the model of the operational amplifier U9-A is: LM324.

[0010] Preferably, the second SR network signal circuit is composed of a resistor R98, a resistor R99, a resistor R100, a resistor R101, a resistor R103, a resistor R115, a capacitor C42, a capacitor C43, a diode Z21, an operational amplifier U9-B and an SR2 network signal terminal, wherein one end of the resistor R100 is connected to the SR2 network signal terminal, and the other end is respectively connected to the resistor R101, the resistor R115, the capacitor C43 and the pin 5 of the operational amplifier U9-B; the resistor R99 and the capacitor C42 are connected in parallel, and the diode Z21 is connected in parallel. One end of the resistor R99 and the capacitor C42 is grounded, and the other end is connected to the resistor R98 and pin 6 of the operational amplifier U9-B respectively. The end of the resistor R98 away from the resistor R99 and the capacitor C42 is connected to the second SR network signal power supply end, and the pin 7 of the operational amplifier U9-B is connected to the resistor R103 and the diode Z21 respectively. The end of the diode Z21 away from the operational amplifier U9-B is connected to the resistor R101, and the end of the resistor R103 away from the operational amplifier U9-B is connected to the positive and negative polarity reversal circuit.

[0011] Preferably, the input voltage of the second SR network signal power supply terminal is 5V.

[0012] Preferably, the resistor R115 and the capacitor C43 are connected in parallel, and one end of the resistor R115 and the capacitor C43 is grounded, and the other end is respectively connected to the resistor R100, the resistor R101 and the pin 5 of the operational amplifier U9-B.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] 1. The present invention provides a control circuit for realizing positive and negative polarity reversal, the control circuit comprising a positive and negative polarity reversal circuit, a first SR network signal circuit and a second SR network signal circuit, wherein the positive and negative polarity reversal circuits are electrically connected to the first SR network signal circuit and the second SR network signal circuit, respectively. When the SR1 network signal terminal and the SR2 network signal terminal on the first SR network signal circuit and the second SR network signal circuit are at a low level, GR1 is at a high level and GR2 is at a low level. Due to the high level of GR1, the transistor Q18 is turned on, the field effect transistor Q12 is not turned on, and the field effect transistor Q15 is turned on; because GR2 is at a low level, the transistor Q19 is not turned on, the field effect transistor Q10 is turned on, and the field effect transistor Q16 is not turned on; as a result, the electrode reversal terminal OUT1 is negative and the electrode reversal terminal OUT2 is positive; similarly, when the SR1 network signal terminal and the SR2 network signal terminal are at a high level, GR1 is at a low level and GR2 is at a high level; at this time, the polarity is reversed, the electrode reversal terminal OUT1 is positive and the electrode reversal terminal OUT2 is negative, realizing the positive and negative reversal of the electrodes. The entire circuit design is simple and ingenious, with low cost, and can be widely used in situations where voltage polarity reversal is required. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a principle block diagram of the present invention;

[0016] Figure 2 1 is a circuit diagram of the positive and negative polarity reversal circuit of the present invention;

[0017] Figure 3 This is a circuit schematic diagram of the first SR network signal circuit of the present invention;

[0018] Figure 4 1 is a circuit schematic diagram of the second SR network signal circuit of the present invention;

[0019] Figure 5 This is a test curve diagram of an embodiment of the present invention.

[0020] The reference numerals and names in the figures are as follows:

[0021] 1. Positive and negative polarity reversal circuit; 2. First SR network signal circuit; 3. Second SR network signal circuit; 10. Control circuit. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0023] In the description of the embodiments of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0024] In the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "installed," "connected," "connected," "fixed," etc. should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the embodiments of the present invention based on specific circumstances.

[0025] Example 1:

[0026] See also Figure 1 An embodiment of the present invention provides: a control circuit for realizing positive and negative polarity reversal, the control circuit 10 includes a positive and negative polarity reversal circuit 1, a first SR network signal circuit 2 and a second SR network signal circuit 3, the positive and negative polarity reversal circuit 1 is electrically connected to the first SR network signal circuit 2 and the second SR network signal circuit 3 respectively, the entire circuit design is simple and ingenious, low cost, and can be widely used in occasions where voltage polarity reversal is required.

[0027] See also Figure 2The positive and negative polarity reversal circuit 1 in the figure is composed of resistor R70, resistor R71, resistor R72, resistor R73, resistor R75, resistor R76, resistor R77, resistor R78, resistor R79, resistor R80, resistor R81, resistor R102, resistor R136, resistor R137, capacitor C68, capacitor C69, Zener diode Z11, Zener diode Z12, transistor Q18, transistor Q19, field effect transistor Q10, field effect transistor Q12, field effect transistor Q15 and field effect transistor Q16. , wherein one end of the resistor R71 is connected to the first SR network signal circuit 2, and the other end is respectively connected to the resistor R72 and the base of the transistor Q18; the emitter of the transistor Q18 is grounded, and the collector is respectively connected to the capacitor C69, the resistor R76, the resistor R137, the voltage-stabilizing diode Z12 and the G electrode of the field-effect transistor Q12, the S electrode of the field-effect transistor Q12 is connected to the electrode inversion terminal OUT1, the D electrode of the field-effect transistor Q12 and the D electrode of the field-effect transistor Q10 are connected to the potential difference V0 terminal, and the S electrode of the field-effect transistor Q10 is connected to the potential difference V0 terminal. The G electrode of the field effect tube Q10 is connected to the collector of the capacitor C68, the resistor R102, the resistor R136, the voltage regulator diode Z11 and the transistor Q19 respectively. The base of the transistor Q19 is connected to the resistor R79 and the resistor R80 respectively, and the emitter of the transistor Q19 is grounded. The end of the resistor R79 away from the transistor Q19 is connected to the second SR network signal circuit 3; one end of the resistor R73 is connected to the first SR network signal circuit 2, and the other end is connected to the resistor R 75 is connected to the G pole of the field effect tube Q15; the S pole of the field effect tube Q15 is grounded, and the D pole is connected to the electrode inversion terminal OUT1; the two ends of the resistor R70 are respectively connected to the S pole and D pole of the field effect tube Q15, and the two ends of the resistor R78 are respectively connected to the S pole and D pole of the field effect tube Q16, the S pole of the field effect tube Q16 is grounded, the D pole is connected to the electrode inversion terminal OUT2, and the G pole is respectively connected to the resistor R77 and the resistor R81, and the end of the resistor R81 away from the field effect tube Q16 is connected to the above-mentioned second SR network signal circuit 3.

[0028] Specifically, the capacitor C69, the resistor R76 and the Zener diode Z12 are connected in parallel, and the capacitor C69, the resistor R76 and the Zener diode Z12 are all electrically connected to the electrode inversion terminal OUT1.

[0029] Specifically, the capacitor C68, resistor R102 and Zener diode Z11 are connected in parallel, and one end of the capacitor C68, resistor R102 and Zener diode Z11 is connected to the electrode inversion end OUT2, and the other end is connected to the resistor R136, field effect transistor Q10 and transistor Q19 respectively.

[0030] Specifically, the resistor R136 and the resistor R137 are both connected to the positive and negative polarity reversal circuit power supply end, and the power supply voltage of the positive and negative polarity reversal circuit power supply end is 18V.

[0031] See also Figure 3 , the first SR network signal circuit 2 in the figure includes a resistor R93, a resistor R94, a resistor R95, a resistor R96, a resistor R97, a capacitor C40, a capacitor C41, a capacitor C56, a diode D27, an SR1 network signal terminal and an operational amplifier U9-A, wherein one end of the resistor R94 is connected to the SR1 network signal terminal, and the other end is connected to the capacitor C40 and the pin 2 of the operational amplifier U9-A respectively; the capacitor C40 is grounded away from the resistor R94; the resistor R95 and the capacitor C41 are connected in parallel , and one end of the resistor R95 and the capacitor C41 are grounded, and the other ends are respectively connected to the resistor R93, the resistor R96 and the pin 3 of the operational amplifier U9-A; the two ends of the capacitor C56 are respectively connected to the pins 4 and 8 of the operational amplifier U9-A; the pin 8 of the operational amplifier U9-A is connected to the 12V power supply end, the pin 4 is grounded, and the pin 1 is respectively connected to the resistor R97 and the diode D27; the end of the resistor R97 away from the operational amplifier U9-A is connected to the above-mentioned positive and negative polarity reversal circuit 1.

[0032] See also Figure 5 , the second SR network signal circuit 3 in the figure is composed of a resistor R98, a resistor R99, a resistor R100, a resistor R101, a resistor R103, a resistor R115, a capacitor C42, a capacitor C43, a diode Z21, an operational amplifier U9-B and an SR2 network signal terminal, wherein one end of the resistor R100 is connected to the SR2 network signal terminal, and the other end is respectively connected to the resistor R101, the resistor R115, the capacitor C43 and the No. 5 pin of the operational amplifier U9-B; the resistor R99 and the capacitor C42 are connected in parallel, and the resistor R One end of 99 and capacitor C42 are grounded, and the other ends are respectively connected to resistor R98 and pin 6 of operational amplifier U9-B. The end of resistor R98 away from resistor R99 and capacitor C42 is connected to the second SR network signal power supply end. Pin 7 of operational amplifier U9-B is respectively connected to resistor R103 and diode Z21. The end of diode Z21 away from operational amplifier U9-B is connected to resistor R101. The end of resistor R103 away from operational amplifier U9-B is connected to the above-mentioned positive and negative polarity reversal circuit 1.

[0033] Specifically, the input voltage of the second SR network signal power supply end is 5V.

[0034] Specifically, the resistor R115 and the capacitor C43 are connected in parallel, and one end of the resistor R115 and the capacitor C43 is grounded, and the other end is connected to the resistor R100, the resistor R101 and the pin 5 of the operational amplifier U9-B respectively.

[0035] Please refer again Figure 3 and Figure 4 In this embodiment, the operational amplifier U9-A and the operational amplifier U9-B are both of the model: LM324.

[0036] Please visit again Figures 1 to 4 When the SR1 network signal terminal and the SR2 network signal terminal on the first SR network signal circuit 2 and the second SR network signal circuit 3 are at a low level, GR1 is at a high level and GR2 is at a low level; because GR1 is at a high level, the transistor Q18 is turned on, the field effect transistor Q12 is not turned on, and the field effect transistor Q15 is turned on; because GR2 is at a low level, the transistor Q19 is not turned on, the field effect transistor Q10 is turned on, and the field effect transistor Q16 is not turned on; as a result, the electrode reversal terminal OUT1 is negative and the electrode reversal terminal OUT2 is positive; by the same token, when the SR1 network signal terminal and the SR2 network signal terminal are at a high level, GR1 is at a low level and GR2 is at a high level; at this time, the polarity is reversed, the electrode reversal terminal OUT1 is positive, and the electrode reversal terminal OUT2 is negative, realizing the positive reversal of the electrode. The entire circuit design is simple and ingenious, with low cost, and can be widely used in occasions where voltage polarity reversal is required.

[0037] Example 2:

[0038] See also Figure 5 In this embodiment, a 120W / 12V / 10A power output device is used to perform the electrode reversal test. In the figure, CH1 is the 12V output voltage and CH3 is the SR control signal. When the SR signal level voltage is adjusted, the polarity of the DC 12V output voltage can be reversed.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A control circuit for achieving positive and negative polarity reversal, characterized in that: The invention comprises a positive and negative polarity reversal circuit (1), a first SR network signal circuit (2) and a second SR network signal circuit (3), wherein the positive and negative polarity reversal circuit (1) is electrically connected to the first SR network signal circuit (2) and the second SR network signal circuit (3), respectively, and the positive and negative polarity reversal circuit (1) comprises a resistor R70, a resistor R71, a resistor R72, a resistor R73, a resistor R75, a resistor R76, a resistor R77, a resistor R78, a resistor R79, a resistor R80, a resistor R81, a resistor R102, a resistor R136, a resistor R137, a capacitor C68, and a capacitor C69.

9. A voltage-stabilizing diode Z11, a voltage-stabilizing diode Z12, a transistor Q18, a transistor Q19, a field-effect transistor Q10, a field-effect transistor Q12, a field-effect transistor Q15, and a field-effect transistor Q16 are formed, wherein one end of a resistor R71 is connected to the first SR network signal circuit (2), and the other end is connected to the resistor R72 and the base of the transistor Q18 respectively; the emitter of the transistor Q18 is grounded, and the collector is connected to the capacitor C69, the resistor R76, the resistor R137, the voltage-stabilizing diode Z12, and the G electrode of the field-effect transistor Q12 respectively, and the S electrode of the field-effect transistor Q12 is connected to the electrode inversion terminal OU T1 is connected, the D pole of the field effect tube Q12 and the D pole of the field effect tube Q10 are connected to the potential difference V0 end, the S pole of the field effect tube Q10 is connected to the electrode reversal end OUT2, the G pole of the field effect tube Q10 is respectively connected to the capacitor C68, the resistor R102, the resistor R136, the voltage regulator diode Z11 and the collector of the transistor Q19, the base of the transistor Q19 is respectively connected to the resistor R79 and the resistor R80, and the emitter of the transistor Q19 is grounded, and the end of the resistor R79 away from the transistor Q19 is connected to the second SR network signal circuit (3); one end of the resistor R73 is connected to the first S The first and second SR network signal circuits (2) are connected to the first SR network signal circuit (3), and the other end is connected to the resistor R75 and the G pole of the field effect tube Q15 respectively; the S pole of the field effect tube Q15 is grounded, and the D pole is connected to the electrode inversion end OUT1; the two ends of the resistor R70 are connected to the S pole and the D pole of the field effect tube Q15 respectively, and the two ends of the resistor R78 are connected to the S pole and the D pole of the field effect tube Q16 respectively; the S pole of the field effect tube Q16 is grounded, the D pole is connected to the electrode inversion end OUT2, and the G pole is connected to the resistor R77 and the resistor R81 respectively; the end of the resistor R81 away from the field effect tube Q16 is connected to the second SR network signal circuit (3).

2. The control circuit for realizing positive and negative polarity reversal according to claim 1, characterized in that: The capacitor C69, the resistor R76 and the Zener diode Z12 are connected in parallel, and the capacitor C69, the resistor R76 and the Zener diode Z12 are all electrically connected to the electrode inversion terminal OUT1.

3. The control circuit for realizing positive and negative polarity reversal according to claim 1, characterized in that: The capacitor C68, resistor R102 and Zener diode Z11 are connected in parallel, and one end of the capacitor C68, resistor R102 and Zener diode Z11 is connected to the electrode inversion end OUT2, and the other ends are connected to the resistor R136, field effect transistor Q10 and transistor Q19 respectively.

4. The control circuit for realizing positive and negative polarity reversal according to claim 1, characterized in that: The resistor R136 and the resistor R137 are both connected to the power supply end of the positive and negative polarity reversal circuit, and the power supply voltage of the power supply end of the positive and negative polarity reversal circuit is 18V.

5. The control circuit for realizing positive and negative polarity reversal according to claim 1, characterized in that: The first SR network signal circuit (2) comprises a resistor R93, a resistor R94, a resistor R95, a resistor R96, a resistor R97, a capacitor C40, a capacitor C41, a capacitor C56, a diode D27, an SR1 network signal terminal and an operational amplifier U9-A, wherein one end of the resistor R94 is connected to the SR1 network signal terminal, and the other end is connected to the capacitor C40 and the pin 2 of the operational amplifier U9-A respectively; the end of the capacitor C40 away from the resistor R94 is grounded; the resistor R95 and the capacitor C41 are connected in parallel , and one end of the resistor R95 and the capacitor C41 are grounded, and the other ends are connected to the resistor R93, the resistor R96 and the pin 3 of the operational amplifier U9-A respectively; the two ends of the capacitor C56 are connected to the pins 4 and 8 of the operational amplifier U9-A respectively; the pin 8 of the operational amplifier U9-A is connected to the 12V power supply end, the pin 4 is grounded, and the pin 1 is connected to the resistor R97 and the diode D27 respectively; the end of the resistor R97 away from the operational amplifier U9-A is connected to the positive and negative polarity reversal circuit (1).

6. The control circuit for realizing positive and negative polarity reversal according to claim 5, characterized in that: The model of the operational amplifier U9-A is: LM324.

7. The control circuit for realizing positive and negative polarity reversal according to claim 1, characterized in that: The second SR network signal circuit (3) is composed of a resistor R98, a resistor R99, a resistor R100, a resistor R101, a resistor R103, a resistor R115, a capacitor C42, a capacitor C43, a diode Z21, an operational amplifier U9-B and an SR2 network signal terminal, wherein one end of the resistor R100 is connected to the SR2 network signal terminal, and the other end is respectively connected to the resistor R101, the resistor R115, the capacitor C43 and the No. 5 pin of the operational amplifier U9-B; the resistor R99 and the capacitor C42 are connected in parallel, and the resistor R100 is connected to the No. 5 pin of the operational amplifier U9-B. One end of R99 and capacitor C42 is grounded, and the other end is connected to resistor R98 and pin 6 of operational amplifier U9-B respectively. The end of resistor R98 away from resistor R99 and capacitor C42 is connected to the second SR network signal power supply end. Pin 7 of operational amplifier U9-B is connected to resistor R103 and diode Z21 respectively. The end of diode Z21 away from operational amplifier U9-B is connected to resistor R101. The end of resistor R103 away from operational amplifier U9-B is connected to positive and negative polarity reversal circuit (1).

8. The control circuit for realizing positive and negative polarity reversal according to claim 7, characterized in that: The input voltage of the second SR network signal power supply terminal is 5V.

9. The control circuit for realizing positive and negative polarity reversal according to claim 7, characterized in that: The resistor R115 and the capacitor C43 are connected in parallel, and one end of the resistor R115 and the capacitor C43 is grounded, and the other end is connected to the resistor R100, the resistor R101 and the pin 5 of the operational amplifier U9-B respectively.

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