A binary regulated bandgap reference temperature drift and output voltage circuit

Abstract

The application discloses a binary regulation band gap reference temperature drift and output voltage circuit and belongs to the integrated circuit field, comprising a band gap reference circuit, a current regulation channel and a first current mirror network and a second current mirror network. The band gap reference circuit can generate a Vout output voltage according to the structure thereof, but if the output voltage Vout deviates from the ideal value, the current on the resistor R3 and the triode Q4 can be adjusted through the first current mirror network, the second current mirror network and the current regulation channel, so that the output voltage Vout changes to the ideal value. The current sources Ibias1 and Ibias2 can be set according to the requirement, the circuit structure is reliable, the response is rapid, and the effective protection circuit work can be realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a binary adjustable bandgap reference temperature drift and output voltage circuit. Background Technology

[0002] Bandgap reference voltages play a crucial role in electronic device and integrated circuit design. When power management circuits require a precise reference voltage to provide a stable and reliable reference voltage for other modules, such as in analog-to-digital converters (ADCs) and DACs, a high-precision, low-temperature-drift reference voltage is essential to ensure accurate signal sampling and output. Summary of the Invention

[0003] The purpose of this invention is to provide a binary adjustable bandgap reference temperature drift and output voltage circuit to solve the problems in the prior art.

[0004] To solve the above-mentioned technical problems, the present invention provides a binary adjustable bandgap reference temperature drift and output voltage circuit, comprising: a bandgap reference circuit, a current regulation path, a first current mirror network and a second current mirror network;

[0005] The bandgap reference circuit generates a reference output voltage Vout through its own circuit structure.

[0006] The current control path has two control paths. By changing the current in the bandgap reference circuit according to the two control paths, the temperature drift of the bandgap reference and the output voltage can be adjusted.

[0007] The first current mirror network mirrors the proportional current according to the magnitude of its own first bias current, and then controls the current path in the first current mirror network to be turned on or off according to the high or low level of the control signal to obtain the first current.

[0008] The second current mirror network mirrors the proportional current according to the magnitude of its own second bias current, and then controls the current path in the second current mirror network to be turned on or off according to the high or low level of the control signal to obtain the second current.

[0009] In one embodiment, the bandgap reference circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an operational amplifier, a first resistor, a second resistor, a third resistor, a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0010] The source terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the power supply voltage VDD. The gate terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the output terminal of the operational amplifier.

[0011] The drain of the first PMOS transistor is connected to the base of the second transistor and the emitter of the first transistor; the drain of the second PMOS transistor is connected to the emitter of the second transistor and the inverting input of the operational amplifier; the drain of the third PMOS transistor is connected to the non-inverting input of the operational amplifier and the first terminal of the first resistor; the drain of the fourth PMOS transistor is connected to the first terminal of the second resistor, and the drain output voltage is Vout.

[0012] The second terminal of the first resistor is connected to the emitter of the third transistor; the second terminal of the second resistor is connected to the first terminal of the third resistor, and the second terminal of the third resistor is simultaneously connected to the base of the third transistor and the emitter of the fourth transistor; the base of the first transistor is grounded, and its collector is grounded; the collector of the second transistor is grounded; the base of the third transistor is connected to the emitter of the fourth transistor and the second terminal of the third resistor, the emitter is connected to the second terminal of the first resistor, and its collector is grounded; the base of the fourth transistor is grounded, the emitter is connected to the second terminal of the third resistor and the base of the third transistor, and its collector is grounded.

[0013] In one embodiment, the current regulation path includes current source I11, current source I12, current source I21, current source I22, and a first switch CK. <0> Second switch CK <0> and the third switch CKN <0> Fourth switch CKN <0> First inverter and second inverter;

[0014] One end of the current source I11 is connected to the power supply VDD, and the other end is connected to the first switch CK. <0> The first terminal, the input terminal of the first inverter, and the first switch CK <0> The second terminal is connected to the third switch CKN <0> The first terminal is connected to the output terminal of the second inverter and the first terminal of the third resistor; one end of the current source I12 is connected to the third switch CKN. <0> The second terminal of I12 is grounded;

[0015] One end of the current source I21 is connected to the power supply VDD, and the other end is connected to the fourth switch CKN. <0> The first terminal, the fourth switch CKN <0> The second terminal is connected to the output terminal of the first inverter, the first terminal of the third resistor, and the second switch CK. <0> The first terminal, one end of the current source I22 is connected to the second switch CK. <0> The second terminal of the circuit is the input terminal of the second inverter, and the other terminal of the current source I12 is grounded.

[0016] In one embodiment, the first current mirror network includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first current source;

[0017] In this configuration, one end of the first current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS transistor. The gate of the first NMOS transistor is simultaneously connected to its own drain, the gate of the second NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the source of the fifth NMOS transistor, and the source is grounded. The drain of the third NMOS transistor is connected to the source of the sixth NMOS transistor, and the source is grounded. The drain of the fourth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source is grounded.

[0018] The first terminal of the first current transistor is connected to the power supply VDD, and the second terminal is simultaneously connected to the drain terminals of the fifth, sixth, and seventh NMOS transistors. The gate terminal of the fifth NMOS transistor is connected to the control signal CK. <1> The gate terminal of the sixth NMOS transistor is connected to the control signal CK. <2> The gate terminal of the seventh NMOS transistor is connected to the control signal CK. <3> .

[0019] In one embodiment, the second current mirror network includes a second current source, an eighth NMOS transistor NM8, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a second current source;

[0020] In this configuration, one end of the second current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is simultaneously connected to its own drain, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the ninth NMOS transistor is connected to the source of the twelfth NMOS transistor, and the source is grounded. The drain of the tenth NMOS transistor is connected to the source of the thirteenth NMOS transistor, and the source is grounded. The drain of the eleventh NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the source is grounded.

[0021] The first terminal of the second current is connected to the power supply VDD, and the second terminal is simultaneously connected to the drain terminals of the twelfth, thirteenth, and fourteenth NMOS transistors. The gate terminal of the twelfth NMOS transistor is connected to the control signal CK. <1> The gate terminal of the thirteenth NMOS transistor is connected to the control signal CK. <2> The gate terminal of the fourteenth NMOS transistor is connected to the control signal CK. <3> .

[0022] This invention provides a binary adjustable bandgap reference temperature drift and output voltage circuit, which can achieve low temperature drift and a stable reference voltage at different temperatures. The invention has a simple structure, and the circuit can be used to provide a reference voltage in high-precision circuits, with wide applications in analog-to-digital converters and digital-to-analog converters. By re-controlling the current flowing through resistor R3 and transistor Q4, the temperature drift is further reduced, and the output voltage reaches the ideal value. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the bandgap reference circuit and current regulation path in this invention.

[0024] Figure 2 This is a schematic diagram of the structure of the first current mirror network in this invention.

[0025] Figure 3 This is a schematic diagram of the structure of the second current mirror network in this invention. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a binary adjustable bandgap reference temperature drift and output voltage circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0027] This invention provides a binary adjustable bandgap reference temperature drift and output circuit, the structure of which is as follows: Figure 1 , Figure 2 and Figure 3 As shown, it includes a bandgap reference circuit, a current regulation path, a current mirror network 1, and a current mirror network 2.

[0028] The bandgap reference circuit generates a reference output Vout through its circuit structure. There are two current control paths. By changing the current through resistor R3 and transistor Q4 in the bandgap reference circuit according to these two paths, the temperature drift of the bandgap reference and the output voltage can be adjusted. Current mirror network 1 mirrors a proportional current based on the magnitude of current source Ibias1, and then controls the current path in current mirror network 1 to open or close based on the high or low level of the CK signal, thus obtaining current I1. Current mirror network 2 mirrors a proportional current based on the magnitude of current source Ibias2, and then controls the current path in current mirror network 2 to open or close based on the high or low level of the CK signal, thus obtaining current I2.

[0029] The bandgap reference circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, an operational amplifier opamp, a first resistor R1, a second resistor R2, a third resistor R3, a first transistor Q1, a second transistor Q2, a third transistor Q3, and a fourth transistor Q4.

[0030] The source of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and its gate is simultaneously connected to the gates of the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4. Its drain is simultaneously connected to the base of the second transistor Q2 and the emitter of the first transistor Q1. The source of the second PMOS transistor PM2 is connected to the power supply voltage VDD, and its gate is simultaneously connected to the gates of the first PMOS transistor PM1, the third PMOS transistor PM3, and the fourth PMOS transistor PM4. Its drain is simultaneously connected to the emitter of the second transistor Q2 and the inverting input of the operational amplifier opamp. The source of the third PMOS transistor PM3 is connected to the power supply voltage VDD, and its gate is simultaneously connected to the gates of the first PMOS transistor PM1, the second PMOS transistor PM2, and the fourth PMOS transistor PM4. Its drain is simultaneously connected to the non-inverting input of the operational amplifier opamp and the first terminal of the first resistor R1. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDD. Its gate is connected to the gates of the first PMOS transistor PM1, the second PMOS transistor PM2, and the third PMOS transistor PM3. Its drain is connected to the first terminal of the second resistor R2, and its drain output voltage is Vout. The non-inverting input of the operational amplifier opamp is connected to the first terminal of resistor R1, and its inverting input is connected to the emitter of the second transistor Q2. Its output is connected to the gates of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4. The first terminal of the first resistor R1 is connected to the non-inverting input of the operational amplifier opamp, and the second terminal is connected to the emitter of the third transistor Q3. The first terminal of the second resistor R2 is connected to the drain of the fourth PMOS transistor PM4 and the output voltage Vout. The second terminal is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the base of the third transistor Q3 and the emitter of the fourth transistor Q4. The base and collector of the first transistor Q1 are grounded, and its emitter is connected to the drain of the first PMOS transistor PM1 and the base of the second transistor Q2. The base of the second transistor Q2 is connected to the drain of the first PMOS transistor PM1 and the emitter of the first transistor Q1, while its collector is grounded. Its emitter is connected to the drain of the second PMOS transistor PM2 and the inverting input of the operational amplifier opamp. The base of the third transistor Q3 is connected to the emitter of the fourth transistor Q4 and the second terminal of the third resistor R3. Its emitter is connected to the second terminal of the first resistor R1, and its collector is grounded. The base of the fourth transistor Q4 is grounded, and its emitter is connected to the second terminal of the third resistor R3 and the base of the third transistor Q3. Its collector is grounded.

[0031] The current control path includes current source I11, current source I12, current source I21, current source I22, and the first switch CK. <0> Second switch CK <0> and the third switch CKN <0> Fourth switch CKN <0> Inverters INV1 and INV2; one end of current source I11 is connected to power supply VDD, and the other end is connected to the first switch CK. <0> The first terminal, the input terminal of inverter INV1, and the first switch CK <0> The second terminal is connected to the third switch CKN <0> The first terminal of the first resistor R3, the output terminal of the inverter INV2; one end of the current source I12 is connected to the third switch CKN. <0> The second terminal of current source I12 is grounded. One terminal of current source I21 is connected to power supply VDD, and the other terminal is connected to the fourth switch CKN. <0> The first terminal, the fourth switch CKN <0> The second terminal is connected to the output terminal of inverter INV1, the first terminal of the third resistor R3, and the second switch CK. <0> The first terminal, one end of the current source I22 is connected to the second switch CK. <0> The second terminal of the inverter INV2 is connected to the input terminal of the inverter, and the other terminal of the current source I12 is grounded.

[0032] like Figure 2 As shown, the current mirror network 1 includes a current source Ibias1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and a current I1.

[0033] In this circuit, one end of the current source Ibias1 is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is simultaneously connected to the drain of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, the gate of the third NMOS transistor NM3, and the gate of the fourth NMOS transistor NM4. The source of the first NMOS transistor NM1 is grounded.

[0034] The drain of the second NMOS transistor NM2 is connected to the source of the fifth NMOS transistor NM5. The gate of the second NMOS transistor NM2 is also connected to the gate of the first NMOS transistor NM1, the gate of the third NMOS transistor NM3, and the gate of the fourth NMOS transistor NM4. The source of the second NMOS transistor NM2 is grounded.

[0035] The drain of the third NMOS transistor NM3 is connected to the source of the sixth NMOS transistor NM6. The gate of the third NMOS transistor NM3 is also connected to the gate of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, and the gate of the fourth NMOS transistor NM4. The source of the third NMOS transistor NM3 is grounded.

[0036] The drain of the fourth NMOS transistor NM4 is connected to the source of the seventh NMOS transistor NM7. The gate of the fourth NMOS transistor NM4 is also connected to the gate of the first NMOS transistor NM1, the gate of the second NMOS transistor NM2, and the gate of the third NMOS transistor NM3. The source of the fourth NMOS transistor NM4 is grounded.

[0037] The first terminal of current I1 is connected to the power supply VDD, and the second terminal is simultaneously connected to the drain terminals of the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM7. The gate terminal of the fifth NMOS transistor NM5 is connected to the control signal CK. <1> The source terminal of the fifth NMOS transistor NM5 is connected to the drain terminal of the second NMOS transistor; the gate terminal of the sixth NMOS transistor NM6 is connected to the control signal CK. <2> The source terminal of the sixth NMOS transistor NM6 is connected to the drain terminal of the third NMOS transistor; the gate terminal of the seventh NMOS transistor NM7 is connected to the control signal CK. <3> The source terminal of the seventh NMOS transistor NM7 is connected to the drain terminal of the fourth NMOS transistor.

[0038] like Figure 3 As shown, similar to the structure of current mirror network 1, current mirror network 2 includes current source Ibias2, eighth NMOS transistor NM8, ninth NMOS transistor NM9, tenth NMOS transistor NM10, eleventh NMOS transistor NM11, twelfth NMOS transistor NM12, thirteenth NMOS transistor NM13, fourteenth NMOS transistor NM14, and current I2.

[0039] One end of the current source Ibias2 is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS transistor NM8. The gate of the eighth NMOS transistor NM8 is also connected to the gate of the ninth NMOS transistor NM9, the tenth NMOS transistor NM10, and the eleventh NMOS transistor NM11. The source of the eighth NMOS transistor NM8 is grounded.

[0040] The drain of the ninth NMOS transistor NM9 is connected to the source of the twelfth NMOS transistor NM12. The gate of the ninth NMOS transistor NM9 is simultaneously connected to the gate of the eighth NMOS transistor NM8, the gate of the tenth NMOS transistor NM10, and the gate of the eleventh NMOS transistor NM11. The source of the ninth NMOS transistor NM9 is grounded.

[0041] The drain of the tenth NMOS transistor NM10 is connected to the source of the thirteenth NMOS transistor NM13. The gate of the tenth NMOS transistor NM10 is simultaneously connected to the gate of the eighth NMOS transistor NM8, the gate of the ninth NMOS transistor NM9, and the gate of the eleventh NMOS transistor NM11. The source of the tenth NMOS transistor NM10 is grounded.

[0042] The drain of the eleventh NMOS transistor NM11 is connected to the source of the fourteenth NMOS transistor NM14. The gate of the eleventh NMOS transistor NM11 is also connected to the gate of the eighth NMOS transistor NM8, the gate of the ninth NMOS transistor NM9, the gate of the tenth NMOS transistor NM10, and the source of the eleventh NMOS transistor NM11 is grounded.

[0043] One end of current I2 is connected to the power supply VDD, and the other end is simultaneously connected to the drain of the twelfth NMOS transistor NM12, the drain of the thirteenth NMOS transistor NM13, and the drain of the fourteenth NMOS transistor NM14. The gate of the twelfth NMOS transistor NM12 is connected to the control signal CK. <1> The source terminal of the twelfth NMOS transistor NM12 is connected to the drain terminal of the ninth NMOS transistor NM9; the gate terminal of the thirteenth NMOS transistor NM13 is connected to the control signal CK. <2> The source terminal of the thirteenth NMOS transistor NM13 is connected to the drain terminal of the tenth NMOS transistor NM10; the gate terminal of the fourteenth NMOS transistor NM14 is connected to the control signal CK. <3> The source terminal of the fourteenth NMOS transistor NM14 is connected to the drain terminal of the eleventh NMOS transistor NM11.

[0044] The detailed working process of this invention is as follows:

[0045] The control signal is CK <0> CK <1> CK <2> CK <3> The circuit is constructed such that the control signals are initially all zero. The output voltage Vout is generated by the bandgap reference circuit structure. The basic principle is that when the reference circuit is working normally, bipolar transistors Q2 and Q3 operate at different current densities, and the difference between their base-collector voltages has a positive temperature coefficient; the base-emitter voltage of the bipolar transistor has a negative temperature coefficient, and a linear combination of the two can form a voltage with a zero temperature coefficient. The clamping effect of the operational amplifier makes V+ = V-. Therefore, the current flowing through resistor R1 is:

[0046]

[0047] In the formula, VT is the thermal voltage, which has a positive temperature coefficient; N is the ratio of the emitter area of ​​Q2 (Q2=Q1) to that of Q3 (Q3=Q4). It is the difference between the emitter and base voltages of the first transistor Q1. It is the difference between the emitter and base voltages of the second transistor Q2. It is the difference between the emitter and base voltages of the third transistor Q3. It is the difference between the emitter and base voltages of the fourth transistor Q4.

[0048] Since transistors PM1 to PM4 form a current mirror structure with the same width-to-length ratio, and the current in each branch is almost equal, the output reference voltage is:

[0049]

[0050] The output voltage can be obtained from the bandgap reference circuit according to the above formula. However, in actual applications, due to manufacturing or process deviations, the output voltage and temperature drift may deviate from the ideal value. In this case, the control signal can be adjusted as needed.

[0051] It mainly consists of a current regulation path, and the control signal CK <0> When the signal is high, the switch can be closed, and the current sources I11 and I12 in the current control path are equal to the current source I1 in current mirror network 1; the current sources I21 and I22 are equal to the current source I2 in current mirror network 2. When the control signal CK... <0> When the current level is high, the power supply, current source I11, current source I22, and ground form a current path in the current regulation path; and because current source I11 and current source I22 are not equal, the remaining current will flow into resistor R3 and transistor Q4 through the node, or the remaining current will flow into current source I22 through the node.

[0052] For example, if the control signal CK <0> When the voltage level is high, the power supply, current source I11, current source I22, and ground form a current path in the current control path. If current source I11 is greater than current source I22, then... This will be channeled into resistor R3 and transistor Q4, causing changes in temperature drift and output voltage Vout. Similarly, if the control signal CK... <0> CKN is at a low level. <0> For CK <0> The inverted signal, in the current control path, the power supply, current source I21, current source I12, and ground form a current path. If current source I21 is less than current source I12, then... The current flowing through resistor R3 and transistor Q4 will decrease. This causes changes in temperature drift and output voltage Vout.

[0053] In current mirror network 1, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 form a current mirror. Based on the width-to-length ratio of NM1 to NM2, NM3, and NM4, the width-to-length ratio of NM1 to NM2, NM3, and NM4 is set to Q:J:K:M = 1:4:2:1, and the control signal CK... <1> Control signal CK <2> Control signal CK <3> When the level is high, the corresponding NMOS transistor can be turned on, thereby controlling the magnitude of the current source I1 flowing through it.

[0054] In current mirror network 2, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9 form a current mirror. Based on the width-to-length ratio of NM6 to NM7, NM8, and NM9, this ratio is set to Q:J:K:M = 1:4:2:1, and the control signal CK... <1> Control signal CK <2> Control signal CK <3> When the level is high, the corresponding NMOS transistor can be turned on, thereby controlling the magnitude of the current source I2 flowing through it.

[0055] To illustrate this more clearly, the present invention provides an example of the output voltage change when binary changes occur in a binary-controlled bandgap reference temperature drift and output voltage circuit. Based on the characteristics of the circuit structure, and for ease of description, we will use... , And current Assuming the current flowing through transistor Q4 is 10uA, and the output voltage Vout is set to 1.2V.

[0056] For each bit change in the control signal from 0000 to 0111, the output voltage is:

[0057]

[0058] here , =1kΩ, Here we assume , The transistor's β is set to 20, and the initial Vout = 1.2V. This is the current flowing through the fourth transistor Q4 when the current regulation path is not open. β is the current flowing through the fourth transistor Q4 after the current regulation path is turned on, ignoring the base current; β is the current amplification factor of the transistor.

[0059] Table 1 lists the control signals CK. <0> : CK <1> : CK <2> : CK <3> When the voltage changes from 0000 to 01111, the output voltage Vout changes, CK <0> If I = 0, then the power supply, I21, I12, and ground maintain a closed circuit, and the current flows... The current flowing through resistor R3 and transistor Q4 decreases. With each adjustment step, Vout decreases by 5.658mV, thereby correcting the situation where the output voltage deviates from the ideal value due to manufacturing or process deviations.

[0060] CK<0>:<1>:<2>:<3> Output voltage Vout / V Adjustment / mV 0000 1.2 0 0001 1.19432 -5.658 0010 1.188684 -11.316 0011 1.183026 -16.974 0100 1.177368 -22.632 0101 1.17171 -28.29 0110 1.166025 -33.948 0111 1.160394 -39.606

[0061] Table 1 Adjustment reduces output voltage

[0062] Table 2 lists the control signals CK. <0> : CK <1> : CK <2> : CK <3> When the voltage changes from 1000 to 11111, the output voltage Vout changes, and CK... <0> =1, then the power supply, I12, I21, and ground maintain a closed circuit, and the current flows... The current flowing through resistor R3 and transistor Q4 increases. With each adjustment step, Vout increases by 4.358mV, thereby correcting the situation where the output voltage deviates from the ideal value due to manufacturing or process deviations.

[0063] CK<0>:<1>:<2>:<3> Output voltage Vout / V Adjustment / mV 1000 1.2 0 1001 1.204358 +4.358 1010 1.208716 +8.716 1011 1.213074 +13.074 1100 1.217432 +17.432 1101 1.22179 +21.79 1110 1.226148 +26.148 1111 1.230506 +30.506

[0064] Table 2 Adjustment to increase output voltage

[0065] It can be seen that the adjustment step can be controlled by controlling the values ​​of Ibias1 and Ibias2, and the current flowing through resistor R3 and transistor Q4 can be controlled by controlling the high and low levels of the control signal, thereby controlling the output voltage Vout. From the table above, it can be analyzed that if we assume... , then CK <0> =0 can reduce its output voltage; CK <0> =1 can increase its output voltage.

[0066] Binary values ​​enable the mirror image ratio through the current mirror to achieve CK. <1> CK <2> CK <3> The current ratio of the current in the circuit is 4:2:1, thus realizing binary current regulation. Finally, the binary current is reflected in the output Vout, and the output Vout is regulated.

[0067] The circuit structure also affects temperature drift, but temperature drift requires specific analysis of the actual circuit to determine how the output voltage changes with temperature. The simulation calculations of the actual circuit are based on this, but the underlying principles are basically the same as those described above, so they will not be elaborated further.

[0068] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A binary-controlled bandgap reference temperature drift and output voltage adjustment circuit, characterized in that, include: Bandgap reference circuit, current regulation path, first current mirror network and second current mirror network; The bandgap reference circuit generates a reference output voltage Vout through its own circuit structure. The first current mirror network mirrors the proportional current according to the magnitude of its own first bias current, and then controls the current path in the first current mirror network to be turned on or off according to the high or low level of the control signal to obtain the first current. The second current mirror network mirrors the proportional current according to the magnitude of its own second bias current, and then controls the current path in the second current mirror network to be turned on or off according to the high or low level of the control signal to obtain the second current; The current regulation path includes current source I11, current source I12, current source I21, current source I22, and first switch CK. <0> Second switch CK <0> and the third switch CKN <0> Fourth switch CKN <0> First inverter and second inverter; One end of the current source I11 is connected to the power supply VDD, and the other end is connected to the first switch CK. <0> The first terminal, the input terminal of the first inverter, and the first switch CK <0> The second terminal is connected to the third switch CKN <0> The first terminal and the output terminal of the second inverter are connected to the first terminal of the third resistor; one end of the current source I12 is connected to the third switch CKN. <0> The second terminal of I12 is grounded; One end of the current source I21 is connected to the power supply VDD, and the other end is connected to the fourth switch CKN. <0> The first terminal, the fourth switch CKN <0> The second terminal is connected to the output terminal of the first inverter and the second switch CK. <0> The first terminal of the first resistor, the first terminal of the third resistor, and one terminal of the current source I22 are connected to the second switch CK. <0> The second terminal of the current source I12 is grounded, and the other terminal of the current source I12 is grounded; The bandgap reference circuit includes a third resistor and a fourth transistor; the first terminal of the third resistor is simultaneously connected to the first switch CK. <0> The second and fourth switches CKN <0> The second end of the third resistor is connected to the emitter of the fourth transistor, and the base and collector of the fourth transistor are both grounded. The current regulation path has two regulation paths. By changing the current of the third resistor and the fourth transistor in the bandgap reference circuit according to the two regulation paths, the temperature drift of the bandgap reference and the output voltage can be regulated.

2. The binary adjustable bandgap reference temperature drift and output voltage circuit as described in claim 1, characterized in that, The bandgap reference circuit also includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, an operational amplifier, a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor; The source terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the power supply voltage VDD. The gate terminals of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to the output terminal of the operational amplifier. The drain of the first PMOS transistor is connected to the base of the second transistor and the emitter of the first transistor; the drain of the second PMOS transistor is connected to the emitter of the second transistor and the inverting input of the operational amplifier; the drain of the third PMOS transistor is connected to the non-inverting input of the operational amplifier and the first terminal of the first resistor; the drain of the fourth PMOS transistor is connected to the first terminal of the second resistor, and the drain output voltage is Vout. The second end of the first resistor is connected to the emitter of the third transistor; the second end of the second resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the base of the third transistor; the base of the first transistor is grounded, and its collector is grounded; the collector of the second transistor is grounded; the base of the third transistor is connected to the emitter of the fourth transistor and the second end of the third resistor, the emitter is connected to the second end of the first resistor, and its collector is grounded.

3. The binary adjustable bandgap reference temperature drift and output voltage circuit as described in claim 1, characterized in that, The first current mirror network includes a first current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a first current source; In this configuration, one end of the first current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the first NMOS transistor. The gate of the first NMOS transistor is simultaneously connected to its own drain, the gate of the second NMOS transistor, the gate of the third NMOS transistor, and the gate of the fourth NMOS transistor. The source of the first NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the source of the fifth NMOS transistor, and the source is grounded. The drain of the third NMOS transistor is connected to the source of the sixth NMOS transistor, and the source is grounded. The drain of the fourth NMOS transistor is connected to the source of the seventh NMOS transistor, and the source is grounded. The first terminal of the first current transistor is connected to the power supply VDD, and the second terminal is simultaneously connected to the drain terminals of the fifth, sixth, and seventh NMOS transistors. The gate terminal of the fifth NMOS transistor is connected to the control signal CK. <1> The gate terminal of the sixth NMOS transistor is connected to the control signal CK. <2> The gate terminal of the seventh NMOS transistor is connected to the control signal CK. <3> .

4. The binary adjustable bandgap reference temperature drift and output voltage circuit as described in claim 1, characterized in that, The second current mirror network includes a second current source, an eighth NMOS transistor NM8, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a second current source; In this configuration, one end of the second current source is connected to the power supply VDD, and the other end is connected to the gate and drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is simultaneously connected to its own drain, the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, and the gate of the eleventh NMOS transistor. The source of the eighth NMOS transistor is grounded. The drain of the ninth NMOS transistor is connected to the source of the twelfth NMOS transistor, and the source is grounded. The drain of the tenth NMOS transistor is connected to the source of the thirteenth NMOS transistor, and the source is grounded. The drain of the eleventh NMOS transistor is connected to the source of the fourteenth NMOS transistor, and the source is grounded. The first terminal of the second current is connected to the power supply VDD, and the second terminal is simultaneously connected to the drain terminals of the twelfth, thirteenth, and fourteenth NMOS transistors. The gate terminal of the twelfth NMOS transistor is connected to the control signal CK. <1> The gate terminal of the thirteenth NMOS transistor is connected to the control signal CK. <2> The gate terminal of the fourteenth NMOS transistor is connected to the control signal CK. <3> .

Images