Starting circuit used in band-gap reference circuit

Abstract

The invention discloses a starting circuit used in a band-gap reference circuit, and belongs to the field of integrated circuits. The starting circuit and the band-gap reference circuit are powered by power supply voltage VCC, the input end of the starting circuit is connected with reference voltage VBGR output by the band-gap reference circuit, and the output end of the starting circuit is connected with the positive input end of an operational amplifier in the band-gap reference circuit; the starting circuit enables the positive input end voltage of an operational amplifier in the band-gap reference circuit to be larger than the negative input end voltage in the circuit working condition changing process, band-gap reference output is kept in a rising state, and the band-gap reference circuit can be separated from a low-voltage degeneracy area all the time. According to the invention, high-reliability guarantee is provided for normal work of the band-gap reference voltage under various working conditions unfavorable for an external power supply; and the risk that the band-gap reference circuit falls into a low-voltage degenerate region due to transistor mismatch caused by limit process deviation is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a start-up circuit used in a bandgap reference circuit. Background Art

[0002] The typical bandgap reference with an operational amplifier in traditional textbooks generally does not have a startup circuit and only corrects process deviations by adjusting the geometric parameters of the input differential transistors. This can cause the output of the bandgap reference circuit to be low. In the case of some extreme process deviations, the bandgap reference output will be at a low voltage degenerate point, causing the risk of the reference voltage not being established normally.

[0003] Therefore, a new startup circuit is urgently needed to correct the problem that the bandgap reference cannot be started normally due to extreme process deviation, improve the yield of the bandgap reference circuit, and improve the reliability of the system. Summary of the invention

[0004] The object of the present invention is to provide a start-up circuit for a bandgap reference circuit, so as to solve the problem that the bandgap reference cannot be started normally due to the correction of the extreme process deviation.

[0005] In order to solve the above technical problems, the present invention provides a start-up circuit for a bandgap reference circuit.

[0006] The startup circuit and the bandgap reference circuit use the power supply voltage VCC for power supply operation, the input end of the startup circuit is connected to the reference voltage VBGR output by the bandgap reference circuit, and the output end of the startup circuit is connected to the positive input end of the operational amplifier in the bandgap reference circuit;

[0007] When the circuit operating condition changes, the startup circuit makes the positive input voltage of the operational amplifier in the bandgap reference circuit greater than the negative input voltage, so that the bandgap reference output remains in an ascending state, and the bandgap reference circuit can always leave the low-voltage degenerate region.

[0008] In one embodiment, the bandgap reference circuit includes an operational amplifier, a first resistor, a second resistor, a third resistor, a first bipolar transistor and a second bipolar transistor; wherein the positive input terminal of the operational amplifier is connected to the second end of the first resistor and the emitter of the second bipolar transistor, and the negative input terminal of the operational amplifier is connected to the second end of the second resistor and the first end of the third resistor; the first bipolar transistor and the second bipolar transistor are used to generate a positive temperature coefficient voltage, and both operate at the same current; the first resistor and the second resistor are equal; the base of the first bipolar transistor and the base of the second bipolar transistor are both connected to the ground to form a diode connection; the emitter terminal of the first bipolar transistor is connected to the second end of the third resistor, and the emitter terminal of the second bipolar transistor is connected to the second end of the first resistor.

[0009] In one embodiment, the startup circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, and a second NMOS tube; the first PMOS tube and the second PMOS tube form a first common-source common-gate structure, and the third PMOS tube and the fourth PMOS tube form a second common-source common-gate structure; the gate of the first PMOS tube and the gate of the third PMOS tube are connected to a bias voltage VB1, and the gate of the second PMOS tube and the gate of the fourth PMOS tube are connected to a bias voltage VB2; the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube; the gate of the first NMOS tube is connected to a bandgap reference output voltage VBGR, the gate of the second NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the positive input terminal of the operational amplifier.

[0010] In one embodiment, the bias voltages VB1 and VB2 in the startup circuit are established by a bias current mirror circuit, and the bias current mirror circuit has two pairs of PMOS type cascode current mirrors and two pairs of NMOS cascode current mirrors, which respectively provide constant currents for two branches;

[0011] The ninth PMOS tube and the tenth PMOS tube form a common source and common gate structure, the sixth NMOS tube N6 and the seventh NMOS tube form a common source and common gate structure, and they form a first current branch; the eleventh PMOS tube and the twelfth PMOS tube form a common source and common gate structure, the eighth NMOS tube and the ninth NMOS tube form a common source and common gate structure, and they form a second current branch;

[0012] The first end of the sixth resistor is connected to the gate of the eighth NMOS transistor, and the second end of the sixth resistor is connected to the gate of the ninth NMOS transistor, and they together form a self-biased common-source common-gate circuit; the source of the ninth NMOS transistor is connected to the emitter of the sixth bipolar transistor, the source of the sixth NMOS transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the emitter of the fifth bipolar transistor;

[0013] The third bias circuit is composed of a seventh PMOS tube, an eighth PMOS tube, a fifth NMOS tube and a fourth bipolar transistor; the source of the fifth NMOS tube is connected to the emitter of the fourth bipolar transistor, the gate of the fifth NMOS tube is connected to the gate of the ninth NMOS tube, the current of the fifth NMOS tube and the fourth bipolar transistor branch is a mirror current of the ninth NMOS tube and the sixth bipolar transistor branch, the gate of the seventh PMOS tube is connected to the gate and drain of the eighth PMOS tube, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are commonly connected to the gates of the tenth PMOS tube and the twelfth PMOS tube, and the third bias circuit provides a bias voltage VB2 to the tenth PMOS tube and the twelfth PMOS tube through the gate voltages of the seventh PMOS tube and the eighth PMOS tube;

[0014] The gate of the ninth PMOS tube is connected to the drain of the tenth PMOS tube to form a low-voltage common-source common-gate bias circuit structure, providing a bias voltage VB1; the fifth PMOS tube, the sixth PMOS tube, the third NMOS tube, the fourth NMOS tube, the thirteenth NMOS tube, the third bipolar transistor and the fourth resistor together form a current source startup circuit; the source of the fifth PMOS tube is connected to VCC, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the drain of the sixth PMOS tube is connected to the gate of the fourth NMOS tube, the gate of the third NMOS tube, and the drain of the thirteenth NMOS tube;

[0015] The emitter of the third bipolar transistor is connected to the source of the fourth NMOS tube, the source of the third NMOS tube, and the source of the thirteenth NMOS tube; the base of the third bipolar transistor is connected to its own collector to form a diode connection mode; the drain of the third NMOS tube is connected to VB1, and the drain of the fourth NMOS tube is connected to VB2. When the circuit is powered on and started, the third NMOS tube and the fourth NMOS tube are turned on to pull down the voltages VB1 and VB2 to start the current source circuit; the gate of the thirteenth NMOS tube is connected to the VA end. When the current source circuit is started, the VA voltage increases to turn on the thirteenth NMOS tube and at the same time cause the third NMOS tube and the fourth NMOS tube to turn off, completing the current source circuit startup process.

[0016] In one implementation, the emitter area of ​​the first bipolar transistor is n times the emitter area of ​​the second bipolar transistor, the emitter area of ​​the fifth bipolar transistor is n times the emitter area of ​​the sixth bipolar transistor, and n is an integer greater than 1.

[0017] The present invention provides a startup circuit for a bandgap reference circuit. By adding a startup circuit, the bandgap reference circuit can always leave the low-voltage degenerate region during the process of circuit operating conditions changing, so that the bandgap reference circuit can work normally. Compared with the prior art, the present invention provides high reliability guarantee for the normal operation of the bandgap reference voltage under various adverse external power supply conditions; and avoids the risk of the bandgap reference circuit falling into the low-voltage degenerate region due to transistor mismatch caused by extreme process deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A circuit diagram showing the functional implementation of the start-up circuit of the bandgap reference;

[0019] Figure 2 The main circuit structure diagram of the starting circuit is shown;

[0020] Figure 3 The schematic diagram of the start-up circuit structure connected to the bandgap reference circuit is shown;

[0021] Figure 4 Shown is a schematic diagram of a current source circuit that provides bias voltage for a critical startup circuit. DETAILED DESCRIPTION

[0022] The following is a further detailed description of a startup circuit for a bandgap reference circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0023] The present invention adds a startup circuit to the bandgap reference circuit, such as Figure 1 As shown, the circuit can ensure that the voltage at the positive input terminal of the operational amplifier in the bandgap reference circuit is greater than the voltage at the negative input terminal even in a very slow startup process, so that the bandgap reference output remains in an upward state, i.e., positive feedback. The bandgap reference circuit is separated from the low-voltage degenerate point and enters the normal working point for establishing the bandgap reference voltage. The output reference voltage continues to rise until it reaches the bandgap reference set voltage value and stabilizes at this reference voltage.

[0024] The startup circuit and the bandgap reference circuit use the power supply voltage VCC for power supply operation, an input end of the startup circuit is connected to the reference voltage VBGR output by the bandgap reference circuit, and an output end of the startup circuit is connected to the positive input end of the operational amplifier circuit in the bandgap reference circuit.

[0025] The bandgap reference circuit comprises an operational amplifier, wherein a positive input terminal of the operational amplifier is connected to the second terminal of the resistor R1 and the emitter of the bipolar transistor Q2, and a negative input terminal of the operational amplifier is connected to the second terminal of the resistor R2 and the first terminal of the resistor R3.

[0026] The two bipolar transistors Q1 and Q2 used to generate the positive temperature coefficient voltage in the bandgap reference circuit operate at substantially the same current, and the resistors R1 and R2 are equal. The emitter area of ​​the bipolar transistor Q1 is n times the emitter area of ​​Q2. The bases of the bipolar transistors Q1 and Q2 are both connected to the ground to form a diode connection. The emitter terminal of the bipolar transistor Q1 is connected to the second end of the resistor R3, and the emitter terminal of the bipolar transistor Q2 is connected to the second end of the resistor R1.

[0027] like Figure 2 The circuit diagram of the implementation mode of the startup circuit in the present invention is shown. The startup circuit has two pairs of PMOS type cascode current mirrors, which provide constant current for two branches respectively. PMOS tubes P1 and P2 form a first cascode structure, and PMOS tubes P3 and P4 form a second cascode structure. The gates of PMOS tubes P1 and P3 are connected to the bias voltage VB1, and the gates of PMOS tubes P2 and P4 are connected to the bias voltage VB2.

[0028] The drain of the PMOS tube P2 is connected to the drain of the NMOS tube N1, and the drain of the PMOS tube P4 is connected to the drain of the NMOS tube N2. The gate of the NMOS tube N1 is connected to the bandgap reference output voltage VBGR, and the gate of the NMOS tube N2 is connected to the drain of the NMOS tube N1. The source of the NMOS tube N2 is connected to the positive input terminal of the operational amplifier.

[0029] (1) The cascode current mirror provides bias current through bias voltages VB1 and VB2.

[0030] (2) During the circuit startup process, when the bandgap reference voltage VBGR has not been established normally, the NMOS tube N1 is in the off state, the drain voltage of the NMOS tube N1 is close to the power supply voltage, the NMOS tube N2 is turned on, and a high voltage is added to the positive input terminal of the operational amplifier. The operational amplifier outputs a high level. As long as the output voltage VBGR is greater than the bipolar transistor turn-on voltage VBE, the bipolar transistors Q1 and Q2 can be turned on. According to the following calculation formula:

[0031]

[0032] Resistance R1 = R2. According to the virtual short principle of the operational amplifier input terminal, the voltage at the positive input terminal is equal to the voltage at the negative input terminal, so the current in resistance R1 is equal to the current in resistance R2, that is, Ic1 = Ic2. The emitter area of ​​the bipolar transistor Q1 is n times that of Q2 (n is an integer greater than 1), and the reverse saturation current of the bipolar transistor Q1 is also n times that of Q2. So:

[0033] V BE2 >V BE1 (3)

[0034] This ensures that the voltage at the positive input of the operational amplifier is greater than the voltage at the negative input. Even if the operational amplifier input transistor mismatch results in a typical offset voltage of 2mV to 5mV under extreme process deviation conditions, it can still ensure that the voltage at the positive input of the operational amplifier is greater than the voltage at the negative input. It can be confirmed that the bandgap reference circuit is still in the positive feedback condition until the bandgap reference input voltage rises to the reference voltage setting value VBGR (about 1.2V) and stabilizes under the condition of mainly negative feedback.

[0035] like Figure 3 The schematic diagram of the start-up circuit of the present invention added to the bandgap reference circuit is shown. The start-up circuit can meet the voltage V at point Y during the system startup process. Y Greater than the voltage V at point X X , ensuring that the bandgap reference circuit is in a positive feedback condition, helping the bandgap reference output voltage to continue to rise with the power supply voltage until it stabilizes at the correct setting value of the bandgap reference.

[0036] like Figure 4 The bias current mirror circuit diagram established by the bias voltages VB1 and VB2 in the startup circuit of the present invention is shown. The bias current source circuit has two pairs of PMOS type cascode current mirrors and two pairs of NMOS cascode current mirrors, which provide constant currents for two branches respectively. PMOS tubes P9 and P10 form a cascode structure, and NMOS tubes N6 and N7 form a cascode structure, which form a first current branch. PMOS tubes P11 and P12 form a cascode structure, and NMOS tubes N8 and N9 form a cascode structure, which form a second current branch. The first end of resistor R6 is connected to the gate of NMOS tube N8, and the second end of resistor R6 is connected to the gate of NMOS tube N9, which together form a self-biased cascode circuit. The source of NMOS tube N9 is connected to the emitter of bipolar transistor Q6, and the source of NMOS tube N6 is connected to the first end of resistor R5, and the second end of resistor R5 is connected to the emitter of bipolar transistor Q5. The emitter area of ​​the bipolar transistor Q5 is n times the emitter area of ​​the bipolar transistor Q6.

[0037] The third bias circuit is composed of a PMOS tube P7, a PMOS tube P8, an NMOS tube N5 and a bipolar transistor Q4. The source of the NMOS tube N5 is connected to the emitter of the bipolar transistor Q4. The gate of the NMOS tube N5 is connected to the gate of the NMOS tube N9. The branch current of the NMOS tube N5 and the bipolar transistor Q4 is the current of the branch of the mirror NMOS tube N9 and the bipolar transistor Q6. The gate of the PMOS tube P7 is connected to the gate and drain of the PMOS tube P8. The drain of the PMOS tube P7 is connected to the source of the PMOS tube P8. The gates of the PMOS tubes P7 and P8 are connected to the gates of the PMOS tubes P10 and P12, that is, the third bias circuit provides the bias voltage VB2 to the PMOS tubes P10 and P12 through the gate voltages of the PMOS tubes P7 and P8. The gate of the PMOS tube P9 is connected to the drain of the PMOS tube P10 to form a low-voltage common source and common gate bias circuit structure, providing the bias voltage VB1.

[0038] PMOS tube P5, PMOS tube P6, NMOS tube N3, NMOS tube N4, NMOS tube N13, bipolar transistor Q3 and resistor R4 together form a current source startup circuit. The source of PMOS tube P5 is connected to VCC, and the drain of PMOS tube P5 is connected to the source of PMOS tube P6. The gate of PMOS tube P5 is connected to the gate of PMOS tube P6 and the first end of resistor R4, and the second end of resistor R4 is grounded. The drain of PMOS tube P6 is connected to the gate of NMOS tube N4, the gate of NMOS tube N3, and the drain of NMOS tube N13. The emitter of bipolar transistor Q3 is connected to the source of NMOS tube N4, the source of NMOS tube N3, and the source of NMOS tube N13. The base of bipolar transistor Q3 is connected to its collector to form a diode connection mode. The drain of NMOS tube N3 is connected to VB1, and the drain of NMOS tube N4 is connected to VB2. When the circuit is powered on and started, NMOS tubes N3 and N4 are turned on to pull down voltages VB1 and VB2 to start the current source circuit. The gate of NMOS tube N13 is connected to the VA terminal. When the current source circuit is started, the VA voltage rises to turn on NMOS tube N13 and turn off NMOS tubes N3 and N4, completing the current source circuit startup process.

[0039] The bias current mirror circuit provides the establishment of bias current during system startup:

[0040] (1) As the power supply voltage rises to a value greater than the PMOS threshold voltage, the PMOS tubes P5 and P6 are always in the normally on state. The gate voltage of the NMOS tubes N3 and N4 is close to the power supply voltage. As long as the power supply voltage is greater than the sum of the NMOS threshold voltage and the bipolar transistor turn-on voltage VBE, the NMOS tubes N3 and N4 are turned on, and the respective drain voltages VB1 and VB2 of the NMOS tubes N3 and N4 are pulled down. The cascode tubes P9 and P10 are turned on, the cascode tubes P11 and P12 are turned on, and the bias branches P7 and P8 are turned on. The current source circuit can start normally to establish the bias current.

[0041] (2) The current source circuit structure is a typical circuit structure that is independent of the power supply voltage. The current source generated is a current that is proportional to the temperature. Among them, P9, P10, P11, and P12 form a low-voltage cascode current mirror structure. The gates of P9 and P11 are biased by diode connection, and the gates of P10 and P12 are biased by a bias circuit composed of branches P7, P8, N5, and Q4. NMOS tubes N8, N9 and resistor R6 form a self-biased cascode structure and together bias the gates of cascode tubes N6 and N7.

[0042] (3) NMOS tubes N6, N9, bipolar transistors Q5, Q6 and resistor R5 form a current source structure that is independent of the power supply voltage. The emitter area of ​​bipolar transistor Q5 is n times the emitter area of ​​Q6, where n is an integer greater than 1. The bias current generated is:

[0043]

[0044] Where k is the Boltzmann constant, T is the absolute temperature in Kelvin, and q is the electron charge constant. The circuit implements a current source circuit that is proportional to temperature and independent of the power supply voltage, and generates stable bias voltages VB1 and VB2 in the circuit to provide bias for other current mirror circuits.

[0045] like Figure 3 As shown in the figure, the startup circuit connects the voltage to the positive input terminal of the operational amplifier in the bandgap reference, so that the voltage at the positive input terminal of the operational amplifier is much greater than the voltage at the negative input terminal, and the operational amplifier outputs a high level. It ensures that the output voltage of the operational amplifier is at a high level during various complex power-on and power-off of the circuit and various different working sequence processes, so that the bipolar transistors Q1 and Q2 can start working normally.

[0046] The output voltage VBGR of the bandgap reference is directly connected to the gate of the NMOS tube N1. After the bandgap reference voltage VBGR is normally established (about 1.2V), the NMOS tube N1 can be normally turned on, so that the drain potential of the NMOS tube N1 is pulled down, that is, the gate voltage of the NMOS tube N2 is close to the ground potential, so the gate-source voltage of the NMOS tube N2 is reverse biased and in a cut-off state, so that the startup circuit is closed, and there is almost no effect on the positive input terminal of the operational amplifier.

[0047] like Figure 4 As shown, PMOS tubes P5 and P6 are always in the normally-on state after the power supply voltage rises to a value greater than the PMOS tube threshold voltage. The gate voltage of NMOS tubes N3 and N4 is close to the power supply voltage. As long as the power supply voltage is greater than the sum of the NMOS tube threshold voltage and the bipolar transistor start-up voltage VBE, NMOS tubes N3 and N4 are turned on, and the respective drain voltages VB1 and VB2 of NMOS tubes N3 and N4 are pulled down. Common-source common-gate tubes P9 and P10 are turned on, common-source common-gate tubes P11 and P12 are turned on, and bias branches P7 and P8 are turned on. The current source circuit can start normally to establish the bias current.

[0048] After the current source circuit starts to establish, the bias voltages VB1 and VB2 also generate stable bias voltages to provide bias for other subsequent circuits.

[0049] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A startup circuit for a bandgap reference circuit, characterized in that: The startup circuit and the bandgap reference circuit use the power supply voltage VCC for power supply operation, the input end of the startup circuit is connected to the reference voltage VBGR output by the bandgap reference circuit, and the output end of the startup circuit is connected to the positive input end of the operational amplifier in the bandgap reference circuit; When the circuit operating condition changes, the startup circuit makes the positive input voltage of the operational amplifier in the bandgap reference circuit greater than the negative input voltage, so that the bandgap reference output remains in an ascending state, and the bandgap reference circuit can always leave the low-voltage degenerate region.

2. The startup circuit for use in a bandgap reference circuit as claimed in claim 1, characterized in that: The bandgap reference circuit comprises an operational amplifier, a first resistor, a second resistor, a third resistor, a first bipolar transistor and a second bipolar transistor; wherein the positive input terminal of the operational amplifier is connected to the second end of the first resistor and the emitter of the second bipolar transistor, and the negative input terminal of the operational amplifier is connected to the second end of the second resistor and the first end of the third resistor; the first bipolar transistor and the second bipolar transistor are used to generate a positive temperature coefficient voltage, and both operate at the same current; the first resistor and the second resistor are equal; the base of the first bipolar transistor and the base of the second bipolar transistor are both connected to the ground to form a diode connection mode; the emitter terminal of the first bipolar transistor is connected to the second end of the third resistor, and the emitter terminal of the second bipolar transistor is connected to the second end of the first resistor.

3. The startup circuit for use in a bandgap reference circuit as claimed in claim 2, characterized in that: The startup circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, and a second NMOS tube; the first PMOS tube and the second PMOS tube form a first common-source common-gate structure, and the third PMOS tube and the fourth PMOS tube form a second common-source common-gate structure; the gate of the first PMOS tube and the gate of the third PMOS tube are connected to a bias voltage VB1, and the gate of the second PMOS tube and the gate of the fourth PMOS tube are connected to a bias voltage VB2; the drain of the second PMOS tube is connected to the drain of the first NMOS tube, and the drain of the fourth PMOS tube is connected to the drain of the second NMOS tube; the gate of the first NMOS tube is connected to a bandgap reference output voltage VBGR, the gate of the second NMOS tube is connected to the drain of the second NMOS tube, and the source of the second NMOS tube is connected to the positive input terminal of the operational amplifier.

4. The startup circuit for use in a bandgap reference circuit as claimed in claim 3, characterized in that: The bias voltages VB1 and VB2 in the startup circuit are established by a bias current mirror circuit, wherein the bias current mirror circuit has two pairs of PMOS type cascode current mirrors and two pairs of NMOS cascode current mirrors, respectively providing constant currents for the two branches; The ninth PMOS tube and the tenth PMOS tube form a common source and common gate structure, the sixth NMOS tube N6 and the seventh NMOS tube form a common source and common gate structure, and they form a first current branch; the eleventh PMOS tube and the twelfth PMOS tube form a common source and common gate structure, the eighth NMOS tube and the ninth NMOS tube form a common source and common gate structure, and they form a second current branch; The first end of the sixth resistor is connected to the gate of the eighth NMOS transistor, and the second end of the sixth resistor is connected to the gate of the ninth NMOS transistor, and they together form a self-biased common-source common-gate circuit; the source of the ninth NMOS transistor is connected to the emitter of the sixth bipolar transistor, the source of the sixth NMOS transistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the emitter of the fifth bipolar transistor; The third bias circuit is composed of a seventh PMOS tube, an eighth PMOS tube, a fifth NMOS tube and a fourth bipolar transistor; the source of the fifth NMOS tube is connected to the emitter of the fourth bipolar transistor, the gate of the fifth NMOS tube is connected to the gate of the ninth NMOS tube, the current of the fifth NMOS tube and the fourth bipolar transistor branch is a mirror current of the ninth NMOS tube and the sixth bipolar transistor branch, the gate of the seventh PMOS tube is connected to the gate and drain of the eighth PMOS tube, the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube, the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are commonly connected to the gates of the tenth PMOS tube and the twelfth PMOS tube, and the third bias circuit provides a bias voltage VB2 to the tenth PMOS tube and the twelfth PMOS tube through the gate voltages of the seventh PMOS tube and the eighth PMOS tube; The gate of the ninth PMOS tube is connected to the drain of the tenth PMOS tube to form a low-voltage common-source common-gate bias circuit structure, providing a bias voltage VB1; the fifth PMOS tube, the sixth PMOS tube, the third NMOS tube, the fourth NMOS tube, the thirteenth NMOS tube, the third bipolar transistor and the fourth resistor together form a current source startup circuit; the source of the fifth PMOS tube is connected to VCC, the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube, the gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube and the first end of the fourth resistor, and the second end of the fourth resistor is grounded; the drain of the sixth PMOS tube is connected to the gate of the fourth NMOS tube, the gate of the third NMOS tube, and the drain of the thirteenth NMOS tube; The emitter of the third bipolar transistor is connected to the source of the fourth NMOS tube, the source of the third NMOS tube, and the source of the thirteenth NMOS tube; the base of the third bipolar transistor is connected to its own collector to form a diode connection mode; the drain of the third NMOS tube is connected to VB1, and the drain of the fourth NMOS tube is connected to VB2. When the circuit is powered on and started, the third NMOS tube and the fourth NMOS tube are turned on to pull down the voltages VB1 and VB2 to start the current source circuit; the gate of the thirteenth NMOS tube is connected to the VA end. When the current source circuit is started, the VA voltage increases to turn on the thirteenth NMOS tube and at the same time cause the third NMOS tube and the fourth NMOS tube to turn off, completing the current source circuit startup process.

5. The startup circuit for use in a bandgap reference circuit as claimed in claim 4, characterized in that: The emitter area of ​​the first bipolar transistor is n times the emitter area of ​​the second bipolar transistor, the emitter area of ​​the fifth bipolar transistor is n times the emitter area of ​​the sixth bipolar transistor, and n is an integer greater than 1.

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