Memory device including content addressable memory and method of inputting and outputting data thereof

Abstract

A memory device is provided that includes a content addressable memory physical layer connected to an external data pad. During the write operation, first data is received from an external data pad. The content addressable memory physical layer transmits, as input data, a data pattern selected from among data patterns stored in the content addressable memory cell array to a selected memory cell of the memory cell array corresponding to an address received from an external device. During a read operation, based on an address received from an external device, the content addressable memory physical layer compares output data read from the memory cell array with a data pattern, and outputs a content addressable memory address corresponding to the data pattern matching a result of the comparison as second data through an external data pad.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0088002 filed on July 6, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a semiconductor memory device, and more particularly, to a memory device including a content addressable memory (CAM) and a method of inputting and outputting data in the memory device. Background Art

[0004] Semiconductor memory devices are generally divided into volatile memory devices and non-volatile memory devices. Volatile memory devices have high read and write speeds, but lose their stored data when their power supply is interrupted. In contrast, non-volatile memory devices can retain their stored data even when their power supply is interrupted.

[0005] Examples of volatile memory devices may include dynamic random access memory devices (DRAM) and static random access memory devices (SRAM). A memory cell of a volatile memory device may include a single N-type transistor used as a switch and a single capacitor storing charge as data DATA. Binary information "1" or "0" may correspond to the presence or absence of charge stored in the capacitor in the memory cell, for example, whether the terminal voltage of the cell capacitor is high or low. The memory cell may be connected to a word line and a bit line. The bit line may be connected to a sense amplifier. The sense amplifier may read the data stored in the memory cell through the bit line based on the voltage applied to the word line.

[0006] With the advancement of packaging technology, a volatile memory device and a memory controller are provided in one package. In addition, a package is being provided in which a memory chip including a volatile memory device is stacked on a logic chip including a memory controller. However, as the bandwidth between the logic chip and the memory chip increases, the occurrence of heating problems caused by input / output power of the memory chip increases. Summary of the invention

[0007] One or more aspects of the present disclosure provide a storage device including a content addressable memory (CAM) storing a plurality of data patterns. The storage device can store the data pattern of the CAM corresponding to the received data in a memory cell array of the storage device to use a smaller number of external data pads than the actual internal data path of the storage device.

[0008] One or more aspects of the present disclosure provide a method of inputting and outputting data in a memory device including a CAM storing a plurality of data patterns.

[0009] One or more aspects of the present disclosure provide a memory device stacked on a memory controller by reducing heat generated from a data pad.

[0010] According to one aspect of the present disclosure, a memory device is provided, comprising: a memory cell array including memory cells; an address decoder configured to output address information based on an address received from an external device; a command decoder configured to generate a memory access signal based on a command received from the external device; a content addressable memory (CAM) cell array configured to store a plurality of data patterns; and a CAM physical layer connected to a plurality of external data pads, the CAM physical layer being configured to: based on the memory access signal being a write operation signal, based on first data received through the plurality of external data pads, send a first data pattern of a plurality of data patterns as input data to a first memory cell of the memory cell array corresponding to the address information, and based on the memory access signal being a read operation signal, compare output data from the memory cell array with the plurality of data patterns based on the address information, and output a first CAM address corresponding to a second data pattern matching the output data as second data through the plurality of external data pads.

[0011] According to another aspect of the present disclosure, a method for operating a memory device is provided, the method comprising: receiving a plurality of content addressable memory (CAM) addresses; receiving a plurality of data patterns through a plurality of external data pads, each of the plurality of data patterns corresponding to one of a plurality of CAM addresses; storing the plurality of data patterns in a CAM cell array based on the plurality of CAM addresses; receiving a write command and a first address; receiving first data through a plurality of external data pads; selecting a first data pattern corresponding to the first data from the plurality of data patterns stored in the CAM cell array; and storing the first data pattern as input data in the memory cell array.

[0012] According to another aspect of the present disclosure, a storage system is provided, comprising: a logic chip including a logic core, a storage controller and a first content addressable memory (CAM) physical layer; and a storage chip stacked on the logic chip, the storage chip including a storage cell array and a second CAM physical layer, wherein the first CAM physical layer includes a first CAM cell array configured to store multiple data patterns, wherein the second CAM physical layer includes a second CAM cell array configured to store multiple data patterns, wherein the first CAM physical layer and the second CAM physical layer are configured to exchange encoded data having a capacity smaller than original data through multiple external data pads based on the multiple data patterns, and wherein the number of the multiple external data pads is smaller than the number of internal data paths of the logic chip or the storage chip.

[0013] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments of the present disclosure are shown in the accompanying drawings, where the same reference letters indicate corresponding parts in the various drawings. The embodiments of the present disclosure will be better understood from the following description with reference to the accompanying drawings, in which:

[0015] Figure 1 is a block diagram illustrating a storage system according to an embodiment.

[0016] Figure 2 It shows Figure 1 Block diagram of a memory device.

[0017] Figure 3 It shows Figure 2 Block diagram of the content-addressable memory physical layer.

[0018] Figure 4 is a table showing an example of a data pattern stored in a content addressable memory cell array according to an embodiment.

[0019] Figure 5 It shows Figure 2 Flowchart of the pattern write operation of the memory device.

[0020] Figure 6 It shows Figure 5 A diagram of the data flow during a mode write operation.

[0021] Figure 7 It shows Figure 2 Flowchart of a write operation of a memory device.

[0022] Figure 8 It shows Figure 7Diagram of the data flow during a write operation.

[0023] Fig. 9 It shows Figure 2 Flowchart of a read operation of a memory device.

[0024] Fig.10 It shows Fig. 9 Diagram of the data flow during a read operation.

[0025] Fig.11 is a diagram showing a three-dimensional stacked storage system according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0027] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be apparent. For example, the order of operations described herein is merely an example and is not limited to those order of operations set forth herein, but can be significantly changed after understanding the disclosure of the present application, except for operations that must be performed in a certain order. In addition, for greater clarity and brevity, the description of features known after understanding the disclosure of the present application may be omitted.

[0028] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein, which will be apparent after understanding the disclosure of the present application.

[0029] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, it may be directly "connected to" or "coupled to" the other component, or there may be one or more other components intervening. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements intervening. Similarly, similar expressions such as "between" and "directly between" and "adjacent to" and "immediately adjacent to" should also be interpreted in the same manner. As used herein, the term "and / or" includes any one of the items listed in the association and any combination of any two or more.

[0030] Although terms such as "first", "second", "third" and the like may be used herein to describe various components, assemblies, regions, layers or parts, these components, assemblies, regions, layers or parts should not be limited by these terms. Instead, these terms are only used to distinguish one component, component, region, layer or part from another component, component, region, layer or part. Therefore, without departing from the teachings of the examples described herein, the first component, component, region, layer or part mentioned in the examples may also be referred to as the second component, component, region, layer or part.

[0031] The terms used herein are only used to describe various examples and are not used to limit the present disclosure. Unless the context clearly indicates otherwise, the articles "one", "an" and "the" are also intended to include plural forms. The terms "include", "comprise" and "have" represent the presence of the features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof. As used herein, the expression "at least one of ..." modifies the entire list of elements after the list of elements without modifying the individual elements of the list. For example, the expression "at least one of a, b and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b and c.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by a person of ordinary skill in the art to which the present disclosure belongs, and based on the understanding of the disclosure of the present application. Terms such as those defined in commonly used dictionaries should be interpreted as having the same meaning as in the context of the relevant technology and the disclosure of the present application, and should not be interpreted as ideal or overly formal meanings unless explicitly defined as such herein. In this article, the use of the term "may" with respect to an example or embodiment (e.g., with respect to what an example or embodiment may include or implement) means that there is at least one example or embodiment in which such a feature is included or implemented, and all example embodiments are not limited thereto.

[0033] The embodiments of the present disclosure are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. As is common in the art, as shown in the accompanying drawings, embodiments may be described and illustrated with blocks that perform the functions described. These blocks (which may be referred to herein as units or modules, etc., or names such as devices, logic, circuits, counters, comparators, generators, converters, etc.) may be physically implemented by analog and / or digital circuits (including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.), and may also be implemented or driven by software and / or firmware (configured to perform the functions or operations described herein).

[0034] Hereinafter, DRAM will be taken as an example to illustrate the features, structures, operations, functions, etc. of the present disclosure. However, the present disclosure is not limited thereto, and therefore, according to other embodiments, the features, structures, operations, functions, etc. of the present disclosure may be implemented or applied to other electronic devices or other storage devices. In addition, those of ordinary skill in the art may easily understand other features, structures, operations, functions, etc. based on the information disclosed herein. The present disclosure may be implemented or applied to other embodiments or devices through other embodiments. In addition, the detailed description may be modified or changed according to viewpoints and applications without departing from the scope, spirit, and other purposes of the present disclosure.

[0035] Figure 1 is a block diagram illustrating a storage system according to an example embodiment. Figure 1 , a memory system 1000 according to an embodiment may include a memory controller 1100 and a memory device 1200 .

[0036] According to example embodiments, the storage controller 1100 may perform one or more operations of controlling the storage device 1200. For example, the storage controller 1100 may perform an access operation to write data into the storage device 1200 or read data stored in the storage device 1200. For example, the storage controller 1100 may generate a command CMD and an address ADDR for writing data into the storage device 1200 or reading data stored in the storage device 1200. The storage controller 1100 may include at least one of a storage controller circuit, a system on chip (SoC), a central processing unit (CPU), a digital signal processor (DSP), and a graphics processing unit (GPU). The SoC may be an application processor (AP). However, the present disclosure is not limited thereto, and therefore, the storage controller 1100 may be implemented by other types of processors or electronic components.

[0037] According to example embodiments, the memory controller 1100 may provide various signals to the memory device 1200 to control the overall operation of the memory device 1200. For example, the memory controller 1100 may control the memory access operation of the memory device 1200. For example, the memory access operation may include, but is not limited to, a read operation and a write operation. The memory controller 1100 may provide a command CMD and an address ADDR to the memory device 1200 to write data DATA into the memory device 1200 or read data DATA from the memory device 1200. In an example case where a write operation is performed, the memory controller 1100 may send or transfer the command CMD, the address ADDR, and the data DATA to the memory device 1200 to write the data DATA into the memory device 1200. In another example case where a read operation is performed, the memory controller 1100 may send or transfer the command CMD and the address ADDR to the memory device 1200 to read the data DATA from the memory device 1200. In this case, the memory controller 1100 may receive the data DATA from the memory device 1200.

[0038] According to example embodiments, the memory controller 1100 may generate various types of commands CMD to control the memory device 1200. For example, the memory controller 1100 may generate a memory request corresponding to a memory operation of changing the state of a memory bank among the memory banks to read or write data DATA. As an example, the memory request may include an activation request for changing the state of a memory bank among the memory banks to an active state. The memory device 1200 may activate a row, such as a word line, included in the memory bank based on the activation request. The memory request may include a precharge request for changing the memory bank from an active state to a standby state after completing the reading or writing of the data DATA. In addition, the memory controller 1100 may generate an input / output (I / O) request for the memory device 1200 to perform a read operation or a write operation of the data DATA. For example, the I / O request may be a column address strobe (CAS) request. In the example case of performing a read operation, the I / O request may include a read request for reading data DATA from an activated memory bank. In the example case of performing a write operation, the I / O request may include a write request for writing data DATA into an activated memory bank. The memory controller 1100 may generate a refresh command to control a refresh operation on a memory bank. However, the types of commands CMD described herein are merely exemplary, and other types of commands CMD may be provided or implemented in a memory system.

[0039] According to example embodiments, the memory device 1200 may output data DATA requested to be read by the memory controller 1100 to the memory controller 1100, or may store data DATA requested to be written by the memory controller 1100 in a memory cell of the memory device 1200. The memory device 1200 may input and output data DATA based on a command CMD and an address ADDR. The memory device 1200 may include a memory bank. The memory device 1200 may include at least one data pad DQ. The memory device 1200 may input and output data DATA through the data pad DQ. The data pad DQ may be connected to an input buffer or an output buffer.

[0040] The memory device 1200 may be a volatile memory device, including but not limited to a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. According to another embodiment, the memory device 1200 may be implemented as a non-volatile memory device, including but not limited to a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), etc. In the following description, the features and advantages of the present disclosure have been described with respect to DRAM, but example embodiments are not limited thereto.

[0041] According to an example embodiment, a memory bank may include a memory cell array divided in units of memory banks. In addition, the memory may include, but is not limited to, a row decoder, a column decoder, a sense amplifier, a write driver, and the like. The memory bank may store the data DATA requested to be written in the memory device 1200 using the write driver, and may read the data DATA requested to be read using the sense amplifier. The memory bank may also include a component for performing a refresh operation of storing and maintaining data in the cell array, or an address-based selection circuit.

[0042] According to an example embodiment, the memory device 1200 may include a content addressable memory physical layer (CAM PHY) 1250. For example, the CAM PHY 1250 may include a content addressable memory (CAM). As an example, the CAM may include a nonvolatile memory. That is, the CAM may include a nonvolatile memory that retains data regardless of whether the power of the nonvolatile memory is turned on or off. The CAM PHY 1250 may store a data pattern in the CAM. The CAM PHY 1250 may use the data DATA received through the data pad DQ as an address of the CAM. The CAM PHY 1250 may store a data pattern corresponding to the data DATA stored in the CAM in a memory cell array of the memory device 1200. The data pattern stored in the CAM may include a capacity of a cell greater than the corresponding data DATA. Therefore, the memory device 1200 may use an external data pad DQ (or external bandwidth) that is less than an internal data path (or internal bandwidth) between the CAM PHY 1250 and the memory cell array of the memory device 1200. That is, the memory device 1200 may use an external bandwidth smaller than an actual internal bandwidth to exchange the same capacity of data with the memory controller 1100. Therefore, the memory device 1200 may reduce heat generated by data exchanged through the external data pad DQ.

[0043] According to example embodiments, the memory controller 1100 may include a CAM PHY (CAM PHY) 1150 using the same protocol as the CAM PHY 1250 of the memory device 1200. For example, the CAM PHY 1150 of the memory controller 1100 may store the same data pattern as the data pattern stored in the CAM PHY 1250 of the memory device 1200. The CAM PHY 1150 of the memory controller 1100 may encode the original data to be transmitted into data DATA based on the data pattern stored in the CAM PHY 1250 of the memory device 1200. The CAM PHY 1250 of the memory device 1200 may decode the data DATA and store the data pattern corresponding to the data DATA in the memory cell array of the memory device 1200. The memory controller 1100 may transmit or receive the data DATA through the controller data pad CDQ. The number of the controller data pads CDQ may be less than the number of internal data paths of the memory controller 1100.

[0044] Figure 2 It shows Figure 1 A block diagram of a memory device. Figure 2, the memory device 1200 may include a memory cell array 1210, an address decoder (ADDR DEC) 1220, a row decoder (ROW DEC) 1221, a column decoder (COL DEC) 1222, a command decoder (CMD) 1230, a bit line sense amplifier (BLSA) 1240, an input / output driver (IODRV) 1241, an input / output sense amplifier (IOSA) 1242, a CAM PHY (CAM PHY) 1250, and a CAM controller 1260. However, the present disclosure is not limited thereto, and therefore, according to other embodiments, the memory device 1200 may include other than the CAM controller 1260. Figure 2 One or more other components other than those shown, or may be omitted Figure 2 In addition, according to the embodiment, one or more components shown in FIG. Figure 2 One or more components shown.

[0045] According to example embodiments, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1210 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0046] According to an example embodiment, the address decoder 1220 may be Figure 1 The memory controller 1100 receives the address ADDR. For example, the address ADDR may include a row address RA indicating or identifying a row of the memory cell array 1210 and a column address CA indicating or identifying a column of the memory cell array 1210. The address decoder 1220 may send the row address RA to the row decoder 1221, and may send the column address CA to the column decoder 1222.

[0047] According to an example embodiment, the row decoder 1221 may select one of a plurality of word lines WL connected to the memory cell array 1210. For example, the row decoder 1221 may decode the row address RA received from the address decoder 1220, select a word line corresponding to the row address RA, and activate the selected word line. Here, the row decoder 1221 may select a single word line based on the row address RA decoded by the address decoder 1220.

[0048] According to example embodiments, the column decoder 1222 may select a bit line from a plurality of bit lines BL of the memory cell array 1210. The column decoder 1222 may decode a column address CA received from the address decoder 1220 to select a bit line BL corresponding to the column address CA.

[0049] According to an example embodiment, the command decoder 1230 may decode the command CMD signal received from the storage controller to generate a control signal. The control signal may include, but is not limited to, a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, and a chip select signal / CS. According to an embodiment, one or more of the control signals may be sent to the row decoder 1221, the column decoder 1222, the CAM controller 1260, or other components of the memory device 1200. The command CMD may include an activation request, a read request, a write request, or a precharge request. The command decoder 1230 may control the overall operation of the row decoder 1221, the column decoder 1222, and the bit line sense amplifier 1240 by a control signal corresponding to the command CMD.

[0050] According to example embodiments, the bit line sense amplifier 1240 may be connected to the bit line BL of the memory cell array 1210. For example, the bit line sense amplifier 1240 may sense a voltage variation of a selected bit line among a plurality of bit lines BL, and may amplify and output the voltage variation.

[0051] According to example embodiments, the input / output driver 1241 may store a data pattern received from the CAM PHY 1250 as output data ODAT in the memory cell array 1210. For example, the input / output driver 1241 may be connected to the CAM PHY 1250 through an internal input path.

[0052] According to example embodiments, the input / output sense amplifier 1242 may transmit output data ODAT to the CAM PHY 1250 based on a voltage sensed and amplified by the bit line sense amplifier 1240. For example, the input / output sense amplifier 1242 may be connected to the CAM PHY 1250 through an internal output path.

[0053] According to an example embodiment, the CAM PHY 1250 may store a data pattern in the CAM cell array 1251. For example, a user may store a frequently used data pattern in the CAM cell array 1251 in advance.

[0054] According to an example embodiment, the CAM PHY 1250 may output input data IDAT based on data DATA received from an external device (e.g., the memory controller 1100). For example, the data DATA may be used as an address of the CAM cell array 1251. The CAM PHY 1250 may transmit the data DATA to the CAM controller 1260. The CAM controller 1260 may control the CAM PHY 1250 to output a data pattern of the CAM cell array 1251 corresponding to the data DATA.

[0055] According to an example embodiment, the CAM PHY 1250 may output data DATA corresponding to the output data ODAT to an external device (e.g., the memory controller 1100). In the example case of receiving a read request from the memory controller 1100, the memory cell array 1210 may output data corresponding to the read request. The bit line sense amplifier 1240 and the input / output sense amplifier 1242 may send the data read from the memory cell array 1210 to the CAM PHY 1250 as the output data ODAT. The CAM PHY 1250 may compare the output data ODAT with the data pattern stored in the CAM cell array 1251. The CAM PHY 1250 may output the address of the data pattern matching the output data ODAT to the outside as the data DATA through the data pad DQ.

[0056] According to an example embodiment, the CAM controller 1260 may control the overall operation of the CAM PHY 1250. In an example case where data DATA and a write request are received from the memory controller 1100, the CAM controller 1260 may control the CAM PHY 1250 to output a data pattern corresponding to the data DATA of the CAM cell array 1251. In an example case where a read request is received from the memory controller 1100, the CAM controller 1260 may control the CAM PHY 1250 to output an address of a matched data pattern as data DATA by comparing the output data ODAT with the data pattern stored in the CAM cell array 1251. In an example case where data DATA and a data pattern storage request are received from the memory controller 1100, the CAM controller 1260 may control the CAM PHY 1250 to store the received data DATA in the CAM cell array 1251 as the data pattern.

[0057] As described above, the CAM PHY 1250 may store a data pattern corresponding to the data DATA received from the memory controller 1100 in the CAM cell array 1251. The CAM PHY 1250 may convert the data DATA into a data pattern stored in the CAM cell array 1251, and convert the data pattern into the data DATA. In addition, the data pattern stored in the CAM cell array 1251 may include a capacity of a cell larger than the corresponding data DATA. Therefore, the memory device 1200 may use an external data pad DQ that is less than an internal data path (e.g., an internal input path or an internal output path) between the CAM PHY 1250 and the memory cell array 1210.

[0058] That is, the memory device 1200 may use an external bandwidth smaller than an actual internal bandwidth to exchange the same capacity of data with the memory controller 1100. Therefore, the memory device 1200 may reduce heat generated by the external data pad DQ.

[0059] Figure 3 It shows Figure 2 Block diagram of the CAM PHY. Figure 2 and Figure 3 , the CAM PHY 1250 may include a CAM cell array 1251 , an input receiver (RCV) 1252 , a data pattern comparator 1253 , and an output driver (DRV) 1254 .

[0060] According to an example embodiment, the CAM PHY 1250 may perform a pattern write operation. For example, the memory device 1200 may store a data pattern DPT to be used in a general write or read operation in the CAM cell array 1251. Here, a general write or read operation may also be referred to as a normal write or read operation, in which a memory controller performs an access operation to access (e.g., read or write) data in the memory cell array 1210. For example, in a pattern write operation that may occur before a general write or read operation, the memory device 1200 may store a plurality of data patterns DPT. However, the present disclosure is not limited thereto, and therefore, the pattern write operation may occur at other times to update the CAM cell array 1251. For example, according to an embodiment, the pattern write operation may occur during or after a general write or read operation to update the CAM cell array 1251 for future general write or read operations. The memory device 1200 may receive a pattern write command and a CAM address from the memory controller 1100. The CAM controller 1260 may receive a pattern write flag through the command decoder 1230. The CAM controller 1260 may receive a CAM address through the address decoder 1220. The CAM controller 1260 may determine that the address received together with the mode write flag is a CAM address. The CAM controller 1260 may select a CAM cell of the CAM cell array 1251 corresponding to the CAM address. The memory device 1200 may receive data DATA through the data pad DQ. The input receiver 1252 may send data DATA to the CAM controller 1260. The CAM controller 1260 may store the data DATA in the selected CAM cell. For example, the CAM controller 1260 may store the data DATA in the CAM cell corresponding to the received CAM address.

[0061] According to an example embodiment, the CAM PHY 1250 may convert (or decode) data DATA received from the memory controller 1100 during a general write operation into input data IDAT to be stored in the memory cell array 1210. For example, the memory device 1200 may receive a write command and a normal address from the memory controller 1100. The CAM controller 1260 may receive a write flag through the command decoder 1230. The memory device 1200 may receive the data DATA through the data pad DQ. The input receiver 1252 may send the data DATA to the CAM controller 1260. The CAM controller 1260 may obtain the CAM address of the CAM cell array 1251 from the data DATA. The CAM controller 1260 may control the CAM cell array 1251 to output a data pattern corresponding to the CAM address. The data pattern may be sent to the input / output driver 1241 through the internal input path IP. The input / output driver 1241 may send the data pattern as the input data IDAT to the memory cell array 1210. The memory cell array 1210 may store the input data IDAT in a normal address.

[0062] According to an example embodiment, the CAM PHY 1250 may convert (or encode) output data ODAT read from the memory cell array 1210 during a general read operation into data DATA to be transmitted to the memory controller 1100. For example, the memory device 1200 may receive a read command and a normal address from the memory controller 1100. The memory cell array 1210 and the bit line sense amplifier 1240 may transmit the output data ODAT corresponding to the normal address to the input / output sense amplifier 1242. The input / output sense amplifier 1242 may transmit the output data ODAT to the data pattern comparator 1253 through the internal output path OP. The data pattern comparator 1253 may compare the output data ODAT with the data pattern DPT stored in the CAM cell array 1251. The data pattern comparator 1253 may transmit a CAM address corresponding to a data pattern matched by comparing the output data ODAT with the data pattern DPT to the output driver 1254. According to an embodiment, the matched data pattern may be a data pattern having the least number of bits different from the output data ODAT among the data pattern DPT. The output driver 1254 may send the determined CAM address through the data path DQ.

[0063] Figure 4 is a table showing an example of a data pattern stored in a CAM cell array according to an embodiment. Figures 2 to 4 , the CAM cell array 1251 can store a data pattern DPT corresponding to the CAM address.

[0064] According to an example embodiment, the CAM cell array 1251 may store a data pattern DPT having a specific data pattern. For example, the data pattern DPT may be set or specified by a user. The data pattern DPT may be stored in the CAM cell array 1251 through a pattern write operation. The data pattern DPT may be set to a pattern frequently used in the storage system 1000. As an example, in Figure 4 , the data pattern DPT may include a first data pattern DPT1 to a sixteenth data pattern DPT16. The first data pattern DPT1 to the sixteenth data pattern DPT16 may correspond to a first CAM address CADDR1 to a sixteenth CAM address CADDR16, respectively. Each data pattern may have a structure in which each CAM address is repeated four times. However, this is an example, and each data pattern may be configured in various ways according to the user's settings.

[0065] According to example embodiments, the data pattern may be configured to have a capacity greater than the CAM address. The CAM address may include a number of bits corresponding to the number of data pads DQ. The data pattern may include a number of bits corresponding to the number of internal data paths (e.g., internal input paths IP or internal output paths OP). For example, in Figure 4 In, the CAM address (e.g., each of the first CAM address CADDR1 to the sixteenth CAM address CADDR16) may include four bits. The data pattern (e.g., each of the first data pattern DPT1 to the sixteenth data pattern DPT16) may include sixteen bits. As an example, the number of external data pads DQ may be less than the number of internal data paths (e.g., internal input paths IP or internal output paths OP). As another example, the number of internal data paths (e.g., internal input paths IP or internal output paths OP) may be configured as an integer multiple of the number of external data pads DQ. In Figure 4 In the embodiment, the CAM address can be exchanged with the memory controller 1100 through four data pads (DQ0, DQ1, DQ2, and DQ3). The data pattern can be exchanged with the memory cell array 1210 through sixteen internal data paths (P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15). Therefore, compared with the data capacity stored in the memory cell array 1210, the memory device 1200 can reduce the heat generated from the data pad DQ. Although Figure 4 It is shown that the CAM address can include four bits and the data pattern can include sixteen bits, but the present disclosure is not limited thereto. Thus, according to another embodiment, the CAM address can be greater than four bits or less than four bits, and the data pattern can be greater than sixteen bits or less than sixteen bits.

[0066] Figure 5 It shows Figure 2 Flowchart of the pattern write operation of the memory device. Figure 6 It shows Figure 5 A diagram of the data flow during a mode write operation. Figure 2 , Figure 5 and Figure 6 , the memory device 1200 may store the data pattern DPT in the CAM cell array 1251. The memory device 1200 may store the data pattern DPT to be used in a general write or read operation in the CAM cell array 1251 before the general write or read operation.

[0067] According to an example embodiment, in operation S110, the method may include receiving information (or instructions) for writing a data pattern into the CAM cell array 1251. For example, the memory device 1200 may receive a pattern write command PWC and a CAM address CADDR. For example, the command decoder 1230 may receive the pattern write command PWC from the memory controller 1100. The command decoder 1230 may send a pattern write flag PWF to the CAM controller 1260 based on the pattern write command PWC. The address decoder 1220 may receive the CAM address CADDR from the memory controller 1100. The address decoder 1220 may send the CAM address CADDR to the CAM controller 1260.

[0068] According to an example embodiment, in operation S120, the method may include receiving a data pattern. For example, the memory device 1200 may receive the data pattern DPT from the memory controller 1100. For example, the memory device 1200 may receive the data pattern DPT through the data pad DQ. The input receiver 1252 may send the data pattern DPT to the CAM controller 1260.

[0069] According to an example embodiment, in operation S130, the method may include selecting a plurality of CAM cells corresponding to a CAM address CADDR in the CAM cell array 1251. For example, the memory device 1200 may select a CAM cell corresponding to the CAM address CADDR of the CAM cell array 1251. For example, the CAM controller 1260 may receive a mode write flag PWF from the command decoder 1230. The CAM controller 1260 may receive a CAM address CADDR from the address decoder 1220. The CAM controller 1260 may determine the address received together with the mode write flag PWF as the CAM address CADDR. The CAM controller 1260 may select a CAM cell corresponding to the CAM address CADDR of the CAM cell array 1251.

[0070] According to an example embodiment, in operation S140, the method may include storing the data pattern in the selected CAM cell. For example, the memory device 1200 may store the received data pattern DPT in the selected CAM cell. For example, the CAM controller 1260 may store the data pattern DPT received from the input receiver 1252 in the selected CAM cell. Since the size of one data pattern is larger than the bandwidth of the data pad DQ, the data pattern DPT may be divided into a plurality of blocks and received through the data pad DQ.

[0071] According to an example embodiment, the data pattern DPT (eg, Figure 4 The number of the first data pattern DPT1 to the sixteenth data pattern DPT1 6) may initially be a CAM address CADDR (eg, Figure 4 The number of the first CAM address CADDR1 to the sixteenth CAM address CADDR16) is calculated. Thereafter, each data pattern DPT may be updated for each CAM address.

[0072] Figure 7 It shows Figure 2 Flowchart of a write operation of a memory device. Figure 8 It shows Figure 7 Figure 1 shows the data flow during a write operation. Figure 2 , Figure 7 and Figure 8 , the memory device 1200 may perform a general write operation. The memory device 1200 may convert (or decode) first data DATA1 received from the memory controller 1100 into input data IDAT to be stored in the memory cell array 1210 during the general write operation.

[0073] According to an example embodiment, in operation S210, the method may include receiving information or instructions for performing a write operation. For example, the memory device 1200 may receive a write command WR and a first address ADDR1 from the memory controller 1100. For example, the command decoder 1230 may receive a write command WR from the memory controller 1100. The command decoder 1230 may send a write flag WRF to the CAM controller 1260 based on the write command WR. The address decoder 1220 may receive the first address ADDR1 from the memory controller 1100. The address decoder 1220 may decode the first address ADDR1 to send a first row address RA1 to the row decoder 1221, and send a first column address CA1 to the column decoder 1222.

[0074] According to example embodiments, in operation S220, the method may include receiving data to be written into a memory cell array of a memory device (e.g., write data). For example, the memory device 1200 may receive first data DATA1 from the memory controller 1100. For example, the memory device 1200 may receive the first data DATA1 through the data pad DQ. The input receiver 1252 may send the first data DATA1 to the CAM controller 1260.

[0075] According to an example embodiment, in operation S230, the method may include obtaining a data pattern corresponding to the write data. For example, the memory device 1200 may search the CAM cell array 1251 for a data pattern DPT corresponding to the first data DATA1. For example, the CAM controller 1260 may receive a write flag WRF from the command decoder 1230. In the example case where the write flag WRF is received, the CAM controller 1260 may obtain a CAM address CADDR of the CAM cell array 1251 according to the first data DATA1. The CAM controller 1260 may control the CAM cell array 1251 to output the data pattern DPT corresponding to the CAM address CADDR through the internal input path IP.

[0076] According to an example embodiment, in operation S240, the method may include storing the data pattern to a memory cell array of the memory device. For example, the memory device 1200 may store the data pattern DPT output from the CAM cell array 1251 as input data IDAT in the memory cell array 1210. For example, the input / output driver 1241 may send the data pattern DPT as input data IDAT to the memory cell array 1210. The memory cell array 1210 may store the input data IDAT in the first address ADDR1 (e.g., a memory cell corresponding to the first row address RA1 and the first column address CA1).

[0077] According to an example embodiment, the memory controller 1100 may transmit the first data DATA1 to the memory device 1200. For example, the memory controller 1100 may encode the same original data as the input data IDAT in the first data DATA1, which is used to access the data pattern in the CAM cell array 1251. The memory device 1200 may decode the first data DATA1 through the CAM PHY 1250 and store the original data in the memory cell array 1210. Therefore, the memory controller 1100 may obtain the effect of transmitting the original data by transmitting the first data DATA1 with a smaller capacity than the original data. The memory device 1200 may obtain the effect of receiving the original data by having a data pad DQ less than the number of internal input paths IP. Therefore, the memory device 1200 may reduce the heat generated by the data pad DQ compared to the capacity of the original data.

[0078] Fig. 9 It shows Figure 2 Flowchart of a read operation of a memory device. Fig.10 It shows Fig. 9 Figure 1 shows the data flow during a read operation. Figure 2 , Fig. 9 and Fig.10 , the memory device 1200 may perform a general read operation. The memory device 1200 may convert (or encode) the output data ODAT read from the memory cell array 1210 during the general read operation into the second data DATA2 to be transmitted to the memory controller 1100.

[0079] According to an example embodiment, in operation S310, the method may include receiving information or instructions for performing a read operation. For example, the memory device 1200 may receive a read command RD and a second address ADDR2 from the memory controller 1100. For example, the command decoder 1230 may receive a read command RD from the memory controller 1100. The command decoder 1230 may send a read flag RDF to the CAM controller 1260 based on the read command RD. The address decoder 1220 may receive the second address ADDR2 from the memory controller 1100. The address decoder 1220 may decode the second address ADDR2 to send a second row address RA2 to the row decoder 1221, and send a second column address CA2 to the column decoder 1222.

[0080] According to an example embodiment, in operation S320, the method may include reading data from a memory cell array of a memory device based on an address received from a memory controller. For example, the memory device 1200 may read output data ODAT from the memory cell array 1210. For example, the memory cell array 1210 and the bit line sense amplifier 1240 may send output data ODAT corresponding to the second address ADDR2 (e.g., a memory cell corresponding to the second row address RA2 and the second column address CA2) to the input / output sense amplifier 1242. The input / output sense amplifier 1242 may send output data ODAT to the data pattern comparator 1253 through an internal output path OP.

[0081] According to an example embodiment, in operation S330, the method may include comparing the data read from the memory cell array with the memory pattern in the CAM cell array. For example, the memory device 1200 may compare the output data ODAT with the data pattern DPT stored in the CAM cell array 1251. For example, the CAM controller 1260 may receive a read flag RDF. In the example case where the read flag RDF is received, the CAM controller 1260 may control the CAM cell array 1251 to provide the data pattern DPT to the data pattern comparator 1253. The data pattern comparator 1253 may select a data pattern (hereinafter referred to as a matching pattern) that matches the output data ODAT among the data patterns DPT. As an example, the data pattern comparator 1253 may select a data pattern having a minimum number of bits different from the output data ODAT as a matching pattern. Therefore, the CAM PHY 1250 may have a function of recovering errors in units of bits. The data pattern comparator 1253 may send a CAM address CADDR corresponding to the matching pattern to the output driver 1254.

[0082] According to an example embodiment, in operation S340, the method may include obtaining a CAM address of a data pattern matching the data read from the memory cell array. For example, the memory device 1200 may output a CAM address CADDR of a matching pattern as the second data DATA2. For example, the output driver 1254 may send the determined CAM address CADDR as the second data DATA2 to the memory controller 1100 through the data path DQ.

[0083] According to an example embodiment, the memory device 1200 may transmit the second data DATA2 encoding the output data ODAT to the memory controller 1100. The memory controller 1100 may obtain the same data as the output data ODAT (or matching pattern) by decoding the second data DATA2. Therefore, the memory device 1200 may achieve the effect of transmitting the output data ODAT by transmitting the second data DATA2 having a smaller capacity than the output data ODAT. The memory device 1200 may obtain the effect of transmitting the output data ODAT by having a data pad DQ less than the number of internal output paths OP. Therefore, the memory device 1200 may reduce the heat generated by the data pad DQ compared to the capacity of the output data ODAT. In addition, during the encoding process of the output data ODAT, even if there is a bitwise error in the output data ODAT, the data pattern comparator 1253 may output the corrected second data DATA2. Therefore, the CAM PHY 1250 may include a bit-level error recovery function.

[0084] Fig.11 is a diagram showing a three-dimensional stacked storage system according to an embodiment. Fig.11 , the memory system 2000 may include a logic chip 2100 and a memory chip 2200. The logic chip 2100 may be electrically connected to the memory chip 2200 via a first bump BP1. The first bump BP1 may electrically connect the controller data pad 2101 and the memory data pad 2201, respectively. For example, each first bump BP1 may electrically connect one of the controller data pads 2101 to one of the memory data pads 2201. The logic chip 2100 may be electrically connected to an external component (or a package external connection pin) via a second bump BP2. For example, the logic chip 2100 may be electrically connected to a package external connection pin via a second bump BP2.

[0085] According to example embodiments, the logic chip 2100 may include a memory controller 2110 and a logic core 2120. The memory controller 2110 and the logic core 2120 may be implemented by various electronic components and / or electronic circuits. Figure 1 Therefore, the configuration and features of the storage controller 1100 of FIG. 1100 will be omitted. Figure 1The storage controller 2110 may include a first CAM PHY 2115. The first CAM PHY 2115 may convert data between the controller data pad 2101 and the controller internal path 2102. The first CAM PHY 2115 may include a CAM cell array and a data pattern comparator. The storage controller 2110 may include a CAM controller that controls the first CAM PHY 2115. The first CAM PHY 2115 may include a CAM cell array and a data pattern comparator. Figure 1 Therefore, the same or similar configuration and features as the CAM PHY 1150 will be omitted. Figure 1 CAM PHY 1150 having the same or similar configuration and features as described above.

[0086] According to example embodiments, the memory chip 2200 may include a memory cell array 2210, a second CAM PHY 2250, and a CAM controller 2260. For example, the memory chip 2200 may include Figure 1 Therefore, the same or similar configuration and features as the memory device 1200 will be omitted. Figure 1 The second CAM PHY 2250 may convert data between the memory data pad 2201 and the memory internal path 2202. The second CAM PHY 2250 may include a CAM cell array and a data pattern comparator. The second CAM PHY 2250 may include a CAM cell array and a data pattern comparator. Figure 2 Therefore, the same or similar configuration and features as the CAM PHY 1250 will be omitted. Figure 2 The CAM controller 2260 may control the overall operation of the second CAM PHY 2250 during a mode write operation, a general write operation, or a general read operation. The CAM controller 2260 may include a Figure 2 The same or similar configuration and features as the CAM controller 1260 of FIG. Figure 2 The CAM controller 1260 has the same or similar configuration and features as described above.

[0087] As described above, the logic chip 2100 and the memory chip 2200 can be connected by external data pads (e.g., controller data pads 2101 or memory data pads 2201) that are less than the internal data path (e.g., controller internal path 2102 or memory internal path 2202). When sending and receiving data, the encoded data can be exchanged through a smaller number of external data pads compared to the data capacity actually used inside the logic chip 2100 or the memory chip 2200. Therefore, the heat generated from the external data pads can be reduced compared to the data capacity actually used inside the logic chip 2100 or the memory chip 2200.

[0088] According to an embodiment of the present disclosure, through data conversion using a CAM, a memory device may use a smaller number of external data pads compared to an internal data path of the memory device.

[0089] According to an embodiment of the present disclosure, as the number of external data pads is reduced, heat generated by the external data pads of a memory device may be reduced.

[0090] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: A memory cell array, comprising a memory cell; an address decoder configured to output address information based on an address received from an external device; a command decoder configured to generate a memory access signal based on a command received from the external device; a content addressable memory CAM cell array configured to store a plurality of data patterns; as well as A CAM physical layer connected to a plurality of external data pads, the CAM physical layer being configured as: Based on the memory access signal being a write operation signal, based on the first data received through the plurality of external data pads, sending a first data pattern among the plurality of data patterns as input data to a first memory cell of the memory cell array corresponding to the address information, and Based on the memory access signal being a read operation signal, the output data from the memory cell array is compared with the multiple data patterns based on the address information, and a first CAM address corresponding to a second data pattern matching the output data is output as second data through the multiple external data pads.

2. The memory device according to claim 1, wherein: The number of the plurality of external data pads is smaller than the number of internal data paths between the CAM physical layer and the memory cell array.

3. The memory device according to claim 1, wherein: The number of internal data paths between the CAM physical layer and the memory cell array is an integer multiple of the number of the plurality of external data pads.

4. The memory device according to claim 1, further comprising: A CAM controller is configured to control an operation of the CAM physical layer based on a command flag corresponding to a command received from the command decoder.

5. The memory device according to claim 4, wherein: The command decoder is configured to send a mode write flag to the CAM controller based on a mode write command, The address decoder is configured to: based on receiving a second CAM address corresponding to the mode write command, send the second CAM address to the CAM controller; The CAM physical layer is configured to: send the input data pattern received from the plurality of external data pads to the CAM controller, and The CAM controller is configured to: based on receiving the pattern write flag, store the input data pattern in a CAM cell of the CAM cell array corresponding to the second CAM address.

6. The memory device according to claim 4, wherein: The CAM physical layer includes an input receiver configured to send the first data received from the plurality of external data pads to the CAM controller, The command decoder is configured to: send a write flag to the CAM controller based on a write command, and The CAM controller is configured to: obtain a third CAM address of the CAM cell array based on the first data received from the input receiver; and output the first data pattern corresponding to the third CAM address based on receiving the write flag.

7. The memory device according to claim 6, further comprising: an input / output driver configured to send the first data pattern as input to the memory cell array, The address information includes a first row address and a first column address corresponding to the write command, and The memory cell array is configured to store the input based on the first row address and the first column address.

8. The memory device according to claim 4, wherein: The command decoder is configured to send a read flag to the CAM controller based on a read command, The address information includes a second row address and a second column address corresponding to the read command, and The memory cell array is configured to output the output data based on the second row address and the second column address.

9. The memory device according to claim 8, further comprising: an input / output sense amplifier configured to send the output data to the CAM physical layer, Wherein, the CAM physical layer includes: a data pattern comparator configured to compare the output data with the plurality of data patterns stored in the CAM cell array and output the first CAM address corresponding to the second data pattern matching the output data; and An output driver is configured to output the first CAM address as the second data through the plurality of external data pads.

10. The memory device according to claim 9, wherein: The data pattern comparator is further configured to determine the second data pattern by identifying one of the plurality of data patterns that has a smallest number of bit differences with the output data.

11. A method of operating a memory device, the method comprising: receiving a plurality of content addressable memory CAM addresses; receiving a plurality of data patterns through a plurality of external data pads, each data pattern of the plurality of data patterns corresponding to one of the plurality of CAM addresses; storing the plurality of data patterns in a CAM cell array based on the plurality of CAM addresses; receiving a write command and a first address; receiving first data through the plurality of external data pads; selecting a first data pattern corresponding to the first data from among the plurality of data patterns stored in the CAM cell array; as well as The first data pattern is stored as input data in a memory cell array.

12. The method according to claim 11, wherein: Selecting the first data mode includes: Obtaining a first CAM address of the CAM cell array based on the first data; and The first data pattern corresponding to the first CAM address is output.

13. The method according to claim 11, further comprising: receiving a read command and a second address; reading output data corresponding to the second address from the memory cell array; comparing the output data with the plurality of data patterns stored in the CAM cell array; The selected CAM address corresponding to the second data pattern matching the output data is output as the second data through the plurality of external data pads.

14. The method according to claim 13, wherein: Comparing the output data to the plurality of data patterns comprises: The second data pattern is determined by identifying one of the plurality of data patterns that has a minimum number of bit differences from the output data.

15. The method according to claim 13, wherein: The number of bits of each of the plurality of data patterns is an integer multiple of the number of bits of the first data or the second data.

16. A storage system comprising: A logic chip, comprising a logic core, a memory controller and a first content addressable memory CAM physical layer; as well as A memory chip is stacked on the logic chip, wherein the memory chip includes a memory cell array and a second CAM physical layer, wherein the first CAM physical layer comprises a first CAM cell array configured to store a plurality of data patterns, wherein the second CAM physical layer comprises a second CAM cell array configured to store the plurality of data patterns, wherein the first CAM physical layer and the second CAM physical layer are configured to exchange encoded data having a smaller capacity than original data through a plurality of external data pads based on the plurality of data modes, and The number of the plurality of external data pads is smaller than the number of internal data paths of the logic chip or the memory chip.

17. The storage system according to claim 16, wherein: The memory chip further includes: an address decoder configured to output address information based on an address received from the logic chip; a command decoder configured to generate a memory access signal based on a command received from the logic chip, Wherein, the second CAM physical layer is configured as: Based on the memory access signal being a write operation signal, based on the first data received from the logic chip, sending a first data pattern among the plurality of data patterns as input data to a first memory cell of the memory cell array corresponding to the address information; and Based on the memory access signal being a read operation signal, the output data from the memory cell array is compared with the multiple data patterns based on the address information, and a first CAM address corresponding to a second data pattern matching the output data is output as second data through the multiple external data pads.

18. The storage system according to claim 17, wherein: The memory chip further includes: A CAM controller is configured to control an operation of the second CAM physical layer based on a command flag corresponding to a command received from the command decoder.

19. The storage system according to claim 18, wherein: The second CAM physical layer is configured to transmit the first data received from the plurality of external data pads to the CAM controller, wherein the command decoder is configured to send a write flag to the CAM controller based on a write command, The CAM controller is configured to: acquire a second CAM address of the CAM cell array according to the first data, and output the first data pattern corresponding to the second CAM address, Wherein, the address information includes a first row address and a first column address, and The memory cell array is configured to store the input data based on the first row address and the first column address.

20. The storage system according to claim 18, wherein: The command decoder is configured to send a read flag to the CAM controller based on a read command, Wherein, the address information includes a second row address and a second column address, wherein the memory cell array is configured to output the output data based on the second row address and the second column address, and Wherein, the second CAM physical layer is configured to: compare the output data with the multiple data patterns stored in the CAM cell array, output the first CAM address corresponding to the second data pattern matching the output data, and output the first CAM address as the second data through the multiple external data pads.

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